Semiconductor device

Abstract

A semiconductor device (1) has a rectangular shape in which the side length in a first direction is equal to or greater than the side length in a second direction in plan view, the semiconductor device comprising: at positions that are included in a first region (A1), 2n+1 elliptical first source pads (111) of a first vertical MOS transistor (10), said source pads being arranged in a stripe pattern and extending in the second direction; and, at positions that are included in a second region (A2), 2n+1 elliptical second source pads (121) of a second vertical MOS transistor (20), said source pads being arranged in a stripe pattern and extending in the second direction, wherein a first source pad (111a) that is closest to a boundary line (90) between the first region (A1) and the second region (A2) among the 2n+1 first source pads (111) is longer than the other first source pads (111), and a second source pad (121a) that is closest to the boundary line (90) among the 2n+1 second source pads (121) is longer than the other second source pads (121).

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] 2. Description of the Related Art Conventionally, semiconductor devices are known that are mounted on a mounting substrate and switch a current path on the mounting substrate between a conductive state and a non-conductive state (see, for example, Japanese Patent Application Laid-Open No. 2003-121998).

[0003] International Publication No. 2020 / 129786

[0004] Generally, current paths through which large currents flow in a mounting substrate are designed to have low conduction resistance, and therefore, a semiconductor device that is mounted on a mounting substrate and switches between a conductive state and a non-conductive state of a current path through which large currents flow is desired to have characteristics suitable for reducing the conduction resistance of the current path in the mounting substrate.

[0005] On the other hand, a semiconductor device is known that is configured by stacking a semiconductor layer and a metal layer in order to reduce the conduction resistance in the semiconductor device.

[0006] When such a semiconductor device, which is constructed by stacking semiconductor layers and metal layers, is mounted face-down on a mounting board in a high-temperature environment, such as during solder reflow, warping may occur in the semiconductor device due to differences in physical properties such as the thermal expansion coefficient and Young's modulus between the semiconductor layer and the metal layer in that high-temperature environment.

[0007] This warping can cause mounting defects such as solder overflow or solder deficiencies.

[0008] Therefore, an object of the present disclosure is to provide a semiconductor device that has characteristics suitable for reducing the conduction resistance of the current path in the mounting board on which it is mounted, and that can suppress the occurrence of mounting defects when the semiconductor device is mounted on the mounting board.

[0009] a first vertical MOS transistor formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region of the semiconductor layer adjacent to the first region in a plan view of the semiconductor device; 2n (n is an integer of 1 or more)+1 first source pads of the first vertical MOS transistor formed on a top surface of the semiconductor device at positions included in the first region in the plan view; a first gate pad of the first vertical MOS transistor; and 2n+1 second source pads of the second vertical MOS transistor formed on a top surface of the semiconductor device at positions included in the second region in the plan view; and a second gate pad of the second vertical MOS transistor. The semiconductor layer has a semiconductor substrate on a back surface side that is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor. is a rectangle having a first side and a second side that extend in a first direction and have the same length, and a third side and a fourth side that extend in a second direction perpendicular to the first direction and have the same length, the third side and the fourth side having lengths that are equal to or shorter than the lengths of the first side and the second side, the first region and the second region being one side and the other side that divide the semiconductor layer in area into two equal halves, the third side is included in the periphery of the first region, the fourth side is included in the periphery of the second region, and the boundary line between the first region and the second region is a first line segment and a second line segment extending straight in a first direction, and a third line segment, a fourth line segment, and a fifth line segment extending straight in the second direction, which are connected in this order from one end of the boundary line to the other end of the boundary line, over the entire length of the third line segment, the entire length of the first line segment, the entire length of the fourth line segment, the entire length of the second line segment, and the entire length of the fifth line segment, and the length of the first line segment changes monotonically in the first direction and the second direction from the one end to the other end, and the length of the first line segment and the length of the second line segment are equal,the third line segment and the fifth line segment have the same length, one end is located on the first side and the other end is located on the second side, the fourth line segment is an imaginary center line of the semiconductor layer that bisects the semiconductor layer in terms of area in the plan view and is located on the center line that extends in a straight line in the second direction, the first gate pad is circular, the center of the first gate pad is located on the center line, there is no other pad between the first gate pad and the second side, and the second gate pad is located on the the center of the second gate pad is located on the center line, there is no other pad between the second gate pad and the first side, the 2n+1 first source pads and the 2n+1 second source pads are oval with the second direction as the longitudinal direction, the 2n+1 first source pads and the 2n+1 second source pads have the same width in the lateral direction, and the 2n+1 first source pads are spaced apart from a first nearest source pad that is closest to the fourth line segment and a first nearest source pad that is closest to the fourth line segment. and 2n first non-nearest source pads that are not nearest to the fourth line segment, wherein the first nearest source pads are arranged such that a line symmetry axis extending in the longitudinal direction coincides with a first nearest equidistant line that is nearest to the fourth line segment among the n+1 first equidistant lines that are imaginary n+1 first equidistant lines extending in the second direction in the first region and that are arranged at equal intervals in the first direction, and the 2n first non-nearest source pads are arranged such that a line symmetry axis extending in the longitudinal direction coincides with a first nearest equidistant line that is nearest to the fourth line segment among the n+1 first equidistant lines. In each of the second source pads, two of the 2n first nearest source pads are arranged such that their longitudinal axes of symmetry coincide with the first nearest equally spaced lines, and the 2n+1 second source pads are comprised of a second nearest source pad that is closest to the fourth line segment and 2n second nearest source pads that are not closest to the fourth line segment, and the second nearest source pads have their longitudinal axes of symmetry that coincide with one of the n+1 imaginary second equally spaced lines that extend in the second direction in the second region,The n+1 second equally spaced lines are arranged at equal intervals in the first direction so as to coincide with a second nearest equally spaced line that is nearest to the fourth line segment, and the 2n second non-nearest source pads are arranged so that, on each of the n second non-nearest equally spaced lines excluding the second nearest equally spaced line among the n+1 second equally spaced lines, a line symmetry axis extending in the longitudinal direction of two of the 2n second non-nearest source pads coincides with the second nearest equally spaced line, and the 2n+1 first source pads and the 2n+1 second source pads are line symmetrical with respect to the center line.

[0010] According to one aspect of the present disclosure, a semiconductor device is provided that has characteristics suitable for reducing the conduction resistance of a current path in a mounting substrate on which the semiconductor device is mounted, and that can suppress the occurrence of mounting defects when the semiconductor device is mounted on the mounting substrate.

[0011] FIG. 1 is a plan view showing an example of the structure of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment. FIG. 3 is a circuit diagram of a semiconductor device according to an embodiment. FIG. 4 is a plan view showing another example of the structure of a semiconductor device according to an embodiment. FIG. 5A is a cross-sectional view schematically showing a state in which a current flows through a first current path of a semiconductor device according to an embodiment. FIG. 5B is a cross-sectional view schematically showing a state in which a current flows through a second current path of a semiconductor device according to an embodiment. FIG. 6 is a circuit diagram of a charge / discharge circuit according to an embodiment. FIG. 7 is an enlarged plan view of a mounting substrate according to an embodiment. FIG. 8 is a schematic view showing a state in which the semiconductor device 1 according to an embodiment is turned upside down.

[0012] (Background to the development of one aspect of the present disclosure) Conventionally, when a semiconductor device constructed by stacking semiconductor layers and metal layers is mounted face-down on a mounting substrate in a high-temperature environment such as solder reflow, and warping occurs in the semiconductor device, it is known that the direction of the warping is the direction in which curvature occurs along the longitudinal direction of the semiconductor device when viewed in a plane.

[0013] For this reason, in the past, in semiconductor devices with the above configuration, one effective measure to ensure the fluidity of the solder during reflow and to suppress the occurrence of mounting defects caused by the above-mentioned warping has been to take measures such as making the shape of the multiple relatively large pads formed on the surface of the semiconductor device oval with its longitudinal direction aligned with the longitudinal direction of the semiconductor layer.

[0014] In response to this, the inventors, through the development of semiconductor devices having the above configuration, have noticed that in cases where the semiconductor device having the above configuration satisfies certain conditions, such as when the difference between the longitudinal length and the lateral length in a planar view is relatively small, the occurrence of mounting defects that cause warping of the semiconductor device does not become a serious problem.

[0015] The inventors then discovered that in such cases, in order to suppress the occurrence of mounting defects, there is relatively little need to align the longitudinal direction of the semiconductor device and the longitudinal direction of the oval pad in the same direction when viewed in a plane.

[0016] Furthermore, the inventors have found that when forming multiple oval pads on the surface of a semiconductor device, if the shapes of the semiconductor devices are the same, the area occupancy rate of the multiple oval pads can be increased by making the longitudinal direction of the semiconductor device and the longitudinal direction of the oval pads perpendicular to each other when viewed in a plane, rather than making the longitudinal direction of the semiconductor device and the longitudinal direction of the oval pads the same direction when viewed in a plane, i.e., making it possible to reduce the conduction resistance of the current path in the semiconductor device.

[0017] Based on these findings, the inventors have conducted repeated experiments and studies, and have arrived at the semiconductor device according to the present disclosure described below.

[0018] a first vertical MOS transistor formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region of the semiconductor layer adjacent to the first region in a plan view of the semiconductor device; 2n (n is an integer of 1 or more)+1 first source pads of the first vertical MOS transistor formed on an upper surface of the semiconductor device at positions included in the first region in the plan view; a first gate pad of the first vertical MOS transistor; and 2n+1 second source pads of the second vertical MOS transistor formed on an upper surface of the semiconductor device at positions included in the second region in the plan view; and a second gate pad of the second vertical MOS transistor. The semiconductor layer has, on a back surface side, a semiconductor substrate that is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor. In the plan view, the semiconductor layer has: a rectangle having a first side and a second side that extend in a first direction and have the same length, and a third side and a fourth side that extend in a second direction perpendicular to the first direction and have the same length, the third side and the fourth side having lengths equal to or shorter than the lengths of the first side and the second side; the first region and the second region are one side and the other side that divide the semiconductor layer into two equal halves in terms of area; the third side is included in the periphery of the first region; the fourth side is included in the periphery of the second region; and the boundary between the first region and the second region is a first line segment and a second line segment extending straight in a direction, and a third line segment, a fourth line segment, and a fifth line segment extending straight in the second direction, which are connected in this order from one end of the boundary line to the other end of the boundary line, over the entire length of the third line segment, the entire length of the first line segment, the entire length of the fourth line segment, the entire length of the second line segment, and the entire length of the fifth line segment, and the length of the first line segment changes monotonically in the first direction and the second direction from the one end to the other end, and the length of the first line segment and the length of the second line segment are equal,the third line segment and the fifth line segment have the same length, one end is located on the first side and the other end is located on the second side, the fourth line segment is an imaginary center line of the semiconductor layer that bisects the semiconductor layer in terms of area in the plan view and is located on the center line that extends in a straight line in the second direction, the first gate pad is circular, the center of the first gate pad is located on the center line, there is no other pad between the first gate pad and the second side, and the second gate pad is located on the the center of the second gate pad is located on the center line, there is no other pad between the second gate pad and the first side, the 2n+1 first source pads and the 2n+1 second source pads are oval with the second direction as the longitudinal direction, the 2n+1 first source pads and the 2n+1 second source pads have the same width in the lateral direction, and the 2n+1 first source pads are spaced apart from a first nearest source pad that is closest to the fourth line segment and a first nearest source pad that is closest to the fourth line segment. and 2n first non-nearest source pads that are not nearest to the fourth line segment, wherein the first nearest source pads are arranged such that a line symmetry axis extending in the longitudinal direction coincides with a first nearest equidistant line that is nearest to the fourth line segment among the n+1 first equidistant lines that are imaginary n+1 first equidistant lines extending in the second direction in the first region and that are arranged at equal intervals in the first direction, and the 2n first non-nearest source pads are arranged such that a line symmetry axis extending in the longitudinal direction coincides with a first nearest equidistant line that is nearest to the fourth line segment among the n+1 first equidistant lines. In each of the second source pads, two of the 2n first nearest source pads are arranged such that their longitudinal axes of symmetry coincide with the first nearest equally spaced lines, and the 2n+1 second source pads are comprised of a second nearest source pad that is closest to the fourth line segment and 2n second nearest source pads that are not closest to the fourth line segment, and the second nearest source pads have their longitudinal axes of symmetry that coincide with one of the n+1 imaginary second equally spaced lines that extend in the second direction in the second region,The n+1 second equally spaced lines are arranged at equal intervals in the first direction so as to coincide with a second nearest equally spaced line that is nearest to the fourth line segment, and the 2n second non-nearest source pads are arranged so that, on each of the n second non-nearest equally spaced lines excluding the second nearest equally spaced line among the n+1 second equally spaced lines, a line symmetry axis extending in the longitudinal direction of two of the 2n second non-nearest source pads coincides with the second nearest equally spaced line, and the 2n+1 first source pads and the 2n+1 second source pads are line symmetrical with respect to the center line.

[0019] In the semiconductor device having the above configuration, when viewed in a plan view, the longitudinal direction of the semiconductor device and the longitudinal directions of the 2n+1 first source pads and the 2n+1 second source pads are perpendicular to each other.

[0020] Therefore, when viewed in a plan view of the semiconductor device, the area occupancy rate of the 2n+1 first source pads and the area occupancy rate of the 2n+1 second source pads can be made larger than in a configuration in which the longitudinal direction of the semiconductor device coincides with the longitudinal directions of the 2n+1 first source pads and the 2n+1 second source pads.

[0021] Therefore, with a semiconductor device having the above configuration, the conduction resistance of the current path of the current flowing between the 2n+1 first source pads and the 2n+1 second source pads can be reduced more than in a configuration in which the longitudinal direction of the semiconductor device coincides with the longitudinal directions of the 2n+1 first source pads and the 2n+1 second source pads when viewed in a plane.

[0022] The semiconductor device having the above configuration also includes a metal layer that generally has a lower resistivity than the semiconductor layer and that forms part of the current path for the current flowing between the first vertical MOS transistor and the second vertical MOS transistor.

[0023] Therefore, according to the semiconductor device having the above configuration, it is possible to reduce the conduction resistance of the current path of the current flowing between the 2n+1 first source pads and the 2n+1 second source pads.

[0024] Furthermore, with the semiconductor device having the above configuration, in a plan view of the semiconductor device, the first gate pad can be moved closer to the second side at the position of the center of the semiconductor device in the first direction on the second side, as close as possible to the second side in accordance with the design rules, and further, the second gate pad can be moved closer to the first side at the position of the center of the semiconductor device in the first direction on the first side, as close as possible to the first side in accordance with the design rules.

[0025] This makes it possible to prevent the first gate pad and the second gate pad from interfering with the current path of the current flowing between the 2n+1 first source pads and the 2n+1 second source pads.

[0026] Therefore, according to the semiconductor device having the above configuration, it is possible to reduce the conduction resistance of the current path of the current flowing between the 2n+1 first source pads and the 2n+1 second source pads.

[0027] In this specification, the center in a planar view refers to the intersection of the diagonals of a rectangular structure in a planar view, such as a semiconductor device; the center of a circular structure in a planar view, such as a gate pad; the center of a circular structure in a planar view, such as a source ... circular structure;

[0028] Furthermore, in the semiconductor device having the above configuration, when viewed in a plane, two first non-nearest source pads are arranged on each of the first non-nearest equally spaced lines, and two second non-nearest source pads are arranged on each of the second non-nearest equally spaced lines.

[0029] Therefore, with the semiconductor device having the above configuration, in a plan view of the semiconductor device, it is possible to suppress the occurrence of mounting defects caused by warpage of the semiconductor device more effectively than with a configuration in which one first non-nearest source pad is arranged on each of the first non-nearest equally spaced lines and one second non-nearest source pad is arranged on each of the second non-nearest equally spaced lines, because the shorter the longitudinal length of each of the first non-nearest source pads, the lower the frequency of mounting defects, and because the shorter the longitudinal length of each of the second non-nearest source pads, the lower the frequency of mounting defects.

[0030] Thus, the semiconductor device having the above configuration has characteristics suitable for reducing the conduction resistance of the current path in the mounting board on which it is mounted, and can suppress the occurrence of mounting defects when the semiconductor device is mounted on the mounting board.

[0031] Furthermore, in the planar view, the longitudinal length of the first nearest source pad may be longer than the longitudinal length of each of the 2n first non-nearest source pads, and the longitudinal length of the second nearest source pad may be longer than the longitudinal length of each of the 2n second non-nearest source pads.

[0032] As a result, in the semiconductor device having the above configuration, in a planar view of the semiconductor device, the first nearest source pad, which is the largest first source pad among the 2n+1 first source pads, and the second nearest source pad, which is the largest second source pad among the 2n+1 second source pads, are arranged nearest to the fourth line segment, which has the highest current density, in the current path of the current flowing between the first vertical MOS transistor and the second vertical MOS transistor.

[0033] Therefore, according to the semiconductor device having the above configuration, it is possible to reduce the conduction resistance of the current path of the current flowing between the 2n+1 first source pads and the 2n+1 second source pads.

[0034] Furthermore, in the planar view, the nearest distance between the two first nearest source pads, whose longitudinal axis of symmetry coincides with the first nearest equally spaced line in each of the n first nearest equally spaced lines in the planar view, and the nearest distance between the two second nearest source pads, whose longitudinal axis of symmetry coincides with the second nearest equally spaced line in each of the n second nearest equally spaced lines in the planar view, may be smaller than the diameter of the first gate pad and the diameter of the second gate pad.

[0035] This makes it possible to suppress a reduction in the area occupancy rate of the 2n first non-nearest source pads due to two first non-nearest source pads being arranged with a gap between them on each first non-nearest equally spaced line in a plan view of the semiconductor device, and a reduction in the area occupancy rate of the 2n second non-nearest source pads due to two second non-nearest source pads being arranged with a gap between them on each second non-nearest equally spaced line.

[0036] Furthermore, in the planar view, the midpoint of an imaginary line segment connecting the nearest points on the peripheries of the two first nearest source pads, whose longitudinal axis of symmetry in each of the n first non-nearest equally spaced lines coincides with the first non-nearest equally spaced line in the planar view, the midpoint of an imaginary line segment connecting the nearest points on the peripheries of the two second nearest source pads, whose longitudinal axis of symmetry in each of the n second non-nearest equally spaced lines coincides with the second non-nearest equally spaced line in the planar view, the center of the first nearest source pad, and the center of the second nearest source pad may be located on a straight line extending in the first direction.

[0037] Furthermore, in the plan view, among the two first non-nearest source pads whose axis of symmetry extending in the longitudinal direction coincides with the first non-nearest equally spaced line in each of the n first non-nearest equally spaced lines in the plan view, the closest distance between the first non-nearest source pad closer to the first side and the first side is shorter than the closest distance between the first nearest source pad and the first side, and among the two first non-nearest source pads whose axis of symmetry extending in the longitudinal direction coincides with the first non-nearest equally spaced line in each of the n first non-nearest equally spaced lines in the plan view, the closest distance between the first non-nearest source pad closer to the second side and the second side is shorter than the closest distance between the first nearest source pad and the second side. and among the two second non-nearest source pads, whose axes of symmetry extending in the longitudinal direction on each of the n second non-nearest equally spaced lines coincide with the second non-nearest equally spaced lines in the plan view, the closest distance between the second non-nearest source pad closer to the first side and the first side may be shorter than the closest distance between the second nearest source pad and the first side; and among the two second non-nearest source pads, whose axes of symmetry extending in the longitudinal direction on each of the n second non-nearest equally spaced lines coincide with the second non-nearest equally spaced lines in the plan view, the closest distance between the second non-nearest source pad closer to the second side and the second side may be shorter than the closest distance between the second nearest source pad and the second side.

[0038] This makes it possible to suppress a decrease in the area occupancy rate of the 2n first non-closest source pads and a decrease in the area occupancy rate of the 2n second non-closest source pads.

[0039] Furthermore, in the plan view, of the two first non-nearest source pads whose axis of symmetry extending in the longitudinal direction coincides with the first non-nearest equally spaced line in each of the n first non-nearest equally spaced lines in the plan view, the distance between the center of the first non-nearest source pad closer to the first side and the first side is longer than the closest distance between the first nearest source pad and the first side, and the distance between the center of the first non-nearest source pad closer to the second side and the second side is longer than the closest distance between the first nearest source pad and the second side. and a distance between the center of the second non-nearest source pad closer to the first side and the first side among the two second non-nearest source pads, whose axis of symmetry extending in the longitudinal direction coincides with the second non-nearest equally spaced line in the plan view, on each of the n second non-nearest equally spaced lines, is longer than a closest distance between the second nearest source pad and the first side, and a distance between the center of the second non-nearest source pad closer to the second side and the second side among the two second non-nearest source pads, whose axis of symmetry extending in the longitudinal direction coincides with the second non-nearest equally spaced line in the plan view, on each of the n second non-nearest equally spaced lines, is longer than a closest distance between the second nearest source pad and the second side.

[0040] Furthermore, in the planar view, the closest distance between the first nearest source pad and the fourth line segment may be shorter than the closest distance in the first direction between two first source pads adjacent to each other in the first direction among the 2n+1 first source pads, and the closest distance between the second nearest source pad and the fourth line segment may be shorter than the closest distance in the first direction between two second source pads adjacent to each other in the first direction among the 2n+1 second source pads.

[0041] Furthermore, when viewed in the plane, if a first length of the semiconductor layer in the first direction is Lx, a second length of the semiconductor layer in the second direction is Ly, and a diameter of the first gate pad and the second gate pad is d, then Ly≦14×d, Lx≦Ly+2×d may be satisfied.

[0042] This allows the semiconductor device to have a rectangular shape that is relatively close to a square in plan view, which reduces the degree of warping that occurs in the semiconductor device in a high-temperature environment.

[0043] Therefore, with the semiconductor device having the above configuration, it is possible to suppress the occurrence of mounting defects when the semiconductor device is mounted on a mounting board.

[0044] Alternatively, n may be 3, and in the planar view, the widths of the 2n+1 first source pads and the 2n+1 second source pads may be smaller than the diameters of the first gate pad and the second gate pad.

[0045] Specific examples of semiconductor devices according to an embodiment of the present disclosure will be described below with reference to the drawings. Each embodiment shown here illustrates a specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangement and connection of the components, steps (processes), and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations are omitted or simplified.

[0046] (Embodiment) A semiconductor device according to an embodiment will be described below. This semiconductor device is a chip-size package type semiconductor device that includes two vertical MOS (Metal Oxide Semiconductor) transistors and can be mounted face-down.

[0047] 1 is a plan view showing an example of the structure of a semiconductor device 1 according to an embodiment. As shown in Fig. 1 , the semiconductor device 1 is a rectangle in plan view having a first side 71 and a second side 72 that are equal in length and extend in a first direction (X-axis direction in Fig. 1 ), and a third side 73 and a fourth side 74 that are equal in length and extend in a second direction (Y-axis direction in Fig. 1 ) perpendicular to the first direction, the third side 73 and the fourth side 74 having lengths shorter than the lengths of the first side 71 and the second side 72.

[0048] In FIG. 1, the outer periphery of a portion 13 (described later) of the first source electrode 11 (not shown in FIG. 1, but described later) in a planar view of the semiconductor device 1 and the outer periphery of a portion 23 (described later) of the second source electrode 21 (not shown in FIG. 1, but described later) in a planar view of the semiconductor device 1 are shown by dashed lines as if they could be seen, but in reality they cannot be seen directly from outside the semiconductor device 1.

[0049] FIG. 2 is a cross-sectional view showing an example of the structure of the semiconductor device 1, taken along the line II-II in FIG.

[0050] FIG. 3 is a circuit diagram of the semiconductor device 1.

[0051] As shown in FIGS. 1 to 3, the semiconductor device 1 includes a semiconductor layer 40, a metal layer 30, an interlayer insulating layer 34, a passivation layer 35, a first vertical MOS transistor 10 formed in a first region A1 of the semiconductor layer 40, and a second vertical MOS transistor 20 formed in a second region A2 of the semiconductor layer 40 adjacent to the first region A1 in a plan view of the semiconductor device 1.

[0052] Here, in a planar view of the semiconductor device 1, the first region A1 and the second region A2 are one and the other of two halves that divide the semiconductor layer 40 in terms of area, and the third side 73 is included in the periphery of the first region A1, and the fourth side 74 is included in the periphery of the second region A2.

[0053] In a planar view of the semiconductor device 1, the boundary line 90 between the first region A1 and the second region A2 is crank-shaped, with a first line segment 91 and a second line segment 92 extending in a straight line in the first direction, and a third line segment 93, a fourth line segment 94, and a fifth line segment 95 extending in a straight line in the second direction, connected in the order of the entire length of the third line segment 93, the entire length of the first line segment 91, the entire length of the fourth line segment 94, the entire length of the second line segment 92, and the entire length of the fifth line segment 95 from one end 61 of the boundary line 90 to the other end 62 of the boundary line 90, and varying monotonically in the first and second directions from one end 61 of the boundary line 90 to the other end 62 of the boundary line 90.

[0054] In this specification, a crank-shaped boundary line means that the boundary line has a shape in which line segments extending in a straight line in a first direction and line segments extending in a straight line in a second direction are alternately connected so as to change monotonically in the first direction and the second direction.

[0055] In addition, in this specification, "monotonically changing" means a monotonically increasing function in a broad sense, or a monotonically decreasing function in a broad sense. That is, a monotonically increasing function in a broad sense refers to a function f(x) such that f(x1)≦f(x2) when x1<x2, and a monotonically decreasing function in a broad sense refers to a function f(x) such that f(x1)≧f(x2) when x1<x2.

[0056] Here, in a planar view of the semiconductor device 1, (1) the length of the first line segment 91 is equal to the length of the second line segment 92, (2) the length of the third line segment 93 is equal to the length of the fifth line segment 95, (3) one end 61 is located on the first side 71, (4) the other end 62 is located on the second side 72, and (5) the fourth line segment 94 is located on the imaginary center line 80 of the semiconductor layer 40 that bisects the semiconductor layer 40 in terms of area, and extends in a straight line in the second direction, in a planar view of the semiconductor device 1.

[0057] The semiconductor device 1 also includes 2n (n is an integer of 1 or more, n is 3 in FIG. 1)+1 first source pads 111 (corresponding to the first source pads 111a to 111g in FIG. 1. Hereinafter, when it is not necessary to explicitly distinguish between the individual pads, the first source pads 111a to 111g will also be simply referred to as "first source pads 111") of the first vertical MOS transistor 10, which are formed at positions included in the first region A1 in a plan view of the semiconductor device 1. The semiconductor device 1 includes a first gate pad 119, 2n+1 second source pads 121 (corresponding to the second source pads 121a to 121g in FIG. 1 ; hereinafter, when it is not necessary to explicitly distinguish between the individual pads, the second source pads 121a to 121g will also be simply referred to as the “second source pads 121”) of the second vertical MOS transistor 20, which are formed at positions included in the second region A2 in a plan view of the semiconductor device 1, and a second gate pad 129 of the second vertical MOS transistor 20.

[0058] In a plan view of the semiconductor device 1, (1) the first gate pad 119 is circular, (2) the center of the first gate pad 119 is located on the center line 80, (3) there are no other pads between the first gate pad 119 and the second side 72, (4) the second gate pad 129 is circular and has the same diameter as the first gate pad 119, (5) the center of the second gate pad 129 is located on the center line 80, and (6) there are no other pads between the second gate pad 129 and the first side 71.

[0059] In a plan view of the semiconductor device 1, (1) the 2n+1 first source pads 111 and the 2n+1 second source pads 121 are oval with the second direction as the longitudinal direction, (2) the 2n+1 first source pads 111 and the 2n+1 second source pads 121 have the same width in the lateral direction, and (3) the 2n+1 first source pads 111 are divided into a first nearest source pad 111a closest to the fourth line segment 94 and 2n first non-nearest source pads 111b to 111g not closest to the fourth line segment 94 (hereinafter, when it is not necessary to explicitly distinguish between the individual pads, they will be referred to as the first non-nearest source pads 111b to 111g). (4) the 2n+1 second source pads 121 consist of a second nearest source pad 121a that is nearest to the fourth line segment 94, and 2n second nearest source pads 121b to 121g that are not nearest to the fourth line segment 94 (hereinafter, when it is not necessary to explicitly distinguish between the individual pads, the second nearest source pads 121b to 121g will also be simply referred to as the "second nearest source pads 121bg").

[0060] Here, in a plan view of the semiconductor device 1, (1) the first nearest source pad 111a is arranged such that a line symmetry axis extending in the longitudinal direction coincides with the first nearest equally spaced line 81a that is closest to the fourth line segment 94 among the n+1 imaginary first equally spaced lines 81a to 81d that extend in the second direction in the first region A1 and are equally spaced in the first direction, and (2) the 2n first non-neighbor source pads 111bg are arranged such that a line symmetry axis extending in the longitudinal direction coincides with the first nearest equally spaced line 81a that is closest to the fourth line segment 94 among the n+1 imaginary first equally spaced lines 81a to 81d that are equally spaced in the first direction, and Among the first equally spaced lines 81d, the n first non-nearest equally spaced lines 81b to 81d excluding the first nearest equally spaced line 81a (hereinafter, when it is not necessary to explicitly distinguish between the individual lines, the first non-nearest equally spaced lines 81b to 81d will also be simply referred to as the "first non-nearest equally spaced line 81bd") are arranged such that the axis of symmetry extending in the longitudinal direction of the two first non-nearest equally spaced source pads 111bg coincides with the first non-nearest equally spaced line 81bd. That is, the first source pads 111 are arranged side by side in a striped pattern in a plan view of the semiconductor device 1.

[0061] In addition, in a plan view of the semiconductor device 1, (1) the second nearest source pad 121a is arranged such that the axis of symmetry extending in the longitudinal direction coincides with the second nearest equally spaced line 82a, which is closest to the fourth line segment 94, among the n+1 imaginary second equally spaced lines 82a to 82d extending in the second direction in the second region A2 and the n+1 imaginary second equally spaced lines 82a to 82d arranged at equal intervals in the first direction; and (2) the 2n second non-nearest source pads 121bg are arranged such that the axis of symmetry extending in the longitudinal direction coincides with the second nearest equally spaced line 82a, which is closest to the fourth line segment 94, among the n+1 imaginary second equally spaced lines 82a to 82d arranged at equal intervals in the first direction. Among the second equally spaced lines 82d, the n second non-nearest equally spaced lines 82b to 82d excluding the second nearest equally spaced line 82a (hereinafter, when it is not necessary to explicitly distinguish between the individual lines, the second non-nearest equally spaced lines 82b to 82d will also be simply referred to as the "second non-nearest equally spaced line 82bd") are arranged such that the axis of symmetry extending in the longitudinal direction of the two second non-nearest equally spaced source pads 121bg coincides with the second non-nearest equally spaced line 82bd. That is, the second source pads 121 are arranged in a striped pattern in a plan view of the semiconductor device 1.

[0062] Here, in a planar view of the semiconductor device 1, (1) the longitudinal length of the first nearest source pad 111a may be longer than the longitudinal length of each of the 2n first non-nearest source pads 111bg, and (2) the longitudinal length of the second nearest source pad 121a may be longer than the longitudinal length of each of the 2n second non-nearest source pads 121bg.

[0063] As a result, in a planar view of the semiconductor device 1, the first nearest source pad 111a, which is the largest first source pad 111 of the 2n+1 first source pads 111, and the second nearest source pad 121a, which is the largest second source pad 121 of the 2n+1 second source pads 121, are arranged closest to the fourth line segment 94, which has the highest current density, in the current path of the current flowing between the first vertical MOS transistor 10 and the second vertical MOS transistor 20.

[0064] Therefore, the conduction resistance of the current path of the current flowing between the 2n+1 first source pads 111 and the 2n+1 second source pads 121 can be reduced.

[0065] In addition, in a plan view of the semiconductor device 1, the 2n+1 first source pads 111 and the 2n+1 second source pads 121 are symmetrical with respect to the center line 80 as the axis of symmetry.

[0066] As shown in FIG. 1 , in a plan view of the semiconductor device 1, the nearest distance between two first nearest source pads 111bg, whose longitudinal axis of symmetry coincides with the first nearest equally spaced line 81bd in each of the n first nearest equally spaced lines 81bd in the plan view of the semiconductor device 1, and the nearest distance between two second nearest source pads 121bg, whose longitudinal axis of symmetry coincides with the second nearest equally spaced line 82bd in each of the n second nearest equally spaced lines 82bd in the plan view of the semiconductor device 1, may be smaller than the diameter of the first gate pad 119 and the diameter of the second gate pad 129.

[0067] This makes it possible to suppress, in a planar view of the semiconductor device 1, a reduction in the area occupancy rate of the 2n first non-nearest source pads 111bg caused by arranging two first non-nearest source pads 111bg with a gap between them on each first non-nearest equally spaced line 81bd, and a reduction in the area occupancy rate of the 2n second non-nearest source pads 121bg caused by arranging two second non-nearest source pads 121bg with a gap between them on each second non-nearest equally spaced line 82bd.

[0068] Furthermore, as shown in FIG. 1 , in a plan view of the semiconductor device 1, the midpoint of an imaginary line segment connecting the nearest points on the peripheries of two first non-nearest-neighbor source pads 111bg, whose longitudinally extending axis of symmetry coincides with the first non-nearest-neighbor equally spaced line 81bd in each of the n first non-nearest-neighbor equally spaced lines 81bd in the plan view of the semiconductor device 1, the midpoint of an imaginary line segment connecting the nearest points on the peripheries of two second non-nearest-neighbor source pads 121bg, whose longitudinally extending axis of symmetry coincides with the second non-nearest-neighbor equally spaced line 82bd in each of the n second non-nearest-neighbor equally spaced lines 82bd in the plan view of the semiconductor device 1, the center 111a1 of the first nearest source pad 111a, and the center 121a1 of the second nearest source pad 121a may be located on a straight line extending in the first direction.

[0069] 1, in the plan view of the semiconductor device 1, (1) in each of the n first non-nearest equally spaced lines 81bd, of the two first non-nearest source pads 111bg whose longitudinal symmetry axes coincide with the first non-nearest equally spaced lines 81bd in the plan view of the semiconductor device 1, the closest distance between the first non-nearest source pad 111bg closer to the first side 71 and the first side 71 is (2) of the two first non-nearest source pads 111bg whose longitudinal symmetry axes coincide with the first non-nearest equally spaced lines 81bd in the plan view of the semiconductor device 1, the closest distance between the first non-nearest source pad 111bg closer to the second side 72 and the second side 72 is shorter than the closest distance between the first nearest source pad 111a and the second side 72. (3) of the two second non-nearest source pads 121bg whose longitudinal symmetry axes coincide with the second non-nearest equally spaced lines 82bd in the plan view of the semiconductor device 1, the closest distance between the second non-nearest source pad 121bg closer to the first side 71 and the first side 71 is shorter than the closest distance between the second nearest source pad 121a and the first side 71 (4) for each of the n second non-nearest equidistant lines 82bd, of the two second non-nearest source pads 121bg whose longitudinal symmetry axis coincides with the second non-nearest equidistant line 82bd in a planar view of the semiconductor device 1, the closest distance between the second non-nearest source pad 121bg closer to the second side 72 and the second side 72 may be shorter than the closest distance between the second nearest source pad 121a and the second side 72.

[0070] This makes it possible to suppress a decrease in the area occupancy rate of the 2n first non-closest source pads 111bg and a decrease in the area occupancy rate of the 2n second non-closest source pads 121bg.

[0071] The reason why, on each first non-nearest equally spaced line 81bd, two first non-nearest source pads 111bg are arranged, instead of one, whose longitudinal axis of symmetry coincides with the first non-nearest equally spaced line 81bd in a planar view of the semiconductor device 1, and the reason why, on each second non-nearest equally spaced line 82bd, two second non-nearest source pads 121bg are arranged, instead of one, whose longitudinal axis of symmetry coincides with the second non-nearest equally spaced line 82bd in a planar view of the semiconductor device 1, is that the longer the longitudinal length of each of the first non-nearest source pads 111bg and second non-nearest source pads 121bg, the higher the frequency of mounting defects.

[0072] Furthermore, in each of the first non-nearest equally spaced lines 81bd, the position in the second direction of the midpoint of an imaginary line segment connecting the nearest points on the periphery of two first non-nearest source pads 111bg, whose axis of symmetry extending in the longitudinal direction coincides with the first non-nearest equally spaced line 81bd in the plan view of the semiconductor device 1, and in each of the second non-nearest equally spaced lines 82bd, the position in the second direction of the midpoint of an imaginary line segment connecting the nearest points on the periphery of two second non-nearest source pads, whose axis of symmetry extending in the longitudinal direction coincides with the second non-nearest equally spaced line 82bd in the plan view of the semiconductor device 1 The reason why the position in the second direction of the midpoint of the imaginary line segment connecting the nearest points on the periphery of 121bg is made to coincide with the position in the second direction of the center 111a1 of the first nearest source pad 111a and the position in the second direction of the center 121a1 of the second nearest source pad 121a is that by doing so, the first non-nearest source pad 111bg and the second non-nearest source pad 121bg can be formed up to the vicinity of the first side 71 or the second side 72.

[0073] 1, in the plan view of the semiconductor device 1, (1) in each of the n first non-nearest equally spaced lines 81bd, of the two first non-nearest source pads 111bg whose longitudinal symmetry axes coincide with the first non-nearest equally spaced lines 81bd in the plan view of the semiconductor device 1, the distance between the center of the first non-nearest source pad 111bg closer to the first side 71 (corresponding to the center 111c1, the center 111e1, or the center 111g1 in FIG. 1) and the first side 71 is (2) of the two first non-nearest source pads 111bg whose longitudinal symmetry axes coincide with the first non-nearest equally spaced lines 81bd in the plan view of the semiconductor device 1, the distance between the center of the first non-nearest source pad 111bg closer to the second side 72 (corresponding to the center 111b1, the center 111d1, or the center 111f1 in FIG. 1 ) and the second side 72 is longer than the distance between the first nearest source pad 111a and the second side 72. (3) of the two second non-nearest source pads 121bg whose longitudinally extending axis of symmetry coincides with the second non-nearest equally spaced line 82bd in the plan view of the semiconductor device 1, the distance between the center of the second non-nearest source pad 121bg closer to the first side 71 (corresponding to the center 121c1, the center 121e1, or the center 121g1 in FIG. 1 ) and the first side 71 is longer than the nearest distance between the second nearest source pad 121a and the first side 71 (4) Among the two second non-nearest source pads 121bg whose longitudinal axis of symmetry coincides with the second non-nearest equally spaced line 82bd in a planar view of the semiconductor device 1 in each of the n second non-nearest equally spaced lines 82bd, the distance between the center of the second non-nearest source pad 121bg closer to the second side 72 (corresponding to center 121b1, center 121d1, or center 121f1 in Figure 1) and the second side 72 may be longer than the closest distance between the second nearest source pad 121a and the second side 72.

[0074] Furthermore, as shown in FIG. 1 , in a plan view of the semiconductor device 1, (1) the closest distance between the first closest source pad 111a and the fourth line segment 94 may be shorter than the closest distance in the first direction between two first source pads 111 adjacent to each other in the first direction among the 2n+1 first source pads 111, and (2) the closest distance between the second closest source pad 121a and the fourth line segment 94 may be shorter than the closest distance in the first direction between two second source pads 121 adjacent to each other in the first direction among the 2n+1 second source pads 121.

[0075] Furthermore, in a planar view of the semiconductor device 1, if a first length of the semiconductor layer 40 in a first direction is Lx, a second length of the semiconductor layer 40 in a second direction is Ly, and the diameter of the first gate pad 119 and the second gate pad 129 is d, then the following may be established: Ly≦14×d Lx≦Ly+2×d

[0076] As a result, the shape of the semiconductor device 1 becomes a rectangle that is relatively close to a square in a plan view of the semiconductor device 1. Therefore, the degree of warping that occurs in the semiconductor device 1 in a high-temperature environment becomes relatively small.

[0077] Therefore, according to the semiconductor device 1 having the above configuration, it is possible to suppress the occurrence of mounting defects when the semiconductor device 1 is mounted on a mounting board.

[0078] In this case, when d is 0.20 mm, typical shapes of the semiconductor device 1 are, for example, a shape in which Ly is 2.0 mm and Lx is 2.0 mm to 2.4 mm, or a shape in which Ly is 2.5 mm and Lx is 2.5 mm to 2.9 mm.

[0079] In this case, when d is 0.25 mm, typical shapes of the semiconductor device 1 are, for example, a shape in which Ly is 2.0 mm and Lx is 2.0 mm to 2.5 mm, a shape in which Ly is 2.5 mm and Lx is 2.5 mm to 3.0 mm, or a shape in which Ly is 3.0 mm and Lx is 3.0 mm to 3.5 mm.

[0080] The reason why Ly is set to be 14×d or less is that experiments, simulations, etc. previously conducted by the inventors have demonstrated that the occurrence of mounting defects can be suppressed if the longitudinal lengths of first nearest source pad 111a and second nearest source pad 121a are up to eight times the diameters of first gate pad 119 and second gate pad 129, and also because the closest distance in the second direction between first gate pad 119 and second side 72, the shortest distance in the second direction between first gate pad 119 and first nearest source pad 111a, the closest distance in the second direction between second gate pad 129 and first side 71, and the shortest distance in the second direction between second gate pad 129 and second nearest source pad 121a are viewed in terms of the diameters of first gate pad 119 and second gate pad 129, respectively.

[0081] Furthermore, the reason why Lx is set to be equal to or less than Ly+2d is that experiments, simulations, etc. previously conducted by the inventors have demonstrated that, as long as Lx is at most two diameters longer than Ly, the degree of warpage that occurs in semiconductor device 1 will be within a range that does not seriously affect the occurrence of mounting defects.

[0082] Also, as shown in FIG. 1 , n is 3, and in a plan view of the semiconductor device 1, the widths of the 2n+1 first source pads 111 and the 2n+1 second source pads 121 may be smaller than the diameters of the first gate pad 119 and the second gate pad 129.

[0083] However, n does not have to be limited to 3 as long as it is an integer of 2 or greater, and may be, for example, 2 or an integer of 4 or greater.

[0084] FIG. 4 is a plan view showing an example of the structure of the semiconductor device 1 when n is 2.

[0085] Returning to FIGS. 1 to 3, the structure of the semiconductor device 1 will be further described.

[0086] The semiconductor layer 40 is configured by stacking a semiconductor substrate 32 and a low-concentration impurity layer 33 .

[0087] The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40 and is made of silicon of a first conductivity type containing impurities at a first concentration.

[0088] The low-concentration impurity layer 33 is disposed on the front surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and is made of silicon of the first conductivity type containing impurities at a second concentration lower than the first concentration. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0089] Generally, there are two types of conductivity types for semiconductors: P type and N type. The first conductivity type may be P type or N type. Here, the first conductivity type is N type and the second conductivity type described below is P type. However, the first conductivity type may be P type and the second conductivity type may be N type.

[0090] In the first region A1 of the low-concentration impurity layer 33, a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in a range from the upper surface of the semiconductor layer 40 to a first predetermined depth.

[0091] A first source region 14 of the first conductivity type containing impurities is formed in the first body region 18 in a range from the upper surface of the semiconductor layer 40 to a second predetermined depth that does not penetrate the first body region 18.

[0092] In addition, in the first region A1 of the low-concentration impurity layer 33, a plurality of gate trenches 17 are formed extending in the second direction within a range from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a third predetermined depth to a part of the low-concentration impurity layer 33.

[0093] Inside each of the plurality of gate trenches 17, a first gate conductor 15 is formed, which is surrounded by a first gate insulating film 16 and extends in the second direction.

[0094] The first gate conductor 15 is electrically connected to a first gate electrode 19 .

[0095] First gate conductor 15 may be, by way of non-limiting example, impurity-doped polysilicon.

[0096] In the second region A2 of the low-concentration impurity layer 33, a second body region 28 containing impurities of the second conductivity type is formed in a range from the upper surface of the semiconductor layer 40 to a first predetermined depth.

[0097] A second source region 24 of the first conductivity type containing impurities is formed in the second body region 28 in a range from the upper surface of the semiconductor layer 40 to a second predetermined depth that does not penetrate the second body region 28.

[0098] In addition, in the second region A2 of the low-concentration impurity layer 33, a plurality of gate trenches 27 are formed extending in the second direction within a range from the upper surface of the semiconductor layer 40 through the second source region 24 and the second body region 28 to a third predetermined depth to a part of the low-concentration impurity layer 33.

[0099] A second gate conductor 25 is formed inside each of the gate trenches 27 and extends in a second direction and is surrounded by a second gate insulating film 26 .

[0100] The second gate conductor 25 is electrically connected to a second gate electrode 29 .

[0101] The second gate conductor 25 may be, by way of non-limiting example, impurity-doped polysilicon.

[0102] With the above-described configurations of the first vertical MOS transistor 10 and the second vertical MOS transistor 20, the semiconductor substrate 32 functions as a common drain region in which the first drain region of the first vertical MOS transistor 10 and the second drain region of the second vertical MOS transistor 20 are shared.

[0103] The metal layer 30 is formed in contact with the rear surface of the semiconductor layer 40, and is made of, for example but not limited to, silver or copper. Note that the metal layer 30 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the semiconductor device 1.

[0104] The interlayer insulating layer 34 is disposed on the upper surface of the semiconductor layer 40 and is formed in contact with the low concentration impurity layer 33 .

[0105] The passivation layer 35 is a protective film that covers the upper surface of the first vertical MOS transistor 10 and the upper surface of the second vertical MOS transistor 20, and has 2n+1 openings that expose each of the 2n+1 first source pads 111 to the outside of the semiconductor device 1, an opening that exposes the first gate pad 119 to the outside of the semiconductor device 1, 2n+1 openings that expose each of the 2n+1 second source pads 121 to the outside of the semiconductor device 1, and an opening that exposes the second gate pad 129 to the outside of the semiconductor device 1.

[0106] Here, "covering the top surfaces of the first vertical MOS transistor 10 and the second vertical MOS transistor 20 with the passivation layer 35" means that the passivation layer 35 is formed on almost the entire surface of the semiconductor device 1, excluding the openings, in a plan view of the semiconductor device 1. Here, "almost the entire surface of the semiconductor device 1" refers to the entire surface of the semiconductor device 1, excluding a small peripheral region remaining on each side of the semiconductor device 1 after dicing, among the wafer regions reserved as dicing margins when dicing the semiconductor device 1 from the wafer. Therefore, in this peripheral region, the interlayer insulating layer 34 is exceptionally exposed on the top surface of the semiconductor device 1.

[0107] Furthermore, the opening in the passivation layer 35 in the present disclosure refers to a shape in which the entire periphery of the opening is closed by the passivation layer 35 in a plan view of the semiconductor device 1. For this reason, a shape in which a part of the periphery in a plan view of the semiconductor device 1 overlaps with the exceptional peripheral region where the interlayer insulating layer 34 is exposed on the top surface of the semiconductor device 1 does not correspond to the opening in the passivation layer 35 in the present disclosure.

[0108] The semiconductor device 1 also includes, at positions included in a first region A1 in a plan view of the semiconductor device 1, a first source electrode 11 functioning as a source electrode of the first vertical MOS transistor 10, and a first gate electrode 19 (not shown in FIG. 2 ) functioning as a gate electrode of the first vertical MOS transistor 10, and at positions included in a second region A2 in a plan view of the semiconductor device 1, a second source electrode 21 functioning as a source electrode of the second vertical MOS transistor 20, and a second gate electrode 29 (not shown in FIG. 2 ) functioning as a gate electrode of the second vertical MOS transistor 20.

[0109] The first source electrode 11 is composed of a portion 12 and a portion 13 , and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13 .

[0110] The portion 12 is a layer that is joined with solder during reflow soldering in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 12 may be plated with gold or the like.

[0111] Portion 13 of first source electrode 11 is a layer that connects portion 12 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0112] The surface of portion 12 is exposed to the surface of semiconductor device 1 through the opening in passivation layer 35. The surface of portion 12 exposed to the surface of semiconductor device 1 through the opening in passivation layer 35 serves as a first source pad 111.

[0113] That is, the first source pad 111 is a portion of the surface of the first source electrode 11 that is exposed to the surface of the semiconductor device 1 through the opening in the passivation layer 35 .

[0114] The first gate electrode 19 may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0115] The surface of the first gate electrode 19 is exposed to the surface of the semiconductor device 1 through the opening in the passivation layer 35. The surface of the first gate electrode 19 exposed to the surface of the semiconductor device 1 through the opening in the passivation layer 35 serves as a first gate pad 119.

[0116] That is, the first gate pad 119 is a portion of the first gate electrode 19 that is exposed to the surface of the semiconductor device 1 through the opening in the passivation layer 35 .

[0117] The second source electrode 21 is composed of a portion 22 and a portion 23 , and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23 .

[0118] Portion 22 is a layer that is joined with solder during reflow soldering in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of portion 22 may be plated with gold or the like.

[0119] Portion 23 of second source electrode 21 is a layer that connects portion 22 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0120] The surface of portion 22 is exposed to the surface of semiconductor device 1 through the opening in passivation layer 35. The surface of portion 22 exposed to the surface of semiconductor device 1 through the opening in passivation layer 35 serves as a second source pad 121.

[0121] That is, the second source pad 121 is a portion of the surface of the second source electrode 21 that is exposed to the surface of the semiconductor device 1 through the opening in the passivation layer 35 .

[0122] The second gate electrode 29 may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver.

[0123] The surface of the second gate electrode 29 is exposed to the surface of the semiconductor device 1 through the opening in the passivation layer 35. The surface of the second gate electrode 29 exposed to the surface of the semiconductor device 1 through the opening in the passivation layer 35 serves as a second gate pad 129.

[0124] That is, the second gate pad 129 is the portion of the second gate electrode 29 that is exposed to the surface of the semiconductor device 1 through the opening in the passivation layer 35 .

[0125] <Operation of Semiconductor Device> Hereinafter, the operation of the semiconductor device 1 having the above configuration will be described.

[0126] In the semiconductor device 1, current flows from either the first source pad 111 or the second source pad 121 as an inlet, through the common drain region and the metal layer 30, and from either the first source pad 111 or the second source pad 121 as an outlet.

[0127] Here, the path through which current flows from the first source pad 111 as an inlet to the second source pad 121 as an outlet is referred to as the first current path, and the path through which current flows from the second source pad 121 as an inlet to the first source pad 111 as an outlet is referred to as the second current path.

[0128] The first current path and the second current path will be described below with reference to FIGS. 5A and 5B.

[0129] FIG. 5A is a cross-sectional view schematically showing how a current flows through a first current path.

[0130] The first current path is formed as follows.

[0131] First, in the semiconductor device 1, a voltage higher than that applied to the second source electrode 21 is applied to the first source electrode 11.

[0132] Next, a voltage equal to or higher than the threshold voltage of the second vertical MOS transistor 20 is applied to the second gate electrode 29 with the voltage of the second source electrode 21 as a reference.

[0133] As a result, a conductive channel is formed in the second body region 28 near the second gate insulating film 26 .

[0134] This forms a first current path through which current flows in the following order: first source electrode 11, first body region 18, low-concentration impurity layer 33, semiconductor substrate 32, metal layer 30, semiconductor substrate 32, low-concentration impurity layer 33, conduction channel formed in second body region 28, second source region 24, and second source electrode 21.

[0135] At this time, although the amount of current is relatively small, the current also flows through a path that bypasses the metal layer 30 by flowing through the semiconductor substrate 32 from the first region A1 to the second region A2 without passing through the metal layer 30, and also flows through a path that bypasses the semiconductor substrate 32 and the metal layer 30 by flowing through the low-concentration impurity layer 33 from the first region A1 to the second region A2 without passing through the semiconductor substrate 32 and the metal layer 30.

[0136] Therefore, in the following description, these paths are also included in the first current path.

[0137] Here, it has been described that the path through which a current flows in the forward direction through the PN junction (body diode) at the contact surface between the first body region 18 and the low-concentration impurity layer 33 in the first vertical MOS transistor 10 constitutes the first current path.

[0138] On the other hand, when a voltage equal to or higher than the threshold voltage of the first vertical MOS transistor 10 is applied to the first gate electrode 19 to form a conduction channel in the first body region 18 near the first gate insulating film 16, the path through which a current passes through this conduction channel also constitutes the first current path.

[0139] When a current flows through this conduction channel, the current flows in the first current path in the following order: first source electrode 11, first source region 14, the conduction channel formed in first body region 18, low-concentration impurity layer 33, semiconductor substrate 32, metal layer 30, semiconductor substrate 32, low-concentration impurity layer 33, the conduction channel formed in second body region 28, second source region 24, and second source electrode 21.

[0140] FIG. 5B is a cross-sectional view that schematically shows how a current flows through the second current path.

[0141] The second current path is formed as follows.

[0142] First, in the semiconductor device 1 , a voltage higher than that applied to the first source electrode 11 is applied to the second source electrode 21 .

[0143] Next, a voltage equal to or higher than the threshold voltage of the first vertical MOS transistor 10 is applied to the first gate electrode 19 with the voltage of the first source electrode 11 as a reference.

[0144] As a result, a conductive channel is formed in the first body region 18 near the first gate insulating film 16 .

[0145] This forms a second current path through which current flows in the following order: second source electrode 21, second body region 28, low-concentration impurity layer 33, semiconductor substrate 32, metal layer 30, semiconductor substrate 32, low-concentration impurity layer 33, conduction channel formed in first body region 18, first source region 14, and first source electrode 11.

[0146] At this time, although the amount of current is relatively small, the current also flows through a path that bypasses the metal layer 30 by flowing through the semiconductor substrate 32 from the second region A2 to the first region A1 without passing through the metal layer 30, and also flows through a path that bypasses the semiconductor substrate 32 and the metal layer 30 by flowing through the low-concentration impurity layer 33 from the second region A2 to the first region A1 without passing through the semiconductor substrate 32 and the metal layer 30.

[0147] Therefore, in the following description, these paths are also included in the second current path.

[0148] Here, it has been explained that the path through which a current flows in the forward direction through the PN junction (body diode) at the contact surface between the second body region 28 and the low-concentration impurity layer 33 in the second vertical MOS transistor 20 constitutes the second current path.

[0149] On the other hand, when a voltage equal to or higher than the threshold voltage of the second vertical MOS transistor 20 is applied to the second gate electrode 29 to form a conduction channel in the second body region 28 near the second gate insulating film 26, the path through which a current passes through this conduction channel also constitutes the second current path.

[0150] When a current flows through this conduction channel, the current flows in the second current path in the following order: second source electrode 21, second source region 24, conduction channel formed in second body region 28, low-concentration impurity layer 33, semiconductor substrate 32, metal layer 30, semiconductor substrate 32, low-concentration impurity layer 33, conduction channel formed in first body region 18, first source region 14, and first source electrode 11.

[0151] <Mounting Example of Semiconductor Device> The semiconductor device 1 configured as described above is mounted face down on a mounting board, for example, and is used as a switching element that switches a current path on the mounting board between a conductive state and a non-conductive state.

[0152] FIG. 6 is a circuit diagram of a charge / discharge circuit 5, which is an example of a circuit used as a switching element when the semiconductor device 1 is mounted face down on a mounting board.

[0153] As shown in FIG. 6 , the charge / discharge circuit 5 includes a semiconductor device 1 , a control IC 2 , a storage battery 3 , and a load 4 .

[0154] The charge / discharge circuit 5 is a circuit that realizes discharging from the storage battery 3 to the load 4 and charging from the load 4 to the storage battery 3 by using the semiconductor device 1 as a switching element.

[0155] The control IC 2 is connected to the semiconductor device 1 and controls the voltage of the first gate electrode 19 and the voltage of the second gate electrode 29 to control the discharge operation from the storage battery 3 to the load 4 and the charge operation from the load 4 to the storage battery 3.

[0156] The semiconductor device 1 is switched to one of the following states: (1) a first state in which the first current path is conductive, (2) a second state in which the second current path is conductive, or (3) a third state in which the first current path and the second current path are non-conductive, by the control IC 2 controlling the voltage of the first gate electrode 19 and the voltage of the second gate electrode 29. In the first state, it is also necessary that the voltage of the first source electrode 11 is higher than the voltage of the second source electrode 21, and in the second state, the voltage of the second source electrode 21 is higher than the voltage of the first source electrode 11.

[0157] That is, in the charge / discharge circuit 5, the semiconductor device 1 functions as a switching element that switches between (1) a conductive state of the charge / discharge circuit 5 in which the current path through which current flows from the storage battery 3 to the load 4 or the current path through which current flows from the load 4 to the storage battery 3 is conductive, depending on the difference in voltage between the first source electrode 11 and the second source electrode 21, and (2) a non-conductive state of the charge / discharge circuit 5 in which both the current path through which current flows from the storage battery 3 to the load 4 and the current path through which current flows from the load 4 to the storage battery 3 are non-conductive, by controlling the voltage of the first gate electrode 19 and the voltage of the second gate electrode 29 by the control IC 2.

[0158] 7 is an enlarged plan view of the portion of the mounting substrate 6 on which the semiconductor device 1 is mounted in a face-down manner in the charge / discharge circuit 5, on which the semiconductor device 1 is mounted. FIG. 8 is a schematic diagram showing how, when the semiconductor device 1 is mounted face-down on the mounting substrate 6, the orientation of the semiconductor device 1 is turned upside down so that the surface of the semiconductor device 1 faces the surface of the mounting substrate 6, that is, how the semiconductor device 1 is rotated 180 degrees around an axis perpendicular to the Z axis (in FIG. 8, the X axis is used as the rotation axis) so that the direction of the Z axis shown in FIG. 1 is reversed.

[0159] In Figure 7, the dashed lines show the outer shape of the semiconductor device 1, which is not actually mounted, and the boundary line 90 of the semiconductor device 1, as if the semiconductor device 1 were mounted on the mounting substrate 6.

[0160] 7 and 8, FET1 denotes the first vertical MOS transistor 10, and FET2 denotes the second vertical MOS transistor 20. In FIG.

[0161] As shown in FIG. 7 , the mounting substrate 6 includes a wiring pattern 51, a wiring pattern 52a, a wiring pattern 52b, a wiring pattern 53, 2n+1 first mounting source pads 511 (corresponding to the first mounting source pads 511a to 511g in FIG. 7 ), a first mounting gate pad 519, 2n+1 second mounting source pads 521 (corresponding to the second mounting source pads 521a to 521g in FIG. 7 ), a second mounting gate pad 529, and a clearance 54.

[0162] The wiring pattern 51 is a wiring pattern formed on the upper surface of the mounting substrate 6 and is electrically connected to the storage battery 3 .

[0163] The wiring pattern 53 is a wiring pattern formed on the upper surface of the mounting substrate 6 and is electrically connected to the load 4 .

[0164] The wiring pattern 52 a is a wiring pattern formed on the upper surface of the mounting substrate 6 and is electrically connected to the control IC 2 .

[0165] The wiring pattern 52 b is a wiring pattern formed on the upper surface of the mounting substrate 6 and is electrically connected to the control IC 2 .

[0166] The clearance 54 is a region that electrically and physically separates the wiring pattern 51 and the wiring pattern 53 .

[0167] The first mounting source pads 511a to 511g are pads formed on the upper surface of the wiring pattern 51 and electrically and physically connected to the wiring pattern 51, and are pads for bonding to the first source pads 111a to 111g, respectively, via a bonding material such as solder when the semiconductor device 1 is mounted face-down on the mounting substrate 6.

[0168] The first mounting gate pad 519 is a pad formed on the upper surface of the wiring pattern 52a and electrically and physically connected to the wiring pattern 52a, and is a pad for bonding to the first gate pad 119 via a bonding material such as solder when the semiconductor device 1 is mounted face-down on the mounting substrate 6.

[0169] The second mounting source pads 521a to 521g are pads formed on the upper surface of the wiring pattern 53 and electrically and physically connected to the wiring pattern 53, and are pads for bonding to the second source pads 121a to 121g, respectively, via a bonding material such as solder when the semiconductor device 1 is mounted face-down on the mounting substrate 6.

[0170] The second mounting gate pad 529 is a pad formed on the upper surface of the wiring pattern 52b and electrically and physically connected to the wiring pattern 52b, and is a pad for bonding to the second gate pad 129 via a bonding material such as solder when the semiconductor device 1 is mounted face-down on the mounting substrate 6.

[0171] As shown in FIG. 7, the semiconductor device 1 is mounted face down on the mounting substrate 6 in a plan view at a position bridging the wiring patterns 51 and 53 that face each other with a clearance 54 therebetween.

[0172] More specifically, the semiconductor device 1 is mounted face-down on the mounting substrate 6 so that the first source pads 111a to 111g are bonded to the first mounting source pads 511a to 511g, respectively, via a bonding material such as solder, the first gate pad 119 and the first mounting gate pad 519 are bonded to the first mounting source pads 521a to 521g, respectively, via a bonding material such as solder, the second source pads 121a to 121g are bonded to the second mounting source pads 521a to 521g, respectively, via a bonding material such as solder, and the second gate pad 129 and the second mounting gate pad 529 are bonded to the second mounting gate pad 529 via a bonding material such as solder.

[0173] As described above, in a plan view of the semiconductor device 1, the center of the first gate pad 119 is located on the center line 80, and no other pads are sandwiched between the first gate pad 119 and the second side 72. Therefore, in a plan view of the semiconductor device 1, the first gate pad 119 can be moved as close as possible to the second side 72, at the center position of the second side 72 in the first direction, as determined by the design rules.

[0174] Furthermore, as described above, in a plan view of the semiconductor device 1, the center of the second gate pad 129 is located on the center line 80, and no other pads are sandwiched between the second gate pad 129 and the first side 71. Therefore, in a plan view of the semiconductor device 1, the second gate pad 129 can be moved as close as possible to the first side 71 in terms of the design rules at the center position of the first side 71 in the first direction of the semiconductor device 1.

[0175] Therefore, as shown in FIG. 7 , in a plan view of the mounting substrate 6, the first mounting gate pad 519 joined to the first gate pad 119, the wiring pattern 52a connected to the first mounting gate pad 519, the second mounting gate pad 529 joined to the second gate pad 129, and the wiring pattern 52b connected to the second mounting gate pad 529 can be arranged at appropriate positions that do not disturb the flow of current in the discharging current path along which current flows from the wiring pattern 51 to the wiring pattern 53 when discharging from the storage battery 3 to the load 4, and in the charging current path along which current flows from the wiring pattern 53 to the wiring pattern 51 when charging from the load 4 to the storage battery 3.

[0176] <Discussion> In the semiconductor device 1 having the above configuration, when viewed in a plane, the longitudinal direction of the semiconductor device 1 and the longitudinal directions of the 2n+1 first source pads 111 and the 2n+1 second source pads 121 are perpendicular to each other.

[0177] Therefore, when viewed in a plan view of the semiconductor device 1, the area occupancy rate of the 2n+1 first source pads 111 and the area occupancy rate of the 2n+1 second source pads 121 can be made larger than in a configuration in which the longitudinal direction of the semiconductor device 1 coincides with the longitudinal directions of the 2n+1 first source pads 111 and the 2n+1 second source pads 121.

[0178] Therefore, with the semiconductor device 1 having the above configuration, the conduction resistance of the current path of the current flowing between the 2n+1 first source pads 111 and the 2n+1 second source pads 121 can be reduced more than in a configuration in which, when viewed in a plane, the longitudinal direction of the semiconductor device 1 coincides with the longitudinal directions of the 2n+1 first source pads 111 and the 2n+1 second source pads 121.

[0179] Furthermore, in the semiconductor device 1 having the above-described configuration, in a planar view of the semiconductor device 1, the first nearest source pad 111a, which is the largest first source pad 111 of the 2n+1 first source pads 111, and the second nearest source pad 121a, which is the largest second source pad 121 of the 2n+1 second source pads 121, are arranged nearest to the fourth line segment 94, which has the highest current density, in the current path of the current flowing between the first vertical MOS transistor 10 and the second vertical MOS transistor 20.

[0180] Therefore, according to the semiconductor device 1 having the above configuration, the conduction resistance of the current path of the current flowing between the 2n+1 first source pads 111 and the 2n+1 second source pads 121 can be reduced.

[0181] Furthermore, the semiconductor device 1 having the above-described configuration includes the metal layer 30, which generally has a lower resistivity than the semiconductor layer 40 and which forms part of the current path of the current flowing between the first vertical MOS transistor 10 and the second vertical MOS transistor 20.

[0182] Therefore, according to the semiconductor device 1 having the above configuration, the conduction resistance of the current path of the current flowing between the 2n+1 first source pads 111 and the 2n+1 second source pads 121 can be reduced.

[0183] Furthermore, with the semiconductor device 1 having the above configuration, in a planar view of the semiconductor device 1, the first gate pad 119 can be moved closer to the second side 72 at the center position of the semiconductor device 1 in the first direction on the second side 72, to a position closest to the second side 72 in accordance with the design rules, and further, the second gate pad 129 can be moved closer to the first side 71 at the center position of the semiconductor device 1 in the first direction on the first side 71, to a position closest to the first side 71 in accordance with the design rules.

[0184] This prevents the first gate pad 119 and the second gate pad 129 from interfering with the current path of the current flowing between the 2n+1 first source pads 111 and the 2n+1 second source pads 121.

[0185] Therefore, according to the semiconductor device 1 having the above configuration, the conduction resistance of the current path of the current flowing between the 2n+1 first source pads 111 and the 2n+1 second source pads 121 can be reduced.

[0186] Furthermore, according to the semiconductor device 1 having the above configuration, when viewed in a plane, two first non-nearest source pads 111bg are arranged on each first non-nearest equally spaced line 81bd, and two second non-nearest source pads 121bg are arranged on each second non-nearest equally spaced line 82bd.

[0187] Therefore, with the semiconductor device 1 having the above configuration, it is possible to suppress the occurrence of mounting defects caused by warpage of the semiconductor device more effectively than with a configuration in which one first non-nearest source pad 111bg is arranged on each of the first non-nearest equally spaced lines 81bd and one second non-nearest source pad 121bg is arranged on each of the second non-nearest equally spaced lines 82bd. This is because the shorter the longitudinal length of each of the first non-nearest source pads 111bg, the lower the frequency of mounting defects, and because the shorter the longitudinal length of each of the second non-nearest source pads 121bg, the lower the frequency of mounting defects.

[0188] Thus, the semiconductor device 1 having the above configuration has characteristics suitable for reducing the conduction resistance of the current path in the mounting substrate 6 on which it is mounted, and is capable of suppressing the occurrence of mounting defects when mounted on the mounting substrate 6.

[0189] (Supplementary Note) While the semiconductor device according to one aspect of the present disclosure has been described above based on the embodiment, the present disclosure is not limited to the embodiment. Various modifications conceivable by a person skilled in the art may also be included within the scope of one or more aspects of the present disclosure, as long as they do not deviate from the spirit of the present disclosure.

[0190] The present disclosure is widely applicable to semiconductor devices and the like that are mounted on a mounting substrate.

[0191] REFERENCE SIGNS LIST 1 semiconductor device 2 control IC 3 storage battery 4 load 5 charge / discharge circuit 6 mounting substrate 10 first vertical MOS transistor 11 first source electrode 12, 13, 22, 23 portion 14 first source region 15 first gate conductor 16 first gate insulating film 17, 27 gate trench 18 first body region 19 first gate electrode 20 second vertical MOS transistor 21 second source electrode 24 second source region 25 second gate conductor 26 second gate insulating film 28 second body region 29 second gate electrode 30 metal layer 32 semiconductor substrate 33 low-concentration impurity layer 34 interlayer insulating layer 35 passivation layer 40 semiconductor layer 51, 52a, 52b, 53 wiring pattern 54 clearance 61 one end 62 other end 71 First side 72 Second side 73 Third side 74 Fourth side 80 Center line 81a First equidistant line, first nearest equidistant line 81b, 81c, 81d First equidistant line, first non-nearest equidistant line 81bd First non-nearest equidistant line 82a Second equidistant line, second nearest equidistant line 82b, 82c, 82d Second equidistant line, second non-nearest equidistant line 82bd Second non-nearest equidistant line 90 Boundary line 91 First line segment 92 Second line segment 93 Third line segment 94 Fourth line segment 95 Fifth line segment 111 First source pad 111a First source pad, first nearest source pad 111b, 111c, 111d, 111e, 111f, 111g first source pad, first non-closest source pad 111bg first non-closest source pad 111a1, 111b1, 111c1, 111d1, 111e1, 111f1, 111g1, 121a1, 121b1, 121c1, 121d1, 121e1, 121f1, f21g1 center 119 first gate pad 121 second source pad 121a second source pad, second closest source pad 121b, 121c, 121d, 121e, 121f, 121g second source pad, second non-closest source pad 121bg second non-closest source pad 129 second gate pad511a, 511b, 511c, 511d, 511e, 511f, 511g First mounting source pad 519 First mounting gate pad 521a, 521b, 521c, 521d, 521e, 521f, 521g Second mounting source pad 529 Second mounting gate pad A1 First region A2 Second region

Claims

1. A chip-size package type semiconductor device capable of face-down mounting, comprising: a semiconductor layer; a metal layer formed in contact with a back surface of the semiconductor layer; a first vertical MOS transistor formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region of the semiconductor layer adjacent to the first region in a plan view of the semiconductor device; 2n (n is an integer of 1 or more)+1 first source pads of the first vertical MOS transistor and a first gate pad of the first vertical MOS transistor formed on an upper surface of the semiconductor device at positions included in the first region in the plan view; 2n+1 second source pads of the second vertical MOS transistor and a second gate pad of the second vertical MOS transistor formed on an upper surface of the semiconductor device at positions included in the second region in the plan view; the semiconductor layer is a rectangle having a first side and a second side that extend in a first direction and have equal lengths, and a third side and a fourth side that extend in a second direction perpendicular to the first direction and have equal lengths, the third side and the fourth side having lengths less than or equal to the lengths of the first side and the second side; the first region and the second region are one side and the other side that divide the semiconductor layer into two equal halves in terms of area; the third side is included in the periphery of the first region, and the fourth side is included in the periphery of the second region; a boundary line between the first region and the second region having a crank shape in which a first line segment and a second line segment extending straight in the first direction and a third line segment, a fourth line segment, and a fifth line segment extending straight in the second direction are connected in this order from one end of the boundary line to the other end of the boundary line, over the entire length of the third line segment, the entire length of the first line segment, the entire length of the fourth line segment, the entire length of the second line segment, and the entire length of the fifth line segment, and which monotonically changes in the first direction and the second direction from the one end to the other end,the first line segment and the second line segment have the same length; the third line segment and the fifth line segment have the same length; the one end is located on the first side and the other end is located on the second side; the fourth line segment is an imaginary center line of the semiconductor layer that bisects the semiconductor layer in terms of area in the plan view and is located on the center line that extends in a straight line in the second direction; the first gate pad is circular, the center of the first gate pad is located on the center line, and no other pads exist between the first gate pad and the second side; the second gate pad is circular with the same diameter as the first gate pad, the center of the second gate pad is located on the center line, and no other pads exist between the second gate pad and the first side; the 2n+1 first source pads and the 2n+1 second source pads are oval shapes with the second direction as a longitudinal direction, and the 2n+1 first source pads and the 2n+1 second source pads have equal widths in the lateral direction; the 2n+1 first source pads consist of a first nearest source pad closest to the fourth line segment and 2n first non-nearest source pads not closest to the fourth line segment; the first nearest source pad is arranged such that an axis of symmetry extending in the longitudinal direction coincides with one of n+1 imaginary first equally spaced lines extending in the second direction in the first region, the first nearest equally spaced line being closest to the fourth line segment among the n+1 first equally spaced lines arranged at equal intervals in the first direction; the 2n first non-nearest neighbor source pads are arranged such that, on each of the n first non-nearest neighbor equally spaced lines among the n+1 first equally spaced lines excluding the first nearest equally spaced line, a line symmetry axis extending in the longitudinal direction of two of the 2n first non-nearest neighbor source pads coincides with the first non-nearest neighbor equally spaced line, and the 2n+1 second source pads comprise a second nearest neighbor source pad closest to the fourth line segment and 2n second non-nearest neighbor source pads that are not closest to the fourth line segment,the second nearest source pad is arranged such that an axis of symmetry extending in the longitudinal direction coincides with a second nearest equally spaced line among n+1 imaginary second equally spaced lines extending in the second direction in the second region and arranged equally spaced in the first direction, the second nearest equally spaced line being closest to the fourth line segment; the 2n second non-nearest source pads are arranged such that, on each of n non-nearest equally spaced lines among the n+1 second equally spaced lines excluding the second nearest equally spaced line, an axis of symmetry extending in the longitudinal direction of two of the 2n second non-nearest source pads coincides with the second non-nearest equally spaced line; and the 2n+1 first source pads and the 2n+1 second source pads are linearly symmetrical with respect to the center line.

2. The semiconductor device according to claim 1, wherein, in the plan view, the longitudinal length of the first nearest source pad is longer than the longitudinal length of each of the 2n first non-nearest source pads, and the longitudinal length of the second nearest source pad is longer than the longitudinal length of each of the 2n second non-nearest source pads.

3. The semiconductor device according to claim 2, wherein in the plan view, the nearest distance between the two first nearest source pads, whose longitudinal axis of symmetry coincides with the first nearest equally spaced line in each of the n first nearest equally spaced lines in the plan view, and the nearest distance between the two second nearest source pads, whose longitudinal axis of symmetry coincides with the second nearest equally spaced line in each of the n second nearest equally spaced lines in the plan view, are smaller than the diameter of the first gate pad and the diameter of the second gate pad.

4. The semiconductor device according to claim 2, wherein, in the plan view, the midpoint of an imaginary line segment connecting the nearest points on the peripheries of the two first nearest source pads, whose axis of symmetry extending in the longitudinal direction on each of the n first non-nearest equally spaced lines coincides with the first non-nearest equally spaced line in the plan view, the midpoint of an imaginary line segment connecting the nearest points on the peripheries of the two second nearest source pads, whose axis of symmetry extending in the longitudinal direction on each of the n second non-nearest equally spaced lines coincides with the second non-nearest equally spaced line in the plan view, the center of the first nearest source pad, and the center of the second nearest source pad are located on a straight line extending in the first direction.

5. In the plan view, of the two first non-nearest source pads whose longitudinal symmetry axes coincide with the first non-nearest equally spaced lines in each of the n first non-nearest equally spaced lines in the plan view, the closest distance between the first non-nearest source pad closer to the first side and the first side is shorter than the closest distance between the first nearest source pad and the first side; and of the two first non-nearest source pads whose longitudinal symmetry axes coincide with the first non-nearest equally spaced lines in each of the n first non-nearest equally spaced lines in the plan view, the closest distance between the first non-nearest source pad closer to the second side and the second side is shorter than the closest distance between the first nearest source pad and the second side; 5. The semiconductor device according to claim 4, wherein, of the two second non-nearest source pads whose longitudinal axes of symmetry on each of the n second non-nearest equally spaced lines coincide with the second non-nearest equally spaced lines in the plan view, a closest distance between the second non-nearest source pad closer to the first side and the first side is shorter than a closest distance between the second nearest source pad and the first side; and, of the two second non-nearest source pads whose longitudinal axes of symmetry on each of the n second non-nearest equally spaced lines coincide with the second non-nearest equally spaced lines in the plan view, a closest distance between the second non-nearest source pad closer to the second side and the second side is shorter than a closest distance between the second nearest source pad and the second side.

6. In the plan view, of the two first non-nearest source pads whose longitudinal symmetry axes coincide with the first non-nearest equally spaced lines in each of the n first non-nearest equally spaced lines in the plan view, the distance between the center of the first non-nearest source pad closer to the first side and the first side is longer than the closest distance between the first nearest source pad and the first side; and of the two first non-nearest source pads whose longitudinal symmetry axes coincide with the first non-nearest equally spaced lines in the plan view, the distance between the center of the first non-nearest source pad closer to the second side and the second side is longer than the closest distance between the first nearest source pad and the second side; 5. The semiconductor device according to claim 4, wherein, of the two second non-nearest source pads whose longitudinal axis of symmetry on each of the n second non-nearest equally spaced lines coincides with the second non-nearest equally spaced line in the plan view, a distance between a center of the second non-nearest source pad closer to the first side and the first side is longer than a closest distance between the second nearest source pad and the first side; and, of the two second non-nearest source pads whose longitudinal axis of symmetry on each of the n second non-nearest equally spaced lines coincides with the second non-nearest equally spaced line in the plan view, a distance between the center of the second non-nearest source pad closer to the second side and the second side is longer than a closest distance between the second nearest source pad and the second side.

7. The semiconductor device according to claim 4, wherein, in the planar view, the closest distance between the first nearest source pad and the fourth line segment is shorter than the closest distance in the first direction between two first source pads adjacent to each other in the first direction among the 2n+1 first source pads, and the closest distance between the second nearest source pad and the fourth line segment is shorter than the closest distance in the first direction between two second source pads adjacent to each other in the first direction among the 2n+1 second source pads.

8. The semiconductor device according to claim 4, wherein, in the plan view, the following relationships hold: Ly≦14×d Lx≦Ly+2×d, where Lx is a first length of the semiconductor layer in the first direction, Ly is a second length of the semiconductor layer in the second direction, and d is a diameter of the first gate pad and the second gate pad.

9. The semiconductor device according to claim 4, wherein n is 3, and in the planar view, the widths of the 2n+1 first source pads and the 2n+1 second source pads are smaller than the diameters of the first gate pad and the second gate pad.

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