Semiconductor device

Abstract

The present invention constitutes a semiconductor device comprising a second semiconductor element stacked on a first semiconductor element, and a contact electrode. The first semiconductor element and the second semiconductor element each have a semiconductor layer and a gate electrode which are stacked in the same direction as the stacking direction of the first semiconductor element and the second semiconductor element. The contact electrode is connected to an end surface in a direction orthogonal to the stacking direction of the semiconductor layer.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] A gate-all-around field-effect transistor (GAA-FET) using nanosheets is known (see, for example, Patent Document 1). Also, a complementary field-effect transistor (CFET) with a structure in which GAA-FETs are vertically stacked is known (see, for example, Patent Document 2).

[0003] The GAA-FET described in Patent Document 1 uses a semiconductor layer containing nanosheets as a layer of semiconductor channel material having a vertical thickness smaller than its width. The GAA-FET has a structure in which nanosheets are vertically stacked at a predetermined interval. Furthermore, the GAA-FET has a structure in which the periphery of the nanosheet channel is surrounded by a gate electrode in a cross section in the gate width direction. That is, the GAA-FET has a nanosheet whose periphery is covered with a gate electrode in a direction perpendicular to the channel length direction. Furthermore, the CFET described in Patent Document 2 has a structure in which GAA-FETs of different conductivity types are vertically stacked. This CFET has a CMOS (complementary metal oxide semiconductor) logic circuit in which one GAA-FET is formed of a pMOS (p-type metal oxide semiconductor) and the other GAA-FET is formed of an nMOS (n-type metal oxide semiconductor).

[0004] US Patent Application Publication No. 2023 / 0170352 US Patent No. 11,201,153

[0005] However, in the above-mentioned GAA-FET and CFET, as the elements become smaller, it is difficult to reduce the resistance value of the nanosheet semiconductor layer and the contact resistance of the connection between the nanosheet semiconductor layer and the contact electrode.

[0006] In order to solve the above-mentioned problems, the present invention provides a semiconductor device that allows the resistance of the semiconductor layer to be reduced.

[0007] The semiconductor device of the present invention includes a first semiconductor element, a second semiconductor element stacked on the first semiconductor element, and a contact electrode connected to at least one of the first semiconductor element and the second semiconductor element. The first semiconductor element and the second semiconductor element have semiconductor layers and gate electrodes stacked in the same direction as the stacking direction of the first semiconductor element and the second semiconductor element. The contact electrode is connected to an end face of the semiconductor layer in a direction perpendicular to the stacking direction.

[0008] According to the present invention, a semiconductor device capable of reducing the resistance of a semiconductor layer can be provided.

[0009] 1 is a cross-sectional view in the gate length direction of a semiconductor device of a first embodiment. FIG. 2 is an enlarged view of a pMOS semiconductor layer of the semiconductor device shown in FIG. 1. FIG. 3 is an enlarged view of an nMOS semiconductor layer of the semiconductor device shown in FIG. 1. FIG. 4 is a cross-sectional view in the gate length direction of a semiconductor device of a second embodiment. FIG. 5 is an enlarged view of a pMOS semiconductor layer of the semiconductor device shown in FIG. 4. FIG. 5 is an enlarged view of an nMOS semiconductor layer of the semiconductor device shown in FIG. 4. FIG. 6 is a cross-sectional view in the gate length direction of a semiconductor device of a third embodiment. FIG. 7 is a cross-sectional view in the gate length direction of a semiconductor device of a fourth embodiment. FIG. 8 is a diagram of a manufacturing process of a semiconductor device. FIG. 9 is a diagram of a manufacturing process of a semiconductor device. FIG. 10 is a diagram of a manufacturing process of a semiconductor device. FIG. 11 is a diagram of a manufacturing process of a semiconductor device. FIG. 12 is a diagram of a manufacturing process of a semiconductor device. FIG. 13 is a diagram of a manufacturing process of a semiconductor device. FIG. 14 is a diagram of a manufacturing process of a semiconductor device. FIG. 15 is a diagram of a manufacturing process of a semiconductor device. FIG. 1 is a diagram of a manufacturing process for a semiconductor device (1). FIG. 2 is a diagram of a manufacturing process for a semiconductor device (1). FIG. 3 is a diagram of a manufacturing process for a semiconductor device (1). FIG. 4 is a diagram of a manufacturing process for a semiconductor device (1). FIG. 5 is a diagram of a manufacturing process for a semiconductor device (2). FIG. 6 is a diagram of a manufacturing process for a semiconductor device (2). FIG. 7 is a diagram of a manufacturing process for a semiconductor device (2). FIG. 8 is a diagram of a manufacturing process for a semiconductor device (2). FIG. 9 is a diagram of a manufacturing process for a semiconductor device (Modification 1). FIG. 10 is a diagram of a manufacturing process for a semiconductor device (Modification 2).

[0010] Hereinafter, examples of embodiments for carrying out the present invention will be described, but the present invention is not limited to the following examples. The description will be given in the following order: 1. First embodiment of semiconductor device 2. Second embodiment of semiconductor device 3. Third embodiment of semiconductor device 4. Fourth embodiment of semiconductor device 5. Semiconductor device manufacturing method (1) 6. Semiconductor device manufacturing method (2)

[0011] 1. First Embodiment of Semiconductor Device Configuration of Semiconductor Device Specific embodiments of the semiconductor device of the present invention will now be described. FIGS. 1-3 show schematic configuration diagrams of a semiconductor device according to a first embodiment. FIG. 1 is a cross-sectional view of a region including a channel portion of the semiconductor device in the gate length direction. FIG. 2 is an enlarged view of a pMOS semiconductor layer of the semiconductor device shown in FIG. 1. FIG. 3 is an enlarged view of an nMOS semiconductor layer of the semiconductor device shown in FIG. 1. Note that cross-sectional views of the semiconductor device in directions other than the gate length direction are omitted from the planar layout diagram, since a configuration similar to that of a conventionally known CFET (Complementary Field-Effect Transistor) can be applied. In the following description, the drawings only show the configuration of the essential parts of the semiconductor device, and other configurations, such as insulating layers, are omitted.

[0012] The semiconductor device 1 shown in FIG. 1 includes a first semiconductor element, a first conductivity type, e.g., a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) 100 (hereinafter, referred to as pMOS 100). The semiconductor device 1 also includes a second semiconductor element, a second conductivity type, e.g., an n-channel MOSFET 100 (hereinafter, referred to as nMOS 200). The pMOS 100 and nMOS 200 are formed on a substrate 10. The pMOS 100 and nMOS 200 are stacked in a direction perpendicular to the main surface of the substrate 10. In the semiconductor device 1, the pMOS 100 is formed on the substrate 10 side, and the nMOS 200 is formed on the pMOS 100. One of the source and drain terminals of the pMOS 100 and the nMOS 200 is connected to a contact electrode 20. Therefore, the pMOS 100 and the nMOS 200 form an inverter circuit with a complementary metal oxide semiconductor (CMOS) structure, with one of the source and drain terminals connected via the contact electrode 20.

[0013] Furthermore, insulating layers 140 and 240 are formed between the pMOS 100 and the nMOS 200. The insulating layer 140 is formed on top of the layer including the gate electrode 120, which is the top layer of the pMOS 100. The insulating layer 240 is formed below the layer including the gate electrode 220, which is the bottom layer of the nMOS 200. The insulating layer 140 above the pMOS 100 and the insulating layer 240 below the nMOS 200 are stacked together.

[0014] The pMOS 100 is a GAA (Gate All Around)-FET consisting of a first laminate in which a gate electrode 120 (first gate electrode) and a semiconductor layer 110 (first semiconductor layer) are stacked. The nMOS 200 is a GAA-FET consisting of a second laminate in which a gate electrode 220 (second gate electrode) and a semiconductor layer 210 (second semiconductor layer) are stacked. The semiconductor layer 110 and the semiconductor layer 210 are both composed of nanosheet semiconductor layers. The nanosheets that form the semiconductor layers 110 and 120 also include nanowire structures.

[0015] [pMOS] The pMOS 100 has a stacked structure of [gate electrode 120 / semiconductor layer 110 / gate electrode 120 / semiconductor layer 110 / gate electrode 120 / semiconductor layer 110 / gate electrode 120] from the substrate 10 side. The pMOS 100 has a contact electrode 20 and a contact electrode 40 on the side of the first stacked body of the semiconductor layer 110 and the gate electrode 120. As described above, the contact electrode 20 is electrically connected to the nMOS 200 formed on top of the pMOS 100. The contact electrode 40 is not located in the cross section shown in FIG. 1 but is located either in front of or behind this cross section in a direction perpendicular to the channel length direction. For this reason, the location of the contact electrode 40 is indicated by a dashed line in FIG. 1. The contact electrode 40 is electrically connected to the semiconductor layer 110 of the pMOS 100. The contact electrode 40 is connected to the source / drain on the side of the semiconductor layer 110 that is different from the source / drain to which the contact electrode 20 is connected.

[0016] The contact electrodes 20, 40 include a metal layer 21, 41 and a barrier layer 22, 42. The contact electrodes 20, 40 have a thin barrier layer 22, 42 formed around the main metal layer 21, 41. The metal layer 21, 41 contains one or more metal materials selected from the group consisting of W, Co, Ti, Cu, and Al, and alloys of these metals. The barrier layer 22, 42 is formed of one or more materials selected from the group consisting of Ti, TiN, Ta, and TaN.

[0017] The semiconductor layer 110 is directly connected to both the contact electrode 20 and the contact electrode 40. The semiconductor layer 110 is formed of, for example, Si or SiGe. The semiconductor layer 110 is preferably SiGe. The semiconductor layer 110 is preferably SiGe with a Ge ratio of 10 atomic % or more and 80 atomic % or less, and more preferably SiGe with a Ge ratio of 30 atomic % or more and 60 atomic % or less.

[0018] When the semiconductor layer 110 is made of SiGe, it is preferable that the orientation of the semiconductor layer 110 in the channel length direction be a plane parallel to the major surface of the substrate 10, i.e., the Miller indices (plane indices) of the crystal plane of SiGe in the stacking direction of the semiconductor layer 110 be the (110) plane. It is also preferable that the orientation index of SiGe in the channel length direction of the semiconductor layer 110 be the <110> orientation. As a result, it is preferable that the orientation in the channel length direction of the semiconductor layer 110 (hereinafter referred to as the channel orientation) be <110> / (110), which is the <110> orientation in the (110) plane of SiGe.

[0019] By forming the semiconductor layer 110 of the pMOS 100 from SiGe with a (110) plane and a channel orientation of <110>, carrier mobility in the semiconductor layer 110 is improved compared to when Si is used. Furthermore, by forming the semiconductor layer 110 of the pMOS 100 from SiGe, spontaneous stress is likely to be applied to the SiGe during the manufacturing process. Therefore, by using SiGe for the semiconductor layer 110, strain is more likely to occur in the SiGe compared to when Si is used, and carrier mobility is likely to be improved.

[0020] Furthermore, by using SiGe for the semiconductor layer 110, sufficient stress is generated without using a component for applying external stress to the semiconductor layer 110, such as a SiGe epitaxial growth layer (eSiGe). That is, there is no need to form eSiGe for external stress on the side surfaces (both end surfaces in the channel length direction) of the semiconductor layer 110. Therefore, the contact electrodes 20 and 40 can be directly connected to the semiconductor layer 110 without the need for an intervening eSiGe or other material. Because the contact electrodes 20 and 40, which contain metal materials such as Ti and W, can be directly connected to the semiconductor layer 110, significant reductions in interface resistance and contact resistance can be achieved. Therefore, by forming the semiconductor layer 110 from SiGe and setting the channel orientation to <110> / (110), it is possible to improve the carrier mobility, increase the current value, and reduce the threshold voltage Vth in the semiconductor layer 110.

[0021] The entire cross section of the channel region of the semiconductor layer 110 in the gate length direction is surrounded by the gate electrode 120. An inner spacer 130 made of an insulating layer is formed between the gate electrode 120 and the contact electrode 20 and the contact electrode 40. Therefore, the gate electrode 120 is not directly connected to the contact electrode 20 and the contact electrode 40.

[0022] Furthermore, in a cross section of the gate electrode 120 in the gate width direction, a thin high-dielectric-constant material layer 125 is provided around the gate electrode 120. The high-dielectric-constant material layer 125 covers the contact surface between the gate electrode 120 and the semiconductor layer 110. Furthermore, the high-dielectric-constant material layer 125 covers the contact surface between the gate electrode 120 and the inner spacer 130. The high-dielectric-constant material layer 125 is then filled with metal to form the gate electrode 120. The high-dielectric-constant material layer 125 is made of, for example, hafnium dioxide (HfO ２ ), hafnium oxynitride (HfON), or the like.

[0023] [nMOS] The nMOS 200 has a stacked structure of [gate electrode 220 / semiconductor layer 210 / gate electrode 220 / semiconductor layer 210 / gate electrode 220 / semiconductor layer 210 / gate electrode 220] from the substrate 10 side. The nMOS 200 has a contact electrode 20 and a contact electrode 30 on the side of the second stacked body of the semiconductor layer 210 and the gate electrode 220. As described above, the contact electrode 20 is electrically connected to the pMOS 100 formed below the nMOS 200. The contact electrode 30 is electrically connected to the semiconductor layer 210 of the nMOS 200. The contact electrode 30 is connected to the source / drain on the side of the semiconductor layer 210 that is different from the source / drain to which the contact electrode 20 is connected.

[0024] The contact electrode 30 includes a metal layer 31 and a barrier layer 32. The contact electrode 30 has a thin-film barrier layer 32 formed around the main metal layer 31. The metal layer 31 includes one or more metal materials selected from the group consisting of W, Co, Ti, Cu, and Al, and alloys of these metals. The barrier layer 32 is formed of one or more materials selected from the group consisting of Ti, TiN, Ta, and TaN.

[0025] The semiconductor layer 210 is directly connected to both the contact electrode 20 and the contact electrode 30. The semiconductor layer 210 is formed of, for example, Si or SiGe. Preferably, it is Si. When the semiconductor layer 210 is Si, it is preferable that the orientation of the semiconductor layer 210 in the channel length direction is a plane parallel to the major surface of the substrate 10, i.e., the Miller indices (plane indices) of the Si crystal plane in the stacking direction of the semiconductor layer 210 are the (100) plane. It is also preferable that the orientation index of Si in the channel length direction of the semiconductor layer 210 is the <110> orientation. As a result, the channel orientation of the semiconductor layer 210 is preferably <110> / (100), which is the <110> orientation in the (110) plane of Si. By making the semiconductor layer 210 of the nMOS 200 Si (100) plane and setting the channel orientation to <110>, the carrier mobility in the semiconductor layer 210 is improved.

[0026] The entire cross section of the channel region of the semiconductor layer 210 in the gate length direction is surrounded by the gate electrode 220. An inner spacer 230 made of an insulating layer is formed between the gate electrode 220 and the contact electrode 20 and the contact electrode 30. Therefore, the gate electrode 220 is not directly connected to the contact electrode 20 and the contact electrode 30.

[0027] Furthermore, in a cross section of the gate electrode 220 in the gate width direction, a thin film high-dielectric-constant material layer 225 is provided around the gate electrode 220. The high-dielectric-constant material layer 225 covers the contact surface between the gate electrode 220 and the semiconductor layer 210. Furthermore, the high-dielectric-constant material layer 225 covers the contact surface between the gate electrode 220 and the inner spacer 230. Then, the inside of the high-dielectric-constant material layer 225 is filled with metal to form the gate electrode 220.

[0028] [pMOS Semiconductor Layer] Next, Fig. 2 shows an enlarged view of the semiconductor layer 110 of the pMOS 100. Fig. 2 shows only one layer of the semiconductor layer 110 that forms the pMOS 100, and the gate electrode 120 and contact electrodes 20 and 40 that sandwich this semiconductor layer 110. As shown in Fig. 2, the semiconductor layer 110 has a channel region 111, a high-concentration impurity region 112, and a silicide region 113. The channel region 111, the high-concentration impurity region 112, and the silicide region 113 are formed over the entire surface in the gate width direction.

[0029] The channel region 111 is disposed in the center of the semiconductor layer 110. The channel region 111 is formed at least in a region adjacent to the gate electrode 120 and a region in contact with the high-dielectric-constant material layer 125. The channel region 111 is formed from a region in which a low concentration of impurities is diffused into Si or SiGe constituting the semiconductor layer 110, or from Si or SiGe in which no impurities are diffused.

[0030] In the semiconductor layer 110, high-concentration impurity regions 112 are arranged on both sides of the channel region 111 in the channel length direction. The high-concentration impurity regions 112 are arranged in the semiconductor layer 110 between the channel region 111 and the contact electrodes 20, 40. In the high-concentration impurity regions 112, first conductivity type impurities such as B are diffused into Si or SiGe constituting the semiconductor layer 110 at a higher concentration than in the channel region 111.

[0031] The high-concentration impurity regions 112 are disposed in the semiconductor layer 110 between the channel region 111 and the contact electrodes 20, 40, and function as the source and drain of the pMOS 100. That is, in a conventional typical GAA-FET, an epitaxially grown layer is formed on the side surface of the semiconductor layer 110 from the semiconductor layer 110, and this epitaxially grown layer is used as the source and drain. In contrast, in the semiconductor device 1, the high-concentration impurity regions 112 that function as the source and drain are formed in the semiconductor layer 110 stacked on the gate electrode 120 and the inner spacer 130.

[0032] The silicide regions 113 are formed on both ends of the semiconductor layer 110 in the channel length direction. The silicide regions 113 are directly connected to the contact electrodes 20, 40 at both ends of the semiconductor layer 110. The silicide regions 113 are metal silicides of Si or SiGe that constitute the semiconductor layer 110. The silicide regions 113 are formed by silicidation of the high-concentration impurity regions 112 with a metal such as Ti, W, Ta, Co, or Ni. In particular, the silicide regions 113 are preferably silicides of one or more metals selected from Ti, Co, and Ni.

[0033] The high-concentration impurity region 112 is a portion connected to the inverted channel region 111 directly below the gate, and it is preferable to reduce the resistance. For this reason, the high-concentration impurity region 112 must have a high concentration of impurities. However, if the high-concentration impurity region 112 comes into contact with the metal that constitutes the contact electrodes 20 and 40, a Schottky junction is likely to occur, and ohmic contact may not be achieved. For this reason, a low-resistance silicide region 113 is formed in the semiconductor layer 110 between the high-concentration impurity region 112 and the contact electrodes 20 and 40. This makes it possible to reduce the connection resistance between the semiconductor layer 110 and the contact electrodes 20 and 40.

[0034] [nMOS Semiconductor Layer] Next, Fig. 3 shows an enlarged view of the semiconductor layer 210 of the nMOS 200. Fig. 3 shows only one layer of the semiconductor layer 210 that forms the nMOS 200, and the gate electrode 220 and contact electrodes 20 and 30 that sandwich this semiconductor layer 210. As shown in Fig. 3, the semiconductor layer 210 has a channel region 211, a high-concentration impurity region 212, and a silicide region 213. The channel region 211, the high-concentration impurity region 212, and the silicide region 213 are formed over the entire surface in the gate width direction.

[0035] The channel region 211 is disposed in the center of the semiconductor layer 210. The channel region 211 is formed at least in a region adjacent to the gate electrode 220 and a region in contact with the high-dielectric-constant material layer 225. The channel region 211 is formed from a region in which a low concentration of impurities is diffused into Si or SiGe constituting the semiconductor layer 210, or from Si or SiGe in which no impurities are diffused.

[0036] In the semiconductor layer 210, high-concentration impurity regions 212 are arranged on both sides of the channel region 211 in the channel length direction. The high-concentration impurity regions 212 are arranged in the semiconductor layer 210 between the channel region 211 and the contact electrodes 20, 30. In the high-concentration impurity regions 212, impurities of the second conductivity type, such as P, are diffused into Si constituting the semiconductor layer 210 at a higher concentration than in the channel region 211.

[0037] The high-concentration impurity regions 212 are disposed in the semiconductor layer 210 between the channel region 211 and the contact electrodes 20, 30, and function as the source and drain of the nMOS 200. That is, in a conventional typical GAA-FET, an epitaxially grown layer is formed on the side surface of the semiconductor layer 110 from the semiconductor layer 110, and this epitaxially grown layer is used as the source and drain. In contrast, in the semiconductor device 1, the high-concentration impurity regions 212 that function as the source and drain are formed in the semiconductor layer 210 stacked on the gate electrode 220 and the inner spacer 230.

[0038] The silicide regions 213 are formed on both ends of the semiconductor layer 210 in the channel length direction. The silicide regions 213 are directly connected to the contact electrodes 20, 30 at both ends of the semiconductor layer 210. The silicide regions 213 are metal silicides of Si that constitute the semiconductor layer 210. The silicide regions 213 are formed by silicidation of the high-concentration impurity regions 212 with a metal.

[0039] The high-concentration impurity region 212 is a portion connected to the inverted channel region 211 directly below the gate, and it is preferable to reduce the resistance. For this reason, the high-concentration impurity region 212 needs to have a high concentration of impurities. However, if the high-concentration impurity region 212 comes into contact with the metal that constitutes the contact electrodes 20 and 30, a Schottky junction is likely to occur, and ohmic contact may not be achieved. For this reason, a low-resistance silicide region 213 is formed in the semiconductor layer 210 between the high-concentration impurity region 212 and the contact electrodes 20 and 30. This makes it possible to reduce the connection resistance between the semiconductor layer 210 and the contact electrodes 20 and 30.

[0040] [Substrate and Electrodes] Next, the substrate and electrodes of the semiconductor device 1 shown in Figures 1-3 will be described. As shown in Figure 1, a pMOS 100 is formed on the substrate 10 side of the semiconductor device 1. In this case, it is preferable that the surface of the substrate 10 on which the semiconductor device 1 is formed has a crystal plane with Miller indices of (110). By epitaxially growing the semiconductor layer 110 of Si, SiGe, or the like of the pMOS 100 from the substrate 10, the surface of the semiconductor layer 110 parallel to the main surface of the substrate 10 can be formed as a (110) plane.

[0041] The gate electrode 60 is connected to the gate electrodes 120 and 220. A potential (gate current) is supplied to the gate electrodes 120 and 220 via the gate electrode 60. The gate electrode 60 is not disposed in the cross section shown in FIG. 1 , but is disposed either in front of or behind this cross section in a direction perpendicular to the channel length direction. For this reason, the position of the gate electrode 60 is indicated by a dashed line in FIG. 1 . An electrode 51 is also connected to the gate electrode 60. The electrode 51 supplies a potential to the gate electrode 60 and to the gate electrodes 120 and 220 connected to the gate electrode 60.

[0042] An electrode 52 is connected to the contact electrode 30. The electrode 52 supplies a source current or a drain current to the contact electrode 30. An electrode (not shown) that supplies a source current or a drain current is also connected to the contact electrode 20 and the contact electrode 40 indicated by the dashed line in FIG. 1 . The gate electrode 60 may be connected to only one of the gate electrodes 120 and 220 rather than to both. In this case, an electrode other than the gate electrode 60 and the electrode 51 is connected to the other gate electrode 120 or 220 that is not connected to the gate electrode 60. This separates the gate electrode 120 from the gate electrode 220, allowing the pMOS 100 and the nMOS 200 to be driven independently.

[0043] [Bonding Between Semiconductor Layers and Contact Electrodes] Next, the bonding between the semiconductor layers 110 and 210 and the contact electrodes 20, 30, and 40 will be described. The semiconductor layers 110 and 210 are connected to the contact electrodes 20, 30, and 40 at the side surfaces of the pMOS 100 and the nMOS 200. Specifically, the side surfaces of the first stacked body forming the pMOS 100 and the second stacked body forming the nMOS 200 are in contact with the side surfaces of the contact electrodes 20, 30, and 40. The end surfaces of the semiconductor layers 110 and 210 are connected to the contact electrodes 20, 30, and 40 in the channel length direction of the semiconductor layers 110 and 210. That is, the contact electrodes 20, 30, and 40 are connected to the end surfaces in the channel length direction, which are perpendicular to the stacking direction of the semiconductor layers 110 and 210 and the gate electrodes 120 and 220, which are stacked in the same direction as the stacking direction of the pMOS 100 and the nMOS 200.

[0044] Furthermore, the portions of the semiconductor layers 110, 210 that are stacked on the inner spacers 130, 230 are connected to the contact electrodes 20, 30, 40. That is, the semiconductor layers 110, 210 in the regions sandwiched between the inner spacers 130, 230 are connected to the side surfaces of the contact electrodes 20, 30, 40. Therefore, the contact electrodes 20, 30, 40 contact the end faces of the inner spacers 130, 230 in a plane that is perpendicular to the position where they are connected to the semiconductor layers 110, 210 (relative to the main surface of the substrate 10).

[0045] 2. Second Embodiment of Semiconductor Device Next, a second embodiment of the semiconductor device will be described. The semiconductor device of the second embodiment is a configuration in which the configuration of the contact electrodes in the semiconductor device of the first embodiment described above is changed. Furthermore, the semiconductor device of the second embodiment is similar to the semiconductor device of the first embodiment described above, except for the changed configuration of the contact electrodes. Therefore, detailed description of the same configuration as the semiconductor device of the first embodiment described above will be omitted.

[0046] 4-6 show schematic configuration diagrams of a semiconductor device according to the second embodiment. FIG. 4 is a cross-sectional view in the gate length direction of a region including a channel portion of the semiconductor device. FIG. 5 is an enlarged view of a pMOS semiconductor layer of the semiconductor device shown in FIG. 4. FIG. 6 is an enlarged view of an nMOS semiconductor layer of the semiconductor device shown in FIG. 4. As with the semiconductor device according to the first embodiment described above, cross-sectional views of the semiconductor device according to the second embodiment other than those in the gate length direction are omitted because they can be configured similarly to conventionally known CFETs.

[0047] 4 has a structure in which a pMOS 100 and an nMOS 200 are stacked. The semiconductor layers 110, 210, gate electrodes 120, 220, inner spacers 130, 230, etc. relating to the pMOS 100 and nMOS 200 can have the same configuration as the semiconductor device of the first embodiment described above.

[0048] The pMOS 100 includes a contact electrode 20 and a contact electrode 40 on the side surfaces of the second stack of the semiconductor layer 110 and the gate electrode 120. The nMOS 200 includes a contact electrode 20 and a contact electrode 30 on the side surfaces of the second stack of the semiconductor layer 210 and the gate electrode 220.

[0049] The contact electrode 20 is connected to one of the sources and drains of the semiconductor layers 110, 210 of the pMOS 100 and the nMOS 200. One of the sources and drains of the pMOS 100 and the nMOS 200 is connected via the contact electrode 20. In other words, the semiconductor device 2 forms an inverter circuit with a CMOS structure.

[0050] As described above, the contact electrode 20 is electrically connected to the nMOS 200 formed on top of the pMOS 100. The contact electrode 40 is not arranged in the cross section shown in FIG. 4, but is arranged either in front of or behind this cross section in a direction perpendicular to the channel length direction. For this reason, the contact electrode 40 is shown by a dashed line in FIG. 4. The contact electrode 40 is connected to the source / drain on a side of the semiconductor layer 110 of the pMOS 100 that is different from the source / drain to which the contact electrode 20 is connected. The contact electrode 30 is connected to the source / drain on a side of the semiconductor layer 210 of the nMOS 200 that is different from the source / drain to which the contact electrode 20 is connected.

[0051] The contact electrode 20 is composed of metal layers 21 and 23. The contact electrode 30 is composed of metal layers 31 and 33. The contact electrode 40 is composed of metal layers 41 and 43. Hereinafter, the metal layers constituting the contact electrodes 20, 30, and 40 are referred to as the first metal layers 21, 31, and 41 and the second metal layers 23, 33, and 43. The contact electrodes 20, 30, and 40 each have a thin second metal layer 23, 33, or 43 formed around the main first metal layer 21, 31, or 41. The first metal layers 21, 31, and 41 and the second metal layers 23, 33, and 43 are formed of, for example, a metal material such as W, Co, Ti, Cu, or Al, or an alloy material of these metals. Preferably, the second metal layers 23, 33, and 43 contain Ti.

[0052] In the semiconductor device 2 described above, the second metal layers 23, 33, and 43 of the contact electrodes 20, 30, and 40 are directly connected to the semiconductor layers 110 and 210. Therefore, the metal layers of the contact electrodes 20, 30, and 40 are directly connected to the semiconductor layers 110 and 210 without a barrier metal such as TiN. As a result, the semiconductor device 2 can achieve a significant reduction in interface resistance and contact resistance at the connection between the semiconductor layers 110 and 210 and the contact electrodes 20, 30, and 40. In particular, as semiconductor devices such as CFETs become increasingly miniaturized, the relative proportion of barrier metal in the contact electrodes increases, making them prone to high-resistance contacts. Therefore, the semiconductor device 2 configured as described above achieves a significant reduction in contact resistance due to the connection between the metal layers of the contact electrodes 20, 30, and 40 and the semiconductor layers 110 and 210.

[0053] 4 shows an example in which the contact electrodes 20, 30, and 40 are formed of two metal layers, namely, first metal layers 21, 31, and 41 and second metal layers 23, 33, and 43. However, the contact electrodes 20, 30, and 40 may be formed of a single metal layer. The above-described metal materials can also be applied to the case of a single metal layer. Furthermore, when the contact electrodes 20, 30, and 40 are formed of two metal layers, the same metal material may be used for each layer.

[0054] 3. Third Embodiment of Semiconductor Device Next, a third embodiment of the semiconductor device will be described. The semiconductor device of the third embodiment is a configuration in which the shape of the pMOS side in the semiconductor device of the first embodiment described above is changed. Furthermore, the semiconductor device of the third embodiment is similar to the semiconductor device of the first embodiment described above, except for the change in the shape of the pMOS side. Therefore, detailed description of the same configuration as the semiconductor device of the first embodiment described above will be omitted.

[0055] 7 shows a schematic configuration diagram of a semiconductor device according to the third embodiment. This is a cross-sectional view of a region including a channel portion of the semiconductor device in the gate length direction. Similar to the semiconductor device according to the first embodiment, the semiconductor device according to the third embodiment can be configured similarly to a conventionally known CFET in cross-sectional views other than those in the gate length direction, and therefore these cross-sectional views are omitted from the drawings. Furthermore, the enlarged views of the pMOS and nMOS semiconductor layers according to the first embodiment can be configured similarly to the semiconductor device according to the first embodiment, and therefore these cross-sectional views are omitted from the drawings.

[0056] 7 has a structure in which a pMOS 100 and an nMOS 200 are stacked. The semiconductor layers 110, 210, gate electrodes 120, 220, inner spacers 130, 230, etc. relating to the pMOS 100 and nMOS 200 can have the same configuration as the semiconductor device of the first embodiment described above.

[0057] The pMOS 100 and the nMOS 200 are stacked with insulating layers 140 and 240 interposed between them. Hereinafter, the side of the pMOS 100 on which the insulating layer 140 is formed, i.e., the side on which the nMOS 200 is stacked (top of the drawing), will be referred to as the bottom of the pMOS 100, and the opposite side (bottom of the drawing) will be referred to as the top of the pMOS 100. Also, the side of the nMOS 200 on which the insulating layer 240 is formed, i.e., the side on which the pMOS 100 is stacked (bottom of the drawing) will be referred to as the bottom of the nMOS 200, and the opposite side (top of the drawing) will be referred to as the top of the nMOS 200. Furthermore, in the semiconductor device 3, the top of the pMOS 100 will be referred to as the back side of the semiconductor device 3, and the top of the nMOS 200 will be referred to as the front side of the semiconductor device 3.

[0058] The pMOS 100 includes a contact electrode 40 and a contact electrode 80 on the side surfaces of a first stack of a semiconductor layer 110 and a gate electrode 120. The contact electrode 40 and the contact electrode 80 are electrically connected to the semiconductor layer 110 of the pMOS 100. The contact electrode 40 is connected to one of the source and drain of the semiconductor layer 110. The contact electrode 80 is connected to the source and drain on the side of the semiconductor layer 110 that is different from the source and drain to which the contact electrode 40 is connected.

[0059] The nMOS 200 includes a contact electrode 30 and a contact electrode 70 on the side of a second stack of a semiconductor layer 210 and a gate electrode 220. The contact electrode 30 is connected to one of the source and drain of the semiconductor layer 210. The contact electrode 70 is connected to the source and drain on the side of the semiconductor layer 210 that is different from the source and drain to which the contact electrode 30 is connected.

[0060] Insulating layers 142, 242 are formed between the contact electrode 80 and the contact electrode 70. Insulating layers 144, 244 are formed between the contact electrode 40 and the contact electrode 30. Insulating layers 142, 144 are formed on the bottom surfaces of the contact electrodes 40, 80 on the bottom side of the pMOS 100. Insulating layers 242, 244 are formed on the bottom surfaces of the contact electrodes 30, 70 on the bottom side of the nMOS 200.

[0061] 7, the contact electrodes 40 and 80 in contact with the semiconductor layer 110 of the pMOS 100 and the contact electrodes 30 and 70 in contact with the semiconductor layer 210 of the nMOS 200 are not connected. Therefore, in the semiconductor device 3, the pMOS 100 and the nMOS 200 are each an independent single circuit.

[0062] The contact electrode 80 connected to the pMOS 100 has a thin-film barrier layer 82 formed around a main metal layer 81. The contact electrodes 40, 80 contact insulating layers 142, 144 with barrier layers 42, 82 formed on the bottoms thereof. In addition, the contact electrodes 40, 80 have the barrier layers 42, 82 in contact with a first stack formed by stacking the semiconductor layer 110 and the gate electrode 120.

[0063] The pMOS 100 includes a gate electrode 62. The gate electrode 62 is connected to a gate electrode 120. A potential is supplied to the gate electrode 120 via the gate electrode 62. The gate electrode 62 is not located in the cross section shown in FIG. 7, but is located either forward or backward from the cross section in a direction perpendicular to the channel length direction. For this reason, the location of the gate electrode 62 is indicated by a dashed line in FIG. 7. A backside electrode 54 is connected to the gate electrode 62. The backside electrode 54 supplies a potential to the gate electrode 62 and the gate electrode 120 connected to the gate electrode 62. A backside electrode 55 is connected to the contact electrode 40. The backside electrode 55 supplies a source current or a drain current to the contact electrode 40. A backside electrode 56 is connected to the contact electrode 80. The backside electrode 56 supplies a source current or a drain current to the contact electrode 80.

[0064] The contact electrode 70 connected to the nMOS 200 has a thin-film barrier layer 72 formed around a main metal layer 71. The contact electrodes 30, 70 contact insulating layers 242, 244 with barrier layers 32, 72 formed on the bottoms thereof. Furthermore, the barrier layers 32, 72 of the contact electrodes 30, 70 contact a second stacked body in which the semiconductor layer 210 and the gate electrode 220 are stacked.

[0065] The nMOS 200 includes a gate electrode 61. The gate electrode 61 is connected to the gate electrode 220. A potential is supplied to the gate electrode 220 via the gate electrode 61. The gate electrode 61 is not disposed in the cross section shown in Figure 7, but is disposed either in front of or behind this cross section in a direction perpendicular to the channel length direction. For this reason, the position of the gate electrode 61 is indicated by a dashed line in Figure 7.

[0066] Furthermore, a surface-side electrode 57 is connected to the gate electrode 61. The surface-side electrode 57 supplies a potential to the gate electrode 61 and the gate electrode 220 connected to the gate electrode 61. A surface-side electrode 58 is connected to the contact electrode 30. The surface-side electrode 58 supplies a source current or a drain current to the contact electrode 30. A surface-side electrode 59 is connected to the contact electrode 70. The surface-side electrode 59 supplies a source current or a drain current to the contact electrode 70.

[0067] The semiconductor device 3 described above includes front-side electrodes 58 and 59 and back-side electrodes 55 and 56 connected to the contact electrodes 30, 40, 70, and 80 above the pMOS 100 and the nMOS 200, respectively. The semiconductor device 3 also includes a front-side electrode 57 and a back-side electrode 54 connected to the gate electrodes 61 and 62 above the pMOS 100 and the nMOS 200, respectively. Because the semiconductor device 3 is not formed directly on a substrate, electrodes and wiring connected to the contact electrodes 30, 40, 70, and 80 can be formed on both the front and back sides of the semiconductor device 3. Therefore, the back-side electrodes 54, 55, and 56 can be formed above the pMOS 100, and the front-side electrodes 57, 58, and 59 can also be formed above the nMOS 200. The semiconductor device 3 allows contacts to be taken out from at least one of the electrodes on one side (front side) and the other side (back side). Therefore, the semiconductor device 3 has improved flexibility in the wiring and electrodes for power supply, and the area in which the semiconductor device 3 is formed can be reduced.

[0068] In the semiconductor device of the third embodiment, the elements may be turned upside down, reversing the arrangement of the pMOS and nMOS. Furthermore, in the semiconductor device of the third embodiment, the contact electrodes of the semiconductor device of the second embodiment may be applied to some or all of the contact electrodes. Furthermore, in the semiconductor device of the third embodiment, either the insulating layers 142 and 242 or the insulating layers 144 and 244 may be removed, and the contact electrodes 30 and 40 or the contact electrodes 70 and 80 may be connected. In this case, the semiconductor device of the third embodiment forms an inverter circuit with a CMOS structure. Furthermore, the semiconductor device of the third embodiment illustrates an example in which the gate electrodes 62 and 120 and the contact electrodes 40 and 80 of the pMOS 100 are connected to backside electrodes 54, 55, and 56. Furthermore, the semiconductor device of the third embodiment illustrates an example in which the gate electrodes 61 and 220 and the contact electrodes 30 and 70 of the nMOS 200 are connected to backside electrodes 57, 58, and 59. However, in the semiconductor device of the third embodiment, in the pMOS 100 and the nMOS 200, the gate electrodes 61, 62, 120, 220 and contact electrodes 30, 40, 79, 80 may be connected to either the back surface side electrodes 54, 55, 56 or the front surface side electrodes 57, 58, 59. Therefore, for example, the configuration may be such that the gate electrodes 62, 120 and contact electrodes 40, 80 of the pMOS 100 are connected to the front surface side electrodes, or the configuration may be such that the gate electrodes 61, 220 and contact electrodes 30, 70 of the nMOS 200 are connected to the back surface side electrodes.

[0069] 4. Fourth Embodiment of Semiconductor Device Next, a fourth embodiment of the semiconductor device will be described. The semiconductor device of the fourth embodiment is a configuration in which the arrangement of the pMOS and nMOS in the semiconductor device of the first embodiment described above is interchanged. Furthermore, the semiconductor device of the fourth embodiment is similar to the semiconductor device of the first embodiment described above, except for the interchange of the arrangement of the pMOS and nMOS. Therefore, detailed description of the same configuration as the semiconductor device of the first embodiment described above will be omitted.

[0070] FIG. 8 shows a schematic configuration diagram of a semiconductor device according to the fourth embodiment. FIG. 8 is a cross-sectional view of a region including a channel portion of the semiconductor device in the gate length direction. Note that, like the semiconductor device according to the first embodiment, cross-sectional views of the semiconductor device according to the fourth embodiment other than those in the gate length direction are omitted from the drawings because the same configuration as that of a conventionally known CFET can be applied. Also, enlarged views of the semiconductor layers of the pMOS and nMOS according to the first embodiment are omitted from the drawings because the same configuration as that of the semiconductor device according to the first embodiment can be applied.

[0071] The semiconductor device 4 shown in FIG. 8 includes a pMOS 100 and an nMOS 200. The pMOS 100 and the nMOS 200 are formed on a substrate 15. The pMOS 100 and the nMOS 200 are stacked in a direction perpendicular to the main surface of the substrate 15. In the semiconductor device 4, the nMOS 200 is formed on the substrate 15 side, and the pMOS 100 is formed on the nMOS 200. The pMOS 100 and the nMOS 200 have one source / drain of the semiconductor layers 110, 210 connected to a contact electrode 20. The pMOS 100 and the nMOS 200 have one source / drain connected via the contact electrode 20. Therefore, the pMOS 100 and the nMOS 200 form an inverter circuit with a CMOS structure.

[0072] The nMOS 200 includes a contact electrode 20 and a contact electrode 30 on the side of the second stack of the semiconductor layer 210 and the gate electrode 220. The contact electrode 20 is electrically connected to the pMOS 100 formed on top of the nMOS 200. The contact electrode 30 is not disposed in the cross section shown in FIG. 8, but is disposed either in front of or behind this cross section in a direction perpendicular to the channel length direction. For this reason, the contact electrode 30 is indicated by a dashed line in FIG. 8. The contact electrode 30 is electrically connected to the semiconductor layer 210 of the nMOS 200. The contact electrode 30 is connected to the source / drain on the side of the semiconductor layer 210 that is different from the source / drain to which the contact electrode 20 is connected.

[0073] The pMOS 100 has a contact electrode 20 and a contact electrode 40 on the side of the first stack of the semiconductor layer 110 and the gate electrode 120. As described above, the contact electrode 20 is electrically connected to the nMOS 200 formed below the pMOS 100. The contact electrode 40 is electrically connected to the semiconductor layer 110 of the pMOS 100. The contact electrode 40 is connected to the source / drain on a side of the semiconductor layer 110 different from the source / drain to which the contact electrode 20 is connected.

[0074] The gate electrode 60 is connected to the gate electrode 120 and the gate electrode 220. A potential is supplied to the gate electrode 120 and the gate electrode 220 via the gate electrode 60. The gate electrode 60 is not disposed in the cross section shown in FIG. 8, but is disposed either in front of or behind this cross section in a direction perpendicular to the channel length direction. For this reason, the position of the gate electrode 60 is indicated by a dashed line in FIG. 8. An electrode 51 is also connected to the gate electrode 60. The electrode 51 supplies a potential to the gate electrode 60 and to the gate electrodes 120 and 220 connected to the gate electrode 60.

[0075] An electrode 52 is connected to the contact electrode 40. The electrode 52 supplies a source current or a drain current to the contact electrode 40. An electrode (not shown) that supplies a source current or a drain current is also connected to the contact electrode 30 indicated by the dashed line in FIG.

[0076] 8, when an nMOS 200 is formed on the substrate 15 side of the semiconductor device 4, the surface of the substrate 15 on which the semiconductor device 4 is formed preferably has a crystal plane with Miller indices of (100). By epitaxially growing a semiconductor layer 210 of Si, SiGe, or the like of the nMOS 200 from the substrate 15, the surface of the semiconductor layer 210 parallel to the main surface of the substrate 15 can be formed as a (100) plane.

[0077] In the semiconductor device 4 of the fourth embodiment, the conductivity type of the GAA-FET formed on the substrate 15 is opposite to that of the semiconductor device 1 of the first embodiment (FIG. 1). In this way, whether the pMOS 100 or the nMOS 200 is disposed on the substrate side to form the CFET, the same effects as those of the semiconductor device of the first embodiment can be obtained. Note that the semiconductor device of the fourth embodiment may use the contact electrodes of the semiconductor device of the second embodiment described above for some or all of the contact electrodes.

[0078] 5. Semiconductor Device Manufacturing Method (1) Next, a method for manufacturing a semiconductor device will be described. As a method for manufacturing a semiconductor device, the manufacturing process of the semiconductor device of the first embodiment shown in FIG. 1 will be described. FIGS. 9 to 28 show manufacturing process diagrams of a semiconductor device. First, as shown in FIG. 9, semiconductor layers 115 and 110 are formed on a substrate 10. In the example shown in FIG. 9, the semiconductor layers 115 and 110 are alternately stacked on the substrate 10, forming four layers of semiconductor layers 115 and three layers of semiconductor layers 110. Furthermore, as shown in FIG. 9, an insulating layer 140 is formed on the uppermost semiconductor layer 115.

[0079] The semiconductor layer 110 is made of SiGe, and the Ge ratio is, for example, 10 atomic % or more and 80 atomic % or less, preferably 30 atomic % or more and 60 atomic % or less. The semiconductor layer 115 is a sacrificial layer used when forming a gate electrode. For this reason, the semiconductor layer 115 is made of SiGe with a Ge ratio that significantly differs in etching rate from the SiGe that constitutes the semiconductor layer 110. The semiconductor layer 115 is in a range that differs in etching rate from the semiconductor layer 110, and the Ge ratio is preferably 10 atomic % or more and 80 atomic % or less. For example, the Ge ratio of the semiconductor layer 115 is preferably 25 atomic %, and the Ge ratio of the semiconductor layer 110 is preferably 30 atomic % or more and 60 atomic % or less.

[0080] The surface of the substrate 10 on which the semiconductor layer 115 is formed has a plane index of (110). The semiconductor layer 110 and the semiconductor layer 115 are formed by epitaxial growth on the substrate 10. Because the substrate 10 on which the semiconductor layer 115 is formed has a (110) plane, the semiconductor layer 115 formed by epitaxial growth also has a plane index of (110) in the stacking direction. Furthermore, the semiconductor layer 110 formed on the semiconductor layer 115 is also formed by epitaxial growth on the (110) plane of the semiconductor layer 115, so the plane index of the plane in the stacking direction is also (110). The insulating layer 140 is made of, for example, SiO ２ The insulating layer 140 is formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0081] Next, as shown in Fig. 10, semiconductor layers 215 and 210 are formed on a substrate 15 separate from the substrate 10. In the example shown in Fig. 10, the semiconductor layers 215 and 210 are alternately stacked on the substrate 15, forming four layers of semiconductor layers 215 and three layers of semiconductor layers 210. Furthermore, as shown in Fig. 10, an insulating layer 240 is formed on the uppermost semiconductor layer 215.

[0082] The semiconductor layer 210 is preferably made of Si. The semiconductor layer 215 is a sacrificial layer used when forming a gate electrode. Therefore, the semiconductor layer 215 is made of SiGe, and the Ge ratio is preferably, for example, 10 atomic % or more and 80 atomic % or less, and more preferably, 30 atomic % or more and 60 atomic % or less.

[0083] The surface of the substrate 15 on which the semiconductor layer 215 is formed has a plane index of (100). The semiconductor layer 210 and the semiconductor layer 215 are formed by epitaxial growth on the substrate 15. Because the substrate 15 on which the semiconductor layer 215 is formed has a (100) plane, the semiconductor layer 215 formed by epitaxial growth also has a plane index of (100) in the stacking direction. Furthermore, the semiconductor layer 210 formed on the semiconductor layer 215 is also formed by epitaxial growth on the (100) plane of the semiconductor layer 215, so the plane index of the plane in the stacking direction is also (100). The insulating layer 240 is made of, for example, SiO ２ The insulating layer 240 is formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0084] Next, as shown in FIG. 11, the substrate 10, semiconductor layers 110, 115, and insulating layer 140 shown in FIG. 9 are stacked with the substrate 15, semiconductor layers 210, 215, and insulating layer 240 shown in FIG. 10, with the insulating layer 140 and the insulating layer 240 facing each other.

[0085] Next, as shown in FIG. 12 , the substrate 15 is removed, and a stacked body 300 is formed on the substrate 10, and the stacked body 300 is made of the semiconductor layers 110, 115, 210, and 215 and the insulating layers 140 and 240. Then, as shown in FIG. 13 , the semiconductor layers 110, 115, 210, and 215 and the insulating layers 140 and 240 are etched on the substrate 10 to form a patterned stacked body 301. For example, the stacked body 301 is patterned by forming a hard mask or the like having a predetermined pattern on the uppermost semiconductor layer 215, and using this mask, the stacked body 300 ( FIG. 12 ) of the semiconductor layers 110, 115, 210, and 215 and the insulating layers 140 and 240 is etched. For example, reactive ion etching (RIE) is used to etch the stacked body 300.

[0086] 14 , the side surfaces of the semiconductor layers 115 and 215 exposed in the gate length direction are selectively etched to form a stacked body 302 in which the side surfaces of the semiconductor layers 115 and 215 are partially removed. As a result, a recess 131 is formed in the side surface of the semiconductor layer 115 relative to the side surface of the semiconductor layer 110, and a recess 231 is formed in the side surface of the semiconductor layer 215 relative to the side surface of the semiconductor layer 210. The semiconductor layers 115 and 215 are etched using isotropic etching such as atomic layer etching (ALE), quasi-ALE, or selective vapor-phase etching. The semiconductor layers 115 and 215 are etched using a technique that allows selective etching between the SiGe constituting the semiconductor layers 115 and 215 and the Si or SiGe constituting the semiconductor layers 110 and 210. The depth of the recesses 131 and 231 on the side surfaces of the semiconductor layers 115 and 215 is adjusted taking into consideration the thickness of the inner spacers 130 and 230 of the semiconductor device 1 .

[0087] 15, a stacked body 303 is formed in which inner spacers 130, 230 are formed in the recesses 131, 231 on the side surfaces of the semiconductor layers 115, 215. The inner spacers 130, 230 are formed, for example, by forming a SiO ２ An insulating layer is formed, and the insulating layer exposed from the side surfaces of the stack 302 is removed by anisotropic etching such as RIE, thereby leaving the inner spacers 130 and 230 in the recesses 131 and 231 on the side surfaces of the semiconductor layers 115 and 215.

[0088] 16 , a dummy contact electrode 90 is formed on the side surface of the stacked body 303. The dummy contact electrode 90 has a dummy contact layer 91 as a main body and a dummy barrier layer 92 formed as a thin film around the periphery of the dummy contact layer 91. The dummy contact layer 91 is formed of, for example, polysilicon or amorphous silicon. The dummy barrier layer 92 is formed of, for example, polysilicon or amorphous silicon in which n-type impurities have been diffused. The dummy barrier layer 92 is formed at least in a position directly in contact with the stacked body 303. In particular, the dummy barrier layer 92 is formed at least in a region directly in contact with the side surface of the semiconductor layer 110 that constitutes the stacked body 303.

[0089] The dummy contact layer 91 and the dummy barrier layer 92 are formed by, for example, CVD or PVD. First, the dummy barrier layer 92 is formed on a resist layer formed in a pattern with openings corresponding to the positions where the dummy contact electrodes 90 are to be formed. Then, the dummy contact layer 91 is formed on the dummy barrier layer 92 to fill the openings. Furthermore, excess dummy contact layer 91, dummy barrier layer 92, and resist layer are removed, and the dummy contact electrodes 90 are formed.

[0090] 17, the dummy contact electrodes 90 formed above the insulating layer 240 are removed. Preferably, the dummy contact electrodes 90 formed below the interface between the insulating layer 140 and the insulating layer 240 are left, and the dummy contact electrodes 90 above the interface are removed. The dummy contact electrodes 90 are made of, for example, polysilicon or amorphous silicon. Therefore, the removal is performed using, for example, plasma etching, which can selectively etch polysilicon or amorphous silicon.

[0091] 18 , a dummy contact electrode 95 is formed on the dummy contact electrode 90 on the side surface of the stacked body 303. The dummy contact electrode 95 has a dummy contact layer 93 as a main body and a dummy barrier layer 94 formed as a thin film around the periphery of the dummy contact layer 93. The dummy contact layer 93 is made of, for example, polysilicon or amorphous silicon. The dummy barrier layer 94 is made of, for example, polysilicon or amorphous silicon in which p-type impurities are diffused. The dummy barrier layer 94 is formed at least in a position directly in contact with the stacked body 303. In particular, the dummy barrier layer 94 is formed at least in a region directly in contact with the side surface of the semiconductor layer 210 constituting the stacked body 303.

[0092] Next, the semiconductor layers 115 and 215 are removed. The removal of the semiconductor layers 115 and 215 uses an etching method that is selective between the semiconductor layers 115 and 215 and the semiconductor layers 110 and 210, which have different composition ratios. The selective etching may be, for example, dry etching using a mixed gas containing hydrogen fluoride and oxygen, or wet etching using a mixed solution of hydrogen fluoride and hydrogen peroxide. Then, the high-dielectric-constant material layers 125 and 225 are formed over the entire surface of the substrate 10. The high-dielectric-constant material layers 125 and 225 are formed using, for example, atomic layer deposition (ALD). By using ALD or the like, the high-dielectric-constant material layers 125 and 225 can be formed simultaneously. The high-dielectric-constant material layers 125 and 225 formed in areas other than those in contact with the semiconductor layers 110 and 210 are then removed using reactive ion etching or the like. As a result, high-dielectric-constant material layers 125 and 225 are formed between the semiconductor layers 110 and 210 and on the inner walls of the inner spacers 130 and 230 shown in FIG.

[0093] Furthermore, after the formation of the high-dielectric-constant material layers 125 and 225, an annealing treatment is performed. This annealing treatment diffuses the impurities contained in the dummy barrier layer 92 and the dummy barrier layer 94 into the semiconductor layers 110 and 210. Specifically, the n-type impurities contained in the dummy barrier layer 92 diffuse into the semiconductor layer 110, and the impurities diffuse from both ends of the semiconductor layer 110, i.e., from the positions in contact with the dummy barrier layer 92, toward the center of the semiconductor layer 110. As a result, as shown in the enlarged view of the semiconductor layer 110 in FIG. 20 , a channel region 111 is formed in the center of the semiconductor layer 110, and high-concentration impurity regions 112 containing n-type impurities are formed at both ends of the channel region 111. Furthermore, the p-type impurities contained in the dummy barrier layer 94 diffuse into the semiconductor layer 210, and the impurities diffuse from both ends of the semiconductor layer 210, i.e., from the positions in contact with the dummy barrier layer 94, toward the center of the semiconductor layer 210. 21 , a channel region 111 is formed in the center of the semiconductor layer 210, and high-concentration impurity regions 212 containing p-type impurities are formed on both ends of the channel region 211. The range and impurity concentration of the impurities diffused in the semiconductor layers 110 and 210 are adjusted by the annealing conditions (temperature, time, etc.) and the impurity concentrations of the dummy barrier layers 92 and 94.

[0094] Next, as shown in FIG. 22 , a gate electrode 120 is formed on the high-dielectric-constant material layer 125, and a dummy gate 121 is formed on the high-dielectric-constant material layer 225. The gate electrode 120 and the dummy gate 121 are formed of, for example, a metal material such as W, Co, Ti, Cu, or Al, or an alloy material of these metals. The gate electrode 120 and the dummy gate 121 are formed by, for example, CVD. Through this process, the gate electrode 120 is formed between the substrate 10, the semiconductor layer 110, and the insulating layer 140, with the high-dielectric-constant material layer 125 interposed therebetween. Furthermore, a dummy gate 121 is formed between the insulating layer 240 and the semiconductor layer 210, and on the semiconductor layer 210, with the high-dielectric-constant material layer 225 interposed therebetween.

[0095] Next, as shown in FIG. 23 , the dummy gate 121 is removed to expose the high-dielectric-constant material layer 225. Then, as shown in FIG. 24 , a gate electrode 220 is formed on the high-dielectric-constant material layer 225. The gate electrode 220 is formed of, for example, a metal material such as W, Co, Ti, Cu, or Al, or an alloy material of these metals. The gate electrode 220 uses a metal different from the gate electrode 120 described above, which has a work function suitable for the nMOS 200 ( FIG. 1 ). The gate electrode 120 is formed of a metal layer having a work function suitable for the pMOS 100 ( FIG. 1 ), and the gate electrode 220 is formed of the metal layer described above, which has a work function suitable for the nMOS 200. This results in a stacked body 304, in which the semiconductor layers 110 and 210, the gate electrode 120, and the electrode 220 are stacked.

[0096] Next, as shown in FIG. 25 , the dummy contact electrodes 90 and 95 formed on the side surfaces of the stacked body 304 are removed to expose the side surfaces of the stacked body 304. Then, as shown in FIG. 26 , the contact electrodes 20, 30, and 40 and the gate electrode 60 are formed. For example, a resist layer is formed to cover the stacked body 304, and then a pattern is formed in the resist layer to form openings at positions where the contact electrodes 20, 30, and 40 will be formed. Then, thin barrier layers 22, 32, and 42 are formed on the entire surface, including the openings in the resist layer. The barrier layers 22, 32, and 42 are formed by CVD, PVD, or the like using a metal material such as Ti, TiN, Ta, or TaN. Furthermore, metal layers 21, 31, and 41 are formed on the barrier layers 22, 32, and 42 to fill the openings in the resist layers. The metal layers 21, 31, and 41 are formed by CVD, PVD, or the like using a metal material such as W, Co, Ti, Cu, or Al. Thereafter, excess barrier layers 22, 32, 42 and metal layers 21, 31, 41 are removed by CMP (Chemical Mechanical Polishing) or the like to form contact electrodes 20, 30, 40. Furthermore, gate electrode 60 is formed by a similar method.

[0097] Furthermore, after the contact electrodes 20, 30, and 40 are formed, an annealing treatment is performed. As a result, the semiconductor layers 110 and 210 in contact with the barrier layers 22, 32, and 42 are silicided. As shown in the enlarged view of the semiconductor layer 110 in FIG. 27 , metals such as Ti and Ta contained in the barrier layers 22 and 42 react with SiGe constituting the semiconductor layer 110, forming silicide regions 113 at both ends of the semiconductor layer 110, i.e., in the high-concentration impurity regions 112 in contact with the barrier layers 22 and 42. As shown in the enlarged view of the semiconductor layer 210 in FIG. 28 , metals such as Ti and Ta contained in the barrier layers 22 and 32 react with Si constituting the semiconductor layer 210, forming silicide regions 213 at both ends of the semiconductor layer 210, i.e., in the high-concentration impurity regions 212 in contact with the barrier layers 22 and 32.

[0098] The semiconductor device of the first embodiment can be manufactured through the above-described steps. In the manufacturing process of the semiconductor device described above, if the substrate 10 is removed and the substrate 15 remains in the step shown in FIG. 12 , the semiconductor device of the fourth embodiment can be manufactured through the same subsequent steps. Furthermore, if the barrier layers 22 and 32 are not formed when forming the contact electrodes 20, 30, and 40 in the step shown in FIG. 26 , the semiconductor device of the second embodiment can be manufactured. In this case, it is preferable to form a second metal layer of Ti, Ta, or the like instead of the barrier layer and silicidize the semiconductor layers 110 and 210 by performing an annealing treatment. Furthermore, if necessary, the second metal layer used for silicidation can be removed and a first metal layer formed, thereby forming the contact electrodes 20, 30, and 40 as a single metal layer.

[0099] 6. Semiconductor Device Manufacturing Method (2) Next, another method for manufacturing a semiconductor device will be described. As another method for manufacturing a semiconductor device, the manufacturing process of the semiconductor device of the third embodiment shown in FIG. 3 will be described. FIGS. 29 to 36 show manufacturing process diagrams of the semiconductor device. First, the processes shown in FIGS. 9 to 24 are performed, and then, as shown in FIG. 29, dummy contact electrodes 90, 95 and gate electrodes 120, 220 are formed on the side surfaces of the stacked body 304.

[0100] 30 , the dummy contact electrode 95 is removed while leaving the dummy contact electrode 90, thereby exposing the side surfaces of the stack of the semiconductor layer 210 and the gate electrode 220 above the insulating layer 240. Next, as shown in FIG. 31 , insulating layers 242 and 244 are formed on the dummy contact electrode 90. Then, as shown in FIG. 32 , the contact electrodes 30 and 70 are formed on the insulating layers 242 and 244, so as to contact the side surfaces of the stack of the semiconductor layer 210 and the gate electrode 220. The insulating layers 242 and 244 are formed using, for example, the same technique as that for the insulating layers 140 and 240. The contact electrodes 30 and 70 are formed using the same technique as that for the contact electrodes 20, 30, and 40.

[0101] Next, as shown in FIG. 33 , a wiring layer 11 is formed on the laminate 304 and on the contact electrodes 30 and 70, and a support substrate 12 is bonded to the wiring layer 11. This wiring layer 11 is, for example, a multilayer wiring layer made up of a plurality of wiring layers and insulating layers. The wiring layer 11 preferably includes the front-side electrodes 57, 58, 59, etc. of the semiconductor device 3 shown in FIG. 7 described above. The wiring layer 11 shown in FIG. 33 shows two wiring layers and vias connecting these wiring layers as an example of a multilayer wiring layer. The laminate structure and wiring form of the wiring layer 11 are not particularly limited.

[0102] Next, as shown in FIG. 34 , the substrate 10, the stacked body 304, the contact electrodes 30 and 70, the dummy contact electrodes 90, the wiring layer 11, and the support substrate 12 are turned upside down. Then, as shown in FIG. 35 , the substrate 10 is removed. This exposes the bottom side of the stacked body 304 and the bottom side of the dummy contact electrode 90, which were in contact with the substrate 10. Furthermore, as shown in FIG. 36 , the dummy contact electrode 90 is removed, and insulating layers 142 and 144 and contact electrodes 40 and 80 are formed. The insulating layers 142 and 144 and the contact electrodes 40 and 80 are formed using the same techniques as those for the insulating layers 242 and 244 and the contact electrodes 30 and 70. Furthermore, by forming various back-side electrodes 54, 55, and 56 and various wiring layers above the contact electrodes 40 and 80 and the stacked body 304, the semiconductor device of the third embodiment described above can be manufactured.

[0103] The semiconductor device of the third embodiment has a configuration in which the gate electrode 120 and the gate electrode 220 are separated to independently drive the pMOS 100 and the nMOS 200. Note that, in the manufacturing process of the semiconductor device described above, by changing the configuration of the insulating layers 142, 144, 242, 244 and the contact electrodes 30, 40, 70, 80, it is also possible to form an inverter circuit with a CMOS structure in which one of the sources and drains of the pMOS 100 and the nMOS 200 is connected.

[0104] For example, as shown in Fig. 37, the contact electrode 30 and the contact electrode 40 are connected. In this embodiment, in the step shown in Fig. 31, one of the insulating layers 242 formed on the side surface of the stacked body 304 on the dummy contact electrode 90 is not formed. Furthermore, in the step shown in Fig. 36, the contact electrode 40 is formed on the one of the contact electrodes 30 on which the insulating layer 242 is not formed, without forming the insulating layer 142. Also, as shown in Fig. 38, a contact electrode 20 continuous with the pMOS 100 and nMOS 200 is formed on one side surface of the stacked body 304. The contact electrode 20 is formed, for example, by a method similar to that in the step shown in Fig. 26.

[0105] The present invention is not limited to the configurations described in the above-described embodiments, and various modifications and changes are possible without departing from the scope of the present invention.

[0106] 1, 2, 3, 4... Semiconductor device, 10, 15... Substrate, 100... pMOS, 11... Wiring layer, 110, 115, 210, 215... Semiconductor layer, 111, 211... Channel region, 112, 212... High concentration impurity region, 113, 213... Silicide region, 12... Support substrate, 121... Dummy gate, 125, 225... High dielectric constant material layer, 130, 230... Inner spacer, 131, 231... Recess, 20, 30, 40, 70, 80... Contact electrode, 200... nMOS, 21, 31, 41, 71, 81... Metal layers, 22, 32, 42, 72, 82... Barrier layers, 23, 33, 43... Second metal layers, 24, 140, 142, 144, 240, 242, 244... Insulating layers, 300, 301, 302, 303, 304... Laminates, 51, 52... Electrodes, 54, 55, 56... Rear electrodes, 57, 58, 59... Front electrodes, 60, 61, 62, 120, 220... Gate electrodes, 90, 95... Dummy contact electrodes, 91, 93... Dummy contact layers, 92, 94... Dummy barrier layers

Claims

1. A semiconductor device comprising: a first semiconductor element; a second semiconductor element stacked on the first semiconductor element; and a contact electrode connected to at least one of the first semiconductor element and the second semiconductor element, wherein the first semiconductor element and the second semiconductor element have semiconductor layers and gate electrodes stacked in the same direction as the stacking direction of the first semiconductor element and the second semiconductor element, and the contact electrode is connected to an end face of the semiconductor layer in a direction perpendicular to the stacking direction.

2. The semiconductor device according to claim 1, wherein the semiconductor layer has a channel region, high-concentration impurity regions arranged on both sides of the channel region in the channel length direction, and silicide regions arranged on both sides of the high-concentration impurity region in the channel length direction, and the silicide regions are connected to the contact electrode.

3. The semiconductor device according to claim 1, wherein the semiconductor layer is a nanosheet semiconductor layer.

4. The semiconductor device according to claim 2, wherein the silicide region contains one or more metals selected from the group consisting of Ti, Co, and Ni.

5. The semiconductor device according to claim 1, wherein the contact electrode contains one or more metal materials selected from the group consisting of W, Co, Ti, Cu, Al, and alloys of these metals, and the metal materials are in contact with the semiconductor layer.

6. The semiconductor device according to claim 1, wherein the semiconductor layer of the first semiconductor element is formed of Si or SiGe, and the semiconductor layer of the second semiconductor element is formed of Si.

7. The semiconductor device according to claim 1, wherein the semiconductor layer of the first semiconductor element has a plane index (110) in the stacking direction, and the semiconductor layer of the second semiconductor element has a plane index (100) in the stacking direction.

8. The semiconductor device according to claim 1, wherein the semiconductor layer of the first semiconductor element has a <110> / (110) orientation in the channel length direction, and the semiconductor layer of the second semiconductor element has a <110> / (100) orientation in the channel length direction.

9. The semiconductor device according to claim 1, further comprising a front surface electrode formed on one side of the first semiconductor element and the second semiconductor element in the stacking direction and supplying a potential to the gate electrode, and a back surface electrode formed on the other side and supplying a potential to the gate electrode.

10. The semiconductor device according to claim 9, further comprising an insulating layer that insulates the gate electrode of the first semiconductor element from the gate electrode of the second semiconductor element, and wherein the gate electrode of the first semiconductor element and the gate electrode of the second semiconductor element are supplied with a potential from at least one of the front surface electrode and the back surface electrode.

11. The semiconductor device according to claim 1, wherein the contact electrode is connected to both the semiconductor layer of the first semiconductor element and the semiconductor layer of the second semiconductor element.

12. The semiconductor device according to claim 9, wherein the contact electrode connected to the semiconductor layer of the first semiconductor element and the contact electrode connected to the semiconductor layer of the second semiconductor element are insulated, and the contact electrode connected to the semiconductor layer of the first semiconductor element and the contact electrode connected to the semiconductor layer of the second semiconductor element are supplied with a potential from at least one of the front surface side electrode and the back surface side electrode.

13. The semiconductor device according to claim 1, further comprising an inverter circuit formed by the first semiconductor element and the second semiconductor element.

14. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element each form an independent, stand-alone circuit.

15. The semiconductor device according to claim 6, wherein the first semiconductor element is a p-channel type semiconductor element, and the second semiconductor element is an n-channel type semiconductor element.

16. The semiconductor device according to claim 15, comprising a substrate on which the first semiconductor element and the second semiconductor element are formed, the first semiconductor element being on the substrate side, and the second semiconductor element being on the first semiconductor element.

17. The semiconductor device according to claim 15, comprising a substrate on which the first semiconductor element and the second semiconductor element are formed, the second semiconductor element being on the substrate side, and the first semiconductor element being on the second semiconductor element.

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