Semiconductor device and method for producing semiconductor device

Abstract

The purpose of the present invention is to increase the strength of a load on an external connection terminal.　This semiconductor device (1) has a circuit board (30), a case (10), first external connection terminals (12a-12d, 12i, 12j), and a sealing member. The case (10) includes a housing member that forms a rectangular outer shape in plan view and houses the circuit board (30). The lower surface of a first edge facing the outside of the housing member in plan view faces the upper surface of the housed circuit board (30) with a gap therebetween. The first external connection terminals (12a-12d, 12i, 12j) protrude in a direction perpendicular to the upper surface of the first edge, and are held by the first edge. The sealing member seals between the upper surface of the circuit board (30) and the lower surface of the first edge.

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] A semiconductor device has been proposed that has a case with a semiconductor circuit and a component that is configured to be attachable to the case and has signal terminals and wiring, the wiring including a spring portion provided between an upper portion of a lead portion and a contact portion (see, for example, Patent Document 1).

[0003] Also, a semiconductor device has been proposed that includes a plate-shaped first terminal that is arranged opposite the first main surface of the insulating sheet and has a protrusion that protrudes outward from the first main surface, and a plate-shaped second terminal that is arranged corresponding to the second main surface of the insulating sheet and has a protrusion that protrudes outward from the second main surface (see, for example, Patent Document 2).

[0004] In addition, a joint structure has been proposed that includes a substrate having one surface layer that is a conductive layer, and a power terminal that includes a first portion that overlaps the conductive layer when viewed in the thickness direction, and a second portion that extends from the first portion in a direction perpendicular to the thickness direction (see, for example, Patent Document 3).

[0005] In addition, a semiconductor device has been proposed that includes a plurality of pins press-fit into a printed circuit board, a resin block having a plurality of through holes into which the pins are press-fit, and a resin case that covers at least a portion of the front board and the resin block (see, for example, Patent Document 4).

[0006] Also, a semiconductor device has been proposed in which a plurality of signal pin terminals and guide pins are arranged in a row and drawn out from a resin case incorporating a main circuit power element and a control circuit element (see, for example, Patent Document 5).

[0007] Also, a semiconductor device has been proposed that includes a plurality of semiconductor modules in which semiconductor chips are mounted on an insulating circuit board and provided in a case, and external connection terminals that connect to the semiconductor chips or the insulating circuit board protrude from the case (see, for example, Patent Document 6).

[0008] Also, a semiconductor device has been proposed that includes a semiconductor element, a mounting portion on the upper surface of which the semiconductor element is mounted, and a plurality of terminal portions arranged above the mounting portion and spaced apart in parallel, with a bent portion at one end (see, for example, Patent Document 7).

[0009] Japanese Patent Application Laid-Open No. 2023-135187 Japanese Patent Application Laid-Open No. 2023-88055 Japanese Patent Application Laid-Open No. 2022-189515 Japanese Patent Application Laid-Open No. 2018-107395 Registered Utility Model No. 3025083 Japanese Patent Application Laid-Open No. 2014-236150 International Publication No. 2020 / 148879

[0010] An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which the strength of the load on the external connection terminals is increased.

[0011] According to one aspect of the invention, there is provided a semiconductor device including a circuit board, a storage member having a rectangular outer shape in a plan view and storing the circuit board, a case in which the underside of a first edge portion facing the outside of the storage member in a plan view faces the upper surface of the stored circuit board with a gap therebetween, a first external connection terminal protruding perpendicular to the upper surface of the first edge portion and held by the first edge portion, and a sealing member that seals the space between the upper surface of the circuit board and the underside of the first edge portion.

[0012] The case may include a sidewall formed on the underside of an outer side of the first edge portion, and a first opening for injecting the sealing member may be formed on the underside of the sidewall.

[0013] The first external connection terminal may be a plurality of terminals arranged along the first edge portion.

[0014] One or more of the first external connection terminals may be arranged on each of the first edge portion and a second edge portion of the housing member that faces the first edge portion.

[0015] The case may further include a terminal holding member arranged adjacent to the storage member in a direction along the first edge portion, and the semiconductor device may further include a second external connection terminal having a flat portion parallel to the upper surface of the storage member and held by the terminal holding member.

[0016] The case, the first external connection terminal, and the second external connection terminal may be integrally molded with the storage member sealing a portion of the first external connection terminal and the terminal holding member sealing a portion of the second external connection terminal.

[0017] The storage member may have a frame shape with a second opening formed in the center when viewed in a plane and including the first edge portion that defines the second opening, and the case may further include a cover member that covers the second opening.

[0018] The storage member may have a shape in which an inner region is closed relative to an outer side of the first edge portion in a plan view.

[0019] The device may further include a wiring board between the upper surface of the circuit board and the lower surface of the first edge portion, facing the circuit board and spaced apart from the upper surface of the circuit board and the lower surface of the first edge portion, with a wiring hole penetrating the lower region of the first edge portion in a planar view, and the first external connection terminal may have a lower end that protrudes from the lower surface of the first edge portion and is inserted into the wiring hole, and be electrically connected to the wiring board.

[0020] The circuit board may further include a semiconductor chip arranged on the upper surface thereof, and the wiring board may further include wiring pins protruding from the lower surface thereof, and the upper surface of the semiconductor chip and the lower ends of the wiring pins may be joined via solder.

[0021] According to one aspect of the invention, there is provided a method for manufacturing a semiconductor device, comprising: a preparation step of preparing a circuit board; a case including a housing member having a rectangular outer shape in a planar view for housing the circuit board, wherein a first external connection terminal is held on the first edge portion in a state in which it protrudes perpendicularly to the upper surface of the first edge portion facing the outside of the housing member in a planar view; a setting step of arranging the case and the circuit board so that the lower surface of the first edge portion faces the upper surface of the circuit board with a gap; and a sealing step of sealing the space between the upper surface of the circuit board and the lower surface of the first edge portion with a sealing member.

[0022] The preparing step may include a molding step of sealing a portion of the first external connection terminal with a constituent material of the case, thereby integrally molding the housing member of the case and the first external connection terminal.

[0023] The case may include a sidewall formed on the underside of the outer side of the first edge portion, and a first opening formed on the underside of the sidewall, and during the sealing process, the sealing material may be injected from the first opening into the area between the upper surface of the circuit board and the lower surface of the first edge portion.

[0024] The case may further include a terminal holding member arranged adjacent to the storage member in a direction along the first edge portion, and the semiconductor device may further include a second external connection terminal having a flat portion parallel to the upper surface of the storage member and held by the terminal holding member, and the preparation process may include a molding process in which a portion of the first external connection terminal and a portion of the second external connection terminal are sealed with a constituent material of the case, and the storage member and the terminal holding member of the case are integrally molded with the first external connection terminal and the second external connection terminal.

[0025] The lower end of the first external connection terminal protrudes from the underside of the first edge portion, and the preparation process further includes preparing a wiring board having a wiring hole therethrough, and the setting process may include a first process of bringing the upper surface of the wiring board toward the underside of the first edge portion, and pressing the lower end of the first external connection terminal into the wiring hole while leaving a gap between the upper surface of the wiring board and the underside of the first edge portion to electrically connect the wiring hole and the first external connection terminal, and a second process of positioning the circuit board on the underside of the wiring board so that the underside of the wiring board faces the upper surface of the circuit board with a gap therebetween.

[0026] A semiconductor chip is placed on the upper surface of the circuit board, and the wiring board further has wiring pins protruding from the lower surface of the wiring board, and after completion of the second step, the method may further include a step of joining the upper surface of the semiconductor chip and the lower ends of the wiring pins via solder in the area between the upper surface of the circuit board and the lower surface of the wiring board.

[0027] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0028] According to the disclosed technique, it is possible to increase the strength of the load on the external connection terminal. The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.

[0029] 1 is a plan view showing the appearance of a semiconductor device; FIG. 2 is a side view showing the appearance of a semiconductor device; FIG. 3 is a plan view of a semiconductor device with a sealing member and a lid member removed; FIG. 4 is a side view of a semiconductor device with a sealing member removed; FIG. 5 is a plan view of a wiring board; FIG. 6 is a plan view of a circuit board and external connection terminals; FIG. 7 is an enlarged cross-sectional view of a portion of the semiconductor device; FIG. 8 is a diagram showing an example of the circuit configuration of a three-level inverter; FIG. 9 is a flowchart showing a manufacturing process of a semiconductor device; FIG. 10 is a diagram showing a process of integrally molding a case and external connection terminals; FIG. 11 is a diagram showing a process of injecting a sealing member from a gate opening; and FIG. 12 is a plan view showing a modified example of a semiconductor device.

[0030] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the X-axis and Y-axis are defined on a horizontal plane, the Z-axis is defined perpendicular to the horizontal plane, and the +Z direction is defined as the upper side and the -Z direction is defined as the lower side. Furthermore, the terms "upper surface," "top," "front surface," "lower surface," "bottom," "rear surface," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity.

[0031] First, the appearance of a semiconductor device according to an embodiment will be described with reference to Figures 1 and 2. Figure 1 is a plan view showing the appearance of the semiconductor device. Figure 2 is a side view showing the appearance of the semiconductor device. Note that Figure 2 is a side view of the semiconductor device 1 of Figure 1 when viewed in the +X direction.

[0032] The semiconductor device 1 is a modularized device that includes a circuit board on which a semiconductor chip is mounted, external connection terminals, etc. The semiconductor device 1 is attached to the front surface (the surface on the +Z direction side) of a cooling module (not shown). The cooling module may be, for example, a heat dissipation base with heat dissipation fins or a cooling device in which a refrigerant circulates inside.

[0033] The semiconductor device 1 has a case 10 that houses a wiring board 20 and a circuit board 30, which will be described later in FIG. 4. The case 10 includes a housing member 10a, terminal holding members 10b and 10c, and a lid member 10d. The terminal holding member 10b is integrally connected to the -Y direction side of the housing member 10a, and the terminal holding member 10c is integrally connected to the +Y direction side of the housing member 10a. The lid member 10d is provided in a second opening 11d, which will be described later, provided in the top surface of the housing member 10a.

[0034] The storage member 10a is, for example, box-shaped and includes a top surface portion 11a that forms an upper surface parallel to a horizontal plane (X-Y plane), side walls parallel to the Y-Z plane, and side walls parallel to the X-Y plane. The side walls parallel to the Y-Z plane are formed on the lower side (-Z direction side) of each end edge of the top surface portion 11a in the +X direction and the -X direction. In FIG. 2, the side wall 11b on the -X direction side is shown, but the reference numeral for the side wall on the +X direction side is omitted. The side walls (reference numerals omitted) parallel to the X-Y plane are formed on the lower side of each end edge of the top surface portion 11a in the +Y direction and the -Y direction.

[0035] The top surface 11a and the side walls on the +X and −X sides may be flat and integrally connected. The side wall on the +Y side may be integral with the end face on the −Y side of the terminal holding member 10c, and the side wall on the −Y side may be integral with the end face on the +Y side of the terminal holding member 10b.

[0036] Furthermore, the storage member 10a is not limited to being box-shaped, and may include an upper surface 11a and side walls parallel to the XY plane formed on the underside of each end edge of the upper surface 11a on the +Y direction side and the -Y direction side.

[0037] The top surface 11a has a rectangular outer shape in plan view. A second opening 11d is formed in the center of the top surface 11a in plan view. In this embodiment, the second opening 11d has a rectangular outer shape in plan view, and the top surface 11a (i.e., the storage member 10a) has a frame shape that defines the second opening 11d in plan view. The second opening 11d is closed by a cover member 10d.

[0038] The storage member 10a includes a storage area 11e (see FIG. 4) surrounded by the lower surface of the top surface portion 11a, side walls on the +X direction side and the -X direction side, and side walls on the +Y direction side and the -Y direction side. The above-mentioned wiring board 20 and circuit board 30 are stored in this storage area 11e. The top surface portion 11a forms the upper exterior of the wiring board 20 and circuit board 30 stored in the storage area 11e.

[0039] Meanwhile, openings for injecting the sealing member 40 are provided on the +X-direction side and the −X-direction side of the storage area 11e. In this embodiment, as an example, sidewalls are also provided on the +X-direction side and the −X-direction side of the storage area 11e, and an opening is provided in a portion of each sidewall. For example, FIG. 2 illustrates a sidewall 11b provided on the −X-direction edge of the top surface portion 11a. A first opening 11c opening downward (toward the −Z direction) is formed in the sidewall 11b. The first opening 11c is formed between the sidewall (terminal holding member 10c) on the +Y-direction side of the storage member 10a and the sidewall (terminal holding member 10b) on the −Y-direction side. The interior of the storage area 11e is sealed with the sealing member 40, and the first opening 11c is blocked from the inside by the sealing member 40. Furthermore, on the upper side of the storage area 11e, the top surface portion 11a and the lower surface of the lid member 10d are blocked from the inside by the sealing member 40.

[0040] The top surface 11a includes a first edge 11a1 and a second edge 11a2 extending in the Y-axis direction on the −X-direction and +X-direction sides of the second opening 11d, respectively. First external connection terminals 12a-12d, 12i, and 12j are provided on the first edge 11a1 on the −X-direction side of the top surface 11a. First external connection terminals 12e-12h are provided on the second edge 11a2 on the +X-direction side of the top surface 11a. The first external connection terminals 12a-12j are columnar and extend generally vertically. The columnar shape may be a rectangular columnar or a cylindrical columnar shape. The ends of the first external connection terminals 12a-12j exposed on the top surface sides (+Z-direction sides) of the first edge 11a1 and the second edge 11a2 may be press-fit pins.

[0041] The first external connection terminals 12a to 12d, 12i, and 12j are held by the first edge 11a1 while penetrating the first edge 11a1 in the vertical direction (±Z direction). The first external connection terminals 12e to 12h are held by the second edge 11a2 while penetrating the second edge 11a2 in the vertical direction (±Z direction). The upper ends of the first external connection terminals 12a to 12j protruding from the upper surface of the upper surface 11a serve as connection terminals for connection to an external circuit. Meanwhile, the lower ends of the first external connection terminals 12a to 12j protruding from the lower surface of the upper surface 11a are inserted into wiring holes provided in the wiring substrate 20 and electrically connected to wiring layers formed on the wiring substrate 20, as described below.

[0042] The terminal holding member 10b is provided with second external connection terminals 13a to 13c. Flat plate portions 13a1 to 13c1 (see FIG. 6) are formed at the ends (outer ends) of the second external connection terminals 13a to 13c on the −Y direction side. The second external connection terminals 13a to 13c are held by the terminal holding member 10b with the upper surfaces of the flat plate portions 13a1 to 13c1 exposed on the upper surface of the terminal holding member 10b. The flat plate portions 13a1 to 13c1 exposed on the upper surface of the terminal holding member 10b serve as connection terminal portions for connecting to an external circuit. Meanwhile, the ends (inner ends) of the second external connection terminals 13a to 13c on the +Y direction side are connected to a circuit pattern on the upper surface of the circuit board 30 inside the housing member 10a, as described below.

[0043] The terminal holding member 10c is provided with a second external connection terminal 13d. A flat plate portion 13d1 (see FIG. 6) is formed at the end (outer end) of the second external connection terminal 13d on the +Y direction side. The second external connection terminal 13d is held by the terminal holding member 10c with the upper surface of the flat plate portion 13d1 exposed on the upper surface of the terminal holding member 10c. The flat plate portion 13d1 exposed on the upper surface of the terminal holding member 10c serves as a connection terminal portion for connecting to an external circuit. Meanwhile, the end (inner end) of the second external connection terminal 13d on the -Y direction side is connected to a circuit pattern on the upper surface of the circuit board 30 inside the housing member 10a, as described below.

[0044] In this embodiment, a three-level inverter circuit is configured by a wiring board 20, a circuit board 30, and a semiconductor chip (described later) housed inside the case 10. The second external connection terminals 13a to 13d correspond to the N terminal, P terminal, neutral terminal, and output terminal of the three-level inverter circuit, respectively. The first external connection terminals 12a to 12h correspond to control terminals for controlling the switching operations of transistors included in the three-level inverter circuit. The first external connection terminals 12i and 12j correspond to output terminals for outputting various sense signals.

[0045] The case 10, which includes the housing member 10a and the terminal holding members 10b and 10c, includes portions of the first external connection terminals 12a-12j and the second external connection terminals 13a-13d, and is integrally molded by injection molding using a thermoplastic resin. The lid member 10d is separately formed by injection molding using a thermoplastic resin. Examples of the thermoplastic resin include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, acrylonitrile butadiene styrene resin, and liquid crystal polymer. The first external connection terminals 12a-12j and the second external connection terminals 13a-13d are formed from a metal with excellent conductivity. Examples of such metals include copper, aluminum, or an alloy containing at least one of these as a main component.

[0046] Fig. 3 is a plan view of the semiconductor device with the sealing member and the lid member removed, and Fig. 4 is a side view of the semiconductor device with the sealing member removed.

[0047] A wiring board 20 and a circuit board 30 are housed inside the housing member 10a (below the upper surface portion 11a). Both the wiring board 20 and the circuit board 30 have a rectangular shape in a plan view. The wiring board 20 is disposed with its upper surface facing the lower surface of the upper surface portion 11a, with a gap therebetween. A plurality of wiring holes (described below) penetrate the wiring board 20, and the lower ends of the first external connection terminals 12a to 12j are press-fitted into the corresponding wiring holes, thereby fixing the wiring board 20 to the upper surface portion 11a. The first external connection terminals 12a to 12j are electrically connected to wiring layers included in the wiring board 20. The circuit board 30 is disposed with its upper surface facing the lower surface of the wiring board 20, with a gap therebetween.

[0048] Multiple semiconductor chips are mounted on the upper surface of the circuit board 30. Among these semiconductor chips, semiconductor chips 31b, 31d, and 31e are illustrated in FIG. Meanwhile, multiple cylindrical wiring pins extending vertically are inserted into the wiring board 20. The upper end of each wiring pin is electrically connected to a wiring layer included in the wiring board 20, and the lower end of each wiring pin is electrically connected via solder to output electrodes and control electrodes on the upper surface of the corresponding semiconductor chip. For example, in FIG. 4, wiring pins 21a and 21b are provided on the wiring board 20, and the lower ends of wiring pins 21a and 21b are electrically connected via solder to the upper surfaces of semiconductor chips 31b and 31e, respectively. Therefore, the first external connection terminals 12a to 12j are electrically connected to the output electrodes and control electrodes of the semiconductor chips via the wiring board 20 and each wiring pin.

[0049] Furthermore, when the wiring board 20 and the circuit board 30 are arranged on the upper surface portion 11a as described above, a sealing member 40 is filled in at least the area between the lower surface of the upper surface portion 11a and the upper surface of the circuit board 30, and the wiring board 20 and the semiconductor chip are sealed by the sealing member 40.

[0050] In this embodiment, the periphery of the circuit board 30 and the lower sidewalls of the upper surface portion 11a are not in contact with the terminal holding members 10b, 10c in a plan view. Therefore, the sealing member 40 is filled in so as to cover the side surfaces of the circuit board 30, and the back surface of the circuit board 30 and the sealing member 40 covering the side surfaces are exposed from the lower side (-Z direction side) of the storage area 11e. In addition, the back surface of the circuit board 30 may be flush with the back surfaces of the storage member 10a of the case 10 and the terminal holding members 10b, 10c.

[0051] A thermosetting resin is used as the sealing material of the sealing member 40. The thermosetting resin is, for example, an epoxy resin. By using such a resin and performing transfer molding on the case 10 that houses the wiring board 20, the circuit board 30, and the semiconductor chip, a highly rigid semiconductor device 1 is manufactured. In particular, high rigidity in the vertical direction (Z-axis direction) of the semiconductor device 1 is obtained, and even when an external force is applied in the vertical direction, a predetermined distance can be maintained between the upper surface portion 11a and the wiring board 20, and between the wiring board 20 and the circuit board 30.

[0052] 5 is a plan view of the wiring board 20. The wiring board 20 is, for example, a multilayer printed circuit board (PCB). In the wiring board 20, for example, a wiring layer may be formed on at least one of the upper and lower surfaces of an insulating layer, and one or more wiring layers may also be formed inside the insulating layer.

[0053] The insulating layer is formed of, for example, an insulating resin. Examples of insulating resins include a paper phenol substrate, a paper epoxy substrate, a glass composite substrate, and a glass epoxy substrate. The wiring layer is formed of a metal with excellent conductivity. Examples of such metals include copper, aluminum, or an alloy containing at least one of these as a main component.

[0054] The wiring board 20 is provided with a plurality of wiring holes (through holes) penetrating the wiring board 20, and a wiring pin is inserted into each wiring hole. The wiring pins are formed from a metal with excellent conductivity. Each wiring hole is connected to a circuit pattern of one of the wiring layers formed on the wiring board 20, and the wiring pins are electrically connected to the circuit patterns connected to the wiring holes into which they are inserted. These wiring pins protrude at least below the corresponding wiring holes. Furthermore, the wiring pins may also protrude above the corresponding wiring holes to an extent that they do not come into contact with the lower surface of the upper surface portion 11a.

[0055] 5 illustrates wiring pins 21a and 21b as such wiring pins. As shown in FIG. 4, the lower ends of wiring pins 21a and 21b are electrically connected via solder to output electrodes and control electrodes on the upper surfaces of semiconductor chips 31b and 31e mounted on circuit board 30.

[0056] Wiring holes (through holes) 22a to 22j penetrate the wiring board 20. The wiring holes 22a to 22d, 22i, and 22j are arranged along the edge of the wiring board 20 on the −X direction side. This edge region faces the lower surface of the first edge portion 11a1 of the upper surface portion 11a when the wiring board 20 is attached to the upper surface portion 11a. The lower ends of the first external connection terminals 12a to 12d, 12i, and 12j are inserted into the wiring holes 22a to 22d, 22i, and 22j, respectively. The wiring holes 22e to 22h are arranged along the edge of the wiring board 20 on the +X direction side. This edge region faces the lower surface of the second edge portion 11a2 of the upper surface portion 11a when the wiring board 20 is attached to the upper surface portion 11a. The lower ends of the first external connection terminals 12e to 12h are inserted into the wiring holes 22e to 22h, respectively.

[0057] The wiring holes 22a to 22j are also connected to the circuit pattern of one of the wiring layers formed on the wiring substrate 20. When the lower ends of the first external connection terminals 12a to 12j are inserted into the wiring holes 22a to 22j, the first external connection terminals 12a to 12j are electrically connected to the circuit patterns connected to the inserted wiring holes 22a to 22j.

[0058] In addition, via holes may be formed through the wiring substrate 20 to electrically connect the wiring layers together.

[0059] Fig. 6 is a plan view of the circuit board and the external connection terminals. As mentioned above, the second external connection terminals 13a to 13d are integrally molded with the case 10. Fig. 6 shows the second external connection terminals 13a to 13d together with the circuit board 30 with the case 10 removed.

[0060] The circuit board 30 includes an insulating plate 32 forming the bottom surface, circuit patterns 33a to 33g formed on the upper surface (surface on the +Z direction side) of the insulating plate 32, and a metal plate (not shown) formed on the lower surface (surface on the −Z direction side) of the insulating plate 32. In addition, semiconductor chips 31a to 31e are mounted on the circuit board 30.

[0061] The insulating plate 32 is made of, for example, a resin. The resin may be a material with low thermal resistance and high insulating properties. Examples of such resins include thermosetting resins and thermoplastic resins. Examples of thermosetting resins include at least one of epoxy resin, cyanate resin, polyimide resin, benzoxazine resin, unsaturated polyester resin, phenolic resin, melamine resin, silicone resin, and maleimide resin. Examples of thermoplastic resins include at least one of acrylic resin and polyamide resin. These resins may also contain a filler. The filler may be made of at least one of an oxide and a nitride. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Furthermore, the filler may be hexagonal boron nitride.

[0062] The insulating plate 32 may be a ceramic substrate instead of a resin. The ceramic substrate is made of ceramic with good thermal conductivity. The ceramic is made of a material whose main components are, for example, aluminum oxide, aluminum nitride, or silicon nitride. The circuit board 30 including the insulating plate 32 having such a configuration can be, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate.

[0063] In this embodiment, the insulating plate 32 is made of resin, and the difference between the linear expansion coefficient of the insulating plate 32 and the linear expansion coefficient of the metal plate and circuit patterns 33a to 33g is small.

[0064] The circuit patterns 33a to 33f and the metal plate are made of a metal with excellent conductivity, such as copper, aluminum, or an alloy containing at least one of these as a main component.

[0065] The semiconductor chips 31a to 31d may be power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) primarily made of silicon carbide. The body diode of the power MOSFET may function as a free wheeling diode (FWD). Each of the semiconductor chips 31a to 31d has, for example, an input electrode (drain electrode) as a main electrode on the back surface, and an output electrode (source electrode) and a control electrode (gate electrode) as main electrodes on the front surface.

[0066] The semiconductor chips 31a to 31d may also include switching elements primarily made of silicon. The switching elements may be, for example, reverse-conducting (RC)-insulated gate bipolar transistors (IGBTs). An RC-IGBT is a semiconductor element in which an IGBT and an FWD are arranged in anti-parallel within a single chip. Each of the semiconductor chips 31a to 31d has, for example, an input electrode (collector electrode) as a main electrode on the back surface, and an output electrode (emitter electrode) and a control electrode (gate electrode) as main electrodes on the front surface.

[0067] The semiconductor chips 31a to 31d may each include a pair of switching elements and diode elements made primarily of silicon. The switching elements are, for example, power MOSFETs or IGBTs. The semiconductor chips including the switching elements include, for example, an input electrode (a drain electrode in a power MOSFET or a collector electrode in an IGBT) as a main electrode on the back surface, and a gate electrode (a source electrode in a power MOSFET or an emitter electrode in an IGBT) as a control electrode and an output electrode (a source electrode in a power MOSFET or an emitter electrode in an IGBT) as a main electrode on the front surface. The diode elements include, for example, Schottky Barrier Diodes (SBDs) and P-intrinsic-N (PiN) diodes used as FWDs. The semiconductor chips including the diode elements include, for example, an output electrode (cathode electrode) as a main electrode on the back surface, and an input electrode (anode electrode) as a main electrode on the front surface.

[0068] In this embodiment, the semiconductor chips 31a to 31d are power MOSFETs made mainly of silicon carbide.

[0069] As an example, four semiconductor chips 31c are mounted on the upper surface of circuit pattern 33c. Although not shown in the figure, input electrodes on the lower surfaces of semiconductor chip 31c are electrically connected to the upper surface of circuit pattern 33c via solder. As an example, four semiconductor chips 31d are mounted on the upper surface of circuit pattern 33d. Although not shown in the figure, input electrodes on the lower surfaces of semiconductor chip 31d are electrically connected to the upper surface of circuit pattern 33d via solder. As an example, four semiconductor chips 31a and four semiconductor chips 31b are mounted on the upper surface of circuit pattern 33e. Although not shown in the figure, input electrodes on the lower surfaces of semiconductor chips 31a and 31b are electrically connected to the upper surface of circuit pattern 33e via solder.

[0070] A semiconductor chip 31e is mounted on the upper surface of the circuit pattern 33g. The semiconductor chip 31e includes semiconductor elements that perform various sensing operations. For example, the semiconductor chip 31e includes a diode element that detects temperature. Although not shown, electrodes provided on the lower surface of the semiconductor chip 31e are electrically connected to the upper surface of the circuit pattern 33g via solder.

[0071] The circuit pattern 33a is electrically connected to the second external connection terminal 13a. Specifically, a flat plate portion 13a1 is formed at the end of the second external connection terminal 13a on the -Y direction side. Furthermore, a horizontally flat plate-shaped connection portion 13a2 is formed at the end of the flat plate portion 13a1 of the second external connection terminal 13a on the +Y direction side, with an intermediate portion (not shown) extending downward (in the -Z direction) interposed therebetween. The lower surface of the connection portion 13a2 is joined to the upper surface of the circuit pattern 33a.

[0072] The circuit pattern 33b is electrically connected to the second external connection terminal 13c. Specifically, a flat plate portion 13c1 is formed at the end of the second external connection terminal 13c on the -Y direction side. Furthermore, a horizontally flat plate-shaped connection portion 13c2 is formed at the end of the flat plate portion 13c1 of the second external connection terminal 13c on the +Y direction side, with an intermediate portion (not shown) extending downward (in the -Z direction) interposed therebetween. The lower surface of the connection portion 13c2 is joined to the upper surface of the circuit pattern 33b.

[0073] The circuit pattern 33d is electrically connected to the second external connection terminal 13b. Specifically, a flat plate portion 13b1 is formed at the end of the second external connection terminal 13b on the -Y direction side. Furthermore, a horizontally flat plate-shaped connection portion 13b2 is formed at the end of the flat plate portion 13b1 of the second external connection terminal 13b on the +Y direction side, with an intermediate portion (not shown) extending downward (in the -Z direction) interposed therebetween. The lower surface of the connection portion 13b2 is joined to the upper surface of the circuit pattern 33d.

[0074] The circuit pattern 33f is electrically connected to the second external connection terminal 13d. Specifically, a flat plate portion 13d1 is formed at the end of the second external connection terminal 13d on the +Y direction side. A horizontally flat plate-shaped connection portion 13d2 is formed at the end of the flat plate portion 13d1 of the second external connection terminal 13d on the -Y direction side, with an intermediate portion (not shown) extending downward (in the -Z direction) interposed therebetween. The lower surface of the connection portion 13d2 is joined to the upper surface of the circuit pattern 33f.

[0075] 7 is an enlarged cross-sectional view of a portion of the semiconductor device, taken along line I1-I1 in FIG.

[0076] In region A, the first external connection terminals 12a and 12b are held by the first edge 11a1 of the upper surface 11a while penetrating the first edge 11a1 in the direction perpendicular to the Z-axis (Z-axis direction). The lower ends of the first external connection terminals 12a and 12b are inserted into wiring holes 22a and 22b, respectively, formed in the wiring substrate 20. For example, circuit patterns 23a and 23b are formed on the upper surface of the wiring substrate 20 at positions surrounding the wiring holes 22a and 22b, respectively. Inserting the lower ends of the first external connection terminals 12a and 12b into the wiring holes 22a and 22b electrically connects the first external connection terminals 12a and 12b to the circuit patterns 23a and 23b, respectively. Press-fitting the lower ends of the first external connection terminals 12a and 12b into the wiring holes 22a and 22b fixes the position of the wiring substrate 20 relative to the first edge 11a1 of the upper surface 11a.

[0077] Furthermore, wiring pins 21a are inserted through wiring board 20 and are electrically connected to, for example, circuit patterns 23c formed on the upper surface of wiring board 20. Meanwhile, circuit patterns 33e are formed on the upper surface of insulating plate 32 of circuit board 30, and semiconductor chip 31b is mounted on the upper surface of circuit pattern 33e via solder 34a. The lower ends of wiring pins 21a are joined to the upper surface of semiconductor chip 31b via solder 34b.

[0078] In this way, a gap is provided between the lower surface of wiring board 20 and the upper surface of circuit board 30 for joining the wiring pins and the semiconductor chip via solder. As described above, sealing member 40 is filled into storage area 11e between the lower surface of upper surface portion 11a and the upper surface of circuit board 30, enclosing wiring board 20. When the filled sealing member 40 hardens, circuit board 30 is fixed to case 10 with a predetermined gap maintained between the lower surface of wiring board 20 and the upper surface of circuit board 30.

[0079] In this embodiment, the first external connection terminals 12a, 12b are press-fit pins, and the +Z direction end portions (outer end portions) 12a1, 12b1 of the first external connection terminals 12a, 12b are elastically deformable. The other first external connection terminals 12c to 12j are press-fit pins with similar configurations. The press-fit pins are press-fitted into receiving terminals. Therefore, during press-fitting, a load is applied in the longitudinal direction of the first external connection terminals 12a to 12j, i.e., in a direction perpendicular to the top surface of the case 10 (the Z-axis direction). Furthermore, as described above, the −Z direction end portions (inner end portions) of the first external connection terminals 12a, 12b are press-fitted into the wiring holes 22a to 22j of the wiring substrate 20. During this press-fitting, a load is also applied in a direction perpendicular to the top surface of the case 10.

[0080] In this embodiment, the first external connection terminals 12a to 12j are held in a case 10, and the semiconductor device 1 is fabricated by transfer molding including such a case 10. By adopting a structure in which the first external connection terminals 12a to 12j are held in the case 10, it is possible to increase the strength of the first external connection terminals 12a to 12j against vertical loads.

[0081] Generally, in transfer mold semiconductor modules, external connection terminals connected to tie bar terminals are often molded while being enclosed in resin. To provide external connection terminals oriented perpendicular to the main surface of a semiconductor module with such a structure, for example, after transfer molding, the carrier portion of the tie bar terminal is cut, and the external connection terminals protruding from the semiconductor module in a direction parallel to the main surface (horizontal direction) are bent vertically. In this case, the vertical rigidity of the external connection terminals is low, making it difficult to provide external connection terminals that are subjected to a vertical load as described above.

[0082] In contrast, the semiconductor device 1 of this embodiment is manufactured by transfer molding, but uses a case 10 that holds the first external connection terminals 12a to 12j that extend vertically upward, thereby making it possible to realize a semiconductor device 1 that is equipped with the first external connection terminals 12a to 12j that have high strength against vertical loads.

[0083] The case 10 and the first external connection terminals 12a to 12j are integrally molded by injection molding. By preparing a molding die for each shape of the case 10, it is possible to easily mold the case 10 in a variety of shapes. This allows for a high degree of design freedom in terms of the mounting position and number of the external connection terminals that extend vertically.

[0084] In addition, the design freedom regarding the shape of the case 10 is high. For example, in this embodiment, as shown in FIG. 7 , the mounting region 11a3, through which the first external connection terminals 12a and 12b pass, of the first edge portion 11a1 of the top surface 11a is formed with a greater vertical thickness than the other regions. This increases the mounting strength of the first external connection terminals 12a and 12b. Thus, the design freedom regarding the thickness of the case 10, including the top surface 11a, is high. Furthermore, an opening for injecting the sealing material 40 is provided in a sidewall (e.g., sidewall 11b) on the X-axis side of the case housing member 10a. The design freedom regarding the position, size, and shape of such an opening is also high.

[0085] Furthermore, the molding process described above allows the case 10 to be manufactured with high precision as designed. For example, the first external connection terminals 12a to 12j protrude from the upper surface (+Z direction) of the case 10. Meanwhile, during transfer molding, a mold (upper mold) is tightly attached to the upper surface of the case 10. Therefore, the protruding first external connection terminals 12a to 12j must be precisely aligned and inserted into the mold cavity, requiring high precision in the horizontal positioning of the first external connection terminals 12a to 12j on the case 10. By integrally molding the case 10 and the first external connection terminals 12a to 12j by injection molding, the horizontal mounting position precision of the first external connection terminals 12a to 12j on the case 10 can be improved.

[0086] In this way, by manufacturing the semiconductor device 1 by transfer molding using the case 10 that holds the first external connection terminals 12a to 12j, it becomes possible to manufacture semiconductor devices 1 with various specifications with high precision.

[0087] As the first external connection terminals 12a to 12j, for example, solder pins may be used instead of press-fit pins.

[0088] 8 is a diagram showing an example of the circuit configuration of a three-level inverter. The semiconductor device 1 includes, for example, a three-level inverter as shown in FIG. 8. This three-level inverter is a T-type NPC (Neutral Point Clamped) inverter circuit and includes four transistors Q1 to Q4. The transistor Q1 corresponds to the semiconductor chip 31d, and the transistor Q2 corresponds to the semiconductor chip 31c. The transistor Q3 corresponds to the semiconductor chip 31b, and the transistor Q4 corresponds to the semiconductor chip 31a.

[0089] The drain electrode of transistor Q1 is connected to the P terminal, which is the positive input terminal, via circuit board 30. The P terminal corresponds to second external connection terminal 13b. The source electrode of transistor Q2 is connected to the N terminal, which is the negative input terminal, via wiring board 20 and circuit board 30. The N terminal corresponds to second external connection terminal 13a.

[0090] The drain electrode of transistor Q3 and the drain electrode of transistor Q4 are connected via circuit board 30, and the source electrode of transistor Q3 is connected to terminal M (neutral terminal), which is an input terminal of intermediate potential, via wiring board 20 and circuit board 30. Terminal M corresponds to second external connection terminal 13c.

[0091] The source electrode of transistor Q1, the drain electrode of transistor Q2, and the source electrode of transistor Q4 are connected via circuit board 30 and wiring board 20, and their connection point is connected to the U terminal, which is an output terminal, via wiring board 20 and circuit board 30. The U terminal corresponds to second external connection terminal 13d.

[0092] The gate electrodes of transistors Q1 to Q4 are connected to gate terminals (control terminals) G1 to G4, which are input terminals for control signals for switching operations, via wiring board 20. Gate terminals G1 to G4 correspond to first external connection terminals 12c, 12g, 12b, and 12f, respectively. Source electrodes of transistors Q1 to Q4 are connected to auxiliary source terminals S1 to S4, which are output terminals, via wiring board 20. Auxiliary source terminals S1 to S4 correspond to first external connection terminals 12d, 12h, 12a, and 12e, respectively.

[0093] In this three-level inverter, when the control signal to gate terminals G1 and G2 is on and the control signal to gate terminals G3 and G4 is off, the output voltage from the U terminal is E / 2. When the control terminal to gate terminals G2 and G3 is on and the control terminal to gate terminals G1 and G4 is off, the output voltage from the U terminal is 0. When the control signal to gate terminals G3 and G4 is on and the control signal to gate terminals G1 and G2 is off, the output voltage from the U terminal is -E / 2.

[0094] As described above, the transistors Q1 to Q4 included in the three-level inverter correspond to the semiconductor chips 31a to 31d, respectively. Furthermore, as shown in FIG. 5, the semiconductor device 1 of this embodiment includes four semiconductor chips 31a to 31d. Therefore, the semiconductor device 1 includes four three-level inverters, each including one of the semiconductor chips 31a to 31d, and these three-level inverters are connected in parallel.

[0095] Although not shown, three semiconductor devices 1 each having the above-described parallel three-level inverters are used in combination. One semiconductor device 1 generates a U-phase output voltage, another semiconductor device 1 generates a V-phase output voltage, and another semiconductor device 1 generates a W-phase output voltage.

[0096] Next, a description will be given of a manufacturing process of the semiconductor device 1. Fig. 9 is a flowchart showing the manufacturing process of the semiconductor device.

[0097] [Step P1] The first external connection terminals 12a to 12j and the second external connection terminals 13a to 13d are fabricated.

[0098] [Step P2] The case 10 is produced by injection molding a resin material. In this step, the case 10 includes the first external connection terminals 12a to 12j and the second external connection terminals 13a to 13d, and is produced by integrally molding the housing member 10a and the terminal holding members 10b and 10c with a resin material. Details of step P2 will be described later using FIG. 10.

[0099] [Process P3] The wiring board 20 is set on the case 10. In this process, the case 10 and wiring board 20 are turned upside down, and the wiring board 20 is attached to the back surface of the top surface 11a of the case 10 (the surface facing the storage area 11e). Specifically, the wiring board 20 is brought close to the back surface of the top surface 11a, and the ends of the first external connection terminals 12a to 12j are inserted into the wiring holes 22a to 22j of the wiring board 20. The wiring board 20 is pressed against the top surface 11a, so that the first external connection terminals 12a to 12j are press-fit into the wiring holes 22a to 22j. This press-fitting is continued until a predetermined distance is created between the back surface of the top surface 11a and the wiring board 20.

[0100] [Process P4] The circuit board 30 is set on the case 10 to which the wiring board 20 has been attached. In this process, the vertical orientation of the case 10 is changed so that the main surface of the case 10 (the surface on which the second external connection terminals 13a-13d are exposed) faces upward. Furthermore, solder is applied to the electrodes on the upper surfaces of the semiconductor chips 31a-31e on the circuit board 30 to bond them to the corresponding wiring pins. The circuit board 30 is then brought closer to the lower surface of the upper surface portion 11a, and positioned so that a predetermined distance is maintained between the circuit board 30 and the wiring board 20.

[0101] [Step P5] Reflow is performed. The case 10 in which the wiring board 20 and the circuit board 30 are set in steps P3 and P4 is heated, and the solder on the electrodes on the upper surfaces of the semiconductor chips 31 a to 31 e is melted. After the solder melts, it is cooled and solidified, and the electrodes on the upper surfaces of the semiconductor chips 31 a to 31 e are joined to the corresponding wiring pins via the solder.

[0102] [Process P6] The case 10 is set in the cavity of a predetermined molding device. At this time, a lid member 10d is also placed in the cavity, and the lid member 10d closes the second opening 11d of the housing member 10a of the case 10. In this molding device, the molten sealing material in the pod is pressurized by a plunger and sent from the pod to a runner, and the sealing material is injected from a gate (described later) into a gate opening (including the first opening 11c) on the side of the opening in the X-axis direction of the housing member 10a.

[0103] The sealing material injected into the inside of the case 10 hardens, and the wiring board 20, the circuit board 30, and the semiconductor chips 31a to 31e are sealed by the sealing member 40. By this type of transfer molding of the case 10, the semiconductor device 1 shown in FIGS.

[0104] Process P6 will be described in detail with reference to Fig. 11. Fig. 10 is a diagram showing the integral molding process of the case and the external connection terminals.

[0105] 9, the first external connection terminals 12a to 12j and the second external connection terminals 13a to 13d produced in process P1 are integrally molded with the case 10 by injection molding. In this process P2, for example, a resin material is filled into a predetermined mold in which the first external connection terminals 12a to 12j and the second external connection terminals 13a to 13d are set. After the filled resin material hardens, the mold is removed. In this way, the case 10 is produced, which includes the first external connection terminals 12a to 12j and the second external connection terminals 13a to 13d, respectively, and in which the housing member 10a and the terminal holding members 10b and 10c are integrally molded.

[0106] Although the case where the top surface 11a of the case 10 is open has been described here, the top surface 11a may be closed without being open, as will be described later.

[0107] This molding increases the degree of freedom in designing the number and positions of the external connection terminals attached to the case 10. For example, as described above, this increases the degree of freedom in designing the number and positions of the first external connection terminals 12a to 12j that extend in the vertical direction (Z-axis direction). This also increases the accuracy of the attachment positions of the first external connection terminals 12a to 12j.

[0108] Furthermore, the design flexibility of the second external connection terminals 13a to 13d, each having a flat portion 13a1 to 13d1, can be increased. For example, the second external connection terminals 13a, 13b and the second external connection terminal 13c are arranged so that they are separated from each other so as not to be electrically connected, and so that they partially overlap in the vertical direction (Z-axis direction). Injection molding can easily produce the case 10 including the second external connection terminals 13a, 13b and the second external connection terminal 13c in this positional relationship.

[0109] 11 is a diagram showing a process of injecting the sealing material from the gate opening, and shows a plan view and a side view of the semiconductor device 1 in a state where the sealing material 40 and the cover member 10d have been removed.

[0110] As described above, openings are formed in the sidewalls of the housing member 10a in the X-axis direction. For example, a first opening 11c is formed in the sidewall 11b on the −X-direction side. In step P6 of FIG. 9 , the sealing member 40 is injected through these openings to seal the inside of the housing member 10a of the case 10.

[0111] 11, in the present embodiment, for example, only a partial area of ​​the first opening 11c is expanded upward (in the +Z direction), and the expanded area forms gate openings 14a and 14b for injecting the sealing material of the sealing member 40 in process P6. In the example of FIG. 11, the sealing material of the sealing member 40 is injected in the +X direction relative to the gate openings 14a and 14b.

[0112] The sealing with the sealing member 40 in this step P6 may be performed with the unsealed semiconductor device 1 shown in FIG. 11 turned upside down.

[0113] As described above, the case 10 is manufactured by injection molding, which increases the degree of freedom in designing the positions and shapes of the openings and gate openings in the side walls in the X-axis direction of the housing member 10a.

[0114] Next, a modified example of the upper structure of the housing member 10a will be described. Fig. 12 is a plan view showing a modified example of the semiconductor device.

[0115] 12, the second opening 11d is not formed in the upper surface 11a of the housing member 10a, and the entire upper surface of the storage area 11e is closed by the upper surface 11a, which is rectangular in plan view. The housing member 10a having such a shape is molded integrally with the terminal holding members 10b and 10c by resin injection molding.

[0116] Here, if a second opening 11d is formed in the upper surface portion 11a as shown in Figure 1, for example, when the wiring board 20 is attached to the case 10 in step P3 of Figure 9, it is possible to visually check the inside of the storage area 11e from the second opening 11d and confirm the quality of the wiring board 20.

[0117] When the second opening 11d is formed as described above, the interior of the storage region 11e may be sealed with the sealing member 40 without closing the second opening 11d with the lid member 10d. In this case, for example, the sealing member 40 may be filled beyond the lower surface of the upper surface portion 11a into the interior of the second opening 11d, sealing the second opening 11d up to the upper surface of the upper surface portion 11a. However, in this case, the sealing material may easily leak from the second opening 11d during transfer molding, and it may be necessary to remove the leaked sealing material (burrs) from the second opening 11d after the sealing material has hardened. In the example of FIG. 1, to prevent this situation, the second opening 11d is closed with the lid member 10d before transfer molding in step P6 of FIG. 9. Alternatively, as described above, when transfer molding is performed with the unsealed semiconductor device 1 shown in FIG. 11 turned upside down, although the second opening 11d of the storage member 10a is closed by the lower mold, it is difficult to completely prevent leakage of the sealing material.

[0118] On the other hand, when there is no need to check the quality of the wiring board 20 attached to the case 10 or when priority is given to the manufacturing efficiency of the semiconductor device 1, the case 10 can be molded so that the top surface 11a is closed from the start, as shown in Figure 12, thereby preventing leakage of the sealing material during transfer molding.

[0119] By integrally molding the first external connection terminals 12a to 12j and the second external connection terminals 13a to 13d with the case 10 by injection molding, as described above, it is possible to easily form both the case 10 having the second opening 11d on the upper surface 11a of the storage member 10a and the case 10 having no second opening 11d by using a mold corresponding to each shape.

[0120] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0121] 1 Semiconductor device 10 Case 10a Storage member 10b, 10c Terminal holding member 10d Lid member 11a Top surface 11a1 First edge 11a2 Second edge 11a3 Mounting area 11b Side wall 11c First opening 11d Second opening 11e Storage area 12a to 12j First external connection terminal 13a to 13d Second external connection terminal 12a1, 12b1 End 13a1, 13b1, 13c1, 13d1 Flat plate portion 13a2, 13b2, 13c2, 13d2 Connection portion 14a, 14b Gate opening 20 Wiring board 21a, 21b Wiring pin 22a to 22j Wiring hole 23a to 23c Circuit pattern 30 Circuit board 31a to 31e Semiconductor chip 32 Insulating plate 33a to 33g Circuit pattern 34a, 34b Solder 40 Sealing member A Area G1 to G4 Gate terminals Q1 to Q4 Transistors S1 to S4 Auxiliary source terminals

Claims

1. A semiconductor device comprising: a circuit board; a case including a housing member having a rectangular outer shape in a plan view and housing the circuit board, wherein the underside of a first edge portion facing the outside of the housing member in a plan view faces an upper surface of the housed circuit board with a gap therebetween; a first external connection terminal protruding perpendicularly to the upper surface of the first edge portion and held by the first edge portion; and a sealing member that seals the gap between the upper surface of the circuit board and the underside of the first edge portion.

2. The semiconductor device according to claim 1, wherein the case includes a sidewall formed on the underside of an outer side portion of the first edge portion, and a first opening for injecting the sealing material is formed on the underside of the sidewall.

3. The semiconductor device according to claim 1, wherein a plurality of the first external connection terminals are arranged along the first edge portion.

4. The semiconductor device according to claim 1, wherein one or more of the first external connection terminals are arranged on each of the first edge portion and a second edge portion of the housing member that faces the first edge portion.

5. The semiconductor device according to claim 1, wherein the case further includes a terminal holding member provided adjacent to the storage member in a direction along the first edge portion, and the semiconductor device further includes a second external connection terminal having a flat portion parallel to the upper surface of the storage member and held by the terminal holding member.

6. The semiconductor device according to claim 5, wherein the case, the first external connection terminal, and the second external connection terminal are integrally molded with the housing member sealing a portion of the first external connection terminal and the terminal holding member sealing a portion of the second external connection terminal.

7. The semiconductor device according to claim 1, wherein the housing member has a frame shape including the first edge portion that defines a second opening at the center when viewed from above, and the case further includes a lid member that closes the second opening.

8. The semiconductor device according to claim 1, wherein the housing member has a shape in which an inner region is closed relative to an outer side of the first edge portion in a plan view.

9. The semiconductor device according to claim 1, further comprising a wiring board between the upper surface of the circuit board and the lower surface of the first edge portion, facing the circuit board and spaced apart from the upper surface of the circuit board and the lower surface of the first edge portion, with a wiring hole penetrating into the lower region of the first edge portion in a planar view, wherein the lower end of the first external connection terminal protrudes from the lower surface of the first edge portion and is inserted into the wiring hole, and is electrically connected to the wiring board.

10. The semiconductor device according to claim 9, further comprising a semiconductor chip disposed on the upper surface of the circuit board, the wiring board further comprising wiring pins protruding from the lower surface of the wiring board, and the upper surface of the semiconductor chip and the lower ends of the wiring pins are joined via solder.

11. A method for manufacturing a semiconductor device, comprising: a preparation step of preparing a circuit board and a case including a housing member having a rectangular outer shape in a plan view for housing the circuit board, the case having a first external connection terminal held by a first edge portion that faces the outside of the housing member in a plan view and protruding perpendicularly to the upper surface of the first edge portion; a setting step of arranging the case and the circuit board so that the lower surface of the first edge portion faces the upper surface of the circuit board with a gap; and a sealing step of sealing the gap between the upper surface of the circuit board and the lower surface of the first edge portion with a sealing member.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the preparation step includes a molding step of sealing a portion of the first external connection terminal with a constituent material of the case, thereby integrally molding the housing member of the case and the first external connection terminal.

13. The method for manufacturing a semiconductor device according to claim 11, wherein the case includes a sidewall formed on the underside of the outer side of the first edge portion, and a first opening is formed on the underside of the sidewall, and in the sealing step, the sealing material is injected through the first opening into the region between the upper surface of the circuit board and the underside of the first edge portion.

14. A method for manufacturing a semiconductor device as described in claim 11, wherein the case further includes a terminal holding member provided adjacent to the storage member in a direction along the first edge portion, and the semiconductor device further includes a second external connection terminal having a flat portion parallel to the upper surface of the storage member and held by the terminal holding member, and the preparation step includes a molding step of sealing a portion of the first external connection terminal and a portion of the second external connection terminal with a constituent material of the case, and integrally molding the storage member and terminal holding member of the case with the first external connection terminal and the second external connection terminal.

15. A method for manufacturing a semiconductor device as described in claim 11, wherein the lower end of the first external connection terminal protrudes from the underside of the first edge portion, and the preparing step further comprises preparing a wiring board having a wiring hole passing therethrough, and the setting step includes: a first step of bringing the upper surface of the wiring board opposite the underside of the first edge portion, bringing the wiring board close to the first edge portion, and press-fitting the lower end of the first external connection terminal into the wiring hole while leaving a gap between the upper surface of the wiring board and the underside of the first edge portion, thereby electrically connecting the wiring hole and the first external connection terminal, and a second step of arranging the circuit board on the underside of the wiring board so that the underside of the wiring board faces the upper surface of the circuit board with a gap therebetween.

16. A method for manufacturing a semiconductor device according to claim 15, wherein a semiconductor chip is placed on the upper surface of the circuit board, and the wiring board further has wiring pins protruding from the lower surface of the wiring board, and further comprising, after completion of the second step, a step of joining the upper surface of the semiconductor chip and the lower ends of the wiring pins via solder in a region between the upper surface of the circuit board and the lower surface of the wiring board.

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