Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention makes it possible to accurately maintain the spacing of a case and a plurality of layers of substrates.　A case of this semiconductor device comprises: an exterior member (11a) facing the upper surface of a wiring board (20) and spaced a second distance from the upper surface of the wiring board (20); an external connection terminal (12a) which is fixed to the exterior member (11a) and the lower end of which is inserted into a wiring hole (22a) of the wiring board (20) and thus electrically connected to the wiring hole (22a); a first spacer member (14a) which protrudes from the lower surface of the exterior member (11a) and is inserted into a guide hole (23a) of the wiring board (20) and the lower end of which is in contact with the upper surface of a circuit board (30), the first spacer member (14a) maintaining a first gap (L1) between the lower surface of the exterior member (11a) and the upper surface of the circuit board (30); and a second spacer member (15a) which protrudes from the lower surface of the exterior member (11a) and the lower end of which is in contact with the upper surface of the wiring board (20), the second spacer member (15a) maintaining a second gap (L2) between the lower surface of the exterior member (11a) and the upper surface of the wiring board (20).

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] A semiconductor device has been proposed that includes a semiconductor mounting substrate on which a semiconductor element is mounted and an implant substrate arranged on the upper surface side of the substrate, in which the end of an implant pin pressed into a via hole provided in the implant substrate is joined and electrically connected to the semiconductor element (see, for example, Cited Document 1).

[0003] In addition, an in-vehicle semiconductor device has been proposed that includes a lower substrate, a positioning plate arranged on the upper side of the lower substrate, an upper substrate arranged on the upper side of the positioning plate, and vertical terminals that are inserted into terminal hole portions formed in both the lower substrate and the upper substrate (see, for example, Reference 2).

[0004] Furthermore, a semiconductor device has been proposed that includes a substrate on which a semiconductor element and first and second terminals are mounted, and a case that includes a terminal holding member that surrounds the first and second terminals (see, for example, Reference 3).

[0005] JP 2013-125803 A JP 2010-278093 A JP 2005-223141 A

[0006] An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can accurately maintain the gap between the case and the multilayer substrate.

[0007] According to one aspect of the invention, there is provided a semiconductor device having: a circuit board; a wiring board facing an upper surface of the circuit board and arranged with a first gap from the upper surface of the circuit board, the wiring board having wiring holes and guide holes therethrough; an exterior member facing the upper surface of the wiring board and arranged with a second gap from the upper surface of the wiring board; external connection terminals fixed to the exterior member and having lower ends inserted into the wiring holes of the wiring board to be electrically connected to the wiring holes; a first spacer member protruding from the lower surface of the exterior member and inserted into the guide holes of the wiring board, and having a lower end abutting the upper surface of the circuit board to maintain a first gap between the lower surface of the exterior member and the upper surface of the circuit board; and a sealing member that fills the first gap and the second gap to seal the wiring board.

[0008] According to one aspect of the invention, a method for manufacturing a semiconductor device includes a preparation step of preparing a case including a circuit board, a wiring board having wiring holes and guide holes therethrough, an exterior member for fixing external connection terminals having one end protruding from one main surface, a first spacer member protruding from the one main surface of the exterior member, and a second spacer member protruding from the one main surface of the exterior member and having a length from the one main surface shorter than that of the first spacer member, and a step of bringing the wiring board close to the exterior member from the one main surface side of the exterior member in the case, inserting the first spacer member into the guide holes, and inserting the external connection terminals into the wiring holes. A method for manufacturing a semiconductor device is provided, which includes a first setting step of inserting one end of a connection terminal to electrically connect the wiring hole and the external connection terminal and abutting the end of the second spacer member against the wiring board; a second setting step of positioning the circuit board opposite the wiring board on the side opposite the exterior member and abutting the first spacer member, which is inserted through the guide hole of the wiring board, against the circuit board; and a sealing step of filling a first gap between the circuit board and the wiring board and a second gap between the wiring board and the exterior member with a sealing member to seal the wiring board.

[0009] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0010] The disclosed technique allows accurate maintenance of the spacing between the case and the multi-layer substrate. These and other objects, features, and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings illustrating preferred embodiments of the present invention by way of example.

[0011] 1 is a plan view showing the appearance of a semiconductor device; FIG. 2 is a side view showing the appearance of a semiconductor device; FIG. 3 is a plan view of a semiconductor device with a sealing member and a lid member removed; FIG. 4 is a side view of a semiconductor device with a sealing member removed; FIG. 5 is a plan view of a wiring board; FIG. 6 is a plan view of a circuit board and external connection terminals; FIG. 7 is a diagram showing an example of a circuit configuration of a three-level inverter; FIG. 8 is a diagram showing the position of a spacer member; FIG. 9 is a cross-sectional view enlarging an attachment area of ​​a spacer member; FIG. 10 is a flowchart showing a manufacturing process of a semiconductor device; FIG. 11 is a diagram showing a process of attaching a wiring board to an exterior member; FIG. 12 is a diagram showing the position of a gate opening; FIG. 13 is a plan view showing a modified example of a spacer member; FIG. 14 is a plan view and a cross-sectional view enlarging an attachment area of ​​a spacer member.

[0012] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the X-axis and Y-axis are defined on a horizontal plane, the Z-axis is defined perpendicular to the horizontal plane, and the +Z direction is defined as the upper side and the -Z direction is defined as the lower side. Furthermore, the terms "upper surface," "top," "front surface," "lower surface," "bottom," "rear surface," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity.

[0013] First, the appearance of a semiconductor device according to an embodiment will be described with reference to Figures 1 and 2. Figure 1 is a plan view showing the appearance of the semiconductor device. Figure 2 is a side view showing the appearance of the semiconductor device. Note that Figure 2 is a side view of the semiconductor device 1 of Figure 1 when viewed in the +X direction.

[0014] The semiconductor device 1 is a modularized device that includes a circuit board on which a semiconductor chip is mounted, external connection terminals, etc. The semiconductor device 1 is attached to the front surface (the surface on the +Z direction side) of a cooling module (not shown). The cooling module may be, for example, a heat dissipation base with heat dissipation fins or a cooling device in which a refrigerant circulates inside.

[0015] The semiconductor device 1 has a case 10 that houses a wiring board 20 and a circuit board 30, which will be described later in FIG. 4. The case 10 includes a housing member 10a, terminal holding members 10b and 10c, and a lid member 10d. The terminal holding member 10b is integrally connected to the -Y direction side of the housing member 10a, and the terminal holding member 10c is integrally connected to the +Y direction side of the housing member 10a. The lid member 10d is provided in an opening 11c, which will be described later, provided in an exterior member 11a. In this case, the lid member 10d may be formed integrally with the exterior member 11a to close the opening 11c.

[0016] The storage member 10a is, for example, box-shaped and includes an exterior member 11a that forms an upper surface parallel to a horizontal plane (X-Y plane), a side wall parallel to the Y-Z plane, and another side wall parallel to the X-Y plane. The side walls parallel to the Y-Z plane are formed on the lower side (-Z direction side) of each end edge of the exterior member 11a in the +X direction and the -X direction. In FIG. 2, the side wall 11b on the -X direction side is shown, but the reference numeral for the side wall on the +X direction side is omitted. The side walls (reference numerals omitted) parallel to the X-Y plane are formed on the lower side of each end edge of the exterior member 11a in the +Y direction and the -Y direction.

[0017] The exterior member 11a and the side walls on the +X and −X sides may be flat and integrally connected. The side wall on the +Y side may be integral with the end face on the −Y side of the terminal holding member 10c, and the side wall on the −Y side may be integral with the end face on the +Y side of the terminal holding member 10b.

[0018] Furthermore, the storage member 10a is not limited to being box-shaped, and may include an exterior member 11a and side walls parallel to the XY plane formed on the underside of each end edge on the +Y direction side and the -Y direction side of the exterior member 11a.

[0019] The exterior member 11a has a rectangular outer shape in plan view. An opening 11c having a rectangular outer shape is formed in the center of the exterior member 11a in plan view. The opening 11c may be closed by a cover member 10d formed integrally with the exterior member 11a.

[0020] The housing member 10a includes an area (storage section) surrounded by the lower surface of the exterior member 11a, side walls on the +X and −X directions, and side walls on the +Y and −Y directions. The above-mentioned wiring board 20 and circuit board 30 are stored in this storage section. The exterior member 11a forms the upper exterior of the wiring board 20 and circuit board 30 stored in the storage section.

[0021] Meanwhile, openings for injecting the sealing member 40 are provided on the +X-direction side and the −X-direction side of the storage section. In this embodiment, as an example, sidewalls are also provided on the +X-direction side and the −X-direction side of the storage section, and an opening is provided in a portion of each sidewall. For example, FIG. 2 illustrates a sidewall 11b provided on the edge of the exterior member 11a on the −X-direction side. The sidewall 11b has an opening 11d that opens downward (toward the −Z direction). The opening 11d is formed between the sidewall (terminal holding member 10c) on the +Y-direction side and the sidewall (terminal holding member 10b) on the −Y-direction side of the storage member 10a. The interior of the storage section is sealed with the sealing member 40, and the opening 11d is blocked from the inside by the sealing member 40. Similarly, the opening 11c of the exterior member 11a is also blocked from the inside by the sealing member 40. As described above, the sealing member 40 that blocks the opening 11c is further blocked by the lid member 10d.

[0022] The exterior member 11a includes edge portions 11a1 and 11a2 (first and second regions) extending in the Y-axis direction on the −X and +X side portions of the opening 11c. External connection terminals 12a to 12d, 12i, and 12j are provided on the edge portion 11a1 of the exterior member 11a. External connection terminals 12e to 12h are provided on the edge portion 11a2 on the +X direction side of the exterior member 11a. The external connection terminals 12a to 12j are columnar and extend in a generally vertical direction. The columnar shape may be a rectangular columnar shape or a cylindrical columnar shape; here, a cylindrical press-fit pin is used as an example.

[0023] The external connection terminals 12a to 12d, 12i, and 12j are fixed to the edge portion 11a1 while penetrating the edge portion 11a1 in the vertical direction (±Z direction). The external connection terminals 12e to 12h are fixed to the edge portion 11a2 while penetrating the edge portion 11a2 in the vertical direction (±Z direction). The upper ends of the external connection terminals 12a to 12j protruding from the upper surface of the exterior member 11a serve as connection terminals for connecting to an external circuit. Meanwhile, the lower ends of the external connection terminals 12a to 12j protruding from the lower surface of the exterior member 11a are inserted into wiring holes provided in the wiring board 20 and electrically connected to wiring layers formed on the wiring board 20, as will be described later.

[0024] The terminal holding member 10b is provided with external connection terminals 13a to 13c. Flat plate portions 13a1 to 13c1 (see FIG. 6) are formed at the ends (outer ends) of the external connection terminals 13a to 13c on the −Y direction side. The external connection terminals 13a to 13c are held by the terminal holding member 10b with the upper surfaces of the flat plate portions 13a1 to 13c1 exposed on the upper surface of the terminal holding member 10b. The flat plate portions 13a1 to 13c1 exposed on the upper surface of the terminal holding member 10b serve as connection terminal portions for connecting to an external circuit. Meanwhile, the ends (inner ends) of the external connection terminals 13a to 13c on the +Y direction side are connected to a circuit pattern on the upper surface of the circuit board 30 inside the housing member 10a, as described below.

[0025] The terminal holding member 10c is provided with external connection terminals 13d. A flat plate portion 13d1 (see FIG. 6) is formed at the end (outer end) of the external connection terminal 13d on the +Y direction side. The external connection terminal 13d is held by the terminal holding member 10c with the upper surface of the flat plate portion 13d1 exposed on the upper surface of the terminal holding member 10c. The flat plate portion 13d1 exposed on the upper surface of the terminal holding member 10c serves as a connection terminal portion for connecting to an external circuit. Meanwhile, the end (inner end) of the external connection terminal 13d on the -Y direction side is connected to a circuit pattern on the upper surface of the circuit board 30 inside the housing member 10a, as described below.

[0026] In this embodiment, a three-level inverter circuit is configured by a wiring board 20, a circuit board 30, and a semiconductor chip (described later) housed inside the case 10. External connection terminals 13a to 13d correspond to the N terminal, P terminal, neutral terminal, and output terminal of the three-level inverter circuit, respectively. External connection terminals 12a to 12h correspond to control terminals for controlling the switching operations of transistors included in the three-level inverter circuit. External connection terminals 12i and 12j correspond to output terminals for outputting sense signals from the semiconductor chip that performs various sense operations.

[0027] The case 10, including the housing member 10a and the terminal holding members 10b and 10c, and a portion of the external connection terminals 12a to 12j and 13a to 13d, is integrally molded by injection molding using a thermoplastic resin. The lid member 10d may be separately formed by injection molding using a thermoplastic resin. Alternatively, the housing member 10a, the terminal holding members 10b and 10c, and the lid member 10d may be integrally molded by injection molding using a thermoplastic resin. Examples of thermoplastic resins include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, acrylonitrile butadiene styrene resin, and liquid crystal polymer. The external connection terminals 12a to 12j and 13a to 13d are formed from a metal with excellent conductivity. Examples of such metals include copper, aluminum, or an alloy containing at least one of these as a main component.

[0028] Fig. 3 is a plan view of the semiconductor device with the sealing member and the lid member removed, and Fig. 4 is a side view of the semiconductor device with the sealing member removed.

[0029] A wiring board 20 and a circuit board 30 are housed on the underside of the exterior member 11a. Both the wiring board 20 and the circuit board 30 have a rectangular shape in a plan view. The wiring board 20 is disposed with its upper surface facing the lower surface of the exterior member 11a, with a second gap between them. A plurality of wiring holes (described below) penetrate the wiring board 20, and the lower ends of the external connection terminals 12a to 12j are press-fitted into the corresponding wiring holes, thereby fixing the wiring board 20 to the exterior member 11a. The external connection terminals 12a to 12j are electrically connected to a wiring layer included in the wiring board 20. The circuit board 30 is disposed with its upper surface facing the lower surface of the wiring board 20, with a first gap between them and the lower surface of the exterior member 11a.

[0030] Multiple semiconductor chips are mounted on the upper surface of the circuit board 30. Figure 4 illustrates semiconductor chips 31b1, 31b2, 31d1, 31d2, and 31e among these semiconductor chips. Meanwhile, multiple cylindrical wiring pins extending vertically are inserted into the wiring board 20, with the upper end of each wiring pin electrically connected to a wiring layer included in the wiring board 20 and the lower end of each wiring pin electrically connected via solder to output electrodes and control electrodes on the upper surface of the corresponding semiconductor chip. For example, in Figure 4, wiring pins 21a and 21b are provided on the wiring board 20, and the lower ends of wiring pins 21a and 21b are electrically connected via solder to the upper surfaces of semiconductor chips 31b1 and 31e, respectively. Therefore, external connection terminals 12a to 12j are electrically connected to the output electrodes and control electrodes of the semiconductor chips via the wiring board 20 and each wiring pin.

[0031] Furthermore, with the wiring board 20 and the circuit board 30 arranged on the exterior member 11a as described above, a sealing member 40 is filled in at least the area between the lower surface of the exterior member 11a and the upper surface of the circuit board 30, and the wiring board 20 and the semiconductor chip are sealed by the sealing member 40. In this embodiment, in a plan view, the periphery of the circuit board 30 and the lower sidewalls of the exterior member 11a are not in contact with the terminal holding members 10b and 10c. Therefore, the sealing member 40 is filled to cover the side surfaces of the circuit board 30, and the back surface of the circuit board 30 is exposed from the back surface (the surface on the -Z direction side) of the housing member 10a (case 10). Furthermore, the back surface of the circuit board 30 may be flush with the back surfaces of the housing member 10a and the terminal holding members 10b and 10c of the case 10.

[0032] A thermosetting resin is used as the sealing material for the sealing member 40. The thermosetting resin is, for example, an epoxy resin. By using such a resin and performing transfer molding on the case 10 housing the wiring board 20, the circuit board 30, and the semiconductor chip, a highly rigid semiconductor device 1 is manufactured. In particular, high rigidity in the vertical direction (Z-axis direction) of the semiconductor device 1 is obtained, and even when an external force is applied in the vertical direction, a predetermined distance can be maintained between the exterior member 11a and the wiring board 20, and between the wiring board 20 and the circuit board 30.

[0033] 5 is a plan view of the wiring board 20. The wiring board 20 is, for example, a multilayer printed circuit board (PCB). In the wiring board 20, for example, a wiring layer may be formed on at least one of the upper and lower surfaces of an insulating layer, and one or more wiring layers may also be formed inside the insulating layer.

[0034] The insulating layer is formed of, for example, an insulating resin. Examples of insulating resins include a paper phenol substrate, a paper epoxy substrate, a glass composite substrate, and a glass epoxy substrate. The wiring layer is formed of a metal with excellent conductivity. Examples of such metals include copper, aluminum, or an alloy containing at least one of these as a main component.

[0035] The wiring board 20 is provided with a plurality of wiring holes (through holes) penetrating the wiring board 20, and wiring pins are inserted into each wiring hole. The wiring pins are formed of a metal with excellent conductivity. Each wiring hole is connected to a circuit pattern of one of the wiring layers formed on the wiring board 20, and the wiring pins are electrically connected to the circuit patterns connected to the wiring holes into which they are inserted. These wiring pins protrude at least below the corresponding wiring hole. The wiring pins may also protrude above the corresponding wiring hole to an extent that they do not contact the lower surface of the exterior member 11a. Note that FIG. 5 illustrates wiring pins 21a and 21b as such wiring pins. As shown in FIG. 4, the lower ends of the wiring pins 21a and 21b are electrically connected via solder to output electrodes and control electrodes on the upper surfaces of the semiconductor chips 31b1 and 31e mounted on the circuit board 30.

[0036] Wiring holes (through holes) 22a to 22j penetrate the wiring board 20. The wiring holes 22a to 22d, 22i, and 22j are arranged along a first edge 20a on the −X direction side of the wiring board 20. When the wiring board 20 is attached to the exterior member 11a, the area of ​​this first edge 20a faces the lower surface of the edge 11a1 of the exterior member 11a. The lower ends of the external connection terminals 12a to 12d, 12i, and 12j are inserted into the wiring holes 22a to 22d, 22i, and 22j, respectively. The wiring holes 22e to 22h are arranged along a second edge 20b on the +X direction side of the wiring board 20. When the wiring board 20 is attached to the exterior member 11a, the area of ​​this second edge 20b faces the lower surface of the edge 11a2 of the exterior member 11a. The lower ends of the external connection terminals 12e to 12h are inserted into the wiring holes 22e to 22h, respectively.

[0037] The wiring holes 22a to 22j are also connected to the circuit pattern of one of the wiring layers formed on the wiring board 20. When the lower ends of the external connection terminals 12a to 12j are inserted into the wiring holes 22a to 22j, the external connection terminals 12a to 12j are electrically connected to the circuit patterns connected to the inserted wiring holes 22a to 22j.

[0038] In addition, via holes may be formed through the wiring substrate 20 to electrically connect the wiring layers together.

[0039] Furthermore, guide holes 23a to 23d penetrate the wiring board 20. Here, guide holes 23a and 23b are arranged along edge 11a1 in a region below edge 11a1 of the exterior member 11a in a plan view when the wiring board 20 is attached to the exterior member 11a. Furthermore, guide holes 23c and 23d are arranged along edge 11a2 in a region below edge 11a2 of the exterior member 11a in a plan view when the wiring board 20 is attached to the exterior member 11a. Details of guide holes 23a to 23d will be described later.

[0040] 6 is a plan view of the circuit board and the external connection terminals. Circuit board 30 includes an insulating plate 32 forming the bottom surface, circuit patterns 33a to 33g formed on the upper surface (the surface on the +Z direction side) of insulating plate 32, and a metal plate (not shown) formed on the lower surface (the surface on the -Z direction side) of insulating plate 32. Semiconductor chips 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, 31d1 to 31d4, and 31e are mounted on circuit board 30.

[0041] The insulating plate 32 is made of, for example, a resin. The resin may be a material with low thermal resistance and high insulation properties, such as a thermosetting resin or a thermoplastic resin. Examples of thermosetting resins include at least one of epoxy resin, cyanate resin, polyimide resin, benzoxazine resin, unsaturated polyester resin, phenolic resin, melamine resin, silicone resin, and maleimide resin. Examples of thermoplastic resins include at least one of acrylic resin and polyamide resin. These resins may further contain a filler. The filler may be made of at least one of an oxide and a nitride. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Furthermore, the filler may be hexagonal boron nitride.

[0042] The insulating plate 32 may be a ceramic substrate instead of a resin. The ceramic substrate is made of ceramic with good thermal conductivity. For example, the ceramic is made of a material whose main components are aluminum oxide, aluminum nitride, or silicon nitride. For the insulating circuit board 30 including the insulating plate 32 having such a configuration, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate can be used.

[0043] In this embodiment, the insulating plate 32 is made of resin, and the difference between the linear expansion coefficient of the insulating plate 32 and the linear expansion coefficient of the metal plate and circuit patterns 33a to 33g is small.

[0044] The circuit patterns 33a to 33f and the metal plate are made of a metal with excellent conductivity, such as copper, aluminum, or an alloy containing at least one of these as a main component.

[0045] The semiconductor chips 31a1-31a4, 31b1-31b4, 31c1-31c4, and 31d1-31d4 may be power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) primarily made of silicon carbide. The body diode of the power MOSFET may function as a free wheeling diode (FWD). Each of the semiconductor chips 31a1-31a4, 31b1-31b4, 31c1-31c4, and 31d1-31d4 has, for example, an input electrode (drain electrode) as a main electrode on the back surface and an output electrode (source electrode) and a control electrode (gate electrode) as main electrodes on the front surface.

[0046] The semiconductor chips 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, and 31d1 to 31d4 may also include switching elements primarily composed of silicon. The switching elements may be, for example, reverse-conducting (RC) insulated gate bipolar transistors (IGBTs). RC-IGBTs are semiconductor elements in which an IGBT and a FWD are arranged in anti-parallel within a single chip. Each of these semiconductor chips 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, and 31d1 to 31d4 has, for example, an input electrode (collector electrode) as a main electrode on its back surface and an output electrode (emitter electrode) and a control electrode (gate electrode) as main electrodes on its front surface.

[0047] The semiconductor chips 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, and 31d1 to 31d4 may each include a pair of switching elements and diode elements made primarily of silicon. The switching elements may be, for example, power MOSFETs or IGBTs. The semiconductor chips including the switching elements include, for example, an input electrode (a drain electrode in a power MOSFET or a collector electrode in an IGBT) as a main electrode on the back surface, and a gate electrode (a source electrode in a power MOSFET or an emitter electrode in an IGBT) as a control electrode and an output electrode (a source electrode in a power MOSFET or an emitter electrode in an IGBT) as a main electrode on the front surface. The diode elements may include, for example, Schottky Barrier Diodes (SBDs) or P-intrinsic-N (PiN) diodes as FWDs. The semiconductor chips including the diode elements include, for example, an output electrode (a cathode electrode) as a main electrode on the back surface, and an input electrode (anode electrode) as a main electrode on the front surface.

[0048] In this embodiment, the semiconductor chips 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, and 31d1 to 31d4 are power MOSFETs made mainly of silicon carbide.

[0049] Semiconductor chips 31c1 to 31c4 are mounted on the upper surface of circuit pattern 33c. Although not shown in the figure, input electrodes on the lower surfaces of semiconductor chips 31c1 to 31c4 are electrically connected to the upper surface of circuit pattern 33c via solder. Semiconductor chips 31d1 to 31d4 are mounted on the upper surface of circuit pattern 33d. Although not shown in the figure, input electrodes on the lower surfaces of semiconductor chips 31d1 to 31d4 are electrically connected to the upper surface of circuit pattern 33d via solder. Semiconductor chips 31a1 to 31a4 and 31b1 to 31b4 are mounted on the upper surface of circuit pattern 33e. Although not shown in the figure, input electrodes on the lower surfaces of semiconductor chips 31a1 to 31a4 and 31b1 to 31b4 are electrically connected to the upper surface of circuit pattern 33e via solder.

[0050] A semiconductor chip 31e is mounted on the upper surface of the circuit pattern 33g. The semiconductor chip 31e includes semiconductor elements that perform various sensing operations. For example, the semiconductor chip 31e includes a diode element that detects temperature. Although not shown, electrodes provided on the lower surface of the semiconductor chip 31e are electrically connected to the upper surface of the circuit pattern 33g via solder.

[0051] The circuit pattern 33a is electrically connected to the external connection terminal 13a. Specifically, a flat plate portion 13a1 is formed at the end of the external connection terminal 13a on the -Y direction side. Furthermore, a horizontally flat plate-shaped connection portion 13a2 is formed at the end of the flat plate portion 13a1 of the external connection terminal 13a on the +Y direction side, with an intermediate portion (not shown) extending downward (in the -Z direction) interposed therebetween. The lower surface of the connection portion 13a2 is joined to the upper surface of the circuit pattern 33a.

[0052] The circuit pattern 33b is electrically connected to the external connection terminal 13c. Specifically, a flat plate portion 13c1 is formed at the end of the external connection terminal 13c on the -Y direction side. Furthermore, a horizontally flat plate-shaped connection portion 13c2 is formed at the end of the flat plate portion 13c1 of the external connection terminal 13c on the +Y direction side, via an intermediate portion (not shown) that extends downward (in the -Z direction). The lower surface of the connection portion 13c2 is joined to the upper surface of the circuit pattern 33b.

[0053] The circuit pattern 33d is electrically connected to the external connection terminal 13b. Specifically, a flat plate portion 13b1 is formed at the end of the external connection terminal 13b on the -Y direction side. Furthermore, a horizontally flat plate-shaped connection portion 13b2 is formed at the end of the flat plate portion 13b1 of the external connection terminal 13b on the +Y direction side, via an intermediate portion (not shown) that extends downward (in the -Z direction). The lower surface of the connection portion 13b2 is joined to the upper surface of the circuit pattern 33d.

[0054] The circuit pattern 33f is electrically connected to the external connection terminal 13d. Specifically, a flat plate portion 13d1 is formed at the end of the external connection terminal 13d on the +Y direction side. Furthermore, a horizontally flat plate-shaped connection portion 13d2 is formed at the end of the flat plate portion 13d1 of the external connection terminal 13d on the -Y direction side, via an intermediate portion (not shown) that extends downward (in the -Z direction). The lower surface of the connection portion 13d2 is joined to the upper surface of the circuit pattern 33f.

[0055] FIG. 7 is a diagram showing an example of the circuit configuration of a three-level inverter. The semiconductor device 1 includes, for example, a three-level inverter as shown in FIG. 7. This three-level inverter is a T-type NPC (Neutral Point Clamped) inverter circuit and includes four transistors Q1 to Q4. The transistor Q1 corresponds to the semiconductor chips 31d1 to 31d4, and the transistor Q2 corresponds to the semiconductor chips 31c1 to 31c4. The transistor Q3 corresponds to the semiconductor chips 31b1 to 31b4, and the transistor Q4 corresponds to the semiconductor chips 31a1 to 31a4.

[0056] The drain electrode of transistor Q1 is connected to the P terminal, which is the positive input terminal, via circuit board 30. The P terminal corresponds to external connection terminal 13b. The source electrode of transistor Q2 is connected to the N terminal, which is the negative input terminal, via wiring board 20 and circuit board 30. The N terminal corresponds to external connection terminal 13a.

[0057] The drain electrode of transistor Q3 and the drain electrode of transistor Q4 are connected via circuit board 30, and the source electrode of transistor Q3 is connected to terminal M (neutral terminal), which is an input terminal of intermediate potential, via wiring board 20 and circuit board 30. Terminal M corresponds to external connection terminal 13c.

[0058] The source electrode of transistor Q1, the drain electrode of transistor Q2, and the source electrode of transistor Q4 are connected via circuit board 30 and wiring board 20, and the connection point between these is connected to the U terminal, which is an output terminal, via wiring board 20 and circuit board 30. The U terminal corresponds to external connection terminal 13d.

[0059] The gate electrodes of transistors Q1 to Q4 are connected to gate terminals (control terminals) G1 to G4, which are input terminals for control signals for switching operations, via wiring board 20. Gate terminals G1 to G4 correspond to external connection terminals 12c, 12g, 12b, and 12f, respectively. Source electrodes of transistors Q1 to Q4 are connected to auxiliary source terminals S1 to S4, which are output terminals, via wiring board 20. Auxiliary source terminals S1 to S4 correspond to external connection terminals 12d, 12h, 12a, and 12e, respectively.

[0060] In this three-level inverter, when the control signal to gate terminals G1 and G2 is on and the control signal to gate terminals G3 and G4 is off, the output voltage from the U terminal is E / 2. When the control terminal to gate terminals G2 and G3 is on and the control terminal to gate terminals G1 and G4 is off, the output voltage from the U terminal is 0. When the control signal to gate terminals G3 and G4 is on and the control signal to gate terminals G1 and G2 is off, the output voltage from the U terminal is -E / 2.

[0061] The semiconductor device 1 of this embodiment is equipped with four sets of transistors Q1 to Q4. Therefore, the semiconductor device 1 includes four sets of three-level inverters each including the transistors Q1 to Q4. These three-level inverters are connected in parallel. Although not shown in the figure, three semiconductor devices 1 each including such parallel three-level inverters are used in combination. One semiconductor device 1 generates a U-phase output voltage, another semiconductor device 1 generates a V-phase output voltage, and another semiconductor device 1 generates a W-phase output voltage.

[0062] Next, the spacer members for positioning the wiring board 20 and the circuit board 30 relative to the exterior member 11a of the case 10 will be described with reference to FIGS.

[0063] 8 is a diagram showing the positions of the spacer members. First spacer members 14a to 14d and second spacer members 15a to 15d are provided on the underside of the exterior member 11a of the case 10. The first spacer members 14a, 14b and the second spacer members 15a, 15b protrude from the underside of the edge portion 11a1 (see FIG. 1) of the exterior member 11a. The first spacer members 14c, 14d and the second spacer members 15c, 15d protrude from the underside of the edge portion 11a2 (see FIG. 1) of the exterior member 11a.

[0064] The first spacer members 14a to 14d and the second spacer members 15a to 15d are columnar in shape. In this embodiment, the first spacer members 14a to 14d and the second spacer members 15a to 15d are cylindrical in shape, but they may also be rectangular in shape. The vertical length (L1) of the first spacer members 14a to 14d is the same. The vertical length (L2) of the second spacer members 15a to 15d is the same and is shorter than that of the first spacer members 14a to 14d.

[0065] When the wiring board 20 is attached to the exterior member 11a, the lower ends of the second spacer members 15a-15d abut against the upper surface of the wiring board 20. This maintains the distance between the lower surface of the exterior member 11a and the upper surface of the wiring board 20 at a predetermined second distance L2. In this state, the first spacer members 14a-14d are inserted through guide holes 23a-23d (see FIG. 5) provided in the wiring board 20, respectively, and the lower ends of the first spacer members 14a-14d abut against the upper surface of the circuit board 30. This maintains the distance between the lower surface of the exterior member 11a and the upper surface of the circuit board 30 at the predetermined first distance L1, and as a result, the distance between the lower surface of the wiring board 20 and the upper surface of the circuit board 30 is also maintained at a predetermined distance. At the same time, the insertion of the first spacer members 14a-14d through the guide holes 23a-23d, respectively, determines the horizontal position of the wiring board 20 relative to the exterior member 11a.

[0066] Fig. 9 is an enlarged cross-sectional view of the mounting area of ​​the spacer member. Fig. 9 is an enlarged cross-sectional view of area A1 in Fig. 8 taken along line I1-I1. However, it is assumed that wiring board 20 and circuit board 30 are mounted inside case 10 as shown in Figs. 3 and 4.

[0067] In region A1, external connection terminals 12a and 12b are fixed to edge portion 11a1 of exterior member 11a while perpendicularly penetrating edge portion 11a1. The lower ends of external connection terminals 12a and 12b are inserted into wiring holes 22a and 22b, respectively, formed in wiring substrate 20. For example, circuit patterns 24a and 24b are formed on the upper surface of wiring substrate 20 at positions surrounding wiring holes 22a and 22b, respectively. Inserting the lower ends of external connection terminals 12a and 12b into wiring holes 22a and 22b electrically connects external connection terminals 12a and 12b to circuit patterns 24a and 24b, respectively. Press-fitting the lower ends of external connection terminals 12a and 12b into wiring holes 22a and 22b fixes wiring substrate 20 to edge portion 11a1 of exterior member 11a.

[0068] In region A1, a first spacer member 14a and a second spacer member 15a protrude from the lower surface of edge portion 11a1 of exterior member 11a. Of these, the lower end of second spacer member 15a abuts against the upper surface of wiring board 20. This maintains a second distance L2, which is the vertical length of second spacer member 15a, between the lower surface of edge portion 11a1 and the upper surface of wiring board 20.

[0069] Here, the second distance L2 is set in advance so that the lower ends of the external connection terminals 12a, 12b reach the lower ends of the wiring holes 22a, 22b or a predetermined position beyond those lower ends. As a result, when the external connection terminals 12a, 12b attached to the exterior member 11a are press-fitted into the wiring holes 22a, 22b of the wiring board 20, the predetermined second distance L2 can be set between the lower surface of the edge portion 11a1 of the exterior member 11a and the upper surface of the wiring board 20 simply by press-fitting them until the tip of the second spacer member 15a abuts on the upper surface of the wiring board 20. Therefore, high positioning accuracy in the vertical direction can be obtained through a simple manufacturing process, and the assembly workability of the semiconductor device 1 can be improved.

[0070] Furthermore, first spacer member 14a is inserted through guide hole 23a provided in wiring board 20, and its lower end abuts against the upper surface of circuit board 30. This maintains a first distance L1, which is the vertical length of first spacer member 14a, between the lower surface of edge portion 11a1 and the upper surface of circuit board 30. As a result, it is possible to maintain a desired distance between the lower surface of wiring board 20 and the upper surface of circuit board 30.

[0071] 9, wiring pins 21a are inserted through wiring board 20 and are electrically connected to, for example, circuit patterns 24c formed on the upper surface of wiring board 20. Meanwhile, circuit patterns 33e are formed on the upper surface of insulating plate 32 of circuit board 30, and semiconductor chip 31b1 is mounted on the upper surface of circuit pattern 33e via solder 34a. The lower ends of wiring pins 21a are joined to the upper surface of semiconductor chip 31b1 via solder 34b.

[0072] As described above, a gap is required between the lower surface of the wiring substrate 20 and the upper surface of the circuit substrate 30 to bond the wiring pins and the semiconductor chip via solder. As described above, the lower ends of the first spacer member 14a and the second spacer member 15a abut against the upper surfaces of the wiring substrate 20 and the circuit substrate 30, respectively, making it possible to easily maintain a desired gap between the lower surface of the wiring substrate 20 and the upper surface of the circuit substrate 30.

[0073] Furthermore, by inserting the first spacer member 14a through the guide hole 23a, the horizontal position of the wiring board 20 relative to the exterior member 11a can be accurately determined with a simple operation. In particular, as described above, when attaching the wiring board 20, the external connection terminals 12a, 12b are inserted into the wiring holes 22a, 22b of the wiring board 20. At this time, by inserting the first spacer member 14a first into the guide hole 23a of the wiring board 20, the positions of the ends of the external connection terminals 12a, 12b can be easily aligned with the positions of the wiring holes 22a, 22b.

[0074] As shown in FIG. 9 , the lower end portion of the first spacer member 14a (the tip portion that abuts against the wiring board 20) has a shape in which the cross-sectional area tapers toward the lower end. This makes it easier to insert the first spacer member 14a into the guide hole 23a. For example, even if the center of the diameter of the first spacer member 14a does not exactly coincide with the center of the diameter of the guide hole 23a in a plan view, the first spacer member 14a can be inserted into the guide hole 23a. This improves the workability when attaching the wiring board 20 to the exterior member 11a. The lower ends of the other first spacer members 14b to 14d also have a shape similar to that of the first spacer member 14a.

[0075] Furthermore, the following can be said about pairs of adjacent first and second spacer members (spacer member pairs) among the first spacer members 14a-14d and the second spacer members 15a-15d. In order to stably maintain a constant distance between the lower surface of the exterior member 11a and the upper surface of the wiring board 20 over the entire opposing surfaces, it is desirable to arrange two or more pairs of spacer members on one edge of the exterior member 11a (e.g., edge 11a1) and one or more pairs of spacer members on the other opposing edge. In this case, it is desirable to arrange two or more pairs of spacer members on one edge near both ends in the Y-axis direction, and to arrange two or more pairs of spacer members on the other edge near the center in the Y-axis direction.

[0076] Furthermore, when four or more pairs of spacer members are arranged, it is desirable to arrange the spacer member pairs at positions close to one end and the other end of one edge in the Y-axis direction, and at positions close to one end and the other end of the other edge in the Y-axis direction (i.e., positions close to the four corners of the outer casing member 11a, which has a rectangular shape when viewed in a plane).

[0077] 10 to 12, the manufacturing process of the semiconductor device 1 will be described. Fig. 10 is a flowchart showing the manufacturing process of the semiconductor device.

[0078] [Process P1] The case 10, wiring board 20, and circuit board 30 are fabricated. In fabricating the case 10, for example, a predetermined mold in which external connection terminals 12a-12j, 13a-13d are set is filled with resin. The mold is then removed, and the case 10 is fabricated, which includes the external connection terminals 12a-12j, 13a-13d, respectively, and in which the housing member 10a, terminal holding members 10b, 10c, and lid member 10d are integrally molded. At this time, the exterior member 11a of the case 10 is provided with first spacer members 14a-14d and second spacer members 15a-15d.

[0079] A circuit pattern is formed on the wiring board 20, and wiring holes 22a-22j and guide holes 23a-23d are penetrated to attach wiring pins. A circuit pattern is formed on the circuit board 30, and semiconductor chips 31a1-31a4, 31b1-31b4, 31c1-31c4, 31d1-31d4, and 31e are joined via solder. In this case, a metal sintered material may be used instead of solder.

[0080] [Process P2] The wiring board 20 is set in the case 10. In this process, the case 10 and the wiring board 20 are inverted upside down, and the wiring board 20 is attached to the back surface of the exterior member 11a of the case 10 (the surface from which the first and second spacer members protrude). First, the wiring board 20 is brought close to the back surface of the exterior member 11a, and the first spacer members 14a to 14d are inserted into the guide holes 23a to 23d of the wiring board 20. Next, the first spacer members 14a to 14d pass through the guide holes 23a to 23d, and the ends of the external connection terminals 12a to 12j are inserted into the wiring holes 22a to 22j of the wiring board 20. As the wiring board 20 is pressed against the exterior member 11a, the external connection terminals 12a to 12j are press-fit into the wiring holes 22a to 22j. Such press-fitting is continued until the ends of the second spacer members 15 a to 15 d come into contact with the wiring board 20 .

[0081] [Process P3] The circuit board 30 is set on the case 10 to which the wiring board 20 has been attached. In this process, the vertical orientation of the case 10 is changed so that the main surface of the case 10 (the surface on which the external connection terminals 13a-13d are exposed) faces upward. Furthermore, solder is applied to the electrodes on the upper surfaces of the semiconductor chips 31a1-31a4, 31b1-31b4, 31c1-31c4, 31d1-31d4, and 31e on the circuit board 30 to bond them to the corresponding wiring pins. The circuit board 30 is then brought closer to the underside of the exterior member 11a, and positioned so that the ends of the first spacer members 14a-14d abut the upper surface of the circuit board 30.

[0082] Here, in a state where the ends of the second spacer members 15a to 15d abut against the wiring board 20 in process P2 and the ends of the first spacer members 14a to 14d abut against the circuit board 30 in process P3, a desired distance is maintained between the lower surface of the exterior member 11a and the upper surface of the wiring board 20, and between the lower surface of the wiring board 20 and the upper surface of the circuit board 30. In this way, the vertical lengths of the first spacer members 14a to 14d and the second spacer members 15a to 15d maintain the above-mentioned distances, thereby improving the workability of attaching the wiring board 20 and the circuit board 30 to the case 10.

[0083] [Process P4] Reflow is performed. The case 10 in which the wiring board 20 and the circuit board 30 are set in process P3 is heated, and the solder is melted. After the solder melts, it is cooled and solidified, and the electrodes on the top surfaces of the semiconductor chips 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, 31d1 to 31d4, and 31e are joined to the corresponding wiring pins via the solder.

[0084] [Step P5] The case 10 is set in the cavity of a predetermined molding device. In the molding device, the molten sealing material in the pod is pressurized by a plunger and sent from the pod to a runner, and the sealing material is injected through a gate, described below, into the openings (including opening 11d) on the side of the housing member 10a in the X-axis direction. The sealing material injected into the inside of the case 10 hardens, and the wiring board 20, the circuit board 30, and the semiconductor chips 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, 31d1 to 31d4, and 31e are sealed with sealing material 40. This transfer molding of the case 10 results in the semiconductor device 1 shown in FIGS. 1 and 2.

[0085] 11 is a diagram showing a process of attaching a wiring board to an exterior member, which is an enlarged cross-sectional view of region A1 in FIG. 8 taken along line I1-I1 in step P2 of FIG.

[0086] As described above, in step P2, the case 10 and the wiring board 20 are in an upside-down state. In this state, the wiring board 20 is brought closer to the rear surface of the exterior member 11a of the case 10 (the surface from which the first spacer member 14a and the second spacer member 15a protrude). Here, the amount of protrusion of the first spacer member 14a from the rear surface of the exterior member 11a is greater than the amount of protrusion of the external connection terminals 12a, 12b. Therefore, before the ends of the external connection terminals 12a, 12b are inserted into the wiring holes 22a, 22b of the wiring board 20, the end of the first spacer member 14a is inserted into the guide hole 23a of the wiring board 20 (step P2-1).

[0087] As described above, the tip portion of the first spacer member 14a (the tip portion that abuts against the wiring substrate 20) has a shape in which the cross-sectional area tapers toward the end. This makes it easier to insert the first spacer member 14a into the guide hole 23a in process P2-1. For example, even if the center of the diameter of the first spacer member 14a does not exactly coincide with the center of the diameter of the guide hole 23a in a plan view, the first spacer member 14a can be inserted into the guide hole 23a. This improves the workability of aligning the first spacer member 14a with the guide hole 23a.

[0088] As the wiring board 20 moves closer to the exterior member 11a, the ends 12a1 and 12b1 of the external connection terminals 12a and 12b are inserted into the wiring holes 22a and 22b of the wiring board 20 (step P2-2). At this time, the first spacer members 14a are inserted into the guide holes 23a, so that the horizontal position of the wiring board 20 is aligned with the exterior member 11a. This allows the ends 12a1 and 12b1 of the external connection terminals 12a and 12b to be smoothly inserted into the wiring holes 22a and 22b.

[0089] In particular, since the external connection terminals 12a, 12b are press-fitted into the wiring holes 22a, 22b, high accuracy is required for aligning the ends 12a1, 12b1 of the external connection terminals 12a, 12b with the wiring holes 22a, 22b. By inserting the first spacer member 14a into the guide hole 23a as described above, the accuracy of such alignment can be improved, thereby improving the workability of the press-fitting. Furthermore, the possibility of damage to the component caused by press-fitting the external connection terminals 12a, 12b while they are misaligned with the wiring holes 22a, 22b can be reduced.

[0090] Fig. 12 is a diagram showing the position of the gate opening, and Fig. 12 shows a plan view and a side view of the semiconductor device 1 with the sealing member 40 and the lid member 10d removed.

[0091] As described above, openings are formed in the sidewalls of the housing member 10a in the X-axis direction. For example, opening 11d is formed in sidewall 11b on the -X direction side. In step P5 of Figure 10, sealing member 40 is injected through these openings to seal the inside of case 10.

[0092] 12, in this embodiment, for example, only a partial area of ​​opening 11d is enlarged upward (in the +Z direction), and the enlarged area constitutes gate openings 16a and 16b for injecting the sealing material for sealing member 40 in step P5 of Fig. 10. In the example of Fig. 12, the sealing material for sealing member 40 is injected in the +X direction relative to gate openings 16a and 16b.

[0093] Here, the first spacer members 14a, 14b and the second spacer members 15a, 15b formed on the edge portion 11a1 of the exterior member 11a are desirably formed at positions offset from the gate openings 16a, 16b in the direction along the edge portion 11a1 (the Y-axis direction). This prevents the spacer members from obstructing the flow of the sealing material of the sealing member 40 from the gate openings 16a, 16b. By offsetting the positions of the first spacer members 14a, 14b from the gate openings 16a, 16b, the sealing member 40 is properly filled inside the case 10, preventing a decrease in insulation and a decrease in the reliability of the semiconductor device 1.

[0094] Next, a description will be given of a modified example in which the shapes of the first spacer member and the second spacer member are changed. In the above embodiment, the first spacer member and the second spacer member are provided as separate columnar members. However, the first spacer member and the second spacer member may be provided as an integrated member.

[0095] Fig. 13 is a plan view showing a modified example of the spacer member, Fig. 13 shows a plan view of the case 10 provided with the modified example of the spacer member.

[0096] 13, the first spacer members 17a to 17d and the second spacer members 18a to 18d are provided near the four corners of the exterior member 11a in a plan view on the underside of the exterior member 11a of the case 10. That is, the first spacer members 17a, 17b and the second spacer members 18a, 18b are provided on the underside of the edge portion 11a1 (see FIG. 1) of the exterior member 11a, and the first spacer members 17c, 17d and the second spacer members 18c, 18d are provided on the underside of the edge portion 11a2 (see FIG. 1) of the exterior member 11a.

[0097] The first spacer member 17a and the second spacer member 18a are formed as an integrated member. The second spacer member 18a is a columnar member that protrudes from the lower surface (the surface on the -Z direction side) of the exterior member 11a. The vertical length of the second spacer member 18a is L2 (see FIG. 9). The first spacer member 17a is a columnar member that shares the same central axis as the second spacer member 18a and has a smaller cross-sectional area than the second spacer member 18a, and is provided to protrude from the lower end of the second spacer member 18a. The length from the lower surface of the exterior member 11a to the lower end of the first spacer member 17a is L1 (see FIG. 9).

[0098] Similarly, the first spacer member 17b and the second spacer member 18b are formed as an integral member. The second spacer member 18b is a columnar member that protrudes from the lower surface of the exterior member 11a, and the vertical length of the second spacer member 18b is L2. The first spacer member 17b is a columnar member that shares the same central axis as the second spacer member 18b and has a smaller cross-sectional area than the second spacer member 18b, and is provided to protrude from the lower end of the second spacer member 18b. The length from the lower surface of the exterior member 11a to the lower end of the first spacer member 17b is L1.

[0099] The first spacer member 17c and the second spacer member 18c are formed as an integrated member. The second spacer member 18c is a columnar member that protrudes from the lower surface of the exterior member 11a, and the vertical length of the second spacer member 18c is L2. The first spacer member 17c is a columnar member that shares the same central axis as the second spacer member 18c and has a smaller cross-sectional area than the second spacer member 18c, and is provided to protrude from the lower end of the second spacer member 18c. The length from the lower surface of the exterior member 11a to the lower end of the first spacer member 17c is L1.

[0100] The first spacer member 17d and the second spacer member 18d are formed as an integrated member. The second spacer member 18d is a columnar member that protrudes from the lower surface of the exterior member 11a, and the vertical length of the second spacer member 18d is L2. The first spacer member 17d is a columnar member that shares the same central axis as the second spacer member 18d and has a smaller cross-sectional area than the second spacer member 18d, and is provided to protrude from the lower end of the second spacer member 18d. The length from the lower surface of the exterior member 11a to the lower end of the first spacer member 17d is L1.

[0101] Guide holes (corresponding to guide holes 23a to 23d in FIG. 7) corresponding to the first spacer members 17a to 17d, respectively, are formed through the wiring board 20. When the wiring board 20 is attached to the lower surface of the exterior member 11a, the ends of the first spacer members 17a to 17d are inserted into the corresponding guide holes of the wiring board 20. For example, if the first spacer members 17a to 17d are cylindrical, the diameter of the guide holes will be the same as the diameter of the first spacer members 17a to 17d.

[0102] In FIG. 13 and the following FIG. 14, the first spacer members 17a to 17d and the second spacer members 18a to 18d are cylindrical, but they may also be prismatic, for example.

[0103] Fig. 14 shows an enlarged plan view and a cross-sectional view of the mounting area of ​​the spacer member. The plan view of Fig. 14 is an enlarged view of area A2 of Fig. 13. The cross-sectional view of Fig. 14 shows a cross-sectional view of the area of ​​the plan view of Fig. 14 taken along line I2-I2 of Fig. 13. However, in the cross-sectional view of Fig. 14, it is assumed that the wiring board 20 and the circuit board 30 are mounted on the case 10 as in Figs. 3 and 4.

[0104] As described above, the first spacer member 17a is a columnar member that has the same central axis as the second spacer member 18a and a smaller cross-sectional area than the second spacer member 18a, and is provided to protrude from the lower end of the second spacer member 18a. When the wiring board 20 is attached to the lower surface of the exterior member 11a of the case 10, the first spacer member 17a is inserted into the guide hole 23a1 of the wiring board 20. The first spacer member 17a passes through the guide hole 23a1, and eventually the lower end of the second spacer member 18a abuts against the upper surface of the wiring board 20.

[0105] In this way, the lower end of the second spacer member 18a abuts against the upper surface of the wiring board 20, thereby maintaining a predetermined second distance L2 between the lower surface of the exterior member 11a and the upper surface of the wiring board 20. Furthermore, by inserting the first spacer member 17a through the guide hole 23a1, it becomes possible to accurately position the wiring board 20 relative to the exterior member 11a in the horizontal direction with a simple operation.

[0106] Furthermore, the circuit board 30 is attached to the case 10 with the lower end of the first spacer member 17a abutting against the upper surface of the circuit board 30. This makes it possible to maintain a predetermined first distance L1 between the lower surface of the exterior member 11a and the upper surface of the circuit board 30, and as a result, it becomes possible to maintain a desired distance between the lower surface of the wiring board 20 and the upper surface of the circuit board 30.

[0107] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0108] 1 semiconductor device 10 case 10a storage member 10b, 10c terminal holding member 10d lid member 11a exterior member 11a1, 11a2 edge portion 11b side wall 11c, 11d opening 12a to 12j, 13a to 13d external connection terminal 12a1, 12b1 end portion 13a1, 13b1, 13c1, 13d1 flat plate portion 13a2, 13b2, 13c2, 13d2 connection portion 14a to 14d, 17a to 17d first spacer member 15a to 15d, 18a to 18d second spacer member 16a, 16b gate opening 20 wiring board 20a first edge portion 20b second edge portion 21a, 21b wiring pin 22a to 22j wiring hole 23a to 23d, 23a1 Guide holes 24a to 24c Circuit patterns 30 Circuit board 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, 31d1 to 31d4, 31e Semiconductor chip 32 Insulating plate 33a to 33g Circuit patterns 34a, 34b Solder 40 Sealing member A1, A2 Area G1 to G4 Gate terminals L1 First interval L2 Second interval Q1 to Q4 Transistors S1 to S4 Auxiliary source terminals

Claims

1. A semiconductor device comprising: a circuit board; a wiring board facing the upper surface of the circuit board and arranged with a first gap from the upper surface of the circuit board, the wiring board having wiring holes and guide holes therethrough; an exterior member facing the upper surface of the wiring board and arranged with a second gap from the upper surface of the wiring board; external connection terminals fixed to the exterior member and having lower ends inserted into the wiring holes of the wiring board to be electrically connected to the wiring holes; a first spacer member protruding from the lower surface of the exterior member and inserted into the guide holes of the wiring board, having a lower end abutting the upper surface of the circuit board to maintain a first gap between the lower surface of the exterior member and the upper surface of the circuit board; and a sealing member filled in the first gap and the second gap to seal the wiring board.

2. The semiconductor device according to claim 1, wherein the external connection terminals are press-fitted into the wiring holes of the wiring substrate.

3. The semiconductor device according to claim 1, wherein the exterior member is formed at least in an area above opposing first and second edge portions of the wiring board in a plan view, and the first spacer member and the second spacer member are formed in two or more sets along the first edge portion in an area of ​​the underside of the exterior member facing the first edge portion, and one or more sets along the second edge portion in an area of ​​the underside of the exterior member corresponding to the second edge portion.

4. The semiconductor device according to claim 1, further comprising a semiconductor chip disposed on the upper surface of the circuit board, the wiring board further comprising wiring pins protruding from the lower surface of the wiring board, and the upper surface of the semiconductor chip and lower ends of the wiring pins are joined via solder in the first gap.

5. The semiconductor device according to claim 1, wherein the exterior member is formed at least in a region above a first edge of the wiring board in a plan view, the case further includes a gate opening on a side of the exterior member through which the sealing member is injected, and the first spacer member and the second spacer member are formed on the underside of the exterior member at positions offset from the gate opening.

6. The semiconductor device according to claim 1, wherein the tip portion of said first spacer member that abuts against the upper surface of said circuit board has a cross-sectional area that tapers off as it approaches the upper surface of said circuit board.

7. The semiconductor device according to claim 1, wherein the second spacer member is columnar, and the first spacer member protrudes from the lower end of the second spacer member and is columnar in shape with a smaller cross-sectional area than the second spacer member.

8. The semiconductor device according to claim 1, further comprising a semiconductor chip that performs switching operations and is arranged on the upper surface of the circuit board, wherein upper ends of the external connection terminals protrude from the upper surface of the exterior member, and the upper ends of the external connection terminals form control terminals that input control signals that control the switching operations of the semiconductor chip.

9. The semiconductor device according to claim 1, wherein the exterior member includes a first region and a second region respectively provided above opposing first and second edge portions of the wiring board in a plan view, an opening is formed in the case between the first region and the second region of the exterior member, and the case further includes a lid member that closes the opening.

10. A preparation process for preparing a case including a circuit board, a wiring board having wiring holes and guide holes therethrough, an exterior member for fixing external connection terminals having one end protruding from one main surface, a first spacer member protruding from the one main surface of the exterior member, and a second spacer member protruding from the one main surface of the exterior member and having a length from the one main surface shorter than that of the first spacer member; a first setting process for bringing the wiring board close to the exterior member from the one main surface side of the exterior member in the case, inserting the first spacer member into the guide hole, inserting one end of the external connection terminal into the wiring hole to electrically connect the wiring hole and the external connection terminal, and abutting an end of the second spacer member against the wiring board; and a second setting process for arranging the circuit board opposite the exterior member with respect to the wiring board, and abutting the first spacer member inserted through the guide hole of the wiring board against the circuit board. a sealing step of filling a first gap between the circuit board and the wiring board and a second gap between the wiring board and the exterior member with a sealing material to seal the wiring board.

11. A method for manufacturing a semiconductor device as described in claim 10, wherein in the first setting step, the first spacer member is inserted into the guide hole with respect to the case placed with one main surface of the exterior member facing upward, one end of the external connection terminal is inserted into the wiring hole, and an end of the second spacer member is abutted against the wiring board to support the wiring board on the second spacer member.

12. The method for manufacturing a semiconductor device according to claim 10, wherein in the first setting step, one end of the external connection terminal is press-fitted into the wiring hole.

13. A method for manufacturing a semiconductor device as described in claim 10, further comprising, between the second setting step and the sealing step, a joining step of joining, via solder in the first gap, a surface of a semiconductor chip arranged on the main surface of the circuit board on the wiring board side, the surface on the wiring board side, to an end of a wiring pin arranged on the wiring board so as to protrude toward the circuit board side.

Images