Submount, semiconductor device, method for manufacturing submount, and method for manufacturing semiconductor device

Abstract

A submount (7) comprises: an electrically insulating layer (70) having a first main surface (77), a second main surface (78) positioned on a back side of the first main surface (77), and a first recessed region (71) that is a region recessed with respect to the first main surface (77) or a region recessed with respect to the second main surface (78); and a first metal layer (metal layer (82)) that covers at least a portion of the first recessed region (71). The thickness of the first metal layer at a position facing the first recessed region (71) is greater than the depth of the first recessed region (71).

Description

Submount, semiconductor device, method for manufacturing submount, and method for manufacturing semiconductor device

[0001] The present disclosure relates to a submount, a semiconductor device, a method for manufacturing a submount, and a method for manufacturing a semiconductor device.

[0002] Conventionally, submounts have been used to mount elements such as semiconductor light-emitting elements. The submount functions as a mounting base for the elements and also as a heat dissipation member. Higher output power is required for semiconductor laser elements, which are an example of semiconductor light-emitting elements. For example, semiconductor laser elements are required to have an input power of 20 W or more when driven in continuous wave (CW) mode. Accordingly, there is a demand for improved heat dissipation performance for submounts on which semiconductor laser elements are mounted.

[0003] For example, Patent Document 1 discloses a submount that combines Cu and an insulating material as a submount that can improve heat dissipation performance.

[0004] JP 2023-164288 A

[0005] However, semiconductor laser elements are required to have even higher output power, and even the submount described in Patent Document 1 does not have sufficient heat dissipation performance.

[0006] The present disclosure has been made to solve such problems, and aims to provide a submount or the like with high heat dissipation performance.

[0007] In order to achieve the above-mentioned object, the submount of the present disclosure comprises a first main surface, a second main surface located on the back side of the first main surface, an electrically insulating insulating layer having a region recessed with respect to the first main surface or a first recessed region that is a region recessed with respect to the second main surface, and a first metal layer covering at least a portion of the first recessed region, wherein the thickness of the first metal layer at a position facing the first recessed region is greater than the depth of the first recessed region.

[0008] In order to achieve the above object, the semiconductor device according to the present disclosure includes the submount and a semiconductor element bonded to the solder layer.

[0009] In order to achieve the above-mentioned object, the method for manufacturing a submount according to the present disclosure includes an insulating layer formation process for forming an insulating layer having a first main surface, a second main surface located on the back side of the first main surface, and a region recessed relative to the first main surface or a first recessed region that is a region recessed relative to the second main surface, and a metal layer formation process for forming a first metal layer that covers at least a portion of the first recessed region, wherein the thickness of the first metal layer at a position facing the first recessed region is greater than the depth of the first recessed region.

[0010] In order to achieve the above object, a method for manufacturing a semiconductor device according to the present disclosure includes the method for manufacturing the submount, and an element bonding step of bonding a semiconductor light emitting element to the solder layer.

[0011] According to the present disclosure, a submount or the like having high heat dissipation performance can be provided.

[0012] 1 is a top view showing the configuration of a semiconductor device according to a first embodiment. FIG. 2 is a bottom view showing the configuration of a semiconductor device according to a first embodiment. FIG. 3 is a first cross-sectional view showing the configuration of a semiconductor device according to a first embodiment. FIG. 4 is a second cross-sectional view showing the configuration of a semiconductor device according to a first embodiment. FIG. 5 is a first cross-sectional view showing the configuration of a submount according to a first embodiment. FIG. 6 is a second cross-sectional view showing the configuration of a submount according to a first embodiment. FIG. 7 is a cross-sectional view showing the stacked configuration of an underlayer of a submount according to a first embodiment. FIG. 8 is a plan view showing the configuration of a semiconductor light-emitting element according to a first embodiment. FIG. 9 is a cross-sectional view showing the configuration of a semiconductor light-emitting element according to a first embodiment. FIG. 10 is a schematic cross-sectional view showing the distribution of Sn in a solder layer near the semiconductor light-emitting element according to a first embodiment. FIG. 11 is a schematic top view illustrating an insulating layer forming step in a method for manufacturing a submount according to a first embodiment. FIG. 12 is a schematic cross-sectional view showing an insulating layer forming step in a method for manufacturing a submount according to a first embodiment. FIG. 13 is a schematic top view illustrating an underlayer forming step in a method for manufacturing a submount according to a first embodiment. FIG. 1 is a schematic cross-sectional view illustrating a metal layer forming step in the method for manufacturing a submount according to embodiment 1. FIG. 2 is a schematic cross-sectional view illustrating a planarizing step in the method for manufacturing a submount according to embodiment 1. FIG. 3 is a schematic top view illustrating an intermediate layer forming step in the method for manufacturing a submount according to embodiment 1. FIG. 4 is a schematic cross-sectional view illustrating an intermediate layer forming step in the method for manufacturing a submount according to embodiment 1. FIG. 5 is a schematic top view illustrating a covering layer forming step in the method for manufacturing a submount according to embodiment 1. FIG. 6 is a schematic cross-sectional view illustrating a covering layer forming step in the method for manufacturing a submount according to embodiment 1. FIG. 7 is a schematic top view illustrating a barrier layer forming step in the method for manufacturing a submount according to embodiment 1. FIG. 8 is a schematic cross-sectional view illustrating a barrier layer forming step in the method for manufacturing a submount according to embodiment 1. FIG. 9 is a schematic top view illustrating a solder layer forming step in the method for manufacturing a submount according to embodiment 1.1 is a schematic cross-sectional view illustrating a solder layer forming step in the method for manufacturing a submount according to embodiment 1. FIG. 2 is a schematic top view illustrating a surface layer forming step in the method for manufacturing a submount according to embodiment 1. FIG. 3 is a schematic top view illustrating a dividing step in the method for manufacturing a submount according to embodiment 1. FIG. 4 is a schematic cross-sectional view illustrating a heating step in the method for manufacturing a semiconductor device according to embodiment 1. FIG. 5 is a schematic cross-sectional view illustrating a contacting step in the method for manufacturing a semiconductor device according to embodiment 1. FIG. 6 is a schematic top view illustrating a first molded body used in an insulating layer forming step in a modified example of embodiment 1. FIG. 7 is a schematic cross-sectional view illustrating a first molded body used in an insulating layer forming step in a modified example of embodiment 1. FIG. 8 is a schematic top view illustrating a configuration of a second molded body used in an insulating layer forming step in a modified example of embodiment 1. FIG. 9 is a schematic cross-sectional view illustrating a first molded body and a second molded body in a laminating step in an insulating layer forming step in a modified example of embodiment 1. FIG. 10 is a schematic cross-sectional view illustrating a first molded body and a second molded body in a firing step in an insulating layer forming step in a modified example of embodiment 1. FIG. 11 is a schematic cross-sectional view illustrating an insulating layer formed in an insulating layer forming step in a modified example of embodiment 1. 1 is a second cross-sectional view showing the configuration of a semiconductor device according to embodiment 2. FIG. 2 is a top view showing the configuration of a semiconductor device according to embodiment 3. FIG. 3 is a cross-sectional view showing the configuration of a semiconductor device according to embodiment 3. FIG. 4 is a schematic top view showing the configuration of a semiconductor device according to modification 1 of embodiment 3. FIG. 5 is a schematic top view showing the configuration of a semiconductor device according to modification 2 of embodiment 3. FIG. 6 is a schematic top view showing the configuration of a semiconductor device according to modification 3 of embodiment 3. FIG. 7 is a first cross-sectional view showing the configuration of a semiconductor device according to embodiment 4. FIG. 8 is a second cross-sectional view showing the configuration of a semiconductor device according to embodiment 4. FIG. 9 is a cross-sectional view showing the configuration of a submount according to embodiment 5. FIG. 10 is a schematic side view showing the configuration of an insulating layer according to modification 1. FIG. 11 is a schematic cross-sectional view showing the configuration of a semiconductor device according to modification 2. FIG. 12 is a schematic top view showing the configuration of a submount according to modification 3. FIG. 13 is a schematic cross-sectional view showing the configuration of a submount according to modification 3.

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below represents a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, arrangement and connection of the components, steps (processes), and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0014] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, the scales and the like do not necessarily match in each figure. In each figure, the same reference numerals are used to denote substantially the same components, and redundant explanations will be omitted or simplified.

[0015] Furthermore, in this specification, terms indicating relationships between elements such as "equal," terms indicating the shapes of elements such as "parallel," "perpendicular," "circular," and "cylindrical," as well as numerical ranges, are not expressions that only express a strict meaning, but are expressions that mean that a range is substantially equivalent, for example, including a difference of about a few percent.

[0016] First Embodiment A semiconductor device according to a first embodiment will be described.

[0017] [1-1. Configuration of Semiconductor Device] A submount, a semiconductor light-emitting element, and a semiconductor device including them according to the present embodiment will be described with reference to FIGS. 1 to 4. FIGS. 1 and 2 are top and bottom views, respectively, illustrating the configuration of a semiconductor device 1 according to the present embodiment. FIGS. 3 and 4 are first and second cross-sectional views, respectively, illustrating the configuration of the semiconductor device 1 according to the present embodiment. FIG. 3 shows a cross section of the semiconductor device 1 taken along line III-III in FIGS. 1 and 2. FIG. 4 shows a cross section of the semiconductor device 1 taken along line IV-IV in FIGS. 1 and 2. Each figure shows mutually orthogonal X-, Y-, and Z-axes. The X-, Y-, and Z-axes are in a right-handed Cartesian coordinate system. The Y-axis direction is parallel to the optical axis of light (laser light) emitted by the semiconductor light-emitting element 10. The Z-axis direction is perpendicular to the first main surface 77 of the insulating layer 70 included in the submount 7.

[0018] As shown in FIGS. 1 to 4, the semiconductor device 1 according to this embodiment includes a submount 7 and a semiconductor light emitting element 10 joined to a solder layer 86 of the submount 7.

[0019] The submount 7 is a base on which elements such as the semiconductor light emitting element 10 are mounted. The submount 7 according to this embodiment will be described using FIGS. 5 to 8 in addition to FIGS. 1 to 4 . FIGS. 5 and 6 are first and second cross-sectional views, respectively, showing the configuration of the submount 7 according to this embodiment. FIG. 5 shows a cross-section of the submount 7 at the same position as the cross-section shown in FIG. 3 . FIG. 6 shows a cross-section of the submount 7 at the same position as the cross-section shown in FIG. 4 . FIGS. 7 and 8 are cross-sectional views showing the layered configuration of the underlayer 81 and underlayer 91 of the submount 7 according to this embodiment. FIGS. 7 and 8 show enlarged views of portions of the flat portions of the underlayer 81 and underlayer 91, respectively.

[0020] The submount 7 according to this embodiment is a base on which an element is mounted. In this embodiment, a semiconductor light emitting element 10 is mounted on the submount 7. As shown in FIGS. 3 to 6 , the submount 7 includes an insulating layer 70 and a metal layer 82. In this embodiment, the submount 7 further includes an underlayer 81, an intermediate layer 83, a coating layer 84, a barrier layer 85, a solder layer 86, an underlayer 91, a metal layer 92, an intermediate layer 93, and a coating layer 94. As shown in FIGS. 5 and 6 , the submount 7 without an element mounted thereon may include a surface layer 87.

[0021] The insulating layer 70 is an electrically insulating layer having a first main surface 77, a second main surface 78 located on the back side of the first main surface 77, and a first recessed region 71, which is a region recessed relative to the first main surface 77 or a region recessed relative to the second main surface 78. In this embodiment, the first recessed region 71 is a region recessed relative to the first main surface 77. The first recessed region 71 does not penetrate the insulating layer 70. In other words, the depth of the first recessed region 71 is smaller than the thickness of the portion of the insulating layer 70 where the first recessed region 71 is not formed (i.e., the distance between the first main surface 77 and the second main surface 78). The insulating layer 70 is a plate-shaped member having the first main surface 77 and the second main surface 78. The insulating layer 70 is formed of an electrically insulating material such as AlN or SiC. The thickness of the portion of the insulating layer 70 where the first recessed region 71 is not formed is 150 μm or more. The thickness of the portion of the insulating layer 70 where the first recessed region 71 is not formed may be 200 μm or less. In this embodiment, the depth of the first recessed region 71 is 50 μm. The thickness T0 of the thinnest portion of the insulating layer 70 in the first recessed region 71 is less than 150 μm. In this embodiment, the thickness T0 is 50 μm or more and less than 150 μm. The thickness T0 may be 50 μm or more and less than 100 μm, or 50 μm or more and less than 75 μm.

[0022] In this embodiment, the first recessed region 71 has a groove-like shape with a width W1 extending in a first direction parallel to the first main surface 77. The first direction is a direction parallel to the Y-axis direction in each drawing. The width W1 of the first recessed region 71 is the maximum dimension of the first recessed region 71 in a second direction parallel to the first main surface 77 and perpendicular to the first direction. The width W1 is, for example, approximately 0.4 mm. The second direction is a direction parallel to the X-axis direction in each drawing. As shown in FIG. 3 , the periphery of the first recessed region 71 has an inclined portion 71s inclined with respect to the first main surface 77. The first recessed region 71 has an inclined portion 71s at both ends of the first recessed region 71 in the second direction. Therefore, the width of the first recessed region 71 in the second direction increases toward the first main surface 77. In this embodiment, the cross section of the first recessed region 71 perpendicular to the first direction has a trapezoidal shape.

[0023] The dimension of the insulating layer 70 in the first direction is, for example, about 1.5 mm, and the dimension in the second direction is, for example, about 1.5 mm.

[0024] The base layer 81 is a conductive layer made of metal that covers at least a portion of the first recessed region 71. In the present embodiment, the base layer 81 has a base portion 81M and an exposed portion 81L, as shown in FIG. 6 and other figures. In a plan view of the first main surface 77, the base layer 81 has a portion disposed in an area excluding both ends of the insulating layer 70 in the X-axis direction and the Y-axis direction (i.e., the peripheral portion of the insulating layer 70), a portion extending from the portion disposed in the area excluding both ends of the insulating layer 70 in the Y-axis direction along the first recessed region 71, and a portion extending to the other end of the insulating layer 70. The base portion 81M is a portion of the base layer 81 that is disposed between the insulating layer 70 and the metal layer 82 and serves as a base for the metal layer 82. In the present embodiment, the base layer 81 contacts the first main surface 77 or the first recessed region 71. The base portion 81M is disposed over the entire area of ​​the first recessed region 71 except for both ends in the Y-axis direction, and on the first main surface 77 adjacent to the area (see, for example, FIGS. 5 and 6 ). The dimensions of the base portion 81M in each of the first and second directions are, for example, approximately 1.4 mm. The exposed portion 81L is a portion of the base layer 81 exposed from the metal layer 82. The exposed portion 81L is disposed on the first main surface 77. In this embodiment, the base layer 81 has four exposed portions 81L. Two exposed portions 81L are connected to one end of the base portion 81M in the first direction, and the other two exposed portions 81L are connected to the other end of the base portion 81M in the first direction. The exposed portions 81L can be used as electrodes for supplying power to the base layer 81, for example, in a process of forming a metal layer 82 by plating.

[0025] As shown in FIG. 7 , the underlayer 81 according to this embodiment includes a first layer 81a, a second layer 81b, a third layer 81c, and a fourth layer 81d. The first layer 81a is a 0.1 μm thick Ti layer disposed on the first main surface 77 and in contact with the first main surface 77 and the first recessed region 71. The second layer 81b is a 5 μm thick Cu layer disposed on the first layer 81a (i.e., disposed on the first main surface 77 via the first layer 81a). The third layer 81c is a 1.0 μm or thick Ni layer disposed on the second layer 81b (i.e., disposed on the first main surface 77 via the first layer 81a and the second layer 81b). The fourth layer 81d is a 0.1 μm or thick Au layer disposed on the third layer 81c (i.e., disposed on the first main surface 77 via the first layer 81a, the second layer 81b, and the third layer 81c).

[0026] The metal layer 82 shown in Figures 3 to 6 is a conductive layer made of metal and disposed on the first main surface 77. The metal layer 82 is an example of a first metal layer that covers at least a portion of the first recessed region 71. The thermal conductivity of the metal layer 82 is greater than that of the insulating layer 70. The metal layer 82 is made of, for example, Cu. In this embodiment, the metal layer 82 covers a portion of the first main surface 77 and a portion of the first recessed region 71 via the base layer 81. The metal layer 82 is disposed on a base portion 81M of the base layer 81. The metal layer 82 is disposed over the entire area of ​​the base portion 81M. The metal layer 82 has a thick film portion 82D disposed opposite the first recessed region 71 and a thin film portion 82F disposed opposite the first main surface 77.

[0027] The thickness (dimension in the Z-axis direction) of metal layer 82 at a position facing first recessed region 71 is greater than the depth of first recessed region 71. In other words, the thickness (dimension in the Z-axis direction) of metal layer 82 at each position facing first recessed region 71 is greater than the depth of first recessed region 71 from first main surface 77 at each position. Therefore, the surface of thick film portion 82D farther from insulating layer 70 (i.e., the interface with intermediate layer 83) is located on the positive side of first main surface 77 in the Z-axis direction.

[0028] In the present embodiment, the width W1 of the first recessed region 71 in the second direction is at least twice the maximum thickness T1 of the thick film portion 82D. The maximum thickness T1 of the thick film portion 82D is, for example, 60 μm or more and 250 μm or less. The thickness of the thin film portion 82F is, for example, 0 μm or more and 150 μm or less, but may be 10 μm or more.

[0029] The intermediate layer 83 is a conductive layer made of metal and disposed on the first main surface 77 via the metal layer 82. In the present embodiment, the intermediate layer 83 is disposed on the first main surface 77 via the base layer 81 and the metal layer 82. The intermediate layer 83 is also disposed between the metal layer 82 and the coating layer 84, and is disposed over the entire area of ​​the metal layer 82. The intermediate layer 83 may have the function of increasing adhesion between the metal layer 82 and the coating layer 84. In the present embodiment, the intermediate layer 83 is a Ni layer having a thickness of 1 μm or more.

[0030] The coating layer 84 is a conductive layer made of metal and disposed on the first main surface 77 via the metal layer 82. In the present embodiment, the coating layer 84 is disposed on the first main surface 77 via the base layer 81, the metal layer 82, and the intermediate layer 83. The coating layer 84 is disposed over the entire area of ​​the intermediate layer 83. In the present embodiment, the coating layer 84 is an Au layer having a thickness of 0.5 μm or more.

[0031] The barrier layer 85 is a conductive layer made of metal and disposed on the first main surface 77 via the metal layer 82. In the present embodiment, the barrier layer 85 is disposed on the first main surface 77 via the coating layer 84, the intermediate layer 83, the metal layer 82, and the underlayer 81. The barrier layer 85 is also disposed between the metal layer 82 and the solder layer 86. More specifically, the barrier layer 85 is disposed between the coating layer 84 and the solder layer 86.

[0032] 1, 3, and 5, the barrier layer 85 is disposed in a region corresponding to the first recessed region 71. That is, as shown in FIG. 1, in a plan view of the first main surface 77, the barrier layer 85 is disposed in a region overlapping the first recessed region 71 and extends in the first direction. The barrier layer 85 extends from one end to the other end of the metal layer 82 in the first direction. Furthermore, the dimension of the barrier layer 85 in the second direction may be larger than the width W1 of the first recessed region 71 in the second direction. The dimension of the barrier layer 85 in the second direction is, for example, 0.7 mm.

[0033] The barrier layer 85 may have a function of suppressing diffusion of metal atoms contained in the solder layer 86 into the coating layer 84. For example, if the solder layer 86 contains Sn, the barrier layer 85 may suppress diffusion of Sn atoms into the coating layer 84 made of Au. In the present embodiment, the barrier layer 85 is a Pt layer having a thickness of 0.25 μm or more.

[0034] The solder layer 86 is a conductive layer made of solder and disposed on the first main surface 77 via the metal layer 82. In the present embodiment, the solder layer 86 is disposed on the first main surface 77 via the base layer 81, the metal layer 82, the intermediate layer 83, the coating layer 84, and the barrier layer 85.

[0035] As shown in FIGS. 1, 3, and 5, the solder layer 86 is disposed in a region of the metal layer 82 corresponding to the first recessed region 71. That is, as shown in FIG. 1, in a plan view of the first main surface 77, the solder layer 86 is disposed in a region overlapping the first recessed region 71 and extends in the first direction. The solder layer 86 extends from one end of the metal layer 82 to the other end in the first direction (see FIG. 4, etc.). The dimension of the solder layer 86 in the second direction may be larger than the width W1 of the first recessed region 71 in the second direction. The dimension of the solder layer 86 in the second direction is, for example, 0.7 mm. That is, the solder layer 86 is disposed over the entire region of the barrier layer 85. In this embodiment, the solder layer 86 is an AuSn layer having a thickness of 4.0 μm. The Au content of the solder layer 86 is, for example, 70±3 wt %.

[0036] 5 and 6 is a conductive layer made of metal and disposed on the first main surface 77 via the metal layer 82 and the solder layer 86. In this embodiment, when heating is performed to bond the semiconductor light emitting element 10 to the submount 7, the surface layer 87 diffuses into the solder layer 86 and is integrated with the solder layer 86 (see FIGS. 3 and 4). The surface layer 87 is, for example, an Au layer with a thickness of 0.04 μm.

[0037] The base layer 91 is a conductive layer made of metal and disposed on the second main surface 78. The base layer 91 contacts the second main surface 78. In this embodiment, as shown in FIG. 6 and other figures, the base layer 91 has a base portion 91M and an exposed portion 91L. The base portion 91M is a portion of the base layer 91 disposed between the insulating layer 70 and the metal layer 92 and serves as a base for the metal layer 92. In this embodiment, the base portion 91M is disposed in a region of the second main surface 78 corresponding to the first recessed region 71. That is, the base portion 91M is disposed in a region overlapping the first recessed region 71 in a plan view of the second main surface 78 (see FIG. 5 and other figures). The dimensions of the base portion 91M in each of the first and second directions are, for example, approximately 1.4 mm. In this embodiment, the base portion 91M is disposed in a position facing the base portion 81M via the insulating layer 70. The exposed portions 91L are portions of the base layer 91 that are exposed from the metal layer 92. In the present embodiment, the base layer 91 has four exposed portions 91L. Two of the exposed portions 91L are connected to one end of the base portion 91M in the first direction, and the other two exposed portions 91L are connected to the other end of the base portion 91M in the first direction. The exposed portions 91L can be used as electrodes for supplying power to the base layer 91, for example, in a process of forming the metal layer 92 by plating.

[0038] As shown in FIG. 8 , the underlayer 91 according to this embodiment includes a first layer 91a, a second layer 91b, a third layer 91c, and a fourth layer 91d. The first layer 91a is a 0.1 μm thick Ti layer disposed on the second main surface 78 and in contact with the second main surface 78. The second layer 91b is a 5 μm thick Cu layer disposed on the first layer 91a (i.e., disposed on the second main surface 78 via the first layer 91a). The third layer 91c is a 1.0 μm or thick Ni layer disposed on the second layer 91b (i.e., disposed on the second main surface 78 via the first layer 91a and the second layer 91b). The fourth layer 91d is a 0.1 μm or thick Au layer disposed on the third layer 91c (i.e., disposed on the second main surface 78 via the first layer 91a, the second layer 91b, and the third layer 91c).

[0039] The metal layer 92 shown in FIGS. 3 to 6 is a conductive layer made of metal and disposed on the second main surface 78. The thermal conductivity of the metal layer 92 is greater than that of the insulating layer 70. The metal layer 92 is made of, for example, Cu. In this embodiment, the metal layer 92 is disposed on a base portion 91M of the base layer 91. The metal layer 92 is disposed over the entire area of ​​the base portion 91M. In this embodiment, the thickness of the metal layer 92 is, for example, not less than 50 μm and not more than 150 μm.

[0040] The intermediate layer 93 is a conductive layer made of metal and disposed on the second main surface 78 via the metal layer 92. In the present embodiment, the intermediate layer 93 is disposed on the second main surface 78 via the base layer 91 and the metal layer 92. The intermediate layer 93 is also disposed between the metal layer 92 and the coating layer 94, and is disposed over the entire area of ​​the metal layer 92. The intermediate layer 93 may have the function of increasing adhesion between the metal layer 92 and the coating layer 94. In the present embodiment, the intermediate layer 93 is a Ni layer having a thickness of 1 μm or more.

[0041] The coating layer 94 is a conductive layer made of metal and disposed on the second main surface 78 via the metal layer 92. In the present embodiment, the coating layer 94 is disposed on the second main surface 78 via the base layer 91, the metal layer 92, and the intermediate layer 93. The coating layer 94 is disposed over the entire area of ​​the intermediate layer 93. In the present embodiment, the coating layer 94 is an Au layer having a thickness of 0.5 μm or more.

[0042] The semiconductor light-emitting element 10 shown in FIGS. 1 to 4 is an example of an element mounted on a submount 7. The semiconductor light-emitting element 10 generates heat during operation, and as shown by the dashed arrows in FIG. 3, the heat is diffused and conducted in the submount 7. The semiconductor light-emitting element 10 according to this embodiment will be described with reference to FIGS. 1 to 4, 9, and 10. FIGS. 9 and 10 are a plan view and a cross-sectional view, respectively, showing the configuration of the semiconductor light-emitting element 10 according to this embodiment. FIG. 10 shows a cross section of the semiconductor light-emitting element 10 taken along line X-X in FIG. 9.

[0043] As shown in FIG. 10 , in this embodiment, the semiconductor light-emitting device 10 includes a semiconductor stack 10S and emits light from a facet 10F (see FIGS. 1 and 9 ) perpendicular to the stacking direction (i.e., the Z-axis direction) of the semiconductor stack 10S. In this embodiment, the semiconductor light-emitting device 10 is a nitride semiconductor laser device having two facets 10F and 10R that form a cavity, as shown in FIGS. 1 and 9 . The facet 10F is a front facet that emits laser light, and the facet 10R is a rear facet that has a higher reflectivity than the facet 10F. In this embodiment, the reflectivities of the facets 10F and 10R are 6% and 98%, respectively. The semiconductor light-emitting device 10 also has a waveguide formed between the facets 10F and 10R. The cavity length of the semiconductor light-emitting device 10 according to this embodiment (i.e., the distance between the facets 10F and 10R) is approximately 1000 μm. The semiconductor light emitting element 10 also emits blue-violet light having a peak wavelength in the 405 nm band, for example.

[0044] 1 and 4 , the end of the semiconductor light emitting element 10 on the end face 10F side may protrude in the first direction from the end of the solder layer 86. This makes it possible to prevent the laser light from the semiconductor light emitting element 10 from being blocked by the solder layer 86.

[0045] As shown in FIG. 10, the semiconductor light emitting element 10 includes a substrate 21, a semiconductor laminate 10S, an insulating layer 30, an adhesion layer 32, a contact electrode 40, a pad layer 50, and an N-side electrode 60.

[0046] The substrate 21 is a plate-like member that serves as a base for the semiconductor light emitting device 10. In this embodiment, the substrate 21 is an N-type GaN substrate.

[0047] The semiconductor stack 10S is a stack including nitride semiconductors. The semiconductor stack 10S has multiple semiconductor layers stacked in the stacking direction (i.e., the Z-axis direction in each drawing). In this embodiment, the semiconductor stack 10S has an N-side semiconductor layer 22, an active layer 23, a P-side semiconductor layer 24, and a contact layer 25.

[0048] The N-side semiconductor layer 22 is an example of a first semiconductor layer of a first conductivity type disposed between the substrate 21 and the active layer 23. The N-side semiconductor layer 22 includes a nitride semiconductor. In this embodiment, the N-side semiconductor layer 22 includes an N-type clad layer having a lower refractive index than the active layer 23. The N-side semiconductor layer 22 is, for example, an N-type AlGaN layer. Note that the N-side semiconductor layer 22 may include a layer other than the N-type clad layer. The N-side semiconductor layer 22 may include, for example, a buffer layer, an optical guide layer, etc.

[0049] The active layer 23 is a light-emitting layer disposed between the N-side semiconductor layer 22 and the P-side semiconductor layer 24. In this embodiment, the active layer 23 includes a nitride semiconductor and has a quantum well structure. The active layer 23 may have a single quantum well or multiple quantum wells. In this embodiment, the active layer 23 has multiple barrier layers made of InGaN and multiple well layers made of InGaN.

[0050] The P-side semiconductor layer 24 is an example of a second semiconductor layer of a second conductivity type that is located farther from the substrate 21 than the active layer 23. The P-side semiconductor layer 24 includes a nitride semiconductor. In this embodiment, the P-side semiconductor layer 24 includes a P-type clad layer that has a lower refractive index than the active layer 23. The P-side semiconductor layer 24 is, for example, a P-type AlGaN layer. The P-side semiconductor layer 24 may include a layer other than the P-type clad layer. The P-side semiconductor layer 24 may include, for example, an optical guide layer, an electron barrier layer, etc. The P-side semiconductor layer 24 may also have a superlattice structure.

[0051] A ridge 24R and two protruding portions 24P are formed in the P-side semiconductor layer 24. The ridge 24R and the two protruding portions 24P are each portions of the P-side semiconductor layer 24 that protrude in the Z-axis direction and extend in the Y-axis direction. The ridge 24R is disposed between the two protruding portions 24P. Two grooves 24T are formed in the P-side semiconductor layer 24, disposed along the ridge 24R and extending in the Y-axis direction. A groove 24T is formed between each of the two protruding portions 24P and the ridge 24R. In this embodiment, the ridge width (i.e., the dimension of the ridge 24R in the X-axis direction) is approximately 30 μm. The dotted lines in FIG. 9 correspond to the positions of the side surfaces of the grooves 24T.

[0052] The contact layer 25 is disposed at a position farther from the substrate 21 than the P-side semiconductor layer 24, and is a layer that makes ohmic contact with the contact electrode 40. In this embodiment, the contact layer 25 is a P-type GaN layer.

[0053] The insulating layer 30 is disposed between the semiconductor laminate 10S and the pad layer 50 and is an electrically insulating layer. The insulating layer 30 has an opening (or a slit) at a position corresponding to the upper surface of the ridge 24R. In this embodiment, the insulating layer 30 is disposed in a region of the upper surface of the P-side semiconductor layer 24 other than the upper surface of the ridge 24R. The insulating layer 30 may be disposed on a part of the upper surface of the ridge 24R. There are no particular limitations on the material that forms the insulating layer 30 as long as it is an insulating material. In this embodiment, the insulating layer 30 is formed of SiO ２ It consists of:

[0054] The adhesion layer 32 is a layer disposed above the insulating layer 30. The adhesion layer 32 is disposed between the insulating layer 30 and the pad layer 50 and functions to enhance adhesion between the pad layer 50 and the insulating layer 30. The adhesion layer 32 has an opening (or slit) at a position corresponding to the opening in the insulating layer 30. In this embodiment, when viewed from above on the substrate 21, the opening in the insulating layer 30 is disposed inside the opening in the adhesion layer 32. The adhesion layer 32 may contain at least one of Ti and Cr. If the adhesion layer 32 contains Ti and the insulating layer 30 is an oxide, the adhesion between the adhesion layer 32 and the insulating layer 30 can be further enhanced. This is because, when the insulating layer 30 is an oxide, the adhesion layer 32, which is made of a metal film, can bond strongly if the adhesion layer 32 is made of a material that easily forms an oxide. In this embodiment, the adhesion layer 32 has a layered structure including a Ti film disposed on the insulating layer 30 and a Pt film disposed on the insulating layer 30 via the Ti film.

[0055] The contact electrode 40 is an electrode in contact with the semiconductor laminate 10S. The contact electrode 40 faces the contact layer 25 and is in contact with the contact layer 25. In this embodiment, the contact electrode 40 is disposed on the ridge 24R. The contact electrode 40 may be, for example, a single layer film or a multilayer film formed of at least one of Ag, Ni, Pd, Cr, and Pt, or may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), InGaZnO, or the like. ｘ The contact electrode 40 may be a transparent conductive film made of a transparent metal oxide such as IGZO. In this embodiment, the contact electrode 40 has a Pd layer in contact with the contact layer 25 and a Pt layer disposed on the contact layer 25 with the Pt layer interposed therebetween.

[0056] The pad layer 50 is a conductive layer that contacts the contact electrode 40. The pad layer 50 contains Au. In this embodiment, the pad layer 50 is an Au layer with a thickness of about 4 μm. The detailed configuration of the pad layer 50 will be described later.

[0057] The N-side electrode 60 is a conductive layer disposed on the principal surface of the substrate 21 opposite to the principal surface on which the semiconductor laminate 10S is disposed. The N-side electrode 60 is a single-layer film or a multilayer film formed of at least one of Cr, Ti, Ni, Pd, and Pt, for example.

[0058] The detailed configuration and effects of the pad layer 50 according to this embodiment will be described.

[0059] As shown in FIG. 10, the pad layer 50 has a contact region 51 and an outer region 52 .

[0060] The contact region 51 is a region of the pad layer 50 that is stacked in a region where the pad layer 50 and the contact electrode 40 are in contact with each other. In the present embodiment, the insulating layer 30 is not disposed in the region between the semiconductor laminate 10S and the pad layer 50, between the semiconductor laminate 10S and the contact region 51.

[0061] When the semiconductor light emitting element 10 is bonded to the submount 7, the solder layer 86 is heated. As a result, the solder layer 86 melts. The pad layer 50 of the semiconductor light emitting element 10 is pressed against the melted solder layer 86. By cooling the solder layer 86 in this state, the solder layer 86 solidifies. As a result, the pad layer 50 is bonded to the solder layer 86. In the bonding process described above, a portion of the pad layer 50 and a portion of the solder layer 86 are mixed together. Some of the Sn atoms in the solder layer 86 diffuse into the pad layer 50 made of Au.

[0062] When the pad layer 50 is bonded to the solder layer 86 , most of the pad layer 50 mixes with the solder layer 86 and becomes part of the solder layer 86 .

[0063] [1-2. Manufacturing Method of Semiconductor Device] A manufacturing method of the semiconductor device 1 according to this embodiment will be described. First, a manufacturing method of the submount 7 included in the semiconductor device 1 will be described with reference to FIGS. 12 to 28. Each of FIGS. 12, 14, 16, 19, 21, 23, 25, 27, and 28 is a schematic top view illustrating each step of the manufacturing method of the submount 7 according to this embodiment. Each of FIGS. 13, 15, 17, 18, 20, 22, 24, and 26 is a schematic cross-sectional view illustrating each step of the manufacturing method of the submount 7 according to this embodiment. FIG. 13 shows a portion of a cross section of the insulating layer 70 taken along line XIII-XIII in FIG. 12. FIG. 15 shows a portion of a cross section of the insulating layer 70 and other components taken along line XV-XV in FIG. 14. FIG. 17 shows a portion of a cross section of the insulating layer 70 and other components taken along line XVII-XVII in FIG. 16. Fig. 18 shows a cross section of the insulating layer 70 and the like at the same position as the cross section shown in Fig. 17. Fig. 20 shows a portion of the cross section of the insulating layer 70 and the like taken along line XX-XX shown in Fig. 19. Fig. 22 shows a portion of the cross section of the insulating layer 70 and the like taken along line XXII-XXII shown in Fig. 21. Fig. 24 shows a portion of the cross section of the insulating layer 70 and the like taken along line XXIV-XXIV shown in Fig. 23. Fig. 26 shows a portion of the cross section of the insulating layer 70 and the like taken along line XXVI-XXVI shown in Fig. 25.

[0064] First, as shown in FIGS. 12 and 13 , an insulating layer 70 is formed having a first main surface 77, a second main surface 78 located behind the first main surface 77, and a first recessed region 71, which is a region recessed relative to the first main surface 77 or a region recessed relative to the second main surface 78 (insulating layer formation process). In this embodiment, in order to simultaneously form multiple submounts 7, a substrate-like insulating layer 70 larger in size than the submounts 7 is prepared, and multiple first recessed regions 71 are formed on the first main surface 77 of the insulating layer 70. In this embodiment, the first recessed region 71 is a region recessed relative to the first main surface 77. The first recessed region 71 is formed, for example, by mechanical processing or laser processing. Note that in FIG. 12 , a single first recessed region 71 is divided and used for multiple submounts 7, but each first recessed region 71 shown in FIG. 12 may be divided. For example, the length of each first recessed region 71 may be divided into lengths corresponding to one submount 7.

[0065] 14 and 15 , an underlayer 81 is formed on the first main surface 77 (underlayer formation step). In this embodiment, in a plan view of the first main surface 77, the underlayer 81 has a rectangular portion corresponding to the underlayer portion 81M and a strip-shaped portion (a portion corresponding to the exposed portion 81L) extending from the rectangular portion in the Y-axis direction along the first recessed region 71. The underlayer 81 is also formed in the first recessed region 71. In the underlayer formation step, an underlayer 91 is formed on the second main surface 78. The underlayer 81 and the underlayer 91 are formed using, for example, sputtering or electron beam evaporation and photolithography.

[0066] 16 and 17 , a metal layer 82 is formed to cover at least a portion of the first recessed region 71 (metal layer forming process). The thickness of the metal layer 82 at a position facing the first recessed region 71 (thick film portion 82D) is greater than the depth of the first recessed region 71. In this embodiment, the metal layer 82 is disposed over the entire area of ​​the base portion 81M of the base layer 81. In the metal layer forming process, a metal layer 92 is also formed on the second main surface 78. The metal layer 92 is disposed over the entire area of ​​the base portion 91M of the base layer 91. The metal layer 82 and the metal layer 92 are formed by, for example, plating. A recess corresponding to the shape of the first recessed region 71 is formed on the surface of the metal layer 82 (the end face farther from the insulating layer 70).

[0067] 18, the surface of the metal layer 82 is planarized (planarization step). In the planarization step, the surface of the metal layer 82 is planarized, for example, by grinding the surface of the metal layer 82.

[0068] 19 and 20 , an intermediate layer 83 is formed (intermediate layer forming step). In this embodiment, the intermediate layer 83 is formed on the first main surface 77 via the base layer 81 and the metal layer 82. The intermediate layer 83 is disposed over the entire area of ​​the metal layer 82. In the intermediate layer forming step according to this embodiment, an intermediate layer 93 is also formed. The intermediate layer 93 is formed on the second main surface 78 via the base layer 91 and the metal layer 92. The intermediate layer 93 is disposed over the entire area of ​​the metal layer 92. The intermediate layers 83 and 93 are formed using, for example, plating, sputtering, or electron beam evaporation, and photolithography.

[0069] 21 and 22 , a coating layer 84 is formed (coating layer forming step). In this embodiment, the coating layer 84 is formed on the first main surface 77 via the base layer 81, the metal layer 82, and the intermediate layer 83. The coating layer 84 is disposed over the entire area of ​​the intermediate layer 83. In the coating layer forming step according to this embodiment, a coating layer 94 is also formed. The coating layer 94 is formed on the second main surface 78 via the base layer 91, the metal layer 92, and the intermediate layer 93. The coating layer 94 is disposed over the entire area of ​​the intermediate layer 93. The coating layers 84 and 94 are formed using, for example, plating, sputtering, or electron beam evaporation, and photolithography.

[0070] Although the present embodiment shows an example in which the intermediate layer forming step and the covering layer forming step are performed separately, the intermediate layer forming step and the covering layer forming step can also be performed together. That is, after forming the mask, the conductive films constituting each intermediate layer and each covering layer may be formed in sequence by sputtering or the like, and the mask and the conductive films on the mask may be removed by etching.

[0071] 23 and 24 , a barrier layer 85 is formed (barrier layer formation step). In this embodiment, the barrier layer 85 is formed on the first main surface 77 via an underlayer 81, a metal layer 82, an intermediate layer 83, and a coating layer 84. The barrier layer 85 is disposed in a region of the metal layer 82 facing the first recessed region 71, with the intermediate layer 83 and the coating layer 84 interposed therebetween. The barrier layer 85 is formed, for example, by using sputtering or electron beam evaporation and photolithography.

[0072] 25 and 26 , a solder layer 86 is formed on the first main surface 77 via the metal layer 82 (solder layer formation process). In this embodiment, the solder layer 86 is formed on the first main surface 77 via the base layer 81, the metal layer 82, the intermediate layer 83, the coating layer 84, and the barrier layer 85. The solder layer 86 is disposed in a region of the metal layer 82 facing the first recessed region 71 via the intermediate layer 83, the coating layer 84, and the barrier layer 85. In this embodiment, the solder layer 86 is disposed over the entire region of the barrier layer 85. The solder layer 86 is formed, for example, by using sputtering or electron beam evaporation and photolithography.

[0073] 27 (and FIG. 5 ), a surface layer 87 is formed on the first main surface 77 via the metal layer 82 (surface layer forming step). In this embodiment, the surface layer 87 is formed on the first main surface 77 via the base layer 81, the metal layer 82, the intermediate layer 83, the coating layer 84, the barrier layer 85, and the solder layer 86. The surface layer 87 is formed over the entire area of ​​the solder layer 86. The surface layer 87 is formed using, for example, sputtering or electron beam evaporation and photolithography.

[0074] In addition, in this embodiment, an example has been shown in which the barrier layer forming process, the solder layer forming process, and the surface layer forming process are performed separately, but these processes can also be performed together, just like the intermediate layer forming process and the coating layer forming process.

[0075] Next, the insulating layer 70 is divided as shown by the dashed lines in Fig. 28 (dividing step). For example, the insulating layer 70 is diced along the dashed lines in Fig. 28 to separate the insulating layer 70 into individual pieces.

[0076] Through the above steps, the submount 7 can be manufactured.

[0077] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Fig. 29 and Fig. 30. Fig. 29 is a schematic cross-sectional view showing a heating step in the method for manufacturing the semiconductor device 1 according to the present embodiment. Fig. 30 is a schematic cross-sectional view showing a contact step in the method for manufacturing the semiconductor device 1 according to the present embodiment. Figs. 29 and 30 show cross sections of the submount 7 and the like at the same position as in Fig. 3.

[0078] In the manufacturing method of the semiconductor device 1, the semiconductor light emitting element 10 is bonded to the solder layer 86 of the submount 7 (bonding step). In the bonding step of this embodiment, first, as shown in FIG. 29 , the solder layer 86 of the submount 7 is heated (heating step). This melts the solder layer 86. Next, as shown in FIG. 30 , the semiconductor light emitting element 10 is brought into contact with the solder layer 86 (contacting step). Next, the solder layer 86 is cooled, thereby bonding the semiconductor light emitting element 10 to the solder layer 86.

[0079] In the joining step according to the present embodiment, the heating step is performed before the contacting step, but the heating step may be performed after the contacting step.

[0080] Through the steps described above, the semiconductor device 1 can be manufactured.

[0081] Although the insulating layer forming step described above illustrates an example in which the first recessed region 71 is formed by machining or the like, the method for forming the first recessed region 71 in the insulating layer forming step is not limited to this example. Below, a modified example of the insulating layer forming step will be described using FIGS. 31 to 36 . FIGS. 31 and 32 are, respectively, a schematic top view and a cross-sectional view of a first compact 75 used in the insulating layer forming step according to this modified example. FIG. 32 shows a cross-section of the first compact 75 taken along line XXXII-XXXII in FIG. 31 . FIG. 33 is a schematic top view illustrating the configuration of a second compact 76 used in the insulating layer forming step according to this modified example. FIG. 34 is a schematic cross-sectional view illustrating the first compact 75 and the second compact 76 in the lamination step of the insulating layer forming step according to this modified example. FIG. 35 is a schematic cross-sectional view illustrating the first compact 75 and the second compact 76 in the firing step of the insulating layer forming step according to this modified example. Fig. 36 is a schematic cross-sectional view showing an insulating layer 70 formed in the insulating layer forming step according to this modification. Figs. 34 to 36 show cross sections of a first molded body 75 and the like at the same position as in Fig. 32.

[0082] In the insulating layer forming process according to this modification, first, a first compact 75 shown in FIGS. 31 and 32 and a second compact 76 shown in FIG. 33 are prepared (compact preparation process). Each of the first compact 75 and the second compact 76 is a component that will become part of the insulating layer 70 when fired. The first compact 75 and the second compact 76 are components formed by compressing and molding granular raw materials that constitute the insulating layer 70. The first compact 75 and the second compact 76 may contain a binder. As shown in FIGS. 31 and 32, the first compact 75 has a plate-like shape and has a plurality of through holes 75h formed therein. As shown in FIG. 33, the second compact 76 has a plate-like shape.

[0083] 34, the first compact 75 and the second compact 76 are stacked (stacking step). In this step, the first compact 75 and the second compact 76 may be integrated by applying pressure or the like. This step allows the formation of a compact having a shape similar to that of the insulating layer 70.

[0084] 35, the stacked first compact 75 and second compact 76 are heated and fired (firing step), thereby producing the insulating layer 70 as shown in FIG.

[0085] In the insulating layer forming process according to this modification, a shape corresponding to the first recessed region 71 is formed in the pre-fired compact. The pre-fired compact has higher toughness than the fired compact, and is therefore less likely to break than the fired compact. Therefore, the thickness of the second compact 76, which corresponds to the thinnest portion of the insulating layer 70, can be made less than 150 μm.

[0086] In the insulating layer formation process of this modified example, no machining or other processing is required to form the first recessed region 71, which prevents the insulating layer 70 from being damaged during processing and prevents debris generated during processing from remaining in the insulating layer 70.

[0087] [1-3. Effects, etc.] The effects of the submount 7, etc. according to this embodiment will be described.

[0088] The submount 7 of this embodiment comprises an electrically insulating insulating layer 70 having a first main surface 77, a second main surface 78 located on the back side of the first main surface 77, and a first recessed region 71 that is a region recessed relative to the first main surface 77, and a metal layer 82 that covers at least a portion of the first recessed region 71, and the thickness of the metal layer 82 at a position facing the first recessed region 71 is greater than the depth of the first recessed region 71.

[0089] As described above, insulating layer 70 of submount 7 according to the present embodiment has first recessed region 71, and metal layer 82 is disposed in at least a portion of first recessed region 71. In other words, a portion of insulating layer 70 is replaced with metal layer 82 having a higher thermal conductivity (i.e., lower thermal resistance) than insulating layer 70. Therefore, submount 7 according to the present embodiment can achieve improved heat dissipation performance compared to a submount having an insulating layer that does not have first recessed region 71.

[0090] In order to improve the heat dissipation performance of the submount 7, it is necessary to reduce the thickness of the insulating layer 70. On the other hand, a thickness of at least approximately 150 nm is considered necessary to stably manufacture and use the insulating layer 70, which is formed of an electrically insulating material such as AlN or SiC, while avoiding damage. In this embodiment, by forming the first recessed region 71 in the insulating layer 70, it is possible to partially reduce the thickness of the insulating layer 70 to less than 150 nm while ensuring the structural strength of the insulating layer 70. Therefore, by using the first recessed region 71 as a heat dissipation path, the heat dissipation performance of the submount 7 can be improved. Furthermore, although the periphery of the first recessed region 71 of the insulating layer 70 is easily damaged (i.e., easily cracked), by covering the first recessed region 71 with the metal layer 82, damage to the periphery of the first recessed region 71 can be suppressed.

[0091] The submount 7 in this embodiment has a solder layer 86 arranged on the first main surface 77 via a metal layer 82, and the solder layer 86 may be arranged in an area of ​​the metal layer 82 corresponding to the first recessed area 71.

[0092] This allows a device such as the semiconductor light emitting device 10 to be bonded to the solder layer 86. By disposing the solder layer 86 in a region corresponding to the first recessed region 71, the first recessed region 71 can be used as a heat dissipation path for the bonded device. The first recessed region 71 has a relatively low thermal conductivity (i.e., high thermal resistance) and a small thickness of the insulating layer 70, thereby reducing the thermal resistance of the heat dissipation path. As shown in FIG. 3 and other figures, in a cross-sectional view perpendicular to the first main surface 77 (perpendicular to the first direction), the width of the first recessed region 71 in a direction parallel to the first main surface 77 (i.e., the second direction) may be wider than the width of the heat generation region of the device in a direction parallel to the first main surface 77. In the example of the semiconductor light emitting device 10 shown in FIG. 10 , the width of the heat generation region corresponds to the ridge width (i.e., the width of the ridge 24R in the X-axis direction). In devices other than the semiconductor light emitting device 10, the heat generation region may be defined as, for example, a region through which current passes. When the width of the first recessed region 71 is wider than the width of the heat generation region, the heat dissipation path including the first recessed region 71 can be efficiently utilized. Furthermore, in a cross-sectional view perpendicular to first main surface 77, the width of first recessed region 71 in a direction parallel to first main surface 77 may be wider than the width of the element in a direction parallel to first main surface 77. When the width of first recessed region 71 is wider than the width of the element, heat that spreads within the element can more efficiently utilize the heat dissipation path that includes first recessed region 71.

[0093] In the submount 7 according to this embodiment, the solder layer 86 extends in a first direction parallel to the first main surface 77, and the width W1 of the first recessed region 71 in a second direction parallel to the first main surface 77 and perpendicular to the first direction may be at least twice the maximum thickness T1 of the metal layer 82 at a position opposite the first recessed region 71.

[0094] When a device such as semiconductor light emitting element 10 is bonded to solder layer 86 of such a submount 7, heat generated by the device is conducted in a direction perpendicular to first main surface 77 and diffuses in directions at an angle of up to approximately 45 degrees relative to this direction (see the dashed arrow in FIG. 3 ). In submount 7 according to this embodiment, by making width W1 of first recessed region 71 at least twice the maximum thickness T1 of metal layer 82 at the position facing first recessed region 71, the heat dissipation path for most of the heat generated by the device bonded to solder layer 86 passes through first recessed region 71. This reduces the thermal resistance in the heat dissipation path.

[0095] In the submount 7 according to this embodiment, the periphery of the first recessed region 71 may have an inclined portion 71 s that is inclined with respect to the first main surface 77 .

[0096] Having the inclined portion 71s on the periphery of the first recessed region 71 in this manner can prevent a step-like portion from being formed on the periphery of the first recessed region 71. When forming the metal layer 82 in a region including a step-like portion, the metal layer 82 may be interrupted at the step-like portion. In this embodiment, having the inclined portion 71s on the periphery of the first recessed region 71 can reduce the step-like portion, thereby reducing the interruption of the metal layer 82, etc.

[0097] The semiconductor device 1 according to this embodiment includes a submount 7 and a semiconductor light emitting element 10 joined to a solder layer 86 .

[0098] The semiconductor device 1 according to this embodiment achieves the same effects as the submount 7 described above. Furthermore, in the semiconductor device 1 according to this embodiment, the semiconductor light emitting element 10 is bonded to the insulating layer 70 at a position corresponding to the first recessed region 71. Therefore, the heat dissipation path of the semiconductor light emitting element 10 passes through the first recessed region 71. This reduces the thermal resistance in the heat dissipation path. This makes it possible to suppress a temperature rise in the semiconductor light emitting element 10.

[0099] The method for manufacturing submount 7 according to this embodiment includes an insulating layer forming step of forming insulating layer 70 having first main surface 77, second main surface 78 located on the back side of first main surface 77, and first recessed region 71 that is a region recessed with respect to first main surface 77, and a metal layer forming step of forming metal layer 82 that covers at least a portion of first recessed region 71. The thickness of metal layer 82 at a position facing first recessed region 71 is greater than the depth of first recessed region 71.

[0100] This makes it possible to manufacture the submount 7 having high heat dissipation performance as described above.

[0101] The method for manufacturing the submount 7 according to this embodiment may include a solder layer formation step of forming a solder layer 86 disposed on the first main surface 77 via the metal layer 82. The solder layer 86 may be disposed in a region of the metal layer 82 that corresponds to the first recessed region 71.

[0102] This allows the manufacture of a submount 7 having a solder layer 86 to which an element such as semiconductor light emitting element 10 can be bonded. By disposing solder layer 86 in an area corresponding to first recessed region 71, first recessed region 71 can be used as a heat dissipation path for the bonded element. In first recessed region 71, insulating layer 70 has a relatively low thermal conductivity (i.e., a high thermal resistance) and is therefore thin, thereby reducing the thermal resistance in the heat dissipation path.

[0103] The method for manufacturing the semiconductor device 1 according to this embodiment includes a method for manufacturing the submount 7 and an element bonding step of bonding the semiconductor light emitting element 10 to the solder layer 86 .

[0104] This achieves the same effects as the above-described method for manufacturing the submount 7. Furthermore, in the method for manufacturing the semiconductor device 1 according to this embodiment, the semiconductor light emitting element 10 is bonded to the insulating layer 70 at a position corresponding to the first recessed region 71. Therefore, the heat dissipation path of the semiconductor light emitting element 10 passes through the first recessed region 71. This reduces the thermal resistance in the heat dissipation path, thereby suppressing the temperature rise of the semiconductor light emitting element 10.

[0105] (Embodiment 2) A submount and the like according to embodiment 2 will be described. The submount according to this embodiment differs from the submount 7 according to embodiment 1 mainly in the position where the first recessed region is formed. Below, the submount and the like according to this embodiment will be described, focusing on the differences from the submount 7 and the like according to embodiment 1.

[0106] [2-1. Configuration of Semiconductor Device] The configuration of the semiconductor device according to this embodiment will be described with reference to Figures 37 and 38. Figures 37 and 38 are first and second cross-sectional views, respectively, showing the configuration of semiconductor device 101 according to this embodiment. Figures 37 and 38 show cross sections perpendicular to the Y-axis direction and the X-axis direction of semiconductor device 101, respectively.

[0107] 37 and 38 , a semiconductor device 101 according to the present embodiment includes a semiconductor light emitting element 10 and a submount 107. The submount 107 according to the present embodiment includes an insulating layer 170 and a metal layer 182. In the present embodiment, the submount 107 further includes an underlayer 181, an intermediate layer 83, a coating layer 84, a barrier layer 85, a solder layer 86, an underlayer 191, a metal layer 192, an intermediate layer 93, and a coating layer 94. The submount 107 without a mounted element may also include a surface layer 87, similar to the submount 7 according to the first embodiment.

[0108] Insulating layer 170 according to the present embodiment is an electrically insulating layer having a first main surface 177, a second main surface 178 located on the back side of first main surface 177, and a first recessed region 171 that is a region recessed relative to second main surface 178. First recessed region 171 has a groove-like shape with a width W1 that extends in a first direction (a direction parallel to the Y-axis direction) parallel to first main surface 177. The shape of first recessed region 171 is the same as the shape of first recessed region 71 according to the first embodiment.

[0109] The base layer 181 is a conductive layer made of metal and disposed on the first main surface 177. The base layer 181 is in contact with the first main surface 177. In the present embodiment, the base layer 181 has a base portion 181M and an exposed portion 181L, as shown in FIG. 38 . In a plan view of the first main surface 177, the base layer 181 has a portion disposed in a region excluding both ends of the insulating layer 170 in the X-axis direction and the Y-axis direction (i.e., the peripheral portion of the insulating layer 170), a portion extending from the portion to one end of the insulating layer 170 in the Y-axis direction along the first recessed region 171, and a portion extending to the other end. The base portion 181M is a portion of the base layer 181 disposed between the insulating layer 170 and the metal layer 182 and serves as a base for the metal layer 182. In the present embodiment, the base portion 181M is disposed in a region of the first main surface 177 corresponding to the first recessed region 171. That is, the base portion 181M is disposed in a region overlapping the first recessed region 171 in a plan view of the first main surface 177. In the present embodiment, the base portion 181M is disposed in a position facing the base portion 191M with the insulating layer 170 interposed therebetween. The exposed portion 181L is a portion of the base layer 181 that is exposed from the metal layer 182. In the present embodiment, the base layer 181 has four exposed portions 181L. Two exposed portions 181L are connected to one end of the base portion 181M in the first direction, and the other two exposed portions 181L are connected to the other end of the base portion 181M in the first direction. The exposed portions 181L can be used as electrodes for supplying power to the base layer 181, for example, in a process of forming the metal layer 182 by plating.

[0110] The base layer 181 according to this embodiment may have a multi-layer structure similar to the base layer 81 according to the first embodiment.

[0111] The metal layer 182 is an example of a second metal layer disposed on the first main surface 177. The metal layer 182 is disposed in a region of the first main surface 177 corresponding to the first recessed region 171. The thermal conductivity of the metal layer 182 is greater than the thermal conductivity of the insulating layer 170. The metal layer 182 is made of, for example, Cu. In this embodiment, the metal layer 182 is disposed on the base portion 181M of the base layer 181. The metal layer 182 is disposed over the entire region of the base portion 181M.

[0112] The solder layer 86 is a conductive layer made of solder and disposed on the first main surface 177 via the metal layer 182. The solder layer 86 is disposed in an area of ​​the metal layer 182 that corresponds to the first recessed area 171.

[0113] The base layer 191 is a conductive layer made of metal that covers at least a portion of the first recessed region 171. In this embodiment, the base layer 191 has a base portion 191M and an exposed portion 191L, as shown in FIG. 38 . The base portion 191M is a portion of the base layer 191 that is disposed between the insulating layer 170 and the metal layer 192 and serves as a base for the metal layer 192. In this embodiment, the base layer 191 contacts the second main surface 178 or the first recessed region 171. The base portion 191M is disposed in the entire region of the first recessed region 171 except for both ends in the Y-axis direction, and on the second main surface 178 adjacent to these regions. The exposed portion 191L ​​is a portion of the base layer 191 that is exposed from the metal layer 192. The exposed portion 191L ​​is disposed on the second main surface 178. In this embodiment, the base layer 191 has four exposed portions 191L. Two of the exposed portions 191L ​​are connected to one end of the base portion 191M in the first direction, and the other two exposed portions 191L ​​are connected to the other end of the base portion 191M in the first direction. The exposed portions 191L ​​can be used as electrodes for supplying power to the base layer 191 in, for example, a process of forming a metal layer 192 or the like by plating.

[0114] The base layer 191 according to this embodiment may have a multi-layer structure, similar to the base layer 91 according to the first embodiment.

[0115] The metal layer 192 is a conductive layer made of metal and disposed on the second main surface 178. The metal layer 192 is an example of a first metal layer that covers at least a portion of the first recessed region 171. The thermal conductivity of the metal layer 192 is greater than that of the insulating layer 170. The metal layer 192 is made of, for example, Cu. In this embodiment, the metal layer 192 covers a portion of the second main surface 178 and a portion of the first recessed region 171 via the base layer 191. The metal layer 192 is disposed on the base portion 191M of the base layer 191. The metal layer 192 is disposed over the entire area of ​​the base portion 191M. The metal layer 192 has a thick film portion 192D disposed opposite the first recessed region 171 and a thin film portion 192F disposed opposite the second main surface 178.

[0116] The thickness (dimension in the Z-axis direction) of metal layer 192 at a position facing first recessed region 171 is greater than the depth of first recessed region 171. In other words, the thickness (dimension in the Z-axis direction) of metal layer 192 at each position facing first recessed region 171 is greater than the depth of first recessed region 171 from second main surface 178 at each position. Therefore, the surface of thick film portion 192D farther from insulating layer 170 (i.e., the interface with intermediate layer 83) is located on the negative side of second main surface 178 in the Z-axis direction.

[0117] In the present embodiment, the width W1 of the first recessed region 171 in the second direction is at least twice the maximum thickness T1 of the thick film portion 192D. The maximum thickness of the thick film portion 192D is, for example, at least 60 μm and at most 250 μm. The thickness of the thin film portion 192F is, for example, at least 10 μm and at most 150 μm.

[0118] [2-2. Manufacturing Method of Semiconductor Device] A manufacturing method of the semiconductor device 101 according to this embodiment will be described. The manufacturing method of the semiconductor device 101 according to this embodiment differs from the manufacturing method of the semiconductor device 1 according to the first embodiment in the manufacturing method of the submount 107.

[0119] The method for manufacturing the submount 107 according to this embodiment differs from the method for manufacturing the submount 7 according to embodiment 1 in the insulating layer formation process, the base layer formation process, the metal layer formation process, the planarization process, and the solder layer formation process.

[0120] In the insulating layer formation process according to this embodiment, an insulating layer 170 is formed having a first main surface 177, a second main surface 178 located on the back side of the first main surface 177, and a first recessed region 171 which is a region recessed relative to the second main surface 178.

[0121] In the base layer forming step according to the present embodiment, base layer 181 is formed on first main surface 177. In addition, in the base layer forming step, base layer 191 is formed on second main surface 178. In the present embodiment, base layer 191 is also formed in first recessed region 171.

[0122] In the metal layer forming step according to the present embodiment, a metal layer 192 is formed to cover at least a portion of the first recessed region 171 (metal layer forming step). The thickness of the metal layer 192 at a position facing the first recessed region 171 is greater than the depth of the first recessed region 171. Also in this embodiment, the metal layer forming step also forms a metal layer 182 that is disposed on the first main surface 177. The metal layer 182 is disposed in a region of the first main surface 177 that corresponds to the first recessed region 171.

[0123] In the planarization step according to this embodiment, the surface of the metal layer 192 is planarized.

[0124] The solder layer forming step according to the present embodiment forms the solder layer 86 disposed on the first main surface 177 via the metal layer 182. The solder layer 86 is disposed in an area of ​​the metal layer 182 that corresponds to the first recessed area 171.

[0125] The semiconductor device 101 can be manufactured by a manufacturing method including the steps described above.

[0126] [2-3. Effects, etc.] Submount 107 according to the present embodiment includes electrically insulating layer 170 having first main surface 177, second main surface 178 located on the back side of first main surface 177, and first recessed region 171 that is a region recessed with respect to second main surface 178, and metal layer 192 that covers at least a portion of first recessed region 171. The thickness of metal layer 192 at a position facing first recessed region 171 is greater than the depth of first recessed region 171.

[0127] The submount 107 according to the present embodiment also achieves the same effects as the submount 7 according to embodiment 1. Furthermore, in the submount 107 according to the present embodiment, no recessed region is formed on the first main surface 177 side of the insulating layer 170, and therefore, when an element is mounted on the first main surface 177 side, the accuracy of the position and tilt of the element can be improved.

[0128] The submount 107 according to this embodiment may include a metal layer 182 disposed on the first main surface 177. The metal layer 182 may be disposed in a region of the first main surface 177 that corresponds to the first recessed region 171.

[0129] By providing the submount 107 with such a metal layer 182 , when an element is mounted on the first main surface 177 side of the submount 107 , heat can be dissipated in the metal layer 182 .

[0130] The submount 107 according to the present embodiment may include a solder layer 86 disposed on the first main surface 177 via the metal layer 182. The solder layer 86 may be disposed in a region of the metal layer 182 that corresponds to the first recessed region 171.

[0131] By providing the submount 107 with such solder layer 86, it is possible to mount a device on the submount 107. Furthermore, by arranging the solder layer 86 in an area corresponding to the first recessed area 171, the first recessed area 171 can be used as a heat dissipation path for the bonded device. In the first recessed area 171, the thickness of the insulating layer 170, which has a relatively low thermal conductivity, is small, so the thermal resistance in the heat dissipation path can be reduced.

[0132] The semiconductor device 101 according to this embodiment includes a submount 107 and a semiconductor light emitting element 10 joined to a solder layer 86 .

[0133] The semiconductor device 101 according to this embodiment achieves the same effects as the submount 107 described above. Furthermore, in the semiconductor device 101 according to this embodiment, the semiconductor light emitting element 10 is bonded to the insulating layer 170 at a position corresponding to the first recessed region 171. Therefore, the heat dissipation path of the semiconductor light emitting element 10 passes through the first recessed region 171. This reduces the thermal resistance in the heat dissipation path. This makes it possible to suppress a temperature rise in the semiconductor light emitting element 10.

[0134] The method for manufacturing submount 107 according to this embodiment includes an insulating layer forming step of forming insulating layer 170 having first main surface 177, second main surface 178 located on the back side of first main surface 177, and first recessed region 171 that is a region recessed with respect to second main surface 178, and a metal layer forming step of forming metal layer 192 that covers at least a portion of first recessed region 171. The thickness of metal layer 192 at a position facing first recessed region 171 is greater than the depth of first recessed region 171.

[0135] This allows the submount 107 to be manufactured with high heat dissipation performance.

[0136] In the metal layer formation step of the method for manufacturing submount 107 according to the present embodiment, metal layer 182 may be formed on first main surface 177. Metal layer 182 may be disposed in a region of first main surface 177 that corresponds to first recessed region 171.

[0137] By providing the submount 107 with such a metal layer 182 , when an element is mounted on the first main surface 177 side of the submount 107 , heat can be dissipated in the metal layer 182 .

[0138] The method for manufacturing submount 107 according to the present embodiment may include a solder layer formation step of forming solder layer 86 disposed on first main surface 177 via metal layer 182. Solder layer 86 may be disposed in a region of metal layer 182 that corresponds to first recessed region 171.

[0139] By providing the submount 107 with such solder layer 86, it is possible to mount a device on the submount 107. Furthermore, by arranging the solder layer 86 in an area corresponding to the first recessed area 171, the first recessed area 171 can be used as a heat dissipation path for the bonded device. In the first recessed area 171, the thickness of the insulating layer 170, which has a relatively low thermal conductivity, is small, so the thermal resistance in the heat dissipation path can be reduced.

[0140] The method for manufacturing the semiconductor device 101 according to this embodiment includes a method for manufacturing the submount 107 and an element bonding step of bonding the semiconductor light emitting element 10 to the solder layer 86 .

[0141] This achieves the same effects as the above-described method for manufacturing the submount 107. Furthermore, in the method for manufacturing the semiconductor device 101 according to this embodiment, the semiconductor light emitting element 10 is bonded to the insulating layer 170 at a position corresponding to the first recessed region 171. Therefore, the heat dissipation path of the semiconductor light emitting element 10 passes through the first recessed region 171. This reduces the thermal resistance in the heat dissipation path, thereby suppressing the temperature rise of the semiconductor light emitting element 10.

[0142] (Embodiment 3) A submount and the like according to embodiment 3 will be described. The submount according to this embodiment differs from the submount 7 according to embodiment 1 mainly in the configuration of the first recessed region. Below, the submount and the like according to this embodiment will be described, focusing on the differences from the submount 7 and the like according to embodiment 1.

[0143] [3-1. Configuration of Semiconductor Device] The configuration of the semiconductor device according to this embodiment will be described with reference to Figures 39 and 40. Figures 39 and 40 are a top view and a cross-sectional view, respectively, showing the configuration of a semiconductor device 201 according to this embodiment. Figure 40 shows a cross section perpendicular to the X-axis direction of the semiconductor device 201.

[0144] 39 and 40 , a semiconductor device 201 according to the present embodiment includes a semiconductor light emitting element 10 and a submount 207 (see FIG. 40 ). The submount 207 according to the present embodiment includes an insulating layer 270 and a metal layer 282. In the present embodiment, the submount 207 further includes an underlayer 281, an intermediate layer 83, a coating layer 84, a barrier layer 85, a solder layer 86, a underlayer 91, a metal layer 92, an intermediate layer 93, and a coating layer 94. The submount 207 without a mounted element may also include a surface layer 87, similar to the submount 7 according to the first embodiment.

[0145] The insulating layer 270 in this embodiment is an electrically insulating layer having a first main surface 277, a second main surface 278 located on the back side of the first main surface 277, and a first recessed region 271 that is a region recessed relative to the first main surface 277.

[0146] The first recessed region 271 according to the present embodiment has a plurality of first recesses 271r, each of which is a region recessed relative to the first main surface 277. In the present embodiment, each of the plurality of first recesses 271r is a recess having a cylindrical shape, and as shown in FIG. 39 , has a circular shape in a plan view of the first main surface 277. The plurality of first recesses 271r are arranged in a line along the first direction. The width in the second direction of each of the plurality of first recesses 271r may be two or more times the maximum thickness of the metal layer 282 at a position facing the first recessed region 271.

[0147] The base layer 281 is a conductive layer made of metal and disposed on the first main surface 277. The base layer 281 contacts the first main surface 277 or the first recessed region 271. In the present embodiment, the base layer 281 has a base portion 281M and an exposed portion 281L, as shown in FIG. 40 . The base portion 281M is a portion of the base layer 281 that is disposed between the insulating layer 270 and the metal layer 282 and serves as a base for the metal layer 282. In the present embodiment, the base portion 281M is disposed in a region of the first main surface 277 that corresponds to the first recessed region 271. In other words, the base portion 281M is disposed in a region that overlaps the first recessed region 271 in a plan view of the first main surface 277. In the present embodiment, the base portion 281M is disposed in a position facing the base portion 281M with the insulating layer 270 interposed therebetween. 39 and 40 , the exposed portions 281L are portions of the base layer 281 that are exposed from the metal layer 282. In the present embodiment, the base layer 281 has four exposed portions 281L. Two of the exposed portions 281L are connected to one end of the base portion 281M in the first direction, and the other two exposed portions 281L are connected to the other end of the base portion 281M in the first direction.

[0148] The base layer 281 according to this embodiment may have a multi-layer structure similar to the base layer 81 according to the first embodiment.

[0149] The metal layer 282 is a conductive layer made of metal and disposed on the first main surface 277. The metal layer 282 is an example of a first metal layer that covers at least a portion of the first recessed region 271. The thermal conductivity of the metal layer 282 is greater than that of the insulating layer 270. The metal layer 282 is made of, for example, Cu. In this embodiment, the metal layer 282 covers a portion of the first main surface 277 and a portion of the first recessed region 271 via the base layer 281. The metal layer 282 is disposed on a base portion 281M of the base layer 281. The metal layer 282 is disposed over the entire area of ​​the base portion 281M. The metal layer 282 has a thick film portion 282D disposed opposite the first recessed region 271 and a thin film portion 282F disposed opposite the first main surface 277.

[0150] 3-2. Effects, etc. In the submount 207 according to this embodiment, the first recessed region 271 includes a plurality of first recesses 271 r, each of which is a region recessed relative to the first main surface 277 .

[0151] Such a submount 207 also achieves the same effects as the submount 107 according to embodiment 1. Furthermore, since the first recessed region 271 includes a plurality of first recesses 271r that are spaced apart from one another, it is possible to reduce distortion in the insulating layer 270 compared to when the first recessed region 271 consists of a single continuous recess. Furthermore, when the first recessed region 271 includes a plurality of first recesses 271r, it is possible to reduce the amount of metal layer 282 disposed in the first recessed region 271.

[0152] [3-3. Modifications] Modifications 1 to 3 of the first recessed region 271 according to the present embodiment will be described with reference to Figs. 41 to 43. Fig. 41 is a schematic top view showing the configuration of a semiconductor device 201a according to Modification 1 of the present embodiment. Fig. 42 is a schematic top view showing the configuration of a semiconductor device 201b according to Modification 2 of the present embodiment. Fig. 43 is a schematic top view showing the configuration of a semiconductor device 201c according to Modification 3 of the present embodiment.

[0153] As shown in FIG. 41 , a semiconductor device 201a according to Modification 1 of this embodiment includes a submount 207a and a semiconductor light emitting element 10. The submount 207a according to Modification 1 includes an insulating layer 270a. The insulating layer 270a has a first recessed region 271a that is a region recessed with respect to a first main surface 277. The first recessed region 271a according to Modification 1 includes a plurality of first recesses 271ra, each of which is a region recessed with respect to the first main surface 277. The plurality of first recesses 271ra may be arranged in a plurality of rows in the first direction. In the example shown in FIG. 41 , the plurality of first recesses 271ra are arranged in two rows. Furthermore, the positions of the plurality of first recesses 271ra arranged in the two rows in the first direction may be different from each other. Furthermore, the arrangement of the plurality of first recesses 271ra may be a so-called staggered arrangement.

[0154] The submount 207a and semiconductor device 201a according to Modification 1 having such a configuration also achieves the same effects as the submount 207 and semiconductor device 201 according to the present embodiment.

[0155] As shown in FIG. 42 , a semiconductor device 201b according to Modification 2 of the present embodiment includes a submount 207b and a semiconductor light emitting element 10. The submount 207b according to Modification 2 includes an insulating layer 270b. The insulating layer 270b has a first recessed region 271b that is a region recessed with respect to the first main surface 277. The first recessed region 271b according to Modification 2 includes a plurality of first recesses 271rb, each of which is a region recessed with respect to the first main surface 277. The plurality of first recesses 271rb are arranged in a line in the first direction. As shown in FIG. 42 , the plurality of first recesses 271rb according to Modification 2 are arranged in a region corresponding to the ridge 24R of the semiconductor light emitting element 10. In other words, the plurality of first recesses 271rb according to Modification 2 overlap the ridge 24R of the semiconductor light emitting element 10 in a plan view of the first main surface 277.

[0156] The submount 207b and semiconductor device 201b according to Modification 2, which have such a configuration, also achieve the same effects as the submount 207 and semiconductor device 201 according to the present embodiment. Furthermore, the multiple first recesses 271rb according to Modification 2 are arranged in a region corresponding to the ridge 24R. This reduces the size of the first recessed region 271b, thereby further reducing distortion in the insulating layer 270b. Furthermore, the first recessed region 271b is arranged in a region corresponding to the ridge 24R, which is a region of the semiconductor light emitting element 10 that generates a particularly large amount of heat, thereby suppressing a decrease in heat dissipation performance. Furthermore, the multiple first recesses 271rb may be arranged only in the region corresponding to the ridge 24R. This allows the first recessed region 271b to be further reduced. Therefore, distortion in the insulating layer 270b can be further reduced.

[0157] As shown in FIG. 43 , a semiconductor device 201c according to Modification 3 of this embodiment includes a submount 207c and a semiconductor light emitting element 10. The submount 207c according to Modification 3 includes an insulating layer 270c. The insulating layer 270c has a first recessed region 271c that is a region recessed with respect to the first main surface 277. The first recessed region 271c according to Modification 3 includes a plurality of first recesses 271rc, each of which is a region recessed with respect to the first main surface 277. The plurality of first recesses 271rc may be arranged in a plurality of rows in the first direction. In the example shown in FIG. 43 , the plurality of first recesses 271rc are arranged in two rows. Furthermore, the plurality of first recesses 271rc are arranged outside and along the region corresponding to the ridge 24R.

[0158] The submount 207c and semiconductor device 201c according to Modification 3 having such a configuration also achieve the same effects as the submount 207 and semiconductor device 201 according to the present embodiment. Furthermore, the multiple first recesses 271rc according to Modification 3 are arranged along the region corresponding to the ridge 24R, which is a region in the semiconductor light emitting element 10 that generates a particularly large amount of heat, thereby improving the heat dissipation performance of the submount 207c.

[0159] Furthermore, the multiple first recesses 271rc are arranged outside the region corresponding to the ridge 24R. This allows the region of the insulating layer 270c on the first main surface 277 side corresponding to the ridge 24R to be flattened. This allows for increased accuracy in the position and inclination of the ridge 24R.

[0160] Furthermore, in each submount according to this embodiment and its modified examples, each first recessed region is a region recessed relative to the first main surface 277, but it may also be a region recessed relative to the second main surface 278.

[0161] (Embodiment 4) A submount and the like according to embodiment 4 will be described. The submount according to this embodiment differs from submount 7 according to embodiment 1 mainly in that the insulating layer has a second recessed region in addition to the first recessed region. Below, the submount and the like according to this embodiment will be described, focusing on the differences from submount 7 and the like according to embodiment 1.

[0162] [4-1. Configuration of Semiconductor Device] The configuration of the semiconductor device according to this embodiment will be described with reference to Figures 44 and 45. Figures 44 and 45 are first and second cross-sectional views, respectively, showing the configuration of semiconductor device 301 according to this embodiment. Figures 44 and 45 show cross sections perpendicular to the Y-axis direction and the X-axis direction of semiconductor device 301, respectively.

[0163] 44 and 45 , a semiconductor device 301 according to the present embodiment includes a semiconductor light emitting element 10 and a submount 307. The submount 307 according to the present embodiment includes an insulating layer 370 and a metal layer 382. In the present embodiment, the submount 307 further includes an underlayer 381, an intermediate layer 83, a coating layer 84, a barrier layer 85, a solder layer 86, a underlayer 391, a metal layer 392, an intermediate layer 93, and a coating layer 94. The submount 307 without a mounted element may also include a surface layer 87, similar to the submount 7 according to the first embodiment.

[0164] The insulating layer 370 according to this embodiment is an electrically insulating layer having a first main surface 377, a second main surface 378 located on the back side of the first main surface 377, and a first recessed region 371 that is a region recessed relative to the first main surface 377. In this embodiment, the first recessed region 371 has a groove-like shape with a width W1 extending in the first direction. The width W1 of the first recessed region 371 in the second direction may be approximately the same as the width W1 of the first recessed region 371 in the second direction according to the first embodiment. The insulating layer 370 also has a second recessed region 372 that is a region recessed relative to the second main surface 378. In this embodiment, the second recessed region 372 has a groove-like shape with a width W2 extending in the first direction. The second recessed region 372 is disposed in a region corresponding to the first recessed region 371. That is, in a plan view of the second main surface 378, the second recessed region 372 overlaps the first recessed region 371.

[0165] The area of ​​the second main surface 378 of the second recessed region 372 in a plan view is larger than the area of ​​the first main surface 377 of the first recessed region 371 in a plan view. Also, as shown in Figure 44, the width W2 of the second recessed region 372 in the second direction is larger than the width W1 of the first recessed region 371 in the second direction.

[0166] The thickness of the portion of the insulating layer 370 where the first recessed region 371 and the second recessed region 372 are not formed is 150 μm or more. The thickness of the portion of the insulating layer 370 where the first recessed region 371 and the second recessed region 372 are not formed may be 200 μm or less. The thickness T0 of the thinnest portion of the insulating layer 370 between the first recessed region 371 and the second recessed region 372 is less than 150 μm. In this embodiment, the thickness T0 is 50 μm or more and less than 150 μm. The thickness T0 may be 50 μm or more and less than 100 μm, or 50 μm or more and less than 75 μm.

[0167] The base layer 381 is a conductive layer made of metal and disposed on the first main surface 377. The base layer 381 contacts the first main surface 377 or the first recessed region 371. In this embodiment, as shown in FIG. 45 , the base layer 381 has a base portion 381M and an exposed portion 381L. The base portion 381M is a portion of the base layer 381 that is disposed between the insulating layer 370 and the metal layer 382 and serves as a base for the metal layer 382. In this embodiment, the base portion 381M is disposed in a region of the first main surface 377 that corresponds to the first recessed region 371. In other words, the base portion 381M is disposed in a region that overlaps the first recessed region 371 in a plan view of the first main surface 377. In this embodiment, the base portion 381M is disposed in a position facing the base portion 391M of the base layer 391, with the insulating layer 370 interposed therebetween. The exposed portions 381L are portions of the base layer 381 that are exposed from the metal layer 382. In the present embodiment, the base layer 381 has four exposed portions 381L. Two of the exposed portions 381L are connected to one end of the base portion 381M in the first direction, and the other two exposed portions 381L are connected to the other end of the base portion 381M in the first direction.

[0168] The base layer 381 according to this embodiment may have a multi-layer structure similar to the base layer 81 according to the first embodiment.

[0169] The metal layer 382 is a conductive layer made of metal and disposed on the first main surface 377. The metal layer 382 is an example of a first metal layer that covers at least a portion of the first recessed region 371. The thermal conductivity of the metal layer 382 is greater than that of the insulating layer 370. The metal layer 382 is made of, for example, Cu. In this embodiment, the metal layer 382 covers a portion of the first main surface 377 and a portion of the first recessed region 371 via the base layer 381. The metal layer 382 is disposed on a base portion 381M of the base layer 381. The metal layer 382 is disposed over the entire area of ​​the base portion 381M. The metal layer 382 has a thick film portion 382D disposed opposite the first recessed region 371 and a thin film portion 382F disposed opposite the first main surface 377. The thickness of the metal layer 382 at the position opposite the first recessed region 371 is greater than the depth of the first recessed region 371.

[0170] The width W1 of the first recessed region 371 in the second direction may be at least twice the maximum thickness T1 of the thick film portion 382D. The maximum thickness T1 of the thick film portion 382D is, for example, 60 μm or more and 250 μm or less. The thickness of the thin film portion 382F is, for example, 10 μm or more and 150 μm or less.

[0171] The base layer 391 is a conductive layer made of metal and disposed on the second main surface 378. The base layer 391 contacts the second main surface 378 or the second recessed region 372. In this embodiment, as shown in FIG. 45 , the base layer 391 has a base portion 391M and an exposed portion 391L. The base portion 391M is a portion of the base layer 391 that is disposed between the insulating layer 370 and the metal layer 392 and serves as a base for the metal layer 392. In this embodiment, the base portion 391M is disposed in a region of the second main surface 378 that corresponds to the second recessed region 372. In other words, the base portion 391M is disposed in a region that overlaps the second recessed region 372 in a plan view of the second main surface 378. In this embodiment, the base portion 391M is disposed opposite the base portion 381M of the base layer 381, with the insulating layer 370 interposed therebetween. The exposed portions 391L are portions of the base layer 391 that are exposed from the metal layer 392. In the present embodiment, the base layer 391 has four exposed portions 391L. Two of the exposed portions 391L are connected to one end of the base portion 391M in the first direction, and the other two exposed portions 391L are connected to the other end of the base portion 391M in the first direction.

[0172] The base layer 391 according to this embodiment may have a multi-layer structure similar to the base layer 91 according to the first embodiment.

[0173] The metal layer 392 is a conductive layer made of metal and disposed on the second main surface 378. The metal layer 392 is an example of a second metal layer that covers at least a portion of the second recessed region 372. The thermal conductivity of the metal layer 392 is greater than that of the insulating layer 370. The metal layer 392 is made of, for example, Cu. In this embodiment, the metal layer 392 covers a portion of the second main surface 378 and a portion of the second recessed region 372 via the base layer 391. The metal layer 392 is disposed on a base portion 391M of the base layer 391. The metal layer 392 is disposed over the entire area of ​​the base portion 391M. The metal layer 392 has a thick film portion 392D disposed opposite the second recessed region 372 and a thin film portion 392F disposed opposite the second main surface 378. The thickness of the metal layer 392 at the position opposite the second recessed region 372 is greater than the depth of the second recessed region 372.

[0174] The width W2 of the second recessed region 372 in the second direction may be at least twice the maximum thickness T2 of the thick film portion 392D. The maximum thickness T2 of the thick film portion 392D is, for example, 60 μm or more and 250 μm or less. The thickness of the thin film portion 382F is, for example, 10 μm or more and 150 μm or less.

[0175] [4-2. Manufacturing Method of Semiconductor Device] A manufacturing method of the semiconductor device 301 according to this embodiment will be described. The manufacturing method of the semiconductor device 301 according to this embodiment differs from the manufacturing method of the semiconductor device 1 according to the first embodiment in the manufacturing method of the submount 307.

[0176] The method for manufacturing the submount 307 according to this embodiment differs from the method for manufacturing the submount 7 according to the first embodiment in the insulating layer forming step, the underlayer forming step, the metal layer forming step, and the planarizing step.

[0177] In the insulating layer formation step according to the present embodiment, insulating layer 370 is formed having first main surface 377, second main surface 378 located on the back side of first main surface 377, and first recessed region 371 which is a region recessed relative to first main surface 377. In the present embodiment, insulating layer 370 has second recessed region 372 which is a region recessed relative to second main surface 378. First recessed region 371 and second recessed region 372 can be formed in the same manner as first recessed region 71 according to the first embodiment.

[0178] In the metal layer forming step according to the present embodiment, a metal layer 382 is formed to cover at least a portion of the first recessed region 371. Furthermore, in the metal layer forming step, a metal layer 392 is formed to cover at least a portion of the second recessed region 372.

[0179] In the planarization step according to the present embodiment, the surface of the metal layer 382 is planarized. In the planarization step, the surface of the metal layer 392 may also be planarized.

[0180] [4-3. Effects, etc.] Submount 307 according to this embodiment includes metal layer 392 disposed on second main surface 378. Insulating layer 370 has second recessed region 372 that is a region recessed with respect to second main surface 378, and second recessed region 372 is disposed in a region corresponding to first recessed region 371. Metal layer 392 covers at least a portion of second recessed region 372, and the thickness of metal layer 392 at a position facing second recessed region 372 is greater than the depth of second recessed region 372.

[0181] The submount 307 according to the present embodiment also achieves the same effects as the submount 7 according to embodiment 1. Furthermore, in the submount 307 according to the present embodiment, recessed regions are formed on both the first main surface 377 side and the second main surface 378 side of the insulating layer 370, which makes it possible to suppress warping of the insulating layer 370 more effectively than when a recessed region is formed only on one main surface side of the insulating layer 370.

[0182] Submount 307 according to the present embodiment may include solder layer 86 disposed on first main surface 377 via metal layer 382. Solder layer 86 may be disposed in a region of metal layer 382 that corresponds to first recessed region 371. The area of ​​second main surface 378 of second recessed region 372 in a plan view may be larger than the area of ​​first main surface 377 of first recessed region 371 in a plan view.

[0183] Such a submount 307 allows elements and the like to be bonded to the solder layer 86. As described above, heat generated in elements is conducted while diffusing, so by increasing the area of ​​the second recessed region 372, which is farther from the solder layer 86 than the first recessed region 371, it is possible to reduce the extent to which the path of heat conducted to the first recessed region 371 extends outside the second recessed region 372. Here, the heat dissipation path passing through the first recessed region 371 and the second recessed region 372 has low thermal resistance because the thickness of the insulating layer 370 is small. Therefore, the submount 307 according to this embodiment can further improve heat dissipation performance.

[0184] The submount 307 according to this embodiment may include a solder layer 86 disposed on the first main surface 377 via a metal layer 382. The solder layer 86 is disposed in a region of the metal layer 382 corresponding to the first recessed region 371 and extends in a first direction parallel to the first main surface 377. The width W2 of the second recessed region 372 in a second direction parallel to the first main surface 377 and perpendicular to the first direction may be greater than the width W1 of the first recessed region 371 in the second direction.

[0185] Such a submount 307 allows elements and the like to be bonded to the solder layer 86. As described above, heat generated in elements is conducted while diffusing, so by increasing the width of the second recessed region 372, which is farther from the solder layer 86 than the first recessed region 371, it is possible to reduce the extent to which the path of heat conducted to the first recessed region 371 extends outside the second recessed region 372. Here, the heat dissipation path passing through the first recessed region 371 and the second recessed region 372 has low thermal resistance because the thickness of the insulating layer 370 is small. Therefore, the submount 307 according to this embodiment can further improve heat dissipation performance.

[0186] In the metal layer formation step of the method for manufacturing submount 307 according to the present embodiment, metal layer 392 is formed on second main surface 378. Insulating layer 370 has second recessed region 372, which is a region recessed with respect to second main surface 378. Metal layer 392 covers at least a portion of second recessed region 372. The thickness of metal layer 392 at a position facing second recessed region 372 is greater than the depth of second recessed region 372.

[0187] This provides the same effects as those of the submount 307 according to the present embodiment described above.

[0188] Fifth Embodiment A submount according to a fifth embodiment will be described. The submount according to this embodiment differs from the submount 7 according to the first embodiment in the configuration of the metal layer. The following description of the submount according to this embodiment will focus on the differences from the submount 7 according to the first embodiment and the like.

[0189] [5-1. Submount Configuration] The configuration of the semiconductor device according to this embodiment will be described with reference to Fig. 46. Fig. 46 is a cross-sectional view showing the configuration of a submount 407 according to this embodiment. Fig. 46 shows a cross section of the submount 407 perpendicular to the Y-axis direction.

[0190] The submount 407 according to the present embodiment includes an insulating layer 70 and a metal layer 482. In the present embodiment, the submount 407 also includes an underlayer 81, an intermediate layer 483, a covering layer 484, a barrier layer 485, a solder layer 486, a surface layer 487, an underlayer 91, a metal layer 92, an intermediate layer 93, and a covering layer 94.

[0191] The metal layer 482 according to the present embodiment has a thick portion 482D and a thin portion 482F. The metal layer 482 differs from the metal layer 82 according to the first embodiment in that it has a recess 482u on its surface. The recess 482u of the metal layer 482 is formed in a region corresponding to the first recessed region 71. The metal layer 482 corresponds to the metal layer 82 according to the first embodiment before the planarization step is performed. In other words, the method for manufacturing the submount 407 according to the present embodiment differs from the method for manufacturing the submount 7 according to the first embodiment in that it does not include the planarization step.

[0192] The intermediate layer 483, the covering layer 484, the barrier layer 485, the solder layer 486, and the surface layer 487 according to the present embodiment are layers having the same composition and thickness as the intermediate layer 83, the covering layer 84, the barrier layer 85, the solder layer 86, and the surface layer 87 according to the first embodiment, respectively. In the present embodiment, each of these layers has a cross-sectional shape that conforms to the surface of the metal layer 482. For example, the surface layer 487 has a recess 487u, and the solder layer 486 has a recess 486u.

[0193] [5-2. Effects] In the submount 407 according to this embodiment, the metal layer 482 has a recess 482u formed on the surface.

[0194] This makes it possible to distinguish between the first main surface 77 side and the second main surface 78 side of the submount 407 based on the metal layer 482 of the recess 482u and the metal layer 92 having a flat surface. Therefore, the surface of the submount 407 on which the element is mounted can be easily identified.

[0195] (Modifications, etc.) Although the submount and the like according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to the above-described embodiments.

[0196] For example, in the first embodiment, the inclined portion 71s of the first recessed region 71 has a planar shape, but the configuration of the inclined portion is not limited to this. A modified example of the inclined portion will be described with reference to FIG. 47 . FIG. 47 is a schematic side view showing the configuration of an insulating layer 570 according to the first modification. The insulating layer 570 shown in FIG. 47 has a first recessed region 571. The periphery of the first recessed region 571 has an inclined portion 571s. As shown in FIG. 47 , the inclined portion 571s may have a curved shape. This can prevent damage to the periphery of the first recessed region 571.

[0197] Furthermore, in the above-described embodiments and modifications, the metal layer disposed on the first principal surface and the metal layer disposed on the second principal surface are disposed at corresponding positions, but the configuration of each metal layer is not limited to this. Modifications of the configuration of each metal layer will be described using Figures 48 and 49. Figures 48 and 49 are schematic cross-sectional views showing the configuration of semiconductor device 1 according to Modifications 2 and 3, respectively. Figures 48 and 49 show a portion of a cross section perpendicular to the X-axis that passes through semiconductor light-emitting element 10 of semiconductor device 1.

[0198] Each semiconductor device 1 shown in FIGS. 48 and 49 differs from the semiconductor device 1 according to the first embodiment in the positions of the ends of the metal layer 92 and the like.

[0199] As shown in FIG. 48 , among the end faces of the metal layer 92 in the first direction, an end face 92E closer to the end face 10F of the semiconductor light-emitting element 10 may be located on the more positive side in the Y-axis direction than an end face 82E, among the end faces of the metal layer 82 in the first direction, closer to the end face 10F of the semiconductor light-emitting element 10. In the semiconductor light-emitting element 10, heat is generated most near the end face 10F. Heat generated near the end face 10F of the semiconductor light-emitting element 10 is conducted from the metal layer 82 toward the insulating layer 70, as indicated by the dashed arrows in FIG. 48 . In this modification, this heat can be diffused in the positive direction in the Y-axis direction in the metal layer 92, as indicated by the dashed arrows in FIG. 48 . Therefore, the heat dissipation performance of the submount 7 can be further improved.

[0200] Furthermore, in each of the submounts according to the above-described embodiments and modifications, only one integrated electrode including a metal layer is formed on the first main surface side, but the electrode configuration is not limited to this. Modifications of the electrode configuration will be described using Figures 49 and 50. Figures 49 and 50 are schematic top and cross-sectional views, respectively, showing the configuration of a submount 607 according to Modification 3. Figure 50 shows a cross section of the submount 607 perpendicular to the Y-axis direction.

[0201] 49 and 50 , like the submount 7 according to embodiment 1, the submount 607 according to this modification further includes an insulating layer 70, a metal layer 82, a base layer 81, an intermediate layer 83, a coating layer 84, a barrier layer 85, a solder layer 86, a base layer 91, a metal layer 92, an intermediate layer 93, and a coating layer 94. Furthermore, the submount 607 includes a base layer 681, a metal layer 682, an intermediate layer 683, and a coating layer 684.

[0202] The underlayer 681, metal layer 682, intermediate layer 683, and coating layer 684 according to this modification have the same composition and thickness as the underlayer 81, metal layer 82, intermediate layer 83, and coating layer 84 according to embodiment 1, respectively. The underlayer 681 is disposed on the first main surface 77 and is separated from the underlayer 81 via a separation region 80i. The metal layer 682 is disposed on the first main surface 77 via the underlayer 81 and is separated from the metal layer 82. The intermediate layer 683 is disposed on the first main surface 77 via the underlayer 81 and metal layer 682 and is separated from the intermediate layer 83. The coating layer 684 is disposed on the first main surface 77 via the underlayer 81, metal layer 682, and intermediate layer 683 and is separated from the coating layer 84.

[0203] As described above, the electrode including the base layer 681, the metal layer 682, the intermediate layer 683, and the covering layer 684 functions as an electrode electrically insulated from the electrode including the base layer 81, the metal layer 82, the intermediate layer 83, and the covering layer 84. The electrode including the metal layer 682 and the like can be used, for example, as a relay electrode.

[0204] In addition, in each of the above embodiments, the element included in the semiconductor device is the semiconductor light emitting element 10, but the configuration of the element is not limited to this. The element included in the semiconductor device may be, for example, any semiconductor element other than the semiconductor light emitting element.

[0205] This disclosure also includes forms obtained by applying various modifications to the embodiments that a person skilled in the art would conceive, and forms realized by arbitrarily combining the components and functions in each embodiment within the scope of the present disclosure.

[0206] The submount and the like according to the present disclosure can be particularly used in, for example, semiconductor devices including high-output semiconductor light-emitting elements.

[0207] 1, 101, 201, 201a, 201b, 201c, 301 Semiconductor device 7, 107, 207, 207a, 207b, 207c, 307, 407, 607 Submount 10 Semiconductor light emitting element 10F, 10R End face 10S Semiconductor laminate 21 Substrate 22 N-side semiconductor layer 23 Active layer 24 P-side semiconductor layer 24P Protrusion 24R Ridge 24T Groove 25 Contact layer 30 Insulating layer 32 Adhesion layer 40 Contact electrode 50 Pad layer 51 Contact region 52 External region 60 N-side electrode 70, 170, 270, 270a, 270b, 270c, 370, 570 Insulating layer 71, 171, 271, 271a, 271b, 271c, 371, 571 First concave region 71s, 571s Inclined portion 75 First molded body 75h Through hole 76 Second molded body 77, 177, 277, 377 First main surface 78, 178, 278, 378 Second main surface 80i Separation region 81, 181, 281, 91, 191, 281, 381, 391, 681 Base layer 81a, 91a First layer 81b, 91b Second layer 81c, 91c Third layer 81d, 91d Fourth layer 81L, 91L, 181L, 191L, 281L, 381L, 391L Exposed part 81M, 91M, 181M, 191M, 281M, 381M, 391M Base portion 82, 182, 92, 192, 282, 382, ​​392, 482, 682 Metal layer 82D, 192D, 382D, 392D, 482D Thick film portion 82E, 92E End surface 82F, 192F, 382F, 392F, 482F Thin film portion 83, 93, 483, 683 Intermediate layer 84, 94, 484, 684 Coating layer 85, 485 Barrier layer 86, 486 Solder layer 87, 487 Surface layer 271r, 271ra, 271rb, 271rc First recess 372 Second recessed region 482u, 486u, 487u Recesses

Claims

1. A submount comprising: an electrically insulating layer having a first main surface, a second main surface located on the back side of the first main surface, and a region recessed relative to the first main surface or a first recessed region that is a region recessed relative to the second main surface; and a first metal layer covering at least a portion of the first recessed region, wherein the thickness of the first metal layer at a position facing the first recessed region is greater than the depth of the first recessed region.

2. The submount according to claim 1, wherein the first recessed area is a region recessed relative to the first main surface.

3. The submount according to claim 2, wherein the submount comprises a second metal layer disposed on the second main surface, the insulating layer has a second recessed region that is recessed relative to the second main surface, the second recessed region is disposed in a region corresponding to the first recessed region, the second metal layer covers at least a portion of the second recessed region, and the thickness of the second metal layer at a position facing the second recessed region is greater than the depth of the second recessed region.

4. The submount according to claim 2 or 3, further comprising a solder layer disposed on the first main surface via the first metal layer, the solder layer being disposed in an area of ​​the first metal layer corresponding to the first recessed area.

5. The submount according to claim 3, further comprising a solder layer disposed on the first main surface via the first metal layer, the solder layer being disposed in a region of the first metal layer corresponding to the first recessed region, and the area of ​​the second recessed region in a plan view of the second main surface being larger than the area of ​​the first recessed region in a plan view of the first main surface.

6. The submount according to claim 3, further comprising a solder layer disposed on the first main surface via the first metal layer, the solder layer being disposed in an area of ​​the first metal layer corresponding to the first recessed area and extending in a first direction parallel to the first main surface, and the width of the second recessed area in a second direction parallel to the first main surface and perpendicular to the first direction being greater than the width of the first recessed area in the second direction.

7. A submount as claimed in any one of claims 4 to 6, wherein the solder layer extends in a first direction parallel to the first main surface, and the width of the first recessed region in a second direction parallel to the first main surface and perpendicular to the first direction is at least twice the maximum thickness of the first metal layer at a position facing the first recessed region.

8. The submount according to claim 1, wherein the first recessed region is a region recessed relative to the second main surface, and the submount comprises a second metal layer disposed on the first main surface, the second metal layer being disposed in a region of the first main surface corresponding to the first recessed region.

9. The submount according to claim 8, further comprising a solder layer disposed on the first main surface via the second metal layer, the solder layer being disposed in an area of ​​the second metal layer corresponding to the first recessed area.

10. A submount according to any one of claims 1 to 9, wherein the first recessed region includes a plurality of first recesses, each of which is a region recessed relative to the first main surface or a region recessed relative to the second main surface.

11. The submount according to any one of claims 1 to 10, wherein the periphery of the first recessed area has an inclined portion inclined with respect to the first main surface.

12. A semiconductor device comprising the submount according to any one of claims 4 to 7 and 9, and a semiconductor element bonded to the solder layer.

13. The semiconductor device according to claim 12, wherein, in a cross-sectional view perpendicular to the first main surface, the width of the first recessed region in a direction parallel to the first main surface is wider than the width of the heat generating region of the semiconductor element in a direction parallel to the first main surface.

14. The semiconductor device according to claim 13, wherein, in a cross-sectional view perpendicular to the first main surface, the width of the first recessed region in a direction parallel to the first main surface is wider than the width of the semiconductor element in a direction parallel to the first main surface.

15. A method for manufacturing a submount, comprising: an insulating layer formation step of forming an insulating layer having a first main surface, a second main surface located on the back side of the first main surface, and a region recessed with respect to the first main surface or a first recessed region that is a region recessed with respect to the second main surface; and a metal layer formation step of forming a first metal layer that covers at least a portion of the first recessed region, wherein the thickness of the first metal layer at a position facing the first recessed region is greater than the depth of the first recessed region.

16. The method for manufacturing a submount according to claim 15, wherein the first recessed region is a region recessed relative to the first main surface.

17. A method for manufacturing a submount as described in claim 16, wherein in the metal layer forming step, a second metal layer is formed to be disposed on the second main surface, the insulating layer has a second recessed region that is recessed relative to the second main surface, the second metal layer covers at least a portion of the second recessed region, and the thickness of the second metal layer at a position facing the second recessed region is greater than the depth of the second recessed region.

18. A method for manufacturing a submount as set forth in claim 16 or 17, further comprising a solder layer forming step of forming a solder layer disposed on the first main surface via the first metal layer, the solder layer being disposed in a region of the first metal layer corresponding to the first recessed region.

19. A method for manufacturing a submount as described in claim 15, wherein the first recessed region is a region recessed relative to the second main surface, and in the metal layer forming step, a second metal layer is formed to be disposed on the first main surface, and the second metal layer is disposed in a region of the first main surface corresponding to the first recessed region.

20. A method for manufacturing a submount as described in claim 19, further comprising a solder layer forming step of forming a solder layer disposed on the first main surface via the second metal layer, the solder layer being disposed in an area of ​​the second metal layer corresponding to the first recessed area.

21. A method for manufacturing a semiconductor device, comprising: a method for manufacturing a submount according to claim 18 or 20; and an element bonding step of bonding a semiconductor light emitting element to the solder layer.

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