Method for manufacturing interposer, intermediate for interposer, and interposer

Abstract

This intermediate for an interposer includes a carrier substrate, a plurality of wiring groups that includes a plurality of wirings provided on the carrier substrate, and an inorganic film that includes an inorganic material and covers each of the wirings in the plurality of wiring groups. In the intermediate for an interposer, the inorganic film is at least partially not provided at a position between adjacent wiring groups.

Description

Interposer manufacturing method, interposer intermediate and interposer

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate to a method for manufacturing an interposer, an interposer intermediate, and an interposer.

[0002] Packaging technology that densely mounts multiple semiconductor elements with different functions, such as CPUs and memories, on a single substrate has been attracting attention. A substrate that electrically connects multiple semiconductor elements is also called an interposer. For example, Patent Documents 1 and 2 disclose semiconductor packages that include an interposer with through electrodes and semiconductor elements mounted on the interposer.

[0003] The interposer described above may be cut out from a laminate (hereinafter referred to as an interposer intermediate) in which multiple interposers are formed together on a carrier substrate. In this case, the interposer is usually cut out from the interposer intermediate. This cutting process is generally called singulation. Then, when the interposer is incorporated into, for example, a semiconductor package, it is peeled off from the small piece of carrier substrate. Also, an interposer intermediate in which multiple interposers are formed together on a substrate with through electrodes that penetrate the front and back of the substrate may be cut out together with a part of the substrate to be singulated.

[0004] Japanese Patent No. 6014907 Japanese Patent No. 6159820 Japanese Patent Laid-Open No. 2018-22894

[0005] The interposer cut out as described above typically includes a plurality of wirings and a resin layer covering the plurality of wirings. In such an interposer, an insulating inorganic film may be provided between each wiring and the resin layer. When such an inorganic film is formed, after the plurality of wirings constituting each interposer are formed, the inorganic film may be formed to cover the plurality of wirings, and then the resin layer may be formed.

[0006] However, when an inorganic film is provided on the interposer intermediate as described above, the inorganic film is cut when the interposer is cut. This may result in the generation of foreign matter from the inorganic film. Furthermore, stress generated during cutting the inorganic film may affect the finished cut. Furthermore, the stress generated during cutting may propagate, potentially causing cracks in the inorganic film in unintended locations, such as areas covering wiring.

[0007] An object of the first embodiment of the present disclosure is to provide an interposer manufacturing method, an interposer intermediate, and an interposer that can effectively solve such problems.

[0008] The first embodiment of the present disclosure relates to the following [1] to

[12] .

[0009] [1] A method for manufacturing an interposer, comprising: a wiring formation process for providing a plurality of wiring groups, each of which includes a plurality of wirings, on a substrate; an inorganic film coating process for coating each of the wirings of the plurality of wiring groups and a portion located between adjacent wiring groups with an inorganic film containing an inorganic material; a removal process for at least partially removing a portion of the inorganic film located between adjacent wiring groups; and a singulation process for separating adjacent wiring groups at locations where the inorganic film does not exist between the adjacent wiring groups.

[0010] [2] In the method for manufacturing an interposer described in [1], in the wiring formation process, the plurality of wiring groups may be provided in a resin layer containing a resin provided on the substrate, and in the inorganic film coating process, the inorganic film may be coated on each of the wirings of the plurality of wiring groups and the resin layer.

[0011] [3] In the method for manufacturing an interposer described in [1] or [2], the resin layer may have a plurality of land portions separated from each other, and the substrate may have a portion exposed between adjacent land portions, and in the wiring forming process, the wiring group may be provided on the plurality of land portions, and in the inorganic film coating process, the inorganic film may be coated on each of the wirings of the plurality of wiring groups, each of the land portions, and the substrate.

[0012] [4] In the method for manufacturing an interposer described in any one of [1] to [3], in the inorganic film coating process, the surface and side of the land portion may be coated with the inorganic film, and in the removal process, the inorganic film located between adjacent land portions may be partially removed while leaving the inorganic film covering the surface and side of the land portion.

[0013] [5] In the method for manufacturing an interposer described in any one of [1] to [4], in the removal process, a boundary portion of the inorganic film may be removed, and the boundary portion may be a predetermined distance away from the wiring of one of the adjacent wiring groups, and also a predetermined distance away from the wiring of the other of the adjacent wiring groups.

[0014] [6] In the method for manufacturing an interposer described in any one of [1] to [5], the singulation process may divide the adjacent wiring groups at a cutting range, and the cutting range may be set to a range away from both edges at a location where the inorganic film is not present between the adjacent wiring groups.

[0015] [7] In the method for manufacturing an interposer described in [6], when the width of the cutting range is defined as cutting width W, the distance from the edge of the area between adjacent wiring groups where the inorganic film does not exist to the edge of the cutting range facing that edge is defined as margin width S, and the specified distance (see [5]) is defined as coated end margin C, the relationship W + S > C may hold.

[0016] [8] The method for manufacturing an interposer described in any one of [1] to [7] may further include a resin layer forming process for forming a resin-containing resin layer on the inorganic film on each wire of the wiring group and on the portion located between the adjacent wiring groups, after removing the portion of the inorganic film located between the adjacent wiring groups.

[0017] [9] In the method for manufacturing an interposer according to any one of [1] to [8], the inorganic film may contain at least one of a metal oxide and a metal nitride.

[0018]

[10] In the method for manufacturing an interposer according to any one of [1] to [9], the wiring may include a seed layer and a plating layer formed from the seed layer.

[0019]

[11] An interposer intermediate comprising: a substrate; a plurality of wiring groups each including a plurality of wirings provided on the substrate; and an inorganic film containing an inorganic material that covers at least each of the wirings of the plurality of wiring groups, wherein the inorganic film is at least partially absent in a position between adjacent wiring groups.

[0020]

[12] In the interposer intermediate described in

[11] , the plurality of wiring groups may be provided on the substrate and in a resin layer containing resin, the resin layer may have a plurality of land portions separated from each other, the substrate may be partially exposed between adjacent land portions, and the inorganic film may include a portion covering the surface and side surfaces of the land portions.

[0021]

[13] An interposer comprising: one or more wiring groups each including a plurality of wirings; and an inorganic film containing an inorganic material covering each of the wirings of the one or more wiring groups, wherein the inorganic film is not provided at least partially from the outer peripheral edge toward the inside.

[0022]

[14] In the interposer described in

[13] , the one or more wiring groups may be provided in a resin layer containing resin, the resin layer may have at least one land portion, and the inorganic film may include a portion covering a side surface of the land portion.

[0023] According to the embodiments of the present disclosure, it is possible to provide an interposer that can suppress the generation of foreign matter from the interposer, and that has wiring appropriately coated with an inorganic film and has a good finish.

[0024] FIG. 1 is a schematic cross-sectional view of an interposer intermediate according to a first embodiment; FIG. 2 is a plan view of the interposer intermediate of FIG. 1; FIG. 3 is a view explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1; FIG. 4 is a view explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1; FIG. 5 is a view explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1; FIG. 6 is a view explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1; FIG. 7 is a view explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1; FIG. 8 is a view explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1; FIG. 9 is a view explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1; FIG. 10 is a view explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1; FIG. 11 is a view explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1; 21. A diagram explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1. A diagram explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1. A diagram explaining a method of manufacturing an interposer from the interposer intermediate of FIG. 1. A schematic cross-sectional view of an interposer intermediate according to a first modified example. A schematic cross-sectional view of an interposer intermediate according to a second modified example. A schematic cross-sectional view of an interposer intermediate according to a third modified example. A diagram explaining a method of manufacturing the interposer intermediate of FIG. 21. A diagram explaining a method of manufacturing the interposer intermediate of FIG. 21. A diagram explaining a method of manufacturing the interposer intermediate of FIG. 21. A diagram explaining a method of manufacturing the interposer intermediate of FIG. 21. A diagram explaining a method of manufacturing the interposer intermediate of FIG. 21. A diagram explaining a method of manufacturing the interposer intermediate of FIG. 21. A schematic cross-sectional view of an interposer intermediate according to a fourth modified example. A schematic cross-sectional view of an interposer intermediate according to a fifth modified example.34A and 34B are cross-sectional views showing an example of an interposer intermediate according to a sixth modification. 34B are cross-sectional views showing an example of an interposer intermediate according to a seventh modification. 34C are cross-sectional views showing an example of an interposer intermediate according to an eighth modification. 34D are cross-sectional views showing an example of an interposer intermediate according to a ninth modification. 34E are cross-sectional views showing an example of an interposer intermediate according to a sixth modification. 34F are cross-sectional views showing an example of an interposer intermediate according to a seventh modification. 34G are cross-sectional views showing an example of an interposer intermediate according to an eighth modification. 34G are cross-sectional views showing an example of an interposer intermediate according to a ninth modification. 34H are cross-sectional views showing an example of an interposer intermediate according to a sixth modification. 34H are cross-sectional views showing an example of an interposer intermediate according to a seventh modification. 34H are cross-sectional views showing an example of an interposer intermediate according to an eighth modification. 34H are cross-sectional views showing an example of an interposer intermediate according to a ninth modification. 34H are cross-sectional views showing an example of an interposer intermediate according to a ninth modification. 34H are cross-sectional views showing an example of an interposer intermediate according to a seven ... 10A and 10B are cross-sectional views showing a step of forming a plating layer of a second wiring layer. FIG. 10B are cross-sectional views showing a step of forming a plating layer of a second wiring layer. FIG. 10C are cross-sectional views showing a step of removing a portion of a seed layer of a second wiring layer. FIG. 10D are cross-sectional views showing a step of forming a second inorganic layer of a second wiring layer. FIG. 10E are cross-sectional views showing a step of forming an opening in the second inorganic layer of a second wiring layer. FIG. 10F are cross-sectional views showing a step of forming an organic layer of a second wiring layer. FIG. 10H are cross-sectional views showing a step of forming an opening in the organic layer of a second wiring layer. FIG. 10H are cross-sectional views showing a step of forming a third wiring layer. FIG. 10I are cross-sectional views showing a step of bonding the top surface of a redistribution layer to a substrate. FIG. 10I are cross-sectional views showing a step of irradiating a release layer with light. FIG. 10I are cross-sectional views showing a step of separating a redistribution layer from a carrier substrate. FIG. 10I are cross-sectional views showing an example of an organic layer and a via in a first modified example. FIG. 10I are cross-sectional views showing a step of forming an opening in the first inorganic layer of a second wiring layer in a first modified example. FIG. 10I are cross-sectional views showing a step of forming an opening in the first inorganic layer of a second wiring layer in a first modified example.68 is a cross-sectional view showing a step of forming an opening in the organic layer of the second wiring layer in the second modified example. FIG. 69 is a cross-sectional view showing a step of forming an organic layer covering the second inorganic layer of the second wiring layer in the second modified example. FIG. 69 is a cross-sectional view showing a step of forming an opening in the organic layer of the second wiring layer in the second modified example. FIG. 69 is a cross-sectional view showing a step of forming an opening in the second inorganic layer of the second wiring layer in the second modified example. FIG. 69 is a cross-sectional view showing an example of an interposer intermediate. FIG. 69 is a diagram illustrating a method of manufacturing an interposer from the interposer intermediate of FIG.

[0025] An interposer manufacturing method and an interposer intermediate for manufacturing an interposer will be described in detail below with reference to the drawings. The following embodiments are examples of embodiments of the present disclosure, and the present disclosure should not be construed as being limited to these embodiments. In this specification, terms such as "substrate," "base material," "sheet," and "film" are not distinguished from one another solely based on differences in nomenclature. For example, the concept of "substrate" includes components that may be called sheets or films. The term "surface" refers to a surface that coincides with the planar direction of a target plate-like component when viewed holistically and comprehensively. The normal direction used with respect to a plate-like component refers to the normal direction to the component's surface. As used in this specification, terms such as "parallel" and "orthogonal," as well as length and angle values, that specify shape, geometric conditions, and their degrees, are interpreted without being bound by strict meanings but include a range within which similar functions can be expected.

[0026] In this specification, when multiple upper limit value candidates and multiple lower limit value candidates are listed for a certain parameter, the numerical range of the parameter may be constructed by combining any one upper limit value candidate with any one lower limit value candidate. For example, consider a description that reads, "Parameter B is, for example, A1 or more, or may be A2 or more, or may be A3 or more. Parameter B is, for example, A4 or less, or may be A5 or less, or may be A6 or less." In this case, the numerical range of parameter B may be A1 or more and A4 or less, A1 or more and A5 or less, A1 or more and A6 or less, A2 or more and A4 or less, A2 or more and A5 or less, A2 or more and A6 or less, A3 or more and A4 or less, A3 or more and A5 or less, or A3 or more and A6 or less.

[0027] In the drawings referred to in this embodiment, the same parts or parts having similar functions are denoted by the same or similar reference numerals, and repeated explanations thereof may be omitted. Furthermore, the dimensional ratios of the drawings may differ from the actual ratios for the convenience of explanation, and some components may be omitted from the drawings.

[0028] First Embodiment The first embodiment is based on and claims priority to Japanese Patent Application No. 2024-46998, filed on March 23, 2024. FIG. 1 is a schematic cross-sectional view of an example of an interposer intermediate 1 for manufacturing an interposer 30. FIG. 2 is a plan view of the interposer intermediate 1. The interposer intermediate 1 has a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 are included in the surface direction of the interposer intermediate 1. The first direction D1 is orthogonal to the second direction D2. The third direction D3 is the thickness direction of the interposer intermediate 1. The third direction D3 is orthogonal to the first direction D1 and the second direction D2.

[0029] The interposer intermediate 1 includes a carrier substrate 2 as a substrate and a plurality of interposers 30 releasably provided on the carrier substrate 2. In this embodiment, a plurality of interposers 30 are collectively formed on the carrier substrate 2, and in the illustrated example, the plurality of interposers 30 are connected to one another. Hereinafter, a component including the plurality of connected interposers 30 will be referred to as an intermediate interposer layer 20. In other words, the intermediate interposer layer 20 corresponds to a portion including the plurality of interposers 30. The interposers 30 are components that are cut out from the intermediate interposer layer 20 during the manufacture of a semiconductor package, for example, and incorporated into the semiconductor package. Each component of the interposer intermediate 1 will be described below.

[0030] (Carrier Substrate) The carrier substrate 2 is a plate material and includes a first surface 2A and a second surface 2B located opposite the first surface 2A. The shape of the carrier substrate 2 in a plan view is rectangular as shown in Fig. 2. However, the shape of the carrier substrate 2 in a plan view may be other shapes such as a circle or a rectangle.

[0031] In this embodiment, the carrier substrate 2 is made of silicon dioxide (SiO ２ ) as a main component. However, the carrier substrate 2 may also be, for example, a glass substrate, a sapphire substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO2) substrate, a lithium niobate substrate, or a tantalum niobate substrate. The carrier substrate 2 may also include two or more of a quartz substrate, a glass substrate, a sapphire substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO2) substrate, a lithium niobate substrate, a tantalum niobate substrate, and a resin substrate. The resin substrate may also include an organic material. For example, the resin substrate may include an epoxy resin, polyethylene, polypropylene, or the like.

[0032] The thickness of the carrier substrate 2 is, for example, 100 μm or more, may be 200 μm or more, or may be 500 μm or more. The thickness of the carrier substrate 2 is, for example, 2 mm or less, may be 1.5 mm or less, or may be 1 mm or less. The area of ​​the carrier substrate 2 is, for example, 0.10 m ２ or more, 0.15 m ２ It may be 0.20 m or more, ２ It may be 0.25 m or more. ２ It should be noted that a substrate with through electrodes may be used as the substrate instead of the carrier substrate 2. In this case, the thickness of the substrate with through electrodes is also the same as that described above.

[0033] (Intermediate interposer layer and interposers) As described above, the intermediate interposer layer 20 includes a plurality of interposers 30. The plurality of interposers 30 are arranged in a matrix in the planar direction as shown in FIG. 2 . The intermediate interposer layer 20 is releasably provided on the carrier substrate 2. This allows the interposers 30 to be releasably attached to the carrier substrate 2 after they are cut out from the intermediate interposer layer 20 together with the carrier substrate 2.

[0034] A release layer may be provided between the carrier substrate 2 and the intermediate interposer layer 20 to facilitate peeling of the intermediate interposer layer 20 or the interposer 30. The release layer may contain, for example, a resin that absorbs laser light and can be decomposed by laser light. In this case, the release layer may contain a thermosetting polyimide or a photocurable polyimide. The thickness of the release layer may be, for example, 0.3 μm or more, or may be 1 μm or more. The thickness of the release layer may be, for example, 30 μm or less, or may be 50 μm or less. Note that when a substrate with through electrodes is used instead of the carrier substrate 2, a release layer may not be provided between the substrate and the intermediate interposer layer 20, or an insulating resin layer may be provided on the surface of the substrate instead of the release layer. Examples of resins contained in the insulating resin layer include polyimide and epoxy.

[0035] Each of the multiple interposers 30 included in the intermediate interposer layer 20 includes a resin layer 31 and multiple wirings 32 covered by the resin layer 31. The intermediate interposer layer 20 includes a front-end process resin layer 21 extending in the surface direction and collectively forming a portion constituting part or all of the resin layer 31 of each interposer 30, and a front-end process wiring layer 22 extending in the surface direction and collectively forming part or all of the wirings 32 included in each interposer 30. The front-end process resin layer 21 contains a resin, and needless to say, the resin layer 31 of each interposer 30 contains the same resin as the front-end process resin layer 21. The front-end process resin layer 21 is a portion that covers the multiple wirings 32 included in the front-end process wiring layer 22. The front-end process resin layer 21 functions as an insulating layer having insulating properties. Therefore, the resin layer 31 in the interposer 30 also functions as an insulating layer.

[0036] The intermediate interposer layer 20 includes a first surface 20A and a second surface 20B. The second surface 20B is located on the opposite side of the first surface 20A. The intermediate interposer layer 20 may include a plurality of stacked resin wiring layers. In the example shown in FIG. 1 , the intermediate interposer layer 20 includes a first resin wiring layer 201 and a second resin wiring layer 202. The first resin wiring layer 201 and the second resin wiring layer 202 are stacked in this order from the carrier substrate 2. The first resin wiring layer 201 and the second resin wiring layer 202 are each composed of a pair of one pre-process resin layer 21 and one pre-process wiring layer 22. A portion of the pre-process resin layer 21 that constitutes the first resin wiring layer 201 may constitute the second surface 20B of the intermediate interposer layer 20. A portion of the pre-process resin layer 21 that constitutes the second resin wiring layer 202 may constitute the first surface 20A of the intermediate interposer layer 20.

[0037] A bundle of multiple wirings 32 included in one interposer 30 and aligned or arranged in the surface direction may be referred to as a wiring group 32G hereinafter. In this embodiment, one interposer 30 includes two wiring groups 32G arranged in two stages in the thickness direction. Of the two wiring groups 32G included in one interposer 30, the first stage wiring group 32G, which is on the carrier substrate 2 side, is included in the pre-process wiring layer 22 of the first resin wiring layer 201. The pre-process wiring layer 22 of the first resin wiring layer 201 includes multiple wiring groups 32G in the first stage. Of the two wiring groups 32G included in one interposer 30, the second stage wiring group 32G is included in the pre-process wiring layer 22 of the second resin wiring layer 202. The pre-process wiring layer 22 of the second resin wiring layer 202 includes multiple wiring groups 32G in the second stage.

[0038] The intermediate interposer layer 20 may include a through electrode (which may also be referred to as a via). The through electrode is a conductive portion extending in the third direction D3 in one resin wiring layer. The through electrode can electrically connect the previous-process wiring layers 22 included in two resin wiring layers adjacent in the third direction D3. The intermediate interposer layer 20 may also include a pad used for connection to, for example, a semiconductor element. The pad may be provided so as to protrude from the first surface 20A of the intermediate interposer layer 20. The pad may also be provided with a bump. The bump includes a conductive material. For example, the bump includes solder. The bump may be connected to a terminal in a BGA (Ball Grid Array) or to a terminal of a semiconductor element. The pad used for connection to the semiconductor may be a previous-process wiring layer 22 exposed on the side from which the carrier substrate 2 is peeled.

[0039] The thickness of the intermediate interposer layer 20 is, for example, 10 μm or more, and may be 25 μm or more. The thickness of the intermediate interposer layer 20 is, for example, 50 μm or less, and may be 45 μm or less. The thickness of the intermediate interposer layer 20 is the distance in the third direction D3 from the first surface 20A to the second surface 20B. The thickness of each resin wiring layer in the intermediate interposer layer 20 is, for example, 2.0 μm or more, and may be 3.0 μm or more. The thickness of each resin wiring layer in the intermediate interposer layer 20 is, for example, 12.0 μm or less, and may be 10.0 μm or less. The thickness of the interposer 30 is the same as the thickness of the intermediate interposer layer 20, and satisfies the above conditions.

[0040] The wiring 32 (pre-process wiring layer 22) included in the intermediate interposer layer 20 or the interposer 30 includes a conductive material. For example, the wiring 32 (pre-process wiring layer 22) may include a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, or chromium, or an alloy using any of these metals, or an oxide or nitride thereof.

[0041] 1, the wiring 32 may include a seed layer 33 and a plating layer 34 formed (grown) from the seed layer 33. The seed layer 33 may be a conductive layer that serves as a base for growing the plating layer 34 by depositing metal ions in a plating solution during an electrolytic plating process in which the plating layer 34 is formed by electrolytic plating, for example.

[0042] The seed layer 33 may be a single layer or may include, for example, two layers. The first layer, which is one of the two layers included in the seed layer 33, may be a layer formed by, for example, a sol-gel method or dip coating. The second layer, which is the other of the two layers included in the seed layer 33, may be a layer formed on the first layer by, for example, electroless plating. However, the seed layer 33 may be formed by a film formation method different from the film formation methods described above, such as sputtering or vapor deposition. The seed layer may include a metal with good conductivity, such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, or chromium, or an alloy using any of these metals.

[0043] In the illustrated example, the wiring 32 is provided on an adhesion layer 35 formed on the surface of the carrier substrate 2 or the surface of the first resin wiring layer 201. More specifically, the wiring 32 included in the first resin wiring layer 201 is provided on the adhesion layer 35 formed on the surface of the carrier substrate 2. This is also true when other layers such as a resin layer are provided on the carrier substrate 2, and an adhesion layer 35 is selected and provided according to the other layers. The wiring 32 included in the second resin wiring layer 202 is provided on the adhesion layer 35 formed on the surface of the first resin wiring layer 201. The surface of the first resin wiring layer 201 on which the adhesion layer 35 is formed is the surface opposite to the surface of the first resin wiring layer 201 facing the carrier substrate 2.

[0044] The adhesion layer 35 may contain a metal such as nickel, titanium, chromium, tin, or aluminum, or an alloy using these metals. Metal oxides may also be used, such as silicon dioxide (SiO ２ ) as a main component, or may be composed solely of a layer mainly composed of silicon dioxide. Other metal oxides, such as zinc oxide, aluminum oxide, titanium oxide, and magnesium oxide, may also be used. The adhesion layer 35 may include, for example, a first portion bonded to the first surface 2A of the carrier substrate 2 and a second portion overlapping the first portion, with the first portion containing silicon nitride as a main component and the second portion containing silicon dioxide as a main component. The adhesion layer 35 may also contain indium tin oxide (ITO). The adhesion layer 35 may be formed by a CVD (Chemical Vapor Deposition) method, vapor deposition, sputtering, or the like.

[0045] The width of the wiring 32 is, for example, 0.5 μm or more, and may be 1.0 μm or more. The width of the wiring 32 is, for example, 5.0 μm or less, 3.0 μm or less, or 2.0 μm or less. The spacing between two adjacent wirings 32 in a planar view is, for example, 0.5 μm or more, and may be 1.0 μm or more. The spacing between two adjacent wirings 32 in a planar view is, for example, 5.0 μm or less, 3.0 μm or less, or 2.0 μm or less. In addition to wirings 32 that satisfy these numerical ranges, the pre-process wiring layer 22 may also include wirings 32 that do not satisfy these numerical ranges.

[0046] The intermediate interposer layer 20 also includes an inorganic film 38 that covers each of the wirings 32 in the plurality of wiring groups 32G of the previous-process wiring layer 22. The inorganic film 38 covers both side surfaces and the front surface of each of the wirings 32, which are surfaces other than the connection surface (rear surface) with the adhesive layer 35. The inorganic film 38 is also provided between adjacent wirings 32.

[0047] Specifically, the inorganic film 38 includes a first inorganic film 38A covering each of the wirings 32 included in the first resin wiring layer 201, and a second inorganic film 38B covering each of the wirings 32 included in the second resin wiring layer 202. The first inorganic film 38A covers each of the wirings 32 included in the first resin wiring layer 201, and also covers a part of the first surface 2A of the carrier substrate 2 that is exposed between adjacent wirings 32 of the plurality of wirings 32 included in the first resin wiring layer 201. The second inorganic film 38B covers each of the wirings 32 included in the second resin wiring layer 202, and also covers a part of the surface of the first resin wiring layer 201 that is exposed between adjacent wirings 32 of the plurality of wirings 32 included in the second resin wiring layer 202.

[0048] On the other hand, in the intermediate interposer layer 20, the inorganic film 38 is not provided at least partially in the positions between the adjacent wiring groups 32G.

[0049] 1 , the first inorganic film 38A partially covers and does not cover a portion of the first surface 2A of the carrier substrate 2 that faces between adjacent wiring groups 32G. Specifically, the first inorganic film 38A covers the first surface 2A in a range from the wiring 32 closest to one of the plurality of wirings 32 in one of adjacent wiring groups 32G in the first resin wiring layer 201 to a predetermined distance C on the other side, and covers the first surface 2A in a range from the wiring 32 closest to one of the plurality of wirings 32 in the other wiring group 32G to the predetermined distance C on the one side, but does not cover the entire first surface 2A between the adjacent plurality of wiring groups 32G.

[0050] The second inorganic film 38B also partially covers and partially does not cover a portion of the surface of the first resin wiring layer 201 that faces between adjacent wiring groups 32G. Specifically, the second inorganic film 38B covers the surface of the first resin wiring layer 201 in a range from the wiring 32 closest to one of the plurality of wirings 32 in one of adjacent wiring groups 32G in the second resin wiring layer 202 to the predetermined distance C on the other side, and covers the surface of the first resin wiring layer 201 in a range from the wiring 32 closest to one of the plurality of wirings 32 in the other wiring group 32G to the predetermined distance C on the one side, but does not cover the entire surface of the first resin wiring layer 201 between the adjacent plurality of wiring groups 32G.

[0051] 1, the area away from both edges of the area where the inorganic film 38 does not exist between adjacent wiring groups 32G, in other words, the center area, is set as the cutting area CA shown in FIG. 1. The cutting area CA is the area sandwiched between two vertical dashed dotted lines aligned horizontally in FIG. 1. When the interposer 30 is cut out, the adjacent wiring groups 32G are separated within the cutting area CA, and the carrier substrate 2 is notched or cut as necessary. The both edges of the area where the inorganic film 38 does not exist between adjacent wiring groups 32G are the ends of the inorganic film 38 after the boundary portions described below have been removed.

[0052] 1 , the width of the cutting area CA (the width in the direction in which adjacent wiring groups 32G are arranged) is defined as the cutting width W, the distance from the edge of the portion between adjacent wiring groups 32G where no inorganic film 38 is present to the edge of the cutting area facing that edge is defined as the margin width S, and the predetermined distance C over which the inorganic film 38 covers the space between adjacent wiring groups 32G from one side is defined as the covered edge margin C. In this embodiment, the relationship W+S>C holds. When this relationship holds, stress is less likely to be transmitted to the inorganic film 38 when cutting in the cutting area CA. This makes it possible to prevent cracks and peeling from occurring in the inorganic film 38.

[0053] The inorganic film 38 has insulating properties. The inorganic film 38 is formed of, for example, a metal oxide, a metal nitride, or the like, and examples of metals used therein include aluminum and silicon. The inorganic film 38 suppresses migration of the metal constituting the wiring 32 into the resin layer 31. The thickness of the inorganic film 38 may be, for example, 0.1 μm or more and 3 μm or less, or 0.5 μm or more and 3 μm or less. The inorganic film 38 may be formed by a CVD (Chemical Vapor Deposition) method, vapor deposition, sputtering, or the like.

[0054] The front-end resin layer 21 in the intermediate interposer layer 20 or the resin layer 31 in the interposer 30 covers the wiring 32 via the inorganic film 38. The front-end resin layer 21 (resin layer 31) in the first resin wiring layer 201 is bonded to the first surface 2A of the carrier substrate 2 at a location where the inorganic film 38 is not present on the first surface 2A of the carrier substrate 2. The front-end resin layer 21 (resin layer 31) in the second resin wiring layer 202 is bonded to the first resin wiring layer 201 at a location where the inorganic film 38 is not present on the surface of the first resin wiring layer 201. This firmly bonds the first resin wiring layer 201 and the second resin wiring layer 202.

[0055] The resin contained in the pre-process resin layer 21 (the material of the pre-process resin layer 21), i.e., the resin contained in the resin layer 31 of the interposer 30 (the material of the resin layer 31), may include a resin such as polyimide. The resin of the pre-process resin layer 21 and the resin of the resin layer 31 may be at least one of polyimide, epoxy resin, acrylic, bismaleimide, polybenzoxazole, and benzocyclobutene.

[0056] (Method of Manufacturing Interposer) Next, a method of manufacturing the interposer 30 will be described. Below, a flow of manufacturing the interposer intermediate 1 and then manufacturing the interposer 30 from the interposer intermediate 1 will be described. Note that, although a method of forming the wiring 32 will be described below, the wiring 32 may be formed by a subtractive method, a semi-additive method, an additive method, or the like, and the method of forming the wiring 32 is not particularly limited.

[0057] First, a carrier substrate 2 is prepared as shown in Fig. 3. In this embodiment, a glass substrate is prepared as the carrier substrate 2.

[0058] 4, an adhesion layer 35 is provided on the first surface 2A of the carrier substrate 2. In this embodiment, the adhesion layer 35 is formed by depositing titanium on the first surface 2A by sputtering, for example. A separate resin layer may be provided before providing the adhesion layer 35. Alternatively, vapor deposition or a sol-gel method may be used instead of sputtering.

[0059] 5, a seed layer 33 is provided on the adhesion layer 35. The seed layer 33 is provided so as to cover the entire surface of the adhesion layer 35. The seed layer 33 may be formed by, for example, a sol-gel method, sputtering, vapor deposition, or the like.

[0060] 6, a plating layer 34 is grown on the seed layer 33. The plating layer 34 is formed by, for example, electrolytic plating.

[0061] 7, a plurality of wiring groups 32G including a plurality of wirings 32 are formed by etching a portion of the adhesion layer 35, the seed layer 33, and the plating layer 34. Here, a plurality of wiring groups 32G are formed that are included in the previous process wiring layer 22 of the first resin wiring layer 201 in the intermediate interposer layer 20. The processes shown in FIGS. 4 to 7 correspond to an example of a wiring formation process.

[0062] 8, each of the wirings 32 of the wiring groups 32G and a portion located between adjacent wiring groups 32G (a part of the first surface 2A of the carrier substrate 2) are coated with an inorganic film 38 containing an inorganic material (an example of an inorganic film coating step). The inorganic film 38 can be formed by a chemical vapor deposition (CVD) method, vapor deposition, sputtering, or the like.

[0063] 9, the inorganic film 38 formed in FIG. 8 is at least partially removed from its portion located between adjacent wiring groups 32G (an example of a removing process). In this embodiment, the boundary portion of the inorganic film 38 is removed in the same manner as in the removing process of the inorganic film 38 of the first resin wiring layer 201. The boundary portion of the inorganic film 38 is located between a position of the wiring 32 of one of the adjacent wiring groups 32G that is a predetermined distance C away from the wiring 32 closest to the other wiring group 32G, and a position of the wiring 32 of the other of the adjacent wiring groups 32G that is a predetermined distance C away from the wiring 32 closest to the one wiring group 32G. In other words, the boundary portion of the inorganic film 38 is separated from the wiring 32 of one of the wiring groups 32G by the predetermined distance C, and also separated from the wiring 32 of the other wiring group 32G by the predetermined distance C.

[0064] 10 , a process for forming a pre-process resin layer 21 is performed to cover the plurality of wiring groups 32G (pre-process wiring layer 22) via an inorganic film 38 (an example of a resin layer formation process). In the process shown in FIG. 10 , the pre-process resin layer 21 is formed as a resin-containing resin layer on the inorganic film 38 on each wiring 32 of the wiring group 32G and in the portion located between adjacent wiring groups 32G. The portion located between adjacent wiring groups 32G is the first surface 2A of the carrier substrate 2. The pre-process resin layer 21 is bonded to the first surface 2A of the carrier substrate 2 through a portion where the inorganic film 38 is not present. If another resin layer is present on the carrier substrate 2, the pre-process resin layer 21 is bonded to the resin layer through a portion where the inorganic film 38 is not present.

[0065] 11, an adhesion layer 35 and a seed layer 33 are provided on the surface of the first resin wiring layer 201 in the same manner as in FIGS. 4 and 5. Furthermore, as shown in FIG. 12, a plating layer 34 is grown from the seed layer 33.

[0066] 13 , a plurality of wiring groups 32G including a plurality of wirings 32 are formed by etching a portion of the adhesion layer 35, the seed layer 33, and the plating layer 34. More specifically, a plurality of wiring groups 32G are formed in the pre-process wiring layer 22 of the second resin wiring layer 202 in the intermediate interposer layer 20. In the step shown in FIG. 13 , a plurality of wiring groups 32G are provided in the pre-process resin layer 21 in the first resin wiring layer 201 provided on the carrier substrate 2. The steps shown in FIGS. 11 to 13 correspond to an example of a wiring formation step. Furthermore, if the adhesion layer 35 and the seed layer 33 are exposed when the carrier substrate 2 is peeled off, they may be etched and removed after the carrier substrate 2 is peeled off.

[0067] 14 , each of the wirings 32 in the wiring groups 32G and a portion between adjacent wiring groups 32G (a portion of the surface of the first resin wiring layer 201) are coated with an inorganic film 38 containing an inorganic material (an example of an inorganic film coating process). The inorganic film 38 can be formed by a chemical vapor deposition (CVD) method, vapor deposition, sputtering, or the like. In the process shown in FIG. 14 , the inorganic film 38 coats each of the wirings 32 in the wiring groups 32G and the resin layer 21 in the first resin wiring layer 201.

[0068] 15, the inorganic film 38 formed in FIG. 14 is at least partially removed from the portions thereof located between adjacent wiring groups 32G (an example of a removing process). In this embodiment, the boundary portions of the inorganic film 38 are removed. The boundary portions of the inorganic film 38 are located between a position of the wiring 32 of one of the adjacent wiring groups 32G that is a predetermined distance C away from the wiring 32 closest to the other wiring group 32G, and a position of the wiring 32 of the other of the adjacent wiring groups 32G that is a predetermined distance C away from the wiring 32 closest to the one wiring group 32G. In other words, the boundary portions of the inorganic film 38 are separated by the predetermined distance C from the wiring 32 of one of the wiring groups 32G and also separated by the predetermined distance C from the wiring 32 of the other wiring group 32G.

[0069] 16 , a process is performed to form a pre-process resin layer 21 that covers the plurality of wiring groups 32G (pre-process wiring layer 22) via the inorganic film 38. This forms the second resin wiring layer 202. The pre-process resin layer 21 is bonded to the surface of the first resin wiring layer 201 via a portion where the inorganic film 38 is not present.

[0070] Then, as shown in Figures 17 and 18, a singulation process is performed in which an interposer 30 is cut out from the carrier substrate 2 and the intermediate interposer layer 20, i.e., the interposer intermediate body 1, along with a portion of the carrier substrate 2, or in which cuts are made down to the carrier substrate 2 to make the intermediate interposer layer 20 into individual interposers 30.

[0071] In this embodiment, as shown in FIG. 17 , a cutting area CA is set in a location where the inorganic film 38 is not present. Then, by cutting the carrier substrate 2 and the intermediate interposer layer 20 in the cutting area CA, the interposer 30 is cut out or notched together with a portion of the carrier substrate 2, i.e., singulated. This cutting may be performed with a cutting blade or by irradiating with laser light. This singulation process forms multiple singulated interposer intermediates, each including a portion of the carrier substrate 2 and the interposer 30. During this singulation process, the absence of the inorganic film 38 in the cutting area CA reduces the risk of foreign matter being generated from the inorganic film 38. Furthermore, this reduces the risk of stress occurring when cutting the inorganic film 38 affecting the finished cut. 18 , the interposer 30 includes one or more wiring groups 32G including a plurality of wirings 32, and an inorganic film 38 including an inorganic material that covers each of the wirings 32 in the one or more wiring groups 32G, with the inorganic film 38 not being provided at least partially from the outer periphery of the interposer 30 toward the inside. In the illustrated example, the outer periphery of the interposer 30 is formed by the outer periphery of the resin layer 31 and a part of the outer periphery of the carrier substrate 2. The singulated interposer intermediate is also referred to as a wiring substrate.

[0072] The interposer intermediate 1 according to the embodiment described above includes a carrier substrate 2, a plurality of wiring groups 32G including a plurality of wirings 32 provided on the carrier substrate 2, and an inorganic film 38 containing an inorganic material that covers each of the wirings 32 in the plurality of wiring groups 32G. In the interposer intermediate 1, the inorganic film 38 is not provided at least partially between adjacent wiring groups 32G. In this embodiment, such an interposer intermediate 1 is formed through a wiring formation process of providing a plurality of wiring groups 32G including a plurality of wirings 32 on the carrier substrate 2, an inorganic film coating process of coating each of the wirings 32 in the plurality of wiring groups 32G and portions located between adjacent wiring groups 32G with an inorganic film 38 containing an inorganic material, and a removal process of at least partially removing portions of the inorganic film 38 located between adjacent wiring groups 32G. Then, in the interposer intermediate 1, the adjacent wiring groups 32G are separated at a location where the inorganic film 38 between the adjacent wiring groups 32G does not exist (for example, the above-mentioned cutting range CA), and an individualization process is performed to cut the carrier substrate 2, thereby manufacturing the interposer 30.

[0073] In the interposer intermediate 1 according to the present embodiment, the interposer intermediate 1 is cut at a location where the inorganic film 38 between adjacent wiring groups 32G does not exist, thereby reducing the risk of foreign matter being generated from the inorganic film 38. In addition, the risk of stress occurring when cutting the inorganic film 38 affecting the finished cut is reduced. Therefore, according to the present embodiment, it is possible to reduce the generation of foreign matter from the interposer 30 and the occurrence of cracks in the inorganic film in unintended locations such as locations covering wiring, and to provide an interposer 30 with a good finish.

[0074] Furthermore, in this embodiment, when removing the inorganic film 38, a portion of the inorganic film 38 located between a position on a wire in one of the adjacent wiring groups 32G that is a predetermined distance C away from the wire 32 closest to the other of the adjacent wiring groups 32G and a position on a wire in the other of the adjacent wiring groups 32G that is a predetermined distance C away from the wire 32 closest to the one of the wiring groups 32G in the other of the adjacent wiring groups 32G is removed. As a result, the inorganic film 38 covers an area in the portion located between the adjacent wiring groups 32G from the wire 32 closest to the other of the multiple wirings 32 in one of the wiring groups 32G to the predetermined distance C on the other side, and covers an area from the wire 32 closest to one of the multiple wirings 32 in the other wiring group 32G to the predetermined distance C on the one side.

[0075] During the singulation process, adjacent wiring groups 32G are separated in a cutting range CA, which is set in a range away from both edges of the area where the inorganic film 38 is not present between adjacent wiring groups 32G, and the carrier substrate 2 is cut. In this embodiment, the width of the cutting range CA is defined as the cutting width W, the distance obtained by subtracting the cutting width W from the width of the area where the inorganic film 38 is not present between adjacent wiring groups 32G is defined as the margin width S, and the predetermined distance C is defined as the coated edge margin C. In this case, stress is less likely to be transmitted to the inorganic film 38 when cutting in the cutting range CA. This makes it possible to prevent cracks and peeling from occurring in the inorganic film 38.

[0076] (Modification) A modification of the first embodiment will be described below. In the modification described below, the same components as those in the first embodiment will be assigned the same reference numerals, and duplicated descriptions will be omitted.

[0077] 19 is a schematic cross-sectional view of an interposer intermediate 1r1 according to a first modified example. The interposer intermediate 1r1 according to the first modified example further includes a plurality of wiring groups 32G in addition to the interposer intermediate 1 according to the above-described embodiment. The further provided plurality of wiring groups 32G are provided on the surface of the second resin wiring layer 202 in the interposer intermediate 1. The plurality of wiring groups 32G include wirings 32 including a seed layer 33 and a plating layer 34 stacked on an adhesion layer 35, and can be formed by the same process as that described using FIGS. 11 to 14 .

[0078] The plurality of wiring groups 32G provided on the surface of the second resin wiring layer 202 are covered with the inorganic film 38. The inorganic film 38 is not provided at least partially even at positions between adjacent wiring groups 32G on the surface of the second resin wiring layer 202. A cutting range CA is set in a location on the surface of the second resin wiring layer 202 where the inorganic film 38 is not present. As a result, the interposer intermediate 1r1 is cut in the cutting range CA, thereby reducing the risk of foreign matter being generated from the inorganic film 38. Furthermore, the risk of stress occurring when cutting the inorganic film 38 affecting the finish of the cut is reduced.

[0079] 20 is a schematic cross-sectional view of an interposer intermediate 1r2 according to the second modified example. In the interposer intermediate 1r2 according to the second modified example, a part of the pre-process resin layer 21 of the second resin wiring layer 202 in the interposer intermediate 1 according to the above-described embodiment is removed, and then a plurality of wiring groups 32G are further provided.

[0080] A portion of the pre-process resin layer 21 of the second resin wiring layer 202 including the cutting range CA is removed, forming a state having a plurality of land portions 202L separated by the cutting range CA. The removal of a portion of the pre-process resin layer 21 may be performed by etching. The pre-process resin layer 21 of the first resin wiring layer 201 is exposed between adjacent land portions 202L. By removing a portion of the pre-process resin layer 21 of the second resin wiring layer 202, a groove 212 recessed from the surface of the pre-process resin layer 21 of the second resin wiring layer 202 is formed in the interposer intermediate body 1r2. The groove 212 aligns with the cutting range CA and serves as a marker for the cutting range CA.

[0081] The wiring group 32G is provided on the surface of each of the plurality of lands 202L. The plurality of wiring groups 32G include wirings 32 including a seed layer 33 and a plating layer 34 stacked on an adhesion layer 35, and are formed by the same process as that described with reference to FIGS.

[0082] The wiring groups 32G provided on the surface of the land portion 202L are covered with the inorganic film 38. The inorganic film 38 is not provided at least partially even in positions between adjacent wiring groups 32G provided on each land portion 202L. As a result, the interposer intermediate 1r2 is cut within the cutting range CA, thereby reducing the risk of foreign matter being generated from the inorganic film 38. Furthermore, the risk of stress when cutting the inorganic film 38 affecting the finish of the cut is reduced.

[0083] 21 is a schematic cross-sectional view of an interposer intermediate 1r3 according to a third modified example. The interposer intermediate 1r3 according to the third modified example does not have the pre-process resin layer 21 of the second resin wiring layer 202 in the interposer intermediate 1 according to the above-described embodiment, and a portion of the pre-process resin layer 21 of the first resin wiring layer 201 has been removed. A portion of the pre-process resin layer 21 of the first resin wiring layer 201 including the cutting range CA has been removed, forming a state having a plurality of land portions 201L separated by the cutting range CA. The removal of the portion of the pre-process resin layer 21 may be performed by etching. The carrier substrate 2 is exposed between adjacent land portions 201L.

[0084] The wiring groups 32G provided on the surface of the land portion 201L are covered with the inorganic film 38. The inorganic film 38 is also not provided at least partially between adjacent wiring groups 32G provided on adjacent lands 201L. As a result, the interposer intermediate 1r3 is cut in the cutting range CA, thereby reducing the risk of foreign matter being generated from the inorganic film 38. Furthermore, the risk of stress when cutting the inorganic film 38 affecting the finish of the cut is reduced.

[0085] 22 to 26 are diagrams illustrating a method for manufacturing an interposer intermediate 1r3 according to the third modified example. When manufacturing the interposer intermediate 1r3, the processes illustrated in FIGS. 3 to 10 described in the above embodiment are performed. Then, as shown in FIG. 22 , a portion of the first resin wiring layer 201, including a cutting area CA, which is a part of the pre-process resin layer 21, is removed. As a result, a plurality of lands 201L separated by the cutting area CA are formed on the carrier substrate 2. The method for removing the portion of the pre-process resin layer 21 is not particularly limited. The portion of the pre-process resin layer 21 may be removed by etching, such as dry etching. If the pre-process resin layer 21 is photosensitive, the portion may be removed by photolithography, for example. If the pre-process resin layer 21 is not photosensitive, the portion of the pre-process resin layer 21 may be removed by irradiating the pre-process resin layer 21 with an energy beam, such as laser light. Even when a portion of the pre-process resin layer 21 is removed by a method other than cutting, the remaining portion of the pre-process resin layer 21 may be referred to as a land portion.

[0086] 23 , an adhesion layer 35 is provided on the plurality of lands 201L and on the first surface 2A of the carrier substrate 2 exposed between the plurality of lands 201L. In the present embodiment, the adhesion layer 35 is formed by depositing silicon dioxide on the first surface 2A by plasma CVD, as an example.

[0087] 24, a seed layer 33 is provided on the adhesion layer 35. The seed layer 33 is provided so as to cover the entire surface of the adhesion layer 35. Thereafter, the seed layer 33 is formed, and a plating layer 34 is grown from the seed layer 33. Then, as shown in FIG. 25, a plurality of wiring groups 32G including a plurality of wirings 32 are formed by etching parts of the adhesion layer 35, the seed layer 33, and the plating layer 34. The wiring group 32G is formed in each of the plurality of land portions 201L.

[0088] 26, an inorganic film 38 containing an inorganic material is then coated on each of the wirings 32 of the plurality of wiring groups 32G, the surface and side surfaces of the land portions 201L, which are resin layers, and the portions located between adjacent wiring groups 32G (part of the first surface 2A of the carrier substrate 2). Then, although not shown, the portions of the inorganic film 38 located between adjacent wiring groups 32G are at least partially removed. This results in the manufacture of an interposer intermediate 1r3 according to the third modified example. Note that the manufacturing process described above is an example, and the manufacturing process of the interposer intermediate 1r3 according to the third modified example is not particularly limited.

[0089] The fourth to seventh modified examples described below are manufactured from the interposer intermediate body 1r3 according to the third modified example.

[0090] 27 is a schematic cross-sectional view of an interposer intermediate 1r4 according to a fourth modification. In the interposer intermediate 1r4, the wiring groups 32G provided on the lands 201L made of the pre-processing resin layer 21 of the first resin wiring layer 201 are each covered with the lands 202L made of the pre-processing resin layer 21, thereby forming the second resin wiring layer 202. The lands 202L cover the wiring groups 32G provided on the lands 201L of the first resin wiring layer 201 via the inorganic film 38, and also cover the surface of the first resin wiring layer 201 where the inorganic film 38 is not present (the surface opposite to the surface on the carrier substrate 2 side).

[0091] The land portion 202L is further provided with a wiring group 32G. The land portion 201L in the first resin wiring layer 201 and the land portion 202L in the second resin wiring layer 202 are joined to each other at a location where the inorganic film 38 is not present. This allows the first resin wiring layer 201 and the second resin wiring layer 202 to be firmly bonded to each other.

[0092] In the interposer intermediate body 1r4 according to the fourth modification, the spacing between adjacent land portions 201L in the first resin wiring layer 201 is the same as the spacing between adjacent land portions 202L in the second resin wiring layer 202. Therefore, in the interposer intermediate body 1r4, a groove 212 of a constant width is formed from its surface to the carrier substrate 2.

[0093] 28 is a schematic cross-sectional view of an interposer intermediate 1r5 according to the fifth modification. In the interposer intermediate 1r5, the distance between adjacent lands 202L in the second resin wiring layer 202 is larger than the distance between adjacent lands 201L in the first resin wiring layer 201. The other configurations of the interposer intermediate 1r5 are the same as those of the interposer intermediate 1r4 according to the fourth modification.

[0094] The land portion 202L in the fifth modification has a smaller volume than that in the fourth modification. However, the land portion 202L covers the wiring group 32G provided on the land portion 201L in the first resin wiring layer 201 via the inorganic film 38, and also covers the surface of the first resin wiring layer 201 where the inorganic film 38 is not present (the surface opposite to the surface on the carrier substrate 2 side), and is bonded to the first resin wiring layer 201. This allows the first resin wiring layer 201 and the second resin wiring layer 202 to be firmly bonded to each other.

[0095] 29 is a schematic cross-sectional view of an interposer intermediate 1r6 according to a sixth modification. In the interposer intermediate 1r6, the land portions 202L of the second resin wiring layer 202 partially penetrate into the gaps between adjacent wiring groups 32G in the first resin wiring layer 201, cover the surfaces and side surfaces of the corresponding land portions 201L in the first resin wiring layer 201, and are bonded to the land portions 201L. The land portions 202L also cover the wiring groups 32G formed on the first resin wiring layer 201 via the inorganic film 38. This ensures that the first resin wiring layer 201 and the second resin wiring layer 202 are firmly bonded to each other.

[0096] 30 is a schematic cross-sectional view of an interposer intermediate 1r7 according to a seventh modification. In the interposer intermediate 1r7, the pre-process resin layer 21 in the second resin wiring layer 202 fills the gaps between adjacent lands 201L in the first resin wiring layer 201 and is bonded to the lands 201L, covering the surfaces of the lands 201L and the wiring group 32G formed on the first resin wiring layer 201 via the inorganic film 38. This ensures a strong bond between the first resin wiring layer 201 and the second resin wiring layer 202.

[0097] 31 is a schematic cross-sectional view of an interposer intermediate 1r8 according to the eighth modification. In the interposer intermediate 1r8, as in the case of the interposer intermediate 1r3 according to the third modification, a portion of the pre-process resin layer 21 of the first resin wiring layer 201 is removed. For example, the pre-process resin layer 21 of the first resin wiring layer 201 located in the cutting range CA is removed. Therefore, each of the first resin wiring layers 201 of the multiple interposers 30 of the interposer intermediate 1r8 has a land portion 201L including a side surface 313.

[0098] 31 , the inorganic film 38 located on the surface 311 of the land portion 201L in the first resin wiring layer 201 may also cover the side surface 313 of the land portion 201L. In this case, after the carrier substrate 2 and the intermediate interposer layer 20 are cut in the cutting range CA, the side surface 313 of the land portion 201L continues to be protected by the inorganic film 38. Therefore, moisture and the like are prevented from penetrating from the side surface 313 into the resin layer 31 of the land portion 201L and the like.

[0099] The penetration of moisture and the like into the resin layer 31 causes deterioration of the wiring 32 due to oxidation corrosion, migration, and the like. Furthermore, the penetration of moisture and the like into the resin layer 31 causes a decrease in the insulating properties of the resin layer 31. According to this modification, the side surface 313 of the land portion 201L is protected by the inorganic film 38, so that deterioration of the wiring 32 and the resin layer 31 is suppressed. Therefore, the reliability of the interposer 30 can be improved.

[0100] 32 is a diagram illustrating a method for manufacturing an interposer intermediate 1r8 according to this modified example. Similar to the manufacturing method of the interposer intermediate 1r3 according to the third modified example shown in FIGS. 22 to 26, wiring groups 32G are formed on each of the plurality of lands 201L, and then an inorganic film 38 is formed. The inorganic film 38 covers each of the wirings 32 of the plurality of wiring groups 32G, the surface and side surfaces of the land portions 201L, which are resin layers, and the portions located between adjacent wiring groups 32G. Subsequently, a removal process is performed to remove a portion of the inorganic film 38.

[0101] In the removal process, the inorganic film 38 located between adjacent land portions 201L is partially removed while leaving the inorganic film 38 covering the surfaces 311 and side surfaces 313 of the land portions 201L. For example, the portion of the inorganic film 38 surrounded by the dotted line in FIG. 32 is removed. As a result, the interposer intermediate 1r8 shown in FIG. 31 is obtained. The portion of the inorganic film 38 removed in the removal process is also referred to as a boundary portion. In FIG. 32, the boundary portion is indicated by the symbol 38R. The boundary portion 38R is located at the boundary between two adjacent wiring groups 32G.

[0102] 33 is a schematic cross-sectional view of an interposer intermediate 1r9 according to a ninth modification. As shown in FIG. 33, the inorganic film 38 located on the surface of the land portion 202L in the second resin wiring layer 202 may also cover the side surface of the land portion 202L. The inorganic film 38 covering the side surface of the land portion 202L may cover the inorganic film 38 covering the side surface of the land portion 201L.

[0103] Although not shown, if the inorganic film 38 located on the surface of the land portion 201L does not cover the side surface of the land portion 201L, the inorganic film 38 located on the surface of the land portion 202L may cover the side surface of the land portion 201L.

[0104] The interposer intermediate 1r8 is cut into individual pieces to produce the interposer 30. The inorganic film 38 of the interposer 30 includes portions that cover the surfaces and side surfaces of the land portions, such as the land portion 201L and the land portion 202L. This allows the reliability of the interposer 30 to be improved.

[0105] Although several modifications of the first embodiment have been described above, it is naturally possible to combine a plurality of modifications as appropriate and apply them to the first embodiment described above.

[0106] Second Embodiment The second embodiment is based on Japanese Patent Application No. 2024-97690 filed on June 17, 2024, and claims priority thereto. The second embodiment relates to a redistribution layer and a manufacturing method thereof. The following table shows some examples of the correspondence between the components of Japanese Patent Application No. 2024-97690, the components of the second embodiment, and the components of the first embodiment.

[0107]

[0108] Packaging technology that densely mounts multiple semiconductor elements with different functions, such as CPUs and memories, on a single substrate is attracting attention. A structure that electrically connects multiple semiconductor elements is also called an interposer. An interposer includes, for example, a wiring layer that includes a conductive layer and an insulating layer. The wiring layer performs, for example, the function of relocating pads or terminals of the semiconductor elements to another location. A structure in which multiple wiring layers are stacked is also called a rewiring layer.

[0109] Each wiring layer includes a conductive layer and an insulating layer at least partially covering the conductive layer. Patent Document 1 discloses a structure in which the insulating layer includes an inorganic layer at least partially covering the conductive layer and an organic layer covering the inorganic layer. The conductive layer includes, for example, a plurality of wirings.

[0110] Delamination that occurs between multiple layers that make up a wiring layer is called delamination. When delamination occurs between an inorganic layer and an organic layer that cover a conductive layer, the reliability of the conductive layer, such as wiring, decreases.

[0111] The second embodiment of the present disclosure aims to provide a redistribution layer and a manufacturing method thereof that can effectively solve such problems.

[0112] The second embodiment of the present disclosure relates to the following [1] to

[16] .

[0113] [1] A redistribution layer comprising a plurality of wiring layers, at least one of the plurality of wiring layers including a first inorganic layer, a plurality of wirings located on the first inorganic layer, a second inorganic layer covering the plurality of wirings, and an organic layer covering the second inorganic layer, wherein the second inorganic layer includes a first portion located between the wirings and the organic layer, and a second portion located between the first inorganic layer and the organic layer.

[0114] [2] In the redistribution layer according to [1], the second portion of the second inorganic layer may be in contact with the first inorganic layer.

[0115] [3] In the redistribution layer described in [1] or [2], the wiring may include a seed layer and a plating layer located on the seed layer, and a portion of the first inorganic layer that overlaps the second portion of the second inorganic layer may include a recess.

[0116] [4] In the redistribution layer according to [3], the recesses in the first inorganic layer may have a depth of 0.05 μm or more.

[0117] [5] In the redistribution layer according to any one of [1] to [4], the first inorganic layer may be located at least on an upper surface of an underlayer including an opening, and the at least one wiring layer may include a via located in the opening of the underlayer.

[0118] [6] In the redistribution layer according to [5], the first inorganic layer may include a side portion located on a side surface of the opening in the underlayer.

[0119] [7] In the redistribution layer according to [6], the thickness of the side surface portion of the first inorganic layer may be smaller than the thickness of the portion of the first inorganic layer located on the upper surface of the underlayer.

[0120] [8] In the redistribution layer according to any one of [6] to [7], a wall surface of the opening in the underlayer may include a notch located on the lower surface of the underlayer, and a side portion of the first inorganic layer may include an intrusion portion located on the notch. The intrusion portion of the first inorganic layer may contact an upper surface of the second inorganic layer located on an upper surface of a pad located on the opening in the underlayer.

[0121] [9] In the redistribution layer according to any one of [1] to [8], the first inorganic layer may contain an inorganic oxide or an inorganic nitride.

[0122]

[10] In the redistribution layer according to any one of [1] to [9], the second inorganic layer may contain an inorganic oxide or an inorganic nitride.

[0123]

[11] In the redistribution layer according to

[10] , the second inorganic layer may include a first layer containing an inorganic nitride and a second layer located on the first layer and containing an inorganic oxide.

[0124]

[12] A method for manufacturing a redistribution layer, comprising: a redistribution step of forming a redistribution layer including a plurality of wiring layers on a substrate; at least one of the plurality of wiring layers including a first inorganic layer, a plurality of wirings located on the first inorganic layer, a second inorganic layer covering the plurality of wirings, and an organic layer covering the second inorganic layer; and the redistribution step includes a step of forming the first inorganic layer, a step of forming the plurality of wirings on the first inorganic layer, a step of forming the second inorganic layer covering the plurality of wirings, and a step of forming an organic layer covering the second inorganic layer.

[0125]

[13] In the method for manufacturing a redistribution layer described in

[12] , the step of forming the plurality of wirings may include a conductive layer forming step, and the conductive layer forming step may include a step of forming a seed layer on the first inorganic layer, a step of forming a resist layer including a plurality of openings on the seed layer, a step of forming a plating layer in the plurality of openings in the resist layer, a step of removing the resist layer, and a seed layer removing step of removing a portion of the seed layer that overlapped the resist layer, and in the seed layer removing step, a recess may be formed in the portion of the first inorganic layer that overlapped the resist layer.

[0126]

[14] In the method for manufacturing a redistribution layer according to

[13] , the seed layer removing step may include a step of removing a portion of the seed layer that overlaps the resist layer by using an ion beam.

[0127]

[15] In the method for manufacturing a redistribution layer according to

[13] or

[14] , the first inorganic layer may be located at least on an upper surface of an underlayer including an opening, and the at least one wiring layer may be located in the opening of the underlayer and include a via formed by the conductive layer forming step.

[0128]

[16] In the method for manufacturing a redistribution layer according to

[15] , the first inorganic layer may include a side portion located on a side surface of the opening in the underlayer.

[0129] According to the second embodiment of the present disclosure, the reliability of the wiring can be improved.

[0130] FIG. 34 is a plan view showing an example of a wiring board group 10. FIG. 35 is a cross-sectional view of the wiring board group 10 of FIG. 34 taken along line XXXV-XXXV. The wiring board group 10 includes a plurality of wiring boards having the same structure. As will be described later, a plurality of wiring boards are obtained by dividing the wiring board group 10. Each of the plurality of wiring boards includes a rewiring layer. That is, the wiring board group 10 includes a plurality of rewiring layers 20.

[0131] The wiring board group 10 has a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 are included in the surface direction of the wiring board group 10. The first direction D1 is perpendicular to the second direction D2. The third direction D3 is the thickness direction of the wiring board group 10. The third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0132] The wiring board group 10 includes a carrier substrate 12, a release layer 13, and a plurality of redistribution layers 20. The release layer 13 is located between the carrier substrate 12 and the redistribution layers 20 in the thickness direction of the wiring board group 10. The release layer 13 is located on the carrier substrate 12.

[0133] Although not shown, the member supporting the redistribution layer 20 is not limited to the carrier substrate 12. For example, the redistribution layer 20 may be disposed on an electrode substrate having openings penetrating the top and bottom surfaces and electrodes with metal wiring formed in the openings. The electrodes located in the openings may be connected to the conductive layer of the redistribution layer 20.

[0134] The redistribution layer 20 may be provided on either the front surface or the back surface, or on both the front surface and the back surface, of a substrate such as the carrier substrate 12 or the electrode substrate. The pattern of the conductive layer of the redistribution layer 20 located on the back surface may be the same as or different from the pattern of the redistribution layer 20 located on the front surface.

[0135] Each component of the wiring board group 10 will be described.

[0136] (Redistribution Layer) The multiple redistribution layers 20 have the same structure as one another. For example, as shown in FIG. 34 , the multiple redistribution layers 20 may have the same structure in a planar view. As shown in FIG. 34 , the multiple redistribution layers 20 may be regularly arranged in the surface direction of the wiring substrate group 10. For example, the multiple redistribution layers 20 may be regularly arranged in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be parallel to the sides of the carrier substrate 12.

[0137] Figure 35 is a cross-sectional view of the wiring board group 10 taken along line XXXV-XXXV in Figure 34. The redistribution layer 20 includes a lower surface 20B and an upper surface 20A. The lower surface 20B faces the carrier substrate 12. The upper surface 20A is located opposite the lower surface 20B. The redistribution layer 20 includes an insulating layer and a plurality of conductive layers 26. The insulating layer includes, for example, an organic layer 25 having insulating properties.

[0138] In this specification, a "lower surface" such as the lower surface 20B means a surface facing the carrier substrate 12 in the state of the wiring substrate group 10. An "upper surface" means a surface located opposite the "lower surface" in the thickness direction.

[0139] Some of the multiple conductive layers 26 may be pads 27. The pads 27 may have upper or lower surfaces that include portions that are not in contact with an insulating material, such as the organic layer 25. For example, when the pads 27 are located on the lower surface 20B of the redistribution layer 20, the lower surface of the pads 27 is not in contact with an insulating material. For example, when the pads 27 are located on the upper surface 20A of the redistribution layer 20, the upper surface of the pads 27 is not in contact with an insulating material. For example, when a portion of the upper surface of the pads 27 is connected to a via, which will be described later, the upper surface of the pads 27 can be said to include a portion that is not in contact with an insulating material. In a plan view, the pads 27 have dimensions that are equal to or larger than the dimensions of the wiring and via, which will be described later.

[0140] Some of the multiple conductive layers 26 may be wirings 28. The wirings 28 extend at least partially in the first direction D1 or the second direction D2. Both the upper and lower surfaces of the wirings 28 may be in contact with an insulating material. The insulating material has insulating properties.

[0141] Some of the multiple conductive layers 26 may be vias 29. The vias 29 extend in the third direction D3. For example, the vias 29 are located in openings formed in the organic layer 25. The vias 29 can electrically connect the conductive layers 26 of two wiring layers adjacent to each other in the third direction D3. The vias 29 may be connected to pads 27.

[0142] The redistribution layer 20 may include a plurality of stacked wiring layers. In the example shown in FIG. 35 , the redistribution layer 20 includes a first wiring layer 201, a second wiring layer 202, and a third wiring layer 203. Each of the plurality of wiring layers may include a plurality of conductive layers 26. At least one of the plurality of wiring layers may include an organic layer 25. The organic layer 25 may overlap the plurality of conductive layers 26 in a planar view. In the example shown in FIG. 35 , the first wiring layer 201 and the second wiring layer 202 include the organic layer 25.

[0143] The first wiring layer 201 may form the lower surface 20B of the redistribution layer 20. The third wiring layer 203 may form the upper surface 20A of the redistribution layer 20. The third wiring layer 203 may be located on the organic layer 25 of the second wiring layer 202 and may include a conductive layer 26 that forms a pad 27.

[0144] The redistribution layer 20 has a thickness T1. The thickness T1 is, for example, 8 μm or more, and may be 16 μm or more, or 24 μm or more. The thickness T1 is, for example, 100 μm or less, and may be 90 μm or less, or 80 μm or less. The thickness T1 is the distance in the third direction D3 from the lower surface 20B to the upper surface 20A. The dimensions of the components of the wiring board group 10, such as the thickness T1, are calculated based on a cross-sectional image of the wiring board group 10 taken with a scanning electron microscope.

[0145] The thickness T2 of each of the multiple wiring layers in the redistribution layer 20 is, for example, 4.0 μm or more, and may be 6.0 μm or more. The thickness T2 of each of the multiple wiring layers in the redistribution layer 20 is, for example, 12.0 μm or less, and may be 10.0 μm or less. The thicknesses T2 of the multiple wiring layers may be the same or different.

[0146] 36 is a cross-sectional view showing an example of the redistribution layer 20. At least one of the multiple wiring layers includes a first inorganic layer 23, multiple wirings 28, a second inorganic layer 24, and an organic layer 25. In the example shown in FIG. 36 , the second wiring layer 202 includes the first inorganic layer 23, multiple wirings 28, the second inorganic layer 24, and the organic layer 25.

[0147] The plurality of wirings 28 are located on the first inorganic layer 23. The second inorganic layer 24 covers the plurality of wirings 28. The organic layer 25 covers the second inorganic layer 24. The second wiring layer 202 may further include a conductive layer 26 other than the wirings 28. For example, the second wiring layer 202 may further include a pad 27 and a via 29. The second inorganic layer 24 may partially cover the pad 27. "Element A covers element B" means that element A and element B at least partially overlap when the redistribution layer 20 is viewed along the normal direction of the lower surface 20B.

[0148] The wiring layers other than the second wiring layer 202 may include all of the first inorganic layer 23, the plurality of wirings 28, the second inorganic layer 24, and the organic layer 25, or may include some of these layers. For example, the third wiring layer 203 may include the first inorganic layer 23, the plurality of wirings 28, and the second inorganic layer 24, but may not include the organic layer 25. For example, the first wiring layer 201 may include a plurality of conductive layers 26 that form pads 27, and an organic layer 25 that covers the plurality of conductive layers 26.

[0149] The first inorganic layer 23, the plurality of wirings 28, the second inorganic layer 24, and the organic layer 25 will be described below.

[0150] (First Inorganic Layer) The first inorganic layer 23 is located on the upper surface of the base layer. The base layer is a layer that supports the first inorganic layer 23. For example, the base layer for the first inorganic layer 23 of the second wiring layer 202 is the organic layer 25 of the first wiring layer 201. The first inorganic layer 23 may be in contact with the upper surface of the base layer. For example, the first inorganic layer 23 of the second wiring layer 202 may be in contact with the upper surface of the organic layer 25 of the first wiring layer 201.

[0151] The first inorganic layer 23 includes an insulating inorganic material. Examples of the inorganic material include inorganic oxides and inorganic nitrides. Examples of the inorganic oxide include SiO ２ The inorganic nitride is, for example, a silicon nitride such as SiN. The inorganic material may be SiOC, SiC, SiOF, SiON, SiCN, or the like.

[0152] The thermal expansion coefficient of the inorganic material of the first inorganic layer 23 is smaller than the thermal expansion coefficient of the organic material of the organic layer 25. The thermal expansion coefficient of the first inorganic layer 23 is, for example, 10.0 ppm / °C or less, or may be 8.0 ppm / °C or less, or may be 5.0 ppm / °C or less.

[0153] The thickness of the first inorganic layer 23 is 0.05 μm or more, optionally 0.10 μm or more, optionally 0.30 μm or more, or optionally 0.50 μm or more. The thickness of the first inorganic layer 23 is, for example, 5.0 μm or less, optionally 3.0 μm or less, or optionally 1.0 μm or less.

[0154] (Wiring) Each of the multiple wirings 28 includes a lower surface 281, an upper surface 282, and a side surface 283. The lower surface 281 faces the first inorganic layer 23. The lower surface 281 may be in contact with the first inorganic layer 23. The upper surface 282 is located on the opposite side of the lower surface 281 in the third direction D3. The side surface 283 is located between the lower surface 281 and the upper surface 282.

[0155] The wiring 28 has a first width W1 and a first height H1. The first width W1 is the maximum dimension of the wiring 28 in a direction perpendicular to the direction in which the wiring 28 extends. The first height H1 is the maximum dimension of the wiring 28 in the third direction D3.

[0156] The first width W1 of the wiring 28 is, for example, 1.0 μm or more, or may be 2.0 μm or more, or 3.0 μm or more. The first width W1 is, for example, 10.0 μm or less, or may be 8.0 μm or less, or may be 6.0 μm or less.

[0157] The smaller the first width W1, the more wires 28 are arranged per unit area of ​​the redistribution layer 20. On the other hand, the smaller the first width W1, the smaller the contact area between the wires 28 and the layer supporting the wires 28. The smaller the contact area, the lower the structural stability of the wires 28. According to this embodiment, as will be described later, the combination of the first inorganic layer 23 and the second inorganic layer 24 can increase the structural stability of the wires 28.

[0158] The ratio H1 / W1 of the first height H1 to the first width W1 is also referred to as the aspect ratio. The aspect ratio of the wiring 28 is, for example, 1.0 or more, or may be 1.5 or more, or may be 2.0 or more. The aspect ratio of the wiring 28 is, for example, 4.0 or less, or may be 3.0 or less.

[0159] The larger the aspect ratio, the lower the electrical resistance per unit length of the wiring 28. On the other hand, the larger the aspect ratio, the lower the structural stability of the wiring 28. By covering the wiring 28 with the second inorganic layer 24, the structural stability of the wiring 28 can be maintained while increasing the aspect ratio of the wiring 28.

[0160] The distance K1 between the two wirings 28 is, for example, 0.5 μm or more, and may be 1.0 μm or more, 2.0 μm or more, or 3.0 μm or more. The distance K1 is, for example, 10.0 μm or less, 8.0 μm or less, or 6.0 μm or less. The distance K1 is measured in the range in which the two wirings 28 extend parallel to each other.

[0161] The smaller the distance K1, the more wires 28 are arranged per unit area of ​​the redistribution layer 20. On the other hand, the smaller the distance K1, the more likely a leakage current will flow between two adjacent wires 28. Covering the wires 28 with the second inorganic layer 24 can also contribute to reducing the leakage current.

[0162] The ratio W1 / K1 of the first width W1 to the interval K1 is, for example, 0.2 or more, or may be 0.3 or more, or may be 1.0 or more. W1 / K1 is, for example, 2.0 or less, or may be 1.7 or less, or may be 1.5 or less.

[0163] The conductive layer 26, such as the wiring 28, includes a conductive material. The conductive layer 26 may include a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc, or an alloy using any of these. The thickness of the conductive layer 26 is, for example, 0.1 μm or more, or may be 0.5 μm or more, or may be 1.0 μm or more. The thickness of the conductive layer 26 is, for example, 15.0 μm or less, or may be 10.0 μm or less, or may be 6.0 μm or less.

[0164] 36 , the second inorganic layer 24 may include a first portion 247 and a second portion 248. The first portion 247 is a portion of the second inorganic layer 24 located between the conductive layer 26, such as the wiring 28, and the organic layer 25. The first portion 247 may be in contact with an upper surface 282 and a side surface 283 of the wiring 28. The second portion 248 is a portion of the second inorganic layer 24 located between the upper surface of the first inorganic layer 23 and the lower surface of the organic layer 25. The second portion 248 may be in contact with the upper surface of the first inorganic layer 23.

[0165] 36 , the wiring 28 is surrounded by the first inorganic layer 23 and the second inorganic layer 24. That is, the first inorganic layer 23 contacts a lower surface 281 of the wiring 28, and a first portion 247 of the second inorganic layer 24 contacts an upper surface 282 and a side surface 283 of the wiring 28. In addition, a second portion 248 of the second inorganic layer 24 contacts the first inorganic layer 23.

[0166] As a comparative example, it is assumed that the second wiring layer 202 does not include the first inorganic layer 23. In this comparative example, the second portion 248 of the second inorganic layer 24 of the second wiring layer 202 contacts the organic layer 25 of the first wiring layer 201. In general, the adhesion between an inorganic material layer and an organic material layer is lower than the adhesion between an inorganic material layer and an inorganic material layer. In this comparative example, there is a concern that delamination may occur between the second portion 248 of the second inorganic layer 24 of the second wiring layer 202 and the organic layer 25 of the first wiring layer 201.

[0167] In the present embodiment, the first inorganic layer 23 is disposed between the second portion 248 of the second inorganic layer 24 of the second wiring layer 202 and the organic layer 25 of the first wiring layer 201. Therefore, the second portion 248 of the second inorganic layer 24 of the second wiring layer 202 is supported by the first inorganic layer 23, not the organic layer 25. According to the present embodiment, compared to the comparative embodiment, the occurrence of delamination on the lower surface of the second portion 248 of the second inorganic layer 24 of the second wiring layer 202 is suppressed. Since the structural stability of the second inorganic layer 24 is improved, the structural stability of the wiring 28 is also improved.

[0168] 36 , the first inorganic layer 23 of the second wiring layer 202 may include a portion located between the pad 27 of the second wiring layer 202 and the organic layer 25 of the first wiring layer 201. By sandwiching the first inorganic layer 23 between the pad 27 and the organic layer 25, peeling of the first inorganic layer 23 from the organic layer 25 may be suppressed.

[0169] Because the wiring 28 is surrounded by the first inorganic layer 23 and the second inorganic layer 24, the wiring 28 is not in contact with the organic layer 25. The organic layer 25 may include a layer in which metal is diffused on its surface due to migration or the like. If two adjacent wirings 28 are in contact with the organic layer 25, it is conceivable that a leakage current will flow between the two wirings 28. According to this embodiment, the leakage current is also reduced.

[0170] The second inorganic layer 24 contains an insulating inorganic material, similar to the first inorganic layer 23. Examples of the inorganic material include inorganic oxides and inorganic nitrides. Examples of the inorganic oxide include SiO ２ The inorganic nitride is, for example, a silicon nitride such as SiN. The inorganic material may be SiOC, SiC, SiOF, SiON, SiCN, or the like.

[0171] The thermal expansion coefficient of the inorganic material of the second inorganic layer 24 is smaller than the thermal expansion coefficient of the organic material of the organic layer 25. The thermal expansion coefficient of the second inorganic layer 24 is, for example, 10.0 ppm / °C or less, or may be 8.0 ppm / °C or less, or may be 5.0 ppm / °C or less.

[0172] The thickness of the second inorganic layer 24 is, for example, 0.05 μm or more, or may be 0.10 μm or more, or 0.30 μm or more, or 0.50 μm or more. The thickness of the second inorganic layer 24 is, for example, 5.0 μm or less, or may be 3.0 μm or less, or 1.0 μm or less.

[0173] The layer of the first inorganic layer 23 in contact with the organic layer 25 of the first wiring layer 201 and the layer of the second inorganic layer 24 in contact with the organic layer 25 of the second wiring layer 202 may contain the same inorganic material. ２ The use of the same inorganic material can prevent delamination between the inorganic layer and the organic layer.

[0174] (Organic Layer) The organic layer 25 includes an organic material having insulating properties, such as polyimide, epoxy, or acrylic.

[0175] The organic layer 25 may include a plurality of fillers distributed in the organic material. By mixing the plurality of fillers into the organic material, the mechanical properties, thermal properties, etc. of the organic layer 25 can be adjusted. The filler may include an inorganic material or an organic material. An example of the filler material is silicon oxide.

[0176] (Specific Examples) Specific examples of each layer of the rewiring layer 20 will be described.

[0177] 37 is a cross-sectional view showing an example of the inorganic layers 23, 24 and the conductive layer 26. The second inorganic layer 24 may include multiple layers made of inorganic materials. For example, the second inorganic layer 24 may include a first layer 241 in contact with the first inorganic layer 23 and the conductive layer 26, and a second layer 242 located on the first layer 241.

[0178] The first layer 241 may have higher adhesion to the conductive layer 26, such as the wiring 28, than the second layer 242. The second layer 242 may have a lower relative dielectric constant than the first layer 241. For example, the first layer 241 may contain an inorganic nitride, and the second layer 242 may contain an inorganic oxide. The inorganic nitride of the first layer 241 may be a silicon nitride such as SiN. The inorganic oxide of the second layer 242 may be SiO ２ Silicon oxides such as silicon dioxide and silicon monoxide may also be used.

[0179] The thickness of the first layer 241 is, for example, 0.05 μm or more, and may be 0.10 μm or more, or 0.20 μm or more. The thickness of the first layer 241 is, for example, 2.0 μm or less, and may be 1.0 μm or less, or 0.50 μm or less. The thickness of the second layer 242 is, for example, 0.05 μm or more, and may be 0.10 μm or more, or 0.20 μm or more. The thickness of the second layer 242 is, for example, 2.0 μm or less, and may be 1.0 μm or less, or 0.50 μm or less.

[0180] Although not shown, the first inorganic layer 23 may include multiple layers made of inorganic materials. For example, the first inorganic layer 23 may include a third layer located on an underlayer such as the organic layer 25, and a fourth layer located on the third layer. The fourth layer may have higher adhesion to the conductive layer 26 such as the wiring 28 than the third layer. For example, the fourth layer may include an inorganic nitride, and the third layer may include an inorganic oxide.

[0181] 37 , the conductive layer 26 may include a seed layer 261 and a plating layer 262. The seed layer 261 is a layer having electrical conductivity. The seed layer 261 may be formed by physical film formation such as sputtering, or may be formed by electroless plating or the like. The plating layer 262 is a layer having electrical conductivity that is formed on the seed layer 261 by electrolytic plating.

[0182] The seed layer 261 in contact with the plating layer 262 may contain a metal material such as copper, nickel, titanium, chromium, zinc, gold, palladium, or silver. The seed layer 261 in contact with the plating layer 262 may contain a compound of these metal materials. The plating layer 262 may contain a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, or zinc, or an alloy using any of these metals.

[0183] The seed layer 261 may include multiple layers. For example, the seed layer 261 may include a first seed layer 2611 and a second seed layer 2612 located on the first seed layer 2611. The first seed layer 2611 and the second seed layer 2612 may be formed by physical film formation such as sputtering. The first seed layer 2611 and the second seed layer 2612 may be formed by electroless plating or the like.

[0184] The first seed layer 2611 is located between an insulating layer such as the release layer 13, the first inorganic layer 23, or the organic layer 25 and the second seed layer 2612. The adhesion between the first seed layer 2611 and the insulating layer may be greater than the adhesion between the second seed layer 2612 and the insulating layer. The first seed layer 2611 may be a conductive layer, such as a metal oxide or metal nitride layer.

[0185] The material of the first seed layer 2611 is different from the material of the second seed layer 2612 and the material of the plating layer 262. Examples of the material of the first seed layer 2611 include titanium, molybdenum, tungsten, tantalum, nickel, chromium, aluminum, palladium, silver, compounds thereof, alloys thereof, oxides or nitrides thereof, etc.

[0186] The second seed layer 2612 is electrically conductive. The second seed layer 2612 is in contact with the plating layer 262. The second seed layer 2612 may contain a metal material such as copper, nickel, titanium, chromium, zinc, or gold. The second seed layer 2612 may also contain a compound of these metal materials. The material of the second seed layer 2612 may be the same as the material of the plating layer 262.

[0187] 38A is a cross-sectional view showing an example of the first inorganic layer 23. A portion of the first inorganic layer 23 overlapping the second portion 248 of the second inorganic layer 24 may include a recess 231. The recess 231 is recessed downward with respect to the upper surface of the first inorganic layer 23 that is in contact with the lower surface 281 of the wiring 28. The recess 231 has a depth H2. The depth H2 is the maximum value of the distance in the third direction D3 between the upper surface of the first inorganic layer 23 that is in contact with the lower surface 281 of the wiring 28 and the recess 231.

[0188] In this application, the term "overlap" means that two components overlap when viewed along the third direction D3.

[0189] As will be described later, the seed layer 261 located between two adjacent wirings 28 is removed after the plating layer 262 is formed. When the seed layer 261 is removed by dry etching, the upper surface of the first inorganic layer 23 located below the seed layer 261 may also be partially removed to form a recess 231. The dry etching is, for example, ion milling.

[0190] The first inorganic layer 23 may include a layer of metal diffused on its surface due to migration or the like. For example, in the step of forming the seed layer 261, a layer of metal diffused may be formed on the surface of the first inorganic layer 23. The layer of metal diffused on the surface of the first inorganic layer 23 may cause leakage current between the two wirings 28.

[0191] When the upper surface of the first inorganic layer 23 is removed by dry etching, the layer in which the metal is diffused is removed from the surface of the first inorganic layer 23. That is, the leakage current path between two adjacent wirings 28 is removed. Therefore, the recess 231 of the first inorganic layer 23 can contribute to suppressing the leakage current.

[0192] The recess 231 of the first inorganic layer 23 includes an edge 232. The edge 232 defines the outer edge of the recess 231 in a plan view. The edge 232 may be located on a side surface 283 of the wiring 28. The edge 232 may be located between two adjacent wirings 28.

[0193] The second portion 248 of the second inorganic layer 24 may include a portion located in the recess 231. That is, the portion of the first inorganic layer 23 removed by dry etching may be compensated for by the second inorganic layer 24. By filling the recess 231 of the first inorganic layer 23 with the second portion 248 of the second inorganic layer 24, the adhesion between the first inorganic layer 23 and the second inorganic layer 24 is increased.

[0194] Fig. 38B is a cross-sectional view showing an example of the first inorganic layer 23. An end 232 of the recess 231 may be located below the lower surface 281 of the wiring 28. The recess 231 shown in Fig. 38B is obtained when a larger portion of the upper surface of the first inorganic layer 23 is removed by dry etching compared to the case of Fig. 38A.

[0195] The recess 231 of the first inorganic layer 23 has a depth H2. The depth H2 is, for example, 0.05 μm or more, and may be 0.10 μm or more, 0.15 μm or more, or 0.20 μm or more. When the depth H2 is 0.05 μm or more, it is possible to suppress the occurrence of leakage current between two adjacent wirings 28. The depth H2 is, for example, 0.50 μm or less, and may be 0.45 μm or less, or 0.40 μm or less.

[0196] 39 is a cross-sectional view showing an example of an organic layer 25 and a via 29. A layer that functions as an underlayer for the first inorganic layer 23, such as the organic layer 25, may include an opening 254. The opening 254 is formed in the organic layer 25 so as to overlap a conductive layer 26, such as a pad 27. The via 29 is located in the opening 254 in the organic layer 25.

[0197] The first inorganic layer 23 may include a side portion 233 located on a side of the opening 254. The side portion 233 may be continuous with a portion of the first inorganic layer 23 located on the top surface of the organic layer 25.

[0198] The side surface portion 233 of the first inorganic layer 23 may be connected to the second inorganic layer 24. For example, the side surface portion 233 of the third wiring layer 203 may be connected to an upper surface portion 243 of the second inorganic layer 24 located on an upper surface 272 of the pad 27. The pad 27 and the via 29 are more securely protected by the first inorganic layer 23 and the second inorganic layer 24.

[0199] The portion of the first inorganic layer 23 located on the upper surface of the organic layer 25 has a thickness T11. The side surface portion 233 of the first inorganic layer 23 has a thickness T12. The thickness T12 may be smaller than the thickness T11. The ratio of the thickness T12 to the thickness T11, T12 / T11, is, for example, 0.95 or less, or may be 0.90 or less, or may be 0.85 or less. The ratio T12 / T11 is, for example, 0.60 or more, or may be 0.65 or more, or may be 0.70 or more.

[0200] The pad 27 includes a lower surface 271, an upper surface 272, and a side surface 273. A portion of the lower surface 271 may be in contact with the first inorganic layer 23. The upper surface of the via 29 may be connected to the lower surface 271. A portion of the upper surface 272 and the side surface 273 may be in contact with the second inorganic layer 24. The lower surface of the via 29 may be connected to the upper surface 272.

[0201] (Carrier Substrate) The carrier substrate 12 is a member that supports the redistribution layer 20. The carrier substrate 12 may include, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a metal substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO2) substrate, a lithium niobate substrate, or a tantalum niobate substrate. The resin substrate may include an organic material. For example, the resin substrate may include epoxy resin, polyethylene, polypropylene, or the like. The metal substrate may be composed solely of a conductive metal such as copper, aluminum, or nickel, or may be composed of multiple metals such as stainless steel. The thickness of the carrier substrate 12 is, for example, 100 μm or more, 200 μm or more, or 500 μm or more. The thickness of the carrier substrate 12 is, for example, 2 mm or less, 1.5 mm or less, or 1 mm or less.

[0202] (Peeling Layer) The peeling layer 13 is a layer that facilitates the operation of peeling the redistribution layer 20 from the carrier substrate 12. The peeling layer 13 includes a first lower surface 131 that faces the carrier substrate 12 and a first upper surface that is located on the opposite side of the first lower surface 131. The peeling layer 13 includes, for example, a resin.

[0203] The release layer 13 is configured so that the adhesion between the release layer 13 and the redistribution layer 20 is reduced by some kind of trigger. The trigger may be irradiation of the release layer 13 with light of a specific wavelength. For example, the release layer 13 may be decomposed by being irradiated with light of a specific wavelength. The trigger may be heating the release layer 13. For example, the release layer 13 may contain a thermoplastic resin.

[0204] The thickness of the release layer 13 is, for example, 0.1 μm or more, optionally 0.2 μm or more, or 0.3 μm or more. The thickness of the release layer 13 is, for example, 1.0 μm or less, optionally 0.8 μm or less, or optionally 0.5 μm or less.

[0205] (Method for Manufacturing the Wiring Board Group) A method for manufacturing the wiring board group 10 will be described.

[0206] As shown in Fig. 40, a carrier substrate 12 is prepared. Subsequently, as shown in Fig. 40, a release layer 13 is formed on the carrier substrate 12. The process of forming the release layer 13 includes, for example, a coating process of coating a solution containing a resin and a solvent, and a drying process of evaporating the solvent after the coating process. Examples of the solvent include propylene glycol monomethyl ether, 2-methoxy-1-methylethyl acetate, N-methyl-2-pyrrolidone, γ-butyrolactone, ethyl lactate, and toluene. The drying process includes, for example, a step of heating the carrier substrate 12.

[0207] Next, a rewiring process is performed to form a rewiring layer 20 including a plurality of wiring layers on the carrier substrate 12. The rewiring process includes, for example, a first wiring process, a second wiring process, and a third wiring process. In the first wiring process, a first wiring layer 201 is formed. In the second wiring process, a second wiring layer 202 is formed on the first wiring layer 201. In the third wiring process, a third wiring layer 203 is formed on the second wiring layer 202.

[0208] 40 is a cross-sectional view showing a first wiring step of forming a first wiring layer 201. The first wiring layer 201 may be formed on the release layer 13. The first wiring step includes a step of forming a conductive layer 26 and a step of forming an organic layer 25. The step of forming the conductive layer 26 and the step of forming the organic layer 25 will be described in detail in the second wiring step described later.

[0209] Although not shown, before the first wiring step, a step of forming an intermediate layer on the release layer 13 may be performed. The intermediate layer may be, for example, a layer that blocks light irradiated onto the release layer 13.

[0210] 41 , the second wiring process may include a process of forming an opening 254 in the organic layer 25 of the first wiring layer 201. The opening 254 penetrates the organic layer 25 in the third direction D3. A portion of the upper surface of the pad 27 of the first wiring layer 201 appears in the opening 254.

[0211] 42 , a step of forming a first inorganic layer 23 on the organic layer 25 of the first wiring layer 201 is carried out. For example, the first inorganic layer 23 is formed by a vapor phase deposition method such as CVD, ALD, or PVD. The first inorganic layer 23 is also formed on the side surfaces of the openings 254 in the organic layer 25 and on the top surfaces of the pads 27 located in the openings 254.

[0212] 43 , a step of forming a first resist layer 71 on the first inorganic layer 23 may be performed. The first resist layer 71 has an opening 711 penetrating the first resist layer 71 in the thickness direction. The opening 711 overlaps a portion of the first inorganic layer 23 located on the upper surface of the pad 27. The opening 711 does not overlap a side portion 233 of the first inorganic layer 23 located on a side surface of the opening 254.

[0213] 44, a step of forming an opening 234 in the first inorganic layer 23 located on the upper surface of the pad 27 is performed. The opening 234 is formed in the first inorganic layer 23 by, for example, dry etching, wet etching, or blasting. The side surface portion 233 may be left unremoved. As shown in FIG. 45, after the opening 234 is formed, the first resist layer 71 is removed.

[0214] Next, a conductive layer forming process is performed to form a conductive layer 26 such as a plurality of wirings 28 on the first inorganic layer 23. For example, as shown in FIG. 46 , a seed layer 261 is formed on the first inorganic layer 23. The seed layer 261 is formed by, for example, sputtering. The seed layer 261 is also formed on the side surfaces of the openings 254 in the organic layer 25 of the first wiring layer 201. The seed layer 261 is also formed on the upper surfaces of the pads 27 located in the openings 254 in the organic layer 25 of the first wiring layer 201.

[0215] Next, as shown in FIG. 47 , a second resist layer 72 is formed on the seed layer 261. The second resist layer 72 has a plurality of openings 721 penetrating the second resist layer 72 in the thickness direction. The openings 721 have a shape corresponding to the plating layer 262 in a plan view. Next, a plating process is performed. In the plating process, as shown in FIG. 48 , the plating layer 262 is formed in the plurality of openings 721 by electrolytic plating.

[0216] 49, a step of removing the second resist layer 72 is then performed. Then, as shown in Fig. 50, a seed layer removal step is performed to remove the seed layer 261 that overlapped the second resist layer 72. A conductive layer 26 including the seed layer 261 and the plating layer 262 is obtained. The conductive layer 26 includes a plurality of wirings 28 located on the first inorganic layer 23, vias 29 located in the openings 254 of the organic layer 25, pads 27 connected to the vias 29, etc.

[0217] In the seed layer removal step, the seed layer 261 overlapping the second resist layer 72 is removed by dry etching, wet etching, blasting, or the like. When dry etching is used, as described above, the upper surface of the first inorganic layer 23 located below the seed layer 261 may also be partially removed to form the recess 231. The dry etching is, for example, ion milling. In ion milling, an ion beam such as an argon ion beam is irradiated onto the seed layer 261.

[0218] 51 , a step of forming the second inorganic layer 24 is performed. For example, the second inorganic layer 24 is formed by a vapor phase deposition method such as CVD, ALD, or PVD. The second inorganic layer 24 covers the conductive layer 26, such as a plurality of wirings 28, and the first inorganic layer 23.

[0219] 52 , a step of forming openings 244 in the second inorganic layer 24 is performed. The openings 244 are formed in the second inorganic layer 24 at positions that overlap the upper surfaces of the pads 27 in a plan view. The openings 244 in the second inorganic layer 24 are formed by, for example, dry etching, wet etching, or blasting, similar to the openings 234 in the first inorganic layer 23.

[0220] Next, as shown in FIG. 53 , a step of forming an organic layer 25 covering the second inorganic layer 24 is performed. For example, the organic layer 25 is formed by applying an organic material onto the second inorganic layer 24 by a spin coating method or the like. Alternatively, the step of forming the organic layer 25 may include a step of attaching a film including an organic material layer onto the second inorganic layer 24. The organic material layer may be transferred onto the second inorganic layer 24 to form the organic layer 25. Next, as shown in FIG. 54 , a step of forming openings 254 in the organic layer 25 at positions overlapping the openings 244 in the second inorganic layer 24 in a plan view is performed. If the organic material is photosensitive, the openings 254 may be formed in the organic layer 25 by an exposure step and a development step. Next, a heating step of heating the organic layer 25 may be performed. The organic layer 25 is cured by the heating step. The heating temperature is, for example, 200° C. or higher.

[0221] 55 , after the second wiring layer 202 including the first inorganic layer 23, the conductive layer 26 such as the plurality of wirings 28, the second inorganic layer 24, and the organic layer 25 is formed, a step of forming the third wiring layer 203 is carried out. The third wiring layer 203 includes the first inorganic layer 23, the conductive layer 26 such as the plurality of wirings 28, and the second inorganic layer 24.

[0222] The rewiring layer 20 is obtained by sequentially forming a plurality of wiring layers, such as a first wiring layer 201, a second wiring layer 202, and a third wiring layer 203, on the carrier substrate 12. The wiring substrate group 10 is obtained by forming a plurality of rewiring layers 20 on the carrier substrate 12.

[0223] (Method for Manufacturing Wiring Board) Next, a method for manufacturing the wiring board 11 will be described.

[0224] A wiring board group 10 is prepared. Subsequently, a dividing process is performed to divide the wiring boards 11. A plurality of wiring boards 11 are manufactured by the dividing process. The wiring board 11 includes a carrier substrate 12, a release layer 13 located on the carrier substrate 12, and a rewiring layer 20 located on the release layer 13.

[0225] 56 and 57 , after the dividing step, a bonding step may be performed in which the wiring substrate 11 is bonded to a substrate 81. The substrate 81 may include a base material 811 and a plurality of terminals 812 located on the base material 811. The substrate 81 may include an adhesive layer 813 covering the plurality of terminals. The adhesive layer 813 may be provided on the wiring substrate 11. In the bonding step, as shown in FIG. 57 , the conductive layer 26 located on the upper surface 20A of the redistribution layer 20 and constituting the pad 27 may be electrically connected to the terminal 812 of the substrate 81.

[0226] 57 and 58 , a peeling process may be performed to peel the redistribution layer 20 from the carrier substrate 12. The peeling process may include an irradiation process of irradiating the peeling layer 13 with light L, as shown in FIG. 57 . In the irradiation process, the light L may reach the peeling layer 13 after transmitting through the carrier substrate 12. The peeling layer 13 may be decomposed by heat generated by the irradiation of the light L. The decomposition reduces the adhesion between the carrier substrate 12 and the redistribution layer 20. As shown in FIG. 58 , the redistribution layer 20 is transferred from the carrier substrate 12 to a substrate 81.

[0227] The structure including the transferred redistribution layer 20 includes a substrate 81 and the redistribution layer 20 located on the substrate 81. This structure may also be referred to as a wiring substrate. In the wiring substrate shown in FIG. 58 , the upper surface 20A of the redistribution layer 20 faces the substrate 81.

[0228] Although not shown, the method of use and distribution of the redistribution layer 20 are not particularly limited. For example, a semiconductor element may be mounted on the lower surface 20B of the redistribution layer 20. The semiconductor element includes a transistor formed of a semiconductor such as silicon. The semiconductor element may be, for example, a CPU, a GPU, an FPGA, a sensor, a memory, or the like. The semiconductor element may be a chiplet in which semiconductor elements such as a CPU, a GPU, an FPGA, a sensor, a memory, or the like are divided by function.

[0229] Although not shown, the redistribution layer 20 may be manufactured on a member including a conductive layer such as the terminal 812, such as the substrate 81. In this case, the redistribution layer 20 is used with the lower surface 20B of the redistribution layer 20 facing the substrate 81. In this case, a semiconductor element may be mounted on the upper surface 20A of the redistribution layer 20.

[0230] The redistribution layer 20 may be distributed in the form of a wiring substrate group 10. The redistribution layer 20 may be distributed in the form of a wiring substrate 11. The redistribution layer 20 may be distributed after being transferred from the carrier substrate 12 to the substrate 81.

[0231] In this embodiment, an inorganic material layer is disposed between the organic material layer and the wiring 28. For example, a first inorganic layer 23 is disposed between the organic layer 25 of the first wiring layer 201, which is an underlying layer of the second wiring layer 202, and the wiring 28 of the second wiring layer 202. Furthermore, a second inorganic layer 24 is disposed between the organic layer 25 of the second wiring layer 202 and the wiring 28. Since the plurality of wirings 28 are surrounded by the first inorganic layer 23 and the second inorganic layer 24, leakage current passing through the organic material layer is prevented from flowing between the plurality of wirings 28.

[0232] The second portion 248 of the second inorganic layer 24 is in contact with the first inorganic layer 23, not the organic layer 25 of the first wiring layer 201. This suppresses delamination from occurring on the lower surface of the second portion 248 of the second inorganic layer 24 of the second wiring layer 202. Since the structural stability of the second inorganic layer 24 is improved, the structural stability of the wiring 28 is also improved.

[0233] The inorganic layers such as the first inorganic layer 23 and the second inorganic layer 24 can also contribute to suppressing deformation such as warping.

[0234] The process of forming the redistribution layer 20 may include a process performed at high temperature, such as a process of heating the organic layer 25. The thermal expansion coefficient of the organic material of the organic layer 25 is greater than that of the other components of the redistribution layer 20. For example, the thermal expansion coefficient of the organic material of the organic layer 25 is greater than that of a substrate, such as the carrier substrate 12. For example, the thermal expansion coefficient of the organic material of the organic layer 25 is greater than that of the conductive layer 26. When the temperature of the components of the redistribution layer 20 decreases after the heating process, stress may be generated due to the difference in the thermal expansion coefficient between the organic layer 25 and the other components. For example, stress may be generated in the substrate, the conductive layer 26, etc.

[0235] According to the present embodiment, since the redistribution layer 20 includes inorganic layers such as the first inorganic layer 23 and the second inorganic layer 24, the stress caused by the organic layer 25 is prevented from affecting components other than the inorganic layers. For example, the occurrence of warping in the redistribution layer 20, the wiring board group 10, or the wiring board 11 is prevented. The occurrence of defects such as deformation and breakage in the conductive layer 26 may be prevented by preventing the occurrence of stress in the conductive layer 26.

[0236] The suppression of warpage will be described in detail. Warpage occurs due to differences in the degree of contraction that occurs in the components of the wiring board group 10 when the temperature returns from a high temperature to room temperature. Assume that the direction of warpage caused by the organic layer 25 is opposite to the direction of warpage caused by the inorganic layer. This warpage relationship is realized, for example, when the thermal expansion coefficient of the organic layer 25 is greater than a reference thermal expansion coefficient and the thermal expansion coefficient of the inorganic layer is smaller than the reference thermal expansion coefficient. The reference thermal expansion coefficient is, for example, the thermal expansion coefficient of the carrier substrate 12, the conductive layer 26, etc.

[0237] When the above-described warpage relationship exists, warpage of the rewiring layer 20, the wiring board group 10, or the wiring board 11 can be suppressed by configuring the inorganic layer so as to cancel the warpage caused by the organic layer 25. For example, the composition, thickness, arrangement, etc. of the inorganic layer are adjusted. For example, the thicker the inorganic layer is, the more the warpage caused by the organic layer 25 can be canceled.

[0238] When the wiring board group 10 includes only one inorganic layer, either the first inorganic layer 23 or the second inorganic layer 24, i.e., only one inorganic layer, the thickness of the inorganic layer is adjusted. In this case, it is possible that the thickness of the inorganic layer becomes excessively large. The thicker the inorganic layer, the more difficult the process of forming an opening in the inorganic layer becomes. For example, the process of forming an opening in the inorganic layer takes longer. Furthermore, the process of forming the inorganic layer also takes longer.

[0239] In order to shorten the time required for the process of forming the inorganic layer, it is conceivable to increase the film formation rate in a film formation method such as a CVD method, a vapor deposition method, a sputtering method, etc. However, if the film formation rate is excessively high, defects such as voids are likely to occur in the inorganic layer.

[0240] The redistribution layer 20 of this embodiment includes two inorganic layers, a first inorganic layer 23 and a second inorganic layer 24. In this case, warpage caused by the organic layer 25 can be canceled by adjusting the thicknesses of the two inorganic layers. Therefore, the thickness of one inorganic layer can be reduced compared to when there is only one inorganic layer. Therefore, warpage of the redistribution layer 20, the wiring board group 10, or the wiring board 11 can be suppressed while suppressing the complexity of manufacturing processes such as the process of forming an opening in the inorganic layer and the process of forming the inorganic layer.

[0241] The above-described embodiment can be modified in various ways. Below, modified examples will be described with reference to the drawings as necessary. In the following description and the drawings used in the following description, parts that can be configured similarly to the above-described embodiment will be designated by the same reference numerals as those used for corresponding parts in the above-described embodiment. Duplicate descriptions will be omitted. Furthermore, if it is clear that the effects obtained in the above-described embodiment can also be obtained in modified examples, the description of those effects may be omitted.

[0242] 59 is a cross-sectional view showing the organic layer 25 and the via 29 in a first modified example. The first inorganic layer 23 does not need to include the above-described side portion 233 located on the side of the opening 254. For example, the end of the first inorganic layer 23 may be located between the upper surface of the organic layer 25 and the lower surface 271 of the pad 27.

[0243] A method for forming the first inorganic layer 23 shown in FIG. 59 will be described.

[0244] 42 , a step of forming the first inorganic layer 23 on the organic layer 25 of the first wiring layer 201 is performed. The first inorganic layer 23 is also formed on the side surfaces of the openings 254 in the organic layer 25 and on the top surfaces of the pads 27 located in the openings 254.

[0245] 60 , a step of forming a first resist layer 71 on the first inorganic layer 23 is performed. The first resist layer 71 has an opening 711 penetrating the first resist layer 71 in the thickness direction. The opening 711 overlaps a portion of the first inorganic layer 23 located on the upper surface of the pad 27. The opening 711 also overlaps a side surface portion 233 of the first inorganic layer 23 located on a side surface of the opening 254. For example, the side surface of the opening 711 overlaps the upper surface of the organic layer 25 in a plan view.

[0246] 61 , the portion of the first inorganic layer 23 that overlaps the opening 711 in plan view is removed to form the opening 234. Thereafter, similar to the case of the above-described embodiment, a step of forming the conductive layer 26 such as the plurality of wirings 28 is carried out.

[0247] In this modification, the second inorganic layer 24 is in contact with the first inorganic layer 23, so that the structural stability of the components of the redistribution layer 20 is improved.

[0248] 62 is a diagram showing an example of a product in which the redistribution layer 20 is mounted. The redistribution layer 20 can be used in a variety of products. For example, the redistribution layer 20 is mounted in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, and the like.

[0249] 63 is a cross-sectional view showing an example of an organic layer 25 and a via 29 in a second modified example. In the example shown in Fig. 63, the third wiring layer 203 includes a first inorganic layer 23 located on the upper surface of the organic layer 25 of the second wiring layer 202. Therefore, the organic layer 25 of the second wiring layer 202 is an underlayer for the first inorganic layer 23 of the third wiring layer 203. The second wiring layer 202 includes the first inorganic layer 23, the second inorganic layer 24, the organic layer 25, and a pad 27.

[0250] The organic layer 25 of the second wiring layer 202 includes an opening 254 that overlaps the pad 27 in a plan view. As shown in Fig. 63, the side surface of the opening 254 may include a notch 254b located on the lower surface of the organic layer 25. The notch 254b is a portion of the organic layer 25 that is recessed outward from the side surface of the opening 254. "Outward" refers to the direction away from the center point of the opening 254 in a plan view. The notch 254b overlaps an upper surface portion 243 of the second inorganic layer 24 that is located on the upper surface 272 of the pad 27 in a plan view.

[0251] 63 , the side surface portion 233 of the first inorganic layer 23 of the third wiring layer 203 located on the side surface of the opening 254 may include a portion located in the notch 254b. The portion of the first inorganic layer 23 located in the notch 254b is also referred to as an intrusion portion, and is denoted by the symbol 233b.

[0252] The penetration portion 233b of the first inorganic layer 23 of the third wiring layer 203 may be in contact with the upper surface portion 243 of the second inorganic layer 24 of the second wiring layer 202. As a result, the contact area between the first inorganic layer 23 of the third wiring layer 203 and the second inorganic layer 24 of the second wiring layer 202 increases. Therefore, the occurrence of interlayer delamination between the first inorganic layer 23 of the third wiring layer 203 and the second inorganic layer 24 of the second wiring layer 202 is suppressed.

[0253] 63, the symbol Sn represents the dimension of the notch 254b in the surface direction of the wiring substrate group 10. When the opening 254 is circular in a plan view, the dimension Sn of the notch 254b is measured in the radial direction of the opening 254. The dimension Sn of the notch 254b is, for example, 0.10 μm or more, or may be 0.30 μm or more, or may be 0.50 μm or more. The dimension Sn of the notch 254b is, for example, 2.00 μm or less, or may be 1.50 μm or less, or may be 1.00 μm or less.

[0254] An example of a method for forming the organic layer 25 and the via 29 according to the second modified example will now be described. FIG. 64 is a cross-sectional view showing a step of forming an opening 254 in the organic layer 25 of the second wiring layer 202 according to the second modified example. In the example shown in FIG. 64 , the side of the opening 254 in the organic layer 25 of the second wiring layer 202 includes a notch 254b recessed outward. The notch 254b is formed, for example, by extending the time of the step of developing the organic layer 25 described in FIG. 54 longer than in the example of FIG. 54 . If the pad 27 is not sufficiently exposed in the opening 254, there is a possibility that the electrical connection between the pad 27 and the via 29 formed on the upper surface of the pad 27 will be insufficient. To increase the reliability of the electrical connection, the time of the step of developing the organic layer 25 is extended.

[0255] Thereafter, a step of forming the first inorganic layer 23 of the third wiring layer 203 is carried out. For example, the first inorganic layer 23 is formed by a vapor phase deposition method such as CVD, ALD, or PVD. The first inorganic layer 23 is formed on the side surface of the opening 254 of the organic layer 25, the inside of the notch 254b on the side, and the top surface of the pad 27 located at the opening 254. Then, an opening is formed in the first inorganic layer 23 located at the top surface of the pad 27. As a result, the first inorganic layer 23 of the third wiring layer 203 shown in FIG. 63 is obtained.

[0256] 65 to 67, another example of the method for forming the organic layer 25 and the vias 29 of the second modified example will be described. Fig. 65 is a cross-sectional view showing a step of forming the organic layer 25 that covers the second inorganic layer 24 of the second wiring layer 202. The organic layer 25 is formed in a state where no openings are formed in the second inorganic layer 24.

[0257] 66 is a cross-sectional view showing a step of forming an opening 254 in the organic layer 25. As shown in Fig. 66, in the step of forming the opening 254 in the organic layer 25, a notch 254b may be formed on a side surface of the opening 254. Although not shown, in the step of forming the opening 254 in the organic layer 25, a notch does not have to be formed on a side surface of the opening 254.

[0258] 67 is a cross-sectional view showing a step of forming an opening 244 in the second inorganic layer 24. In the step of forming the opening 244 in the second inorganic layer 24, a notch 254b may be formed on a side surface of the opening 244 in the organic layer 25.

[0259] Because the second inorganic layer 24 contains an insulating material, charges may accumulate on the upper surface of the second inorganic layer 24 in the process of forming the opening 244 in the second inorganic layer 24. For example, a notch 254b may be formed on the side surface of the opening 254 in the organic layer 25 due to a reaction between charges on the upper surface of the second inorganic layer 24 and radicals contained in the organic layer 25.

[0260] Although several modifications of the second embodiment have been described above, it is of course possible to combine a plurality of modifications as appropriate and apply them to the above-described embodiment.

[0261] The first embodiment or its modification may be combined with the second embodiment or its modification, for example, the two inorganic layers technique of the second embodiment may be applied to the interposer intermediate of the first embodiment, as described below.

[0262] 68 is a cross-sectional view showing an example of the interposer intermediate 1. The inorganic film 38 of the intermediate interposer layer 20 may include a first inorganic layer 23 and a second inorganic layer 24. For example, the inorganic film 38 of the first resin wiring layer 201 may include a first inorganic layer 23 and a second inorganic layer 24. For example, the inorganic film 38 of the second resin wiring layer 202 may include a first inorganic layer 23 and a second inorganic layer 24.

[0263] The first inorganic layer 23 is located on the upper surface of the base layer. The base layer is a layer that supports the first inorganic layer 23. For example, the base layer for the first inorganic layer 23 of the first resin wiring layer 201 is the carrier substrate 2. The first inorganic layer 23 of the first resin wiring layer 201 may or may not be in contact with the first surface 2A of the carrier substrate 2. For example, the base layer for the first inorganic layer 23 of the second wiring layer 202 is the previous-process resin layer 21 of the first resin wiring layer 201. The first inorganic layer 23 of the second wiring layer 202 may or may not be in contact with the upper surface of the previous-process resin layer 21.

[0264] The second inorganic layer 24 covers the multiple wirings 32. As in the second embodiment, the second inorganic layer 24 may include a first portion and a second portion. The first portion is a portion of the second inorganic layer 24 located between a conductive layer such as the wirings 32 and the previous-step resin layer 21. The first portion may be in contact with the upper and side surfaces of the wirings 32. The second portion is a portion of the second inorganic layer 24 located between the upper surface of the first inorganic layer 23 and the lower surface of the previous-step resin layer 21. The second portion may be in contact with the upper surface of the first inorganic layer 23.

[0265] 68 , the wiring 32 is surrounded by the first inorganic layer 23 and the second inorganic layer 24. That is, the first inorganic layer 23 is in contact with the lower surface of the wiring 32, and a first portion of the second inorganic layer 24 is in contact with the upper surface and side surfaces of the wiring 32. Furthermore, a second portion of the second inorganic layer 24 is in contact with the first inorganic layer.

[0266] In the example shown in Figure 68, as in the first embodiment described above, the first inorganic layer 23 and the second inorganic layer 24 are not provided at least partially in the positions between adjacent wiring groups 32G in the interposer intermediate 1.

[0267] FIG. 69 is a diagram illustrating a method for manufacturing an interposer 30 from the interposer intermediate 1 of FIG. 68 . As in the first embodiment described above, the interposer 30 is manufactured by performing a singulation process in which adjacent wiring groups 32G are separated at locations where the first inorganic layer 23 and the second inorganic layer 24 are not present between the adjacent wiring groups 32G, and the carrier substrate 2 is cut. This reduces the risk of foreign matter being generated from the first inorganic layer 23 and the second inorganic layer 24. Furthermore, this reduces the risk of stresses generated when cutting the first inorganic layer 23 and the second inorganic layer 24 affecting the finished cut. Therefore, this example can prevent foreign matter from being generated from the interposer 30 and cracks from occurring in the inorganic film in unintended locations, such as locations covering the wiring, and can provide an interposer 30 with a good finish.

[0268] In this example, the resin layer 31 of the first resin wiring layer 201 and the resin layer 31 of the second resin wiring layer 202 are bonded to each other at locations where the first inorganic layer 23 and the second inorganic layer 24 are not present. As a result, the resin layer 31 of the first resin wiring layer 201 and the resin layer 31 of the second resin wiring layer 202 are firmly bonded to each other.

[0269] Since the inorganic film 38 includes the first inorganic layer 23 and the second inorganic layer 24, warping of the rewiring layer 20, the wiring board group 10, or the wiring board 11 is suppressed, as in the case of the second embodiment described above.

[0270] The positional relationship between the end of the first inorganic layer 23 and the end of the second inorganic layer 24 is not particularly limited. For example, the position of the end of the first inorganic layer 23 may coincide with the position of the end of the second inorganic layer 24. For example, the end of the first inorganic layer 23 may be located outside the end of the second inorganic layer 24. Here, "outside" means a direction approaching the cutting range CA. In this case, the end of the second inorganic layer 24 is located on the upper surface of the first inorganic layer 23. For example, the end of the first inorganic layer 23 may be located inside the end of the second inorganic layer 24. Here, "inside" means a direction away from the cutting range CA. In this case, the end of the second inorganic layer 23 may be covered by the second inorganic layer 24.

[0271] 1, 1r1, 1r2, 1r3, 1r4, 1r5, 1r6, 1r7...interposer intermediate body 2...carrier substrate 2A...first surface 2B...second surface 10...wiring substrate group 11...wiring substrate 20...intermediate interposer layer 20A...first surface 20B...second surface 21...pre-process resin layer 22...pre-process wiring layer 201...first resin wiring layer 201L...land portion 202...second resin wiring layer 202L...land portion 212...groove 23...first inorganic layer 24...second inorganic layer 25...organic layer 26...conductive layer 27...pad 28...wiring 29...via 30...interposer 31...resin layer 32...wiring 32G...wiring group 33...seed layer 34...plating layer 35...adhesion layer 38...inorganic film 38A... First inorganic film 38B... Second inorganic film CA... Cutting range W... Cutting width S... Margin width C... Predetermined distance (coated edge margin)

Claims

1. A method for manufacturing an interposer, comprising: a wiring formation process for providing a plurality of wiring groups, each of which includes a plurality of wirings, on a substrate; an inorganic film coating process for coating each of the wirings of the plurality of wiring groups and portions located between adjacent wiring groups with an inorganic film containing an inorganic material; a removal process for at least partially removing portions of the inorganic film located between adjacent wiring groups; and a singulation process for separating adjacent wiring groups at locations where the inorganic film does not exist between the adjacent wiring groups.

2. A method for manufacturing an interposer as described in claim 1, wherein in the wiring formation process, the plurality of wiring groups are provided on a resin layer containing resin provided on the substrate, and in the inorganic film coating process, the inorganic film is coated on each of the wirings of the plurality of wiring groups and the resin layer.

3. A method for manufacturing an interposer as described in claim 2, wherein the resin layer has a plurality of land portions separated from each other, and the substrate has a portion exposed between adjacent land portions, the wiring formation process provides the wiring groups on the plurality of land portions, and the inorganic film coating process coats each of the wirings of the plurality of wiring groups, each of the land portions, and the substrate with the inorganic film.

4. A method for manufacturing an interposer as described in claim 3, wherein in the inorganic film coating process, the surface and side surfaces of the land portions are coated with the inorganic film, and in the removal process, the inorganic film located between adjacent land portions is partially removed while leaving the inorganic film covering the surface and side surfaces of the land portions.

5. A method for manufacturing an interposer as described in claim 1, wherein in the removal process, a boundary portion of the inorganic film is removed, and the boundary portion is a predetermined distance away from the wiring of one of the adjacent wiring groups and a predetermined distance away from the wiring of the other of the adjacent wiring groups.

6. A method for manufacturing an interposer as described in claim 5, wherein the singulation process divides the adjacent wiring groups at a cutting range, and the cutting range is set to a range away from both edges of a location where the inorganic film does not exist between the adjacent wiring groups.

7. A method for manufacturing an interposer as described in claim 6, wherein the width of the cutting range is defined as cutting width W, the distance from the edge of the area between adjacent wiring groups where no inorganic film exists to the edge of the cutting range facing said edge is defined as margin width S, and the specified distance is defined as coated end margin C, and the relationship W + S > C holds.

8. A method for manufacturing an interposer as described in claim 1 or 7, further comprising a resin layer formation process for forming a resin-containing resin layer on the inorganic film on each wire of the wiring group and on the portion located between adjacent wiring groups after removing the portion of the inorganic film located between adjacent wiring groups.

9. The method for manufacturing an interposer according to claim 1, wherein the inorganic film includes at least one of a metal oxide and a metal nitride.

10. The method for manufacturing an interposer according to claim 1, wherein the wiring includes a seed layer and a plating layer formed from the seed layer.

11. An interposer intermediate comprising: a substrate; a plurality of wiring groups including at least a plurality of wirings provided on the substrate; and an inorganic film including an inorganic material covering each of the wirings of the plurality of wiring groups, wherein the inorganic film is at least partially absent in positions between adjacent wiring groups.

12. An interposer intermediate as described in claim 11, wherein the plurality of wiring groups are provided on the substrate and in a resin layer containing resin, the resin layer has a plurality of land portions separated from each other, the substrate is partially exposed between adjacent land portions, and the inorganic film includes a portion covering the surface and side surfaces of the land portions.

13. An interposer comprising: one or more wiring groups each including a plurality of wirings; and an inorganic film containing an inorganic material covering each of the wirings of the one or more wiring groups, wherein the inorganic film is not provided at least partially from the outer peripheral edge toward the inside.

14. An interposer as described in claim 13, wherein the one or more wiring groups are provided in a resin layer containing resin, the resin layer has at least one land portion, and the inorganic film includes a portion covering a side surface of the land portion.

Images