Loop-break decision feedback equalizer

Abstract

The present invention relates to a loop-break decision feedback equalizer and, more specifically, to a technology designed to split each parallel way of an analog-to-digital converter (ADC) at multiple points (indexes) and perform DFE technology in parallel from multiple starting points, thereby requiring only the feedback time corresponding to the number of MUXs in each segment and thus alleviating the feedback time constraint compared to conventional DFE, so that the technology is suitable for high-speed operation.

Description

Loop Break Decision Feedback Equalizer

[0001] The present invention relates to a loop-break decision feedback equalizer, and more particularly, to a loop-break decision feedback equalizer designed to divide the execution of a decision feedback equalizer (DFE) into segments to form independent loops, thereby alleviating feedback time and achieving high-speed communication.

[0002]

[0003] Decision feedback equalization (DFE) is a technology used in communications systems, designed to reduce signal distortion and improve data transmission quality. Conventional DFEs operate by selectively selecting and combining signals from multiple possible inputs using multiplexers (MUXs). This allows DFEs to respond flexibly to a variety of situations and offers the advantage of selecting the optimal signal path based on specific conditions or parameters.

[0004] Conventional decision feedback equalizers utilize loop-unrolling techniques, which often fail to meet the required feedback time due to the numerous multiplexers (MUXs) required. Feedback time, defined as the time required to process symbols determined in the previous time step and reflect the symbol decision in the current time step, is closely related to the performance of the decision feedback equalizer and impacts the overall data transmission and processing speed. Therefore, optimizing feedback time is essential for ensuring signal quality and enhancing the reliability of communication systems.

[0005] To solve these feedback time constraints, Sliding Block DFE was designed in the past, but it has the disadvantage of consuming many cycles in terms of latency.

[0006] In addition, another proposal, Look-Ahead DFE, has the disadvantage that the area increases exponentially as the feedback time is reduced.

[0007] There is an increasing demand for the development of a decision feedback equalizer that overcomes the shortcomings of these conventional technologies, that is, that enables efficient feedback time mitigation not only in terms of latency but also in terms of area.

[0008]

[0009] In this regard, “IEEE Transactions on Circuits and Systems. Part 2: Express Briefs, A 10-Gb / s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor, 2012, ISSN 1549-4414” discloses a technique for measuring the magnitude of received signals with different data patterns, using this to estimate inter-symbol interference, and determine the amount of adaptation required.

[0010]

[0011] The present invention has been devised to solve the problems of the prior art as described above, and the purpose of the present invention is to provide a loop break decision feedback equalizer designed to be suitable for high speed by dividing multiple points (Indexes) of a parallel way of an ADC (Analog-Digital Converter) to perform DFE technology in parallel in a form with multiple starting points, so that only a feedback time equivalent to the MUX of the corresponding segment is required, thereby easing the feedback time constraints compared to the prior DFE and making it suitable for high speed.

[0012]

[0013] According to one embodiment of the present invention, a loop break decision feedback equalizer comprises: a loop segment module including first to n loop segments, receiving a digital signal (Yffe) and generating a candidate data signal (Dffe) and a correct candidate selection signal (Affe) at a current time step; a buffer storing the candidate data signal (Dffe) and the correct candidate selection signal (Affe) at the current time step and providing the candidate data signal (Ddfe) and the correct candidate selection signal (Adfe) at a time step one step prior to the current time step; and a loop break select module receiving the candidate data signal (Ddfe) and the correct candidate selection signal (Adfe) and outputting a final output signal (Dout), wherein the loop break select module preferably selects a part of the candidate data signals (Ddfe) based on the correct candidate selection signal (Adfe) and outputs the final output signal (Dout).

[0014] Furthermore, it is preferable that the ith loop segment included in the loop segment module includes a correct answer candidate calculation module and a start candidate calculation module, and the correct answer candidate calculation module utilizes loop unrolling to input the digital signal (Yffe[i][0]) and output a correct answer candidate selection signal (Affe[i]) at the corresponding current time step, and the start candidate calculation module utilizes loop unrolling to input the digital signal ({Yffe[i][1], …, Yffe[i][m-1]}) and output a candidate data signal (Dffe[i]) at the corresponding current time step.

[0015] Furthermore, it is preferable that the above-described correct answer candidate calculation module receives the digital signal (Yffe[i][0]) and the candidate data signal (Dffe[n]) output by the nth loop segment, and outputs a correct answer candidate selection signal (Affe[i]) at the corresponding current time step.

[0016] Furthermore, it is preferable that the above-mentioned start candidate calculation module receives the digital signal (Yffe[i][1]) and a preset constant value as input and outputs a candidate data signal (Dffe[i]) at the corresponding current time step.

[0017] Furthermore, it is preferable that the above-mentioned start candidate calculation module receives the digital signal ({Yffe[i][2], …, Yffe[i][m-1]}) and the candidate data signal ({Dffe[1], …, Dffe[m-1]}) as input, and outputs the candidate data signal (Dffe[i]) at the corresponding current time step.

[0018] Furthermore, it is preferable that the loop break selection module includes a correct answer preprocessing module and a correct answer postprocessing module, wherein the correct answer preprocessing module receives the correct answer candidate selection signal (Adfe[i]) as input and outputs the correct answer selection signal (Abefo[i]) at the corresponding current time step, and the correct answer postprocessing module receives the candidate data signal (Ddfe[i]) as input and outputs the final output signal (Dout[i]).

[0019] Furthermore, it is preferable that the above-mentioned correct answer preprocessing module receives the correct answer candidate selection signal (Adfe[i]) and the correct answer selection signal (Abefo[i-1]) at a time step one step prior to the corresponding current time step, and outputs the correct answer selection signal (Abefo[i]) at the corresponding current time step.

[0020] Furthermore, it is preferable that the above-mentioned correct answer post-processing module receives the candidate data signal (Ddfe[i]) and the correct answer selection signal (Abefo[i]) as input and outputs the final output signal (Dout[i]).

[0021] Furthermore, it is preferable that the loop break selection module further includes a buffer for storing the candidate data signal (Ddfe[i]) at the current time step.

[0022]

[0023] The loop break decision feedback equalizer of the present invention, having the above configuration, unlike the existing DFE, divides the k-way of the ADC into segments and performs DFE in parallel for each, that is, by dividing the execution of the DFE into segments and forming an independent loop, the feedback time can be relaxed as much as desired, and thus has the advantage of being suitable for high-speed communication. Through this, it has the advantage of being able to achieve low latency and small area. With the loop segment structure using multiple candidates, there is the advantage of being able to achieve ultra-high-speed communication due to the emergence of ADCs with multiple ways due to the relaxation of the feedback time.

[0024] Furthermore, rather than all ADC paths receiving a single feedback signal, this circuit independently receives feedback through each arbitrarily divided loop segment. In other words, rather than fixing the starting point of the DFE data to a single point, this circuit performs DFE in parallel and simultaneously on multiple candidates, outputting overlapping values ​​and selecting among the resulting candidate values. This structure offers the advantage of further alleviating the existing DFE feedback time constraints.

[0025]

[0026] FIG. 1 is an exemplary drawing showing a wireline transceiver to which a loop break decision feedback equalizer according to one embodiment of the present invention is applied.

[0027] FIG. 2 and FIG. 3 are circuit diagrams of a loop break decision feedback equalizer according to one embodiment of the present invention.

[0028] FIG. 4 and FIG. 5 are detailed diagrams showing a circuit diagram of a loop segment module of a loop break decision feedback equalizer according to one embodiment of the present invention.

[0029] FIG. 6 and FIG. 7 are detailed diagrams showing a circuit diagram of a loop break selection module of a loop break decision feedback equalizer according to one embodiment of the present invention.

[0030]

[0031] The loop-break decision feedback equalizer of the present invention will now be described in detail with reference to the accompanying drawings. The drawings presented below are provided as examples to ensure that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the drawings presented below and may be embodied in other forms. Furthermore, like reference numerals designate like elements throughout the specification.

[0032] In this case, if there is no other definition in the technical and scientific terms used, they have the meaning commonly understood by a person of ordinary skill in the technical field to which this invention belongs, and the description of known functions and configurations that may unnecessarily obscure the gist of the present invention in the following description and attached drawings are omitted.

[0033]

[0034] A Loop Break Decision Feedback Equalizer (LBDFE) according to one embodiment of the present invention includes, as illustrated in FIG. 1, a Loop segment module that performs DFE technology in parallel by cutting off multiple points (Index) of a parallel way of an ADC so that there are multiple starting points, and a Loop Break Select module that overlaps all DFE starting points that are performed in parallel with the DFE results from the previous index for all cases of 4-PAM (4-Pulse Amplitude Modulation) (00, 01, 10, 11) values ​​and selects the correct answer by comparing them at the next time step.

[0035] That is, unlike the existing DFE, it divides the k-way of the ADC into segments and performs DFE in parallel for each, that is, it divides the DFE execution into segments and forms an independent loop, so the feedback time can be relaxed as much as desired, which has the advantage of being suitable for high-speed communication. Through this, it has the advantage of being able to achieve low latency and small area. With the loop segment structure that utilizes multiple candidates, it has the advantage of being able to achieve ultra-high-speed communication due to the emergence of ADCs with multiple ways due to the relaxation of the feedback time.

[0036] Additionally, since the outputs of each segment are candidates for the correct answer, it is desirable to configure a module (loop break selection module) for selecting them at the next time step.

[0037] A loop-break decision feedback equalizer according to one embodiment of the present invention is a circuit that receives feedback independently through each arbitrarily divided loop segment, rather than having all ways of the ADC receive a single feedback. In other words, rather than fixing the starting point of DFE data to a single point, it is a structural circuit that performs DFE in parallel and simultaneously on multiple candidates, outputs overlapping values, and selects the resulting candidate values. This has the advantage of further alleviating the existing DFE feedback time constraint.

[0038]

[0039] A loop break decision feedback equalizer according to one embodiment of the present invention is preferably largely composed of a loop segment module (100), a loop break selection module (200), and a buffer, as illustrated in FIG. 2.

[0040] Let's take a closer look at each component:

[0041] The above loop segment module (100) preferably includes 1 to n loop segments (for example, 100-1, ..., 100-8), receives a digital signal (Yffe), and generates a candidate data signal (Dffe) and a correct candidate selection signal (Affe) at the current time step. That is, Affe and Dffe corresponding to the same starting point are output. An overlap value exists for selection at the next time step.

[0042] It is preferable that the above buffer stores a candidate data signal (Dffe) and a correct candidate selection signal (Affe) at the current time step, and provides a candidate data signal (Ddfe) and a correct candidate selection signal (Adfe) at a time step one step prior to the current time step.

[0043] It is preferable that the above loop break select module (200) receives the candidate data signal (Ddfe) and the correct candidate selection signal (Adfe) and outputs the final output signal (Dout).

[0044] It is preferable that the above loop break selection module (200) selects some of the candidate data signals (Ddfe) based on the correct answer candidate selection signal (Adfe) and outputs the final output signal (Dout).

[0045] Here, referring to FIGS. 2 to 4, Yffe is {Yffe[1], … , Yffe[n]},

[0046] Yffe[i] is {Yffe[i][0], … , Yffe[i][m-1]}, 1 ≤ i ≤ n,

[0047] Affe is {Affe[1], … , Affe[n]},

[0048] Affe[i] is {Affe[i][0], … , Affe[i][3]}, 1 ≤ i ≤ n,

[0049] Dffe is {Dffe[1], … , Dffe[n]},

[0050] Dffe[i] is {Dffe[i][1], … , Dffe[i][4]},

[0051] Dffe[i][j] is {Dffe[i][j][0], … , Dffe[i][j][m-1]}, 1 ≤ i ≤ n, 1 ≤ j ≤ 4,

[0052] Ddfe is {Ddfe[1], … , Ddfe[n]},

[0053] Ddfe[i] is {Ddfe[i][1], … , Ddfe[i][4]},

[0054] Ddfe[i][j][ is {Ddfe[i][j][0], … , Ddfe[i][j][7]}, 1 ≤ i ≤ n, 1 ≤ j ≤ 4,

[0055] Adfe is {Adfe[1], … , Adfe[n]},

[0056] Adfe[i] is {Adfe[i][0], … , Adfe[i][3]},

[0057] Dout is {Dout[1], … , Dout[n]},

[0058] Dout[i] is {Dout[i][0], …, Dout[i][7]}, and it is desirable that 1 ≤ i ≤ n.

[0059] Also, when the number of ADC output data sets per clock cycle is n, n is set from 1 to q (1 ≤ n ≤ q), and the larger n is, the faster the operation is. Most preferably, n = q, and m is preferably q / n.

[0060] In the loop break decision feedback equalizer according to one embodiment of the present invention, a description is given for the case where m is 8, but this is only one embodiment.

[0061]

[0062] Each of the i-th loop segments (100-1, ..., 100-i) included in the above loop segment module (100) preferably includes a correct answer candidate calculation module (101) and a start candidate calculation module (102), and each time step (clock) is preferably composed of 2 to 3 stages.

[0063] The first stage represents the time step at which the loop segment operates, and it is desirable to input the output of the FFE and perform the DFE in parallel from the starting point (Index) of each point. It is desirable that each starting point be the value of all cases of 4-PAM (00, 01, 10, 11). Each starting point overlaps with the result of the last point derived from the previous loop segment, so that comparison and selection are performed in the next time step. That is, the calculated value of Loop Unrolling is assigned as input to four MUXs corresponding to all cases. The selection values ​​of the MUX at the starting point are input as 00, 01, 10, and 11.

[0064] In detail, it is preferable that the above-mentioned correct answer candidate calculation module (101) utilizes a loop unrolling DFE to input the digital signal (Yffe[i][0]) and output the correct answer candidate selection signal (Affe[i]) at the corresponding current time step.

[0065] The above-mentioned correct answer candidate calculation module (101) receives the digital signal (Yffe[i][0]) and the candidate data signal (Dffe[n]) output by the nth loop segment, and outputs the correct answer candidate selection signal (Affe[i]) at the corresponding current time step.

[0066] It is preferable that the above-mentioned start candidate calculation module (102) utilizes a loop unrolling DFE to input the digital signal ({Yffe[i][1], …, Yffe[i][m-1]}) and output the candidate data signal (Dffe[i]) at the corresponding current time step.

[0067] The above-mentioned start candidate calculation module (102) preferably receives the digital signal (Yffe[i][1]) and a preset constant value as input, and outputs the candidate data signal (Dffe[i]) at the corresponding current time step, and preferably receives the digital signal ({Yffe[i][2], …, Yffe[i][m-1]}) and the candidate data signal ({Dffe[1], …, Dffe[m-1]}) as input, and outputs the candidate data signal (Dffe[i]) at the corresponding current time step.

[0068]

[0069] Since the above loop break selection module (200) proceeds with DEF by setting a starting point in parallel, there are as many MUX chains as the number of DFEs within the designated rope segment, so that more feedback time constraints can be secured than the MUX chains of the existing DFE. It has an advantage that it can be designed so that a desired amount of feedback time can be obtained because it has a structure that can arbitrarily designate the position of breaking the starting point. For example, it is possible to do it irregularly, such as 0, 12, 24 or 0, 10, 24, but since the feedback timing is adjusted to the maximum value, it is preferable to proceed regularly, such as 0, 4, 8, ... or 0, 8, 16. ... or 0, 16, 32, ....

[0070] Among the output values ​​of the first stage, the true correct answer (Adfe) value is selected with the result of the starting point overlapping from the previous loop segment.

[0071] The first section is a circuit that finds the correct answer for each starting point that starts in parallel, and proceeds in the form of feedback.

[0072] That is, referring to FIG. 3, FIG. 6 and FIG. 7, the reason why the MUX result of Adfe,0 is entered into the MUX selection of Adfe,8 is because the value of Adfe,8 is output due to the results of the starting point of Adfe,0. The corresponding MUX continuously selects and selects the correct answer of the starting point. The selected correct answer is entered as the input of the loop break selection module to select the final output. Optionally, the loop break selection module after the applicable Register selects the Ddfe value (= Dsel value) corresponding to the correct answer as the final output.

[0073] That is, the loop break selection module (200) further includes a buffer that stores the candidate data signal (Ddfe[i]) at the current time step.

[0074] The optionally applicable Register (Register pipelining) can be applied in case the MUX chain feedback time constituting the loop break selection module (200) does not match, and it can be designed with three clock stages, and if not, it can be designed with only two clock stages by outputting directly without the Register.

[0075] In detail, the loop break selection module (200) preferably includes a correct answer preprocessing module (201) and a correct answer postprocessing module (202), as shown in FIGS. 3, 6, and 7.

[0076] It is preferable that the above correct answer preprocessing module (201) receives the correct answer candidate selection signal (Adfe[i]) and outputs the correct answer selection signal (Abefo[i]) at the corresponding current time step.

[0077] It is preferable that the above correct answer preprocessing module (201) receives the correct answer candidate selection signal (Adfe[i]) and the correct answer selection signal (Abefo[i-1]) at a time step one step prior to the corresponding current time step, and outputs the correct answer selection signal (Abefo[i]) at the corresponding current time step.

[0078] It is preferable that the above-mentioned correct answer post-processing module (202) receives the candidate data signal (Ddfe[i]) and outputs the final output signal (Dout[i]).

[0079] It is preferable that the above correct answer post-processing module (202) receives the candidate data signal (Ddfe[i]) and the correct answer selection signal (Abefo[i]) and outputs the final output signal (Dout[i]).

[0080] Here, Abefo is {Abefo[1], … , Abefo[n]}, Abefo[i] is {Abefo[i][0], … , Abefo[i][m-1]}, 1 ≤ i ≤ n.

[0081]

[0082] As described above, the present invention has been described with specific details such as specific components and limited example drawings, but these are provided only to help a more general understanding of the present invention, and the present invention is not limited to the above-described embodiment, and those skilled in the art to which the present invention pertains can make various modifications and variations from this description.

[0083] Therefore, the idea of ​​the present invention should not be limited to the described embodiments, and all things that are equivalent or equivalent to the scope of the patent claims as well as the scope of the patent claims are considered to fall within the scope of the idea of ​​the present invention.

[0084]

[0085] [Explanation of symbols]

[0086] 1000: Transceiver

[0087] 100: Loop segment module

[0088] 100-1, …, 100-8: Loop segments

[0089] 101: Correct Answer Candidate Calculation Module

[0090] 102: Start Candidate Evaluation Module

[0091] 200: Loop Break Selection Module

[0092] 201: Correct Answer Preprocessing Module

[0093] 202: Correct Answer Post-processing Module

Claims

1. A loop segment module including 1 to n loop segments, receiving a digital signal (Yffe) and generating a candidate data signal (Dffe) and a correct candidate selection signal (Affe) at the current time step; A buffer that stores a candidate data signal (Dffe) and a correct candidate selection signal (Affe) at the current time step and provides a candidate data signal (Ddfe) and a correct candidate selection signal (Adfe) at a time step one step prior to the current time step; and A loop break select module that receives the candidate data signal (Ddfe) and the correct candidate selection signal (Adfe) and outputs a final output signal (Dout); Including, but not limited to, The above loop break selection module A loop break decision feedback equalizer that selects some of the candidate data signals (Ddfe) based on the above correct answer candidate selection signal (Adfe) and outputs the final output signal (Dout). (Here, Yffe is {Yffe[1], …, Yffe[n]}, Yffe[i] is {Yffe[i][0], … , Yffe[i][m-1]}, 1 ≤ i ≤ n, Affe is {Affe[1], … , Affe[n]}, Affe[i] is {Affe[i][0], … , Affe[i][3]}, 1 ≤ i ≤ n, Dffe is {Dffe[1], … , Dffe[n]}, Dffe[i] is {Dffe[i][1], … , Dffe[i][4]}, Dffe[i][j] is {Dffe[i][j][0], … , Dffe[i][j][m-1]}, 1 ≤ i ≤ n, 1 ≤ j ≤ 4, Ddfe is {Ddfe[1], … , Ddfe[n]}, Ddfe[i] is {Ddfe[i][1], … , Ddfe[i][4]}, Ddfe[i][j][ is {Ddfe[i][j][0], … , Ddfe[i][j][7]}, 1 ≤ i ≤ n, 1 ≤ j ≤ 4, Adfe is {Adfe[1], … , Adfe[n]}, Adfe[i] is {Adfe[i][0], … , Adfe[i][3]}, Dout is {Dout[1], … , Dout[n]}, Dout[i] is {Dout[i][0], …, Dout[i][7]}, where 1 ≤ i ≤ n.) 2. In paragraph 1, The i loop segment included in the above loop segment module is Includes a correct answer candidate calculation module and a starting candidate calculation module, The above correct answer candidate calculation module By utilizing loop unrolling, the digital signal (Yffe[i][0]) is input and the correct answer candidate selection signal (Affe[i]) at the corresponding current time step is output. The above starting candidate calculation module A loop-breaking decision feedback equalizer that utilizes loop unrolling to input the digital signal ({Yffe[i][1], …, Yffe[i][m-1]}) and output a candidate data signal (Dffe[i]) at the corresponding current time step.

3. In paragraph 2, The above correct answer candidate calculation module A loop break decision feedback equalizer that receives the above digital signal (Yffe[i][0]) and the candidate data signal (Dffe[n]) output by the nth loop segment, and outputs a correct candidate selection signal (Affe[i]) at the corresponding current time step.

4. In paragraph 2, The above starting candidate calculation module A loop break decision feedback equalizer that receives the above digital signal (Yffe[i][1]) and a preset constant value as input and outputs a candidate data signal (Dffe[i]) at the corresponding current time step.

5. In paragraph 4, The above starting candidate calculation module A loop-break decision feedback equalizer that receives the above digital signal ({Yffe[i][2], …, Yffe[i][m-1]}) and candidate data signal ({Dffe[1], …, Dffe[m-1]}) and outputs the candidate data signal (Dffe[i]) at the corresponding current time step.

6. In paragraph 1, The above loop break selection module Includes a correct answer preprocessing module and a correct answer postprocessing module, The above correct answer preprocessing module Receive the above correct answer candidate selection signal (Adfe[i]) as input, and output the correct answer selection signal (Abefo[i]) at the corresponding current time step, The above correct answer post-processing module A loop-break decision feedback equalizer that receives the candidate data signal (Ddfe[i]) as input and outputs a final output signal (Dout[i]). (Here, Abefo is {Abefo[1], …, Abefo[n]}, Abefo[i] is {Abefo[i][0], … , Abefo[i][m-1]}, 1 ≤ i ≤ n.) 7. In paragraph 6, The above correct answer preprocessing module A loop-break decision feedback equalizer that receives the correct answer candidate selection signal (Adfe[i]) and the correct answer selection signal (Abefo[i-1]) at a time step one step prior to the current time step, and outputs the correct answer selection signal (Abefo[i]) at the current time step.

8. In paragraph 7, The above correct answer post-processing module A loop-break decision feedback equalizer that receives the candidate data signal (Ddfe[i]) and the correct answer selection signal (Abefo[i]) as input and outputs a final output signal (Dout[i]).

9. In paragraph 6, The above loop break selection module A buffer for storing a candidate data signal (Ddfe[i]) at the current time step; A loop break decision feedback equalizer further comprising:

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