Latch circuit with reduced propagation delay
The latch circuit in data transceivers reduces propagation delay by adjusting the baseline voltage with an offset voltage, enhancing data frequency and efficiency in memory devices.
WO2025198663A1 Publication Date: 2025-09-25MICRON TECHNOLOGY INC
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Patent Information
- Application Number
- PCT/US2024/056742
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-10-28
- Filing Date
- 2024-11-20
- Publication Date
- 2025-09-25
AI Technical Summary
Technical Problem
Data transceivers in memory devices suffer from significant propagation delays, limiting data frequency and efficiency.
Method used
A latch circuit with a decision feedback equalizer (DFE) that reduces propagation delay by adjusting the baseline voltage using an offset voltage based on previously received data bits, allowing for reduced sampling times and operation cycles.
Benefits of technology
The latch circuit achieves reduced propagation delay, enabling higher data frequencies and lower power consumption while minimizing inter-symbol interference and distortion.
✦ Generated by Eureka AI based on patent content.
Abstract
This disclosure is directed to a latch circuit (74) of a decision feedback equalizer (DFE) (72). The latch circuit (74) may sample (e.g., clock-in) each input data bit during a respective sampling time of each latch circuit (74) operation cycle after a reduced propagation delay compared to other latch circuits (74). The latch circuit (74) may have a reset time and a tracking time before each sampling time that may reduce the propagation delay of each data bit being received during the sampling time. During the track time, the latch circuit (74) may combine (e.g., add, subtract) an offset voltage, generated based on based on one or more previously received data bits and / or characteristics of the latch circuit (74), with a baseline voltage of the latch circuit (74). The latch circuit (74) may sense a logic level of each data bit being received during the sampling time based on detecting changes to the baseline voltage combined with the offset voltage.
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