Systems and methods for semiconductor device integration

Abstract

Semiconductor devices and methods of manufacturing the semiconductor devices are provided. A wafter having a plurality of devices, such as die, and scribe streets between the devices is obtained. Through-wafer vias are fabricated in at least one scribe streets, and dicing is performed on the wafer along the scribe streets to form the semiconductor devices. One or more redistribution layers may be provided on top and / or bottom surfaces of the wafer.

Description

SYSTEMS AND METHODS FOR SEMICONDUCTOR DEVICE INTEGRATIONTECHNICAL FIELD

[0001] This disclosure relates to integrating semiconductor devices, and in particular, designing and assembling components for vertical integration.BACKGROUND

[0002] The electronics industry is entering a new era of integration. It is moving from designing electronic systems using hundreds of independent components, both active and passive, to using system components. These systems may contain many, if not all, of those components in one packaged device. The result of system level integration, also known as Heterogeneous Integration (HI), is the ability to reduce the size of the system. One type of integrated device is the System in Package or “SiP” device, an example of which is illustrated in FIG. 1. Additional examples are provided in U.S. Patent No. 11,171,126 to Murtuza et al. and US Patent No. 11,610,844 to Frantz et al.

[0003] However, certain challenges exist. For instance, existing SiP and other HI devices, among others, fail to fully utilize the vertical (e.g., the Z-axis or third dimension beyond the X- and Y- axis) dimension. Thus, there remains a need for improved systems and methods for semiconductor device integration to efficiently utilize the available space of a given system.SUMMARY

[0004] According to embodiments, a method of manufacturing a semiconductor device is provided that comprises: obtaining a wafter having a plurality of die (or devices) and scribe streets between the die (or devices); fabricating through-wafer vias in at least one scribe street; and dicing (e.g., sawing, singulation, etc.) the wafer along the scribe streets. In certain aspects, the dicing (or sawing, singulating, etc.) is performed through a plurality of the through-wafer vias to form a plurality of partial vias, and / or the dicing (or sawing, singulating, etc.) is performed between two adjacent through- wafer vias in a scribe street. In some embodiments, the method further comprises one or more of forming a first redistribution layer (RDL) on a top surface of the wafer; and / or forming a second redistribution layer (RDL) on a bottom surface of the wafer.

[0005] According to some embodiments, a semiconductor device is provided that comprises: a substrate (e.g., wafer), where a plurality of devices (e.g., die) are formed in / on the substrate; a plurality of scribe streets are provided between the plurality of devices (e.g., between adjacent die); and a plurality of vias that extend through the substrate, where the plurality of vias are locatedin the scribe streets. In some embodiments, the substrate is a silicon wafer and the vias are through- silicon-vias (TSV s). The device may also include a first redistribution layer (RDL) on a top surface of the substrate; and / or a second redistribution layer (RDL) on a bottom surface of the substrate.

[0006] According to some embodiments, a semiconductor device is provided that comprises: a substrate, where an active region of the device is provided on an upper surface of the substrate; and at least one via extending through the substrate, where the via is located outside of the active region. In embodiments, the at least via is located on an outer edge of the device. The semiconductor devices may be used in a system. For instance, according to embodiments, a system comprises a first semiconductor device and a second semiconductor device, where the first device is stacked on the second device. The system may also include a base substrate (e.g., where the first and second devices are stacked on the base substrate). In embodiments, the first and second die / device are interconnected using their respective vias; and / or the first and second die / device are interconnected using a bottom RDL of the first device and a top RDL of the second device.

[0007] According to embodiments, a method is provided comprising: mounting a first semiconductor device onto a base substrate; and stacking a second semiconductor device onto the first device.

[0008] According to embodiments, a connection device comprises: an array of conductive pins; and a mounting header; where the conductive pins are all attached to the mounting header. The pins may be removably attached to the header.

[0009] According to embodiments, a device (e.g., module, component, etc.) comprises: a substrate (e.g., with a plurality of vias and internal traces); at least one die mounted on a first surface of the substrate; and at least one connection element at an outer edge of the substrate, where the connection element is one or more of a pin, spacer, and / or ball. The device may also include a second die mounted on a second, opposite surface of the substrate. The devices may be stacked to form a system and interconnected using the connection elements.

[0010] According to embodiments, a semiconductor device (e.g., a SiP) comprises: a plurality of active and passive components, a base substrate comprising a plurality of layers with etched conductive paths and a plurality of vias associated therewith for making operative interconnections between the plurality of components, and a plurality of areas on the surface of the substrate for mounting components, where each of the plurality of areas on the surface of the substrate for mounting components is configured / arranged for mounting components of the plurality ofcomponents, a plurality of interposer substrates aligned in a vertical manner / arrangement where each interposer substrate comprises a plurality of layers with etched conductive paths and a plurality of vias associated therewith for making operative interconnections between components mounted thereon, a plurality of areas on the surface of each of the interposer substrate, for mounting components, and a plurality of input / output pads at one or more edges of each one of the plurality of interposer substrates for interconnections, and / or a plurality of power, ground, and input / output connectors interconnecting with the input / output pads at the edges of each interposer substrate of the plurality of interposer substrates to interconnect with each other and with the base substrate of the SiP, where the substrates and components are optionally encapsulated, or a lid is added, to cover and protect the plurality of components mounted on the substrates.

[0011] According to embodiments, a packaged System in a Package (SiP), comprises: a SiP substrate comprising multiple layers with etched conductive paths, multiple vias associated therewith for making interconnections, conductive pads for additional interconnections, and exterior connectors, a plurality of components mounted on the substrate and operatively interconnected using the vias and etched conductive paths, and an area of the substrate suitable for operatively connecting a riser structure having a plurality of interconnecting pins for making a plurality of connections to the SiP substrate, where the riser structure comprises a plurality of structural conductive paths for operative interconnections between a series of stacked substrates operatively connected to the structural conductive paths, the SiP substrate and the exterior connectors located on the exterior surface of the SiP package.

[0012] According to embodiments, a Device Stack Module (DSM) comprises: one or more substrates each populated with multiple components, electrically interconnected using traces and vias on and in each of the substrates and on one or more of its surfaces, a stacking structure to rigidly attach mechanically and operatively interconnect electrically the substrates together at the edge of each substrate, the one or more substrates are electrically interconnected using electrical conductors in the stacking structure, the stacking structure capable of electrically and mechanically connecting to a heterogeneous integrating device’s (System in Package’s) substrate and, optionally, top surface. Other DSMs, or modifications of the foregoing, may be provided in some embodiments.

[0013] According to embodiments, a SiP device comprises: at least two substrates each populated with components operationally interconnected and mounted thereon, where the components oneach of the substrates are operationally interconnected with traces and vias associated with each substrate (each respective substrate), electrical interconnectors operationally connected with traces on an external surface of a substrate of the at least two substrates and arranged to space / arrange the at least two substrates in a horizontally layered manner and such that components on one substrate may be operationally interconnected by the electrical interconnectors to components of a different substrate, a SiP substrate for mounting the spaced apart at least two substrates and their associated individual components in an operational manner with components on the SiP substrate using the electrical interconnectors, and mounting external connectors on an exterior surface of the SiP substrate.

[0014] These and other features of the disclosure will become apparent to those skilled in the art from the following detailed description of the disclosure, taken together with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 illustrates a System in Package (“SiP”) device.

[0016] FIGs. 2A-2C illustrate a system according to some embodiments, where FIG. 2A is a top plan view, FIG. 2B is a schematic side elevation view, and FIG. 2C is top partial 3D plan view.

[0017] FIG. 3 illustrates an array of conductive pins according to some embodiments.

[0018] FIGs. 4A and 4B illustrate devices according to some embodiments.

[0019] FIG. 5 illustrates devices according to some embodiments.

[0020] FIGs. 6 A and 6B illustrate systems according to some embodiments.

[0021] FIGs. 7A and 7B illustrate systems according to some embodiments.

[0022] FIGs. 8A, 8B, 8C, 8D and 8E depict different views of devices according to some embodiments.

[0023] FIGs. 9A, 9B, 9C, and 9D illustrate systems according to some embodiments.

[0024] FIG. 10 is a flow chart of a process according to some embodiments.

[0025] FIGs. 11A, 11B, and 11C illustrate systems according to some embodiments.

[0026] FIGs. 12A-12H and 12J-12M depict steps of a process according to some embodiments.

[0027] FIG. 13 is a flow chart of a process according to some embodiments.

[0028] FIG 14 illustrates a wafer according to some embodiments.

[0029] FIGs. 15A and 15B illustrate a wafer according to some embodiments.

[0030] FIGs. 16A-16F depict steps of a process according to some embodiments.

[0031] FIGs. 17A-17F depict steps of a process according to some embodiments.

[0032] FIGs. 18A and 18B illustrate devices according to some embodiments.

[0033] FIGs. 19A and 19B illustrate devices according to some embodiments.

[0034] FIGs. 20A, 20B, and 20C illustrate stacked arrangements according to some embodiments.

[0035] FIGs. 21A-21H illustrate systems and devices according to some embodiments.

[0036] FIG. 22 and 23 are flow charts of processes according to some embodiments.

[0037] For one or more of the figures provided in this disclosure, the z-axis or vertical axis and associated relative dimensions and sizes of the other axes are not necessarily to scale. For some figures, dimensions may be exaggerated for ease of depiction purposes.DETAILED DESCRIPTION

[0038] Heterogeneous Integration (HI) enables integration of devices, with diverse fabrication technologies, such as digital, analog, optical, and memory processes. Other devices may also be integrated, including active and / or passive devices and components (e.g., discrete circuits, sensors, power management devices, and various non-silicon devices). Some examples of non-silicon devices are mechanical, biologic, organic, fluid, etc. components, as well as germanium and gallium nitride (GaN). In some embodiments, even HI devices, such as chiplets or SiPs for instance, may be integrated as a component in another HI device. Additionally, HI devices may include mechanical devices. One example is mechanical energy source using vibration or heat to create energy (e.g. a self -winding watch concept). HI devices are also attractive because they may allow for miniaturization of a complete system in a single package. In some cases, use of HI can reduce an entire microelectronic system on a printed circuit board (which may be tens of square cm in size) to a single package of a square cm or less. Using HI technology is Systems on Module (SOM) devices, System in Package (“SiP”) devices, Multi-Chip Module (MCM) devices, and chiplets can provide components or systems that are otherwise impossible or impractical to integrate in a single silicon circuit such as an ASIC or SoC.

[0039] One benefit of a SiP is that it can allow for building prototypes to test a system design or manufacturing low volume devices prior to further integration of some of the components into a single monolithic silicon circuit, where it is possible to later employ SoC technology to produce a SoC as a standalone device or a reduced size component in a SiP. Additionally, HI device solutions can be used to combine multiple functional components and devices in a single package. These devices may be either entirely customized for a specific function or purpose, or they may begeneral -purpose building blocks (e.g., smart blocks) around which other specific components may be added for a specific application or end use. However, existing SiP and other HI devices fail to fully utilize the vertical (Z-axis or third dimension beyond the X- and Y-axis) dimension to reduce the footprint of the system. According to embodiments, the ability to reduce the physical size of a system by optimizing its volume rather than just its area (footprint) becomes an additional tool available as pail of the toolset of the system designer. In certain aspects, using Z-axis Integration (ZAI) by stacking subsystems trades off the area of the HI or SiP device with its thickness. The footprint of the HI or SiP device may be reduced as its thickness (Z-dimension) is increased.

[0040] One or more embodiments provide apparatuses and methods for stacking multiple silicon die having Through Silicon Vias (TSVs) on the edges of each die, combined with Re-Distribution Layers (RDLs) on the top and / or bottom surfaces of each die. That is, a bare die is converted from a single surface contact device to a two surface contact device without disturbing the components in the active area that makes up the die. While silicon and TSVs are used as an example, other material systems and vias may be use in embodiments. Additionally, apparatuses and methods for stacking semiconductor components are provided that include stacks of substrates (e.g., mezzanine substrates), each of which may be populated with active and passive components that may be employed to implement one or more subsystems. In both instances, each individual layer of the stack may be interconnected with each other and / or with a substrate of a HI or SiP device, allowing more subsystems to be used in the integration without increasing the area (footprint) of the device. The integration implementations described herein can have numerous applications.

[0041] For example, many microprocessors, microcomputers, and programmable or nonprogrammable logic devices offer an exceptionally flexible solution that may be customized through programming for a desired system or end use. In most systems, these processors and devices need a set of support components to build a complete system. Such support components include, for example, DDR and FLASH memories, power supplies, PHY interfaces, wireless modules, security devices, other active devices, and potentially, hundreds of passive devices and components. These support components may be referred to as “system components” or “Peripheral Functional Components” (PFCs). Today systems are typically designed stalling with discrete components that are used to implement a desired circuit, one subsystem at a time. This process is unique for each design, which takes additional design resources, extending the development timeline, and increasing development risk.

[0042] Referring now to FIG. 1 , a side view of a heterogeneous integrated device, such as a System in Package (SiP), is illustrated. The SiP of FIG. 1 can include, for instance, a base substrate 201 populated with various active components 207 and passive components 208, which are electrically interconnected using traces 211 and vias 214 in and on the substrate 201. The substrate 201 may include multiple spaced apart conductive layers that may be etched or otherwise created to provide a pattern of conductive traces or “circuitizations” within each conductive layer, which are insulated from the other conductive layers and with conductive traces on the exterior surfaces of the substrate. In some instances, these patterns may be used to operationally interconnect different components mounted on the substrate, for instance, using vias to make electrical connections between the conductive layers. External connectors 204, such as a ball grid array (BGA) or other features, are used in this embodiment and are mechanically and electrically attached to the base substrate to allow external connections to other components in a system (not shown). In this example, the device is encapsulated with either mold compound 225 or covered with a lid (not shown). In some embodiments, the device of FIG. 1 may be a high-performance SiP using a high- performance processor that is attached to substrate 201, and at least one associated memory device. Here, the processor and memory are electrically interconnected with traces and vias on and internal to substrate 201. As depicted in FIG. 1, the high-performance module may also include other components, for example, a power management component, a voltage control device, a QSPI memory component, a plurality of passive devices (resistors, capacitors, inductors, etc.), active devices (transistors, diodes, etc.), and I / O components (wired and wireless communication devices, analog input and output devices). Examples of high-performance devices could include those in which the state of the art is extended or exceeded in order to meet the minimal requirements of the system. In addition to the attached components, a heat sink may be attached to the processor. Finally, in this example, the SiP is encapsulated 225 and interconnection balls 204 in the form of a ball grid array (BGA) are attached to the bottom side of substrate 201. A lid may also be used. In FIG. 1, substrate 201 has a plurality of separated, internal conductive layers that are etched into traces 211 and vias 214, for instance, to make the required operative interconnections for the various components of the SiP.

[0043] Although FIG. 1 illustrates a processor or microprocessor, other high-speed components, that may or may not include a processor, may also be employed in these configurations. Such highspeed components may be digital logic devices, analog circuits or mixed signal devices. Inaddition, high speed interconnections between a high-speed memory device and other high-speed components may be made through the substrate using a variety of bus bit widths. However, the layout of the various components of the prior ail SiP or other HI device typically only takes into consideration the x and y dimensions of the underlying SiP substate. Thus, there is a need for a SiP or other HI device module or subsystem that may integrate at least a substantial portion or all of the “system components” named above, which when mated with appropriate standalone microprocessors and programmable logic devices, avoids the need for a custom design for the overall system by using a stacked substrate module (SSM) as a starting point for the system design.

[0044] According to embodiments, stacked substrate modules (SSM) or stacked substate components (SSC) are provided. These modules / components may be used in various types of system or device designs, including for example SiPs or other HI devices.

[0045] Aspects of the disclosure provide one or more minimally viable stacked substrate modules having the potential for added customizations for specific purposes and end uses. Such a substrate module may be combined with another HI device and used for special applications, such as handheld devices requiring additional miniaturization, or a harsh environment requiring additional ruggedness. From a user’ s perspective, stacked substrate modules according to some embodiments can: reduce development times, reduce development risks, and lower overall costs for system development, debug, and deployment. Another benefit is extending the market for system components such as processor / memory component families, analog, digital, optical, and mixed- signal accelerator components. Additional benefits may also be a result of the use of such a stacked substrate modules (SSMs) that are not listed above. Examples of components which may be individually, or in combination, integrated in such a SSM may, for example, include DRAMs (e.g. DDR3, DDR4 or LPDDR4), eMMC flash memory, QSPI flash memory, Ethernet PHY, power management IC (PMIC) and LDO regulator, passive components, conduits for pass-through signals, TPM, wireless module, and other special purpose components.

[0046] For instance, a HI device (e.g., SiP) integration using the 3rd dimension is accomplished by creating stacking modules or components. Some examples are through-interposer vias (TIVs) in addition to through silicon vias (TSVs) for an individual substrate. Several different types of stacking embodiments using TIV are provided herein and include: (1) using a pin array as described with respect to FIGs. 2-7 ; (2) using ball attachments as described with respect to FIGs. 8, 11 and 12; and (3) using substrate separators, as described with respect to FIG. 9. However,these embodiments are just examples and other similar embodiments may be employed. Beyond these three stacking embodiments using TIVs, a fourth embodiment using a combination of through silicon vias (TSVs) and redistribution layers (RDLs) with die are discussed with reference to FIGs. 14-22. Many of the embodiments disclosed herein may use, for example, memory devices stacked on substrates that are appropriately and operationally electrically connected, using for example, pins, balls, or separators. The resulting stacked substrates may also be used as a component in the SiP or other HI device to which it is to be attached. According to embodiments, in each of the TIV and TSV / RDL embodiments, multiple active and passive components may also be attached on one or both sides of any one or all the substrates / die employed in a stack. Each substrate / die may have different internal and surface interconnect arrangements using internal (in the substrate) or surface electrical traces and vias or external (in the stacking structure; interconnectors.

[0047] FIGs. 2A, 2B, and 2C depict different views of an example of an SSC or SSM employing multiple substrates. FIG. 2A is a top view, FIG. 2B is a side view, and FIG. 2C is top partial 3D view of one of the substrates in the SSC / SSM. This first embodiment for a stacked system uses pins as the TIVs to interconnect the two or more stacked substrates (which can be considered interposers).

[0048] According to embodiments, FIGs. 2A-2C depict examples of a stacked substrate arrangement of the present disclosure employing a plurality of substrates for use in a HI device, like a System in Package (SiP). While the examples use packaged systems, they may be applied to other systems as well. In certain aspects, the present disclosure provides methods and systems for stacking substrates populated with operatively interconnected components, which may be packaged or bare die, to take advantage of the third dimension in semiconductor products. More particularly, the stacking system of the present disclosure may employ multiple physical mechanisms for interconnecting and aligning the substrates used for stacking. Such mechanisms include, for example, through interposer vias (TIVs), in addition to through silicon vias (TSVs). These mechanisms provide and assure both physical alignment of stacked substrates and allow for the desired interconnections of components on different substrates in the stack, and interconnections with other internal and external components.

[0049] Referring initially to FIG. 2B, there is provided a side view of a stacked substrate system / module / device of the present disclosure employing a plurality of stack substrates 202 thatare electrically and mechanically attached to a device base substrate 201. In this embodiment, there arc three stack substrates 202, each depicted with two die 203 attached, one to the top surface and one to the bottom surface. Dies 203 are electrically connected to stack pins 212 of stack 221 (e.g., interposer stack), for instance, as described with respect to FIGs. 4-7. In embodiments, other components, such as active components 207 and passive devices 208 may be provided and attached to the device base substrate 201. Finally, external connectors 204 are attached to the bottom side of the device base substrate 201. FIG. 2B depicts a HI device (like a SiP) 220 that has a base substate 201 with active components 207 and passive components 208 mounted thereon and operationally interconnected using the electrical traces 111 and vias 114 provided by the base substrate, similar to the example of FIG. 1. These active and passive devices may be, for example, processors (analog, digital or mixed signal), memories (analog or digital), power management, communications (wired, wireless, optical), sensors, and interfaces (analog, digital, optical). For ease of depiction and description purposes, other components are not illustrated for each of the substrates 202, although other components both active and passive, as noted above, may also be mounted on each of the substrates 202 and operationally interconnected using the electrical traces and vias provided by each such substrate. Similarly, although each die 203 is depicted as extending the length of the substrate 202, the top and bottom surface of each substate 202 may be populated with multiple die, packaged component(s), and various active and passive components (see FIG. 4B). The number, combination of and interconnection of such components depends on the functionality to be provided by a specific substrate and its interconnections with other components on other substrates in the stack or on the SiP base substrate, or optionally other external components. Each substrate may optionally contain multiple components, such as for example, as depicted in FIG. 1, but on both sides of the substrates employed in a stack. In some embodiments, a HI device 220 has a base substate 201 with external connectors 204 and is encapsulated with an optional encapsulant 225. External connectors 209 are also depicted on one of the active components; other such connectors may be present on any of the other components mounted on base substrate 201 in the SiP, or any of the substrates 202 employed in the stack 221. And as shown in FIG. 2B, stack pins 212 may also be extended to the top surface 226 of the device’s encapsulant 225 for additional external connections.

[0050] Referring now to FIG. 2A, a simplified, partially transparent, top view of the top of the stack of substrates (each with attached die) as depicted in FIG. 2B is provided. In embodiments,the stack is included in a system in package (SiP) and attached to SiP base substrate 201 for form a system 200. Substrate stack 221 may comprise multiple substrates 202, each populated with die 203 on one or two sides of stack substrate 202. Although in this example only one die is attached to each side of the stack substrate in the stack, the variability of configurations of components on each substrate 202 may include, for example, die 203 populated on either one side or both sides (depicted in this example) of stack substrate 202, multiple die populated on one or both sides of the substrate (see FIG. 4B), combinations of die, packaged devices, passive devices, optical devices, and thermal management components. Although not shown in FIG. 2A, multiple active 207 and passive components 208 may also be attached to each exterior surface of stack substrate 202. As depicted in FIG. 2 A and 2C, the stack pins 212 and their associated openings 222 are aligned along opposite edges of a stack substrate 202.

[0051] FIG. 2C depicts a simplified partially three-dimensional see-through top view of a representative example of one of the populated substrates of FIG. 2B. This may be, according to embodiments, a populated interposer or sub-assembly 240. Again, for ease of depiction purposes, in this depiction a single die 203 is attached to the substrate 202 (only the top of die 203 is visible in this Figure), but additional die may be used. In FIG. 2C the die 203 is attached to the circuitization of substrate 202 using flip-chip methodology (bumps not seen) and is electrically connected via substrate 202 to the pins 212. According to embodiments, pins 212 are inserted in the holes 222 in the substrate 202 and connected by the traces 211 connected to the holes 222 and landing pads of the die (not shown). Die 203 may be, for example, but not limited to, memory devices, processors, communications devices, sensors, or optical devices. Again, for simplicity only one die 203 is depicted on the top surface in FIG. 2C, but multiple die, packaged devices and passive or active components may be attached in other embodiments. Further each populated substrate in the stack may have a different set of components. Further, FIG. 2C depicts only one row of via holes 222 on each side of substrate 202, but multiple such rows may be included to properly interconnect all the components in the stack depicted in FIG. 2B. The via holes 222 in a substrate 202 are where the structural and conductive stack pins 212 are mechanically and electrically connected to stacked substrates, for optionally interconnecting the substrates in a stack with each other, some external circuitry and with the base substrate of a SiP (when present).

[0052] FIG. 3 depicts a connection structure 300 comprising an array of conductive pins 212, all attached to a mounting header 301, according to some embodiments. As described with respect toFIG. 7B, the mounting header 301 can he removed to allow each stack pin 212 to be electrically disconnected from the other pins in the array. In more detail, FIG. 3 depicts a scries of conductive pins 212 that are fixedly but removably attached to a mounting base 301. The pins 212 are arranged to match and align with the openings 222 in substrates 202 that are stacked; the openings 222 may be oriented as depicted in FIG. 2C. During assembly of the stacked substrates 202, the mounting base 301 and associated pins 212 may be inverted and the required number of populated substrates 202 properly stacked and mechanically and electrically attached to the pins 212. Then, stacked assembly 221 may be inverted and attached to a corresponding set of conductive pads on the surface of a HI device or SiP base substrate, or a set of exterior conductors may be attached to form a completed stacked component. If a completed stacked component is all that is desired, this component may be encapsulated and then the portion of the encapsulation covering the mounting base 301 may be removed by grinding (or any other suitable removal procedure) to expose the individual pins and allow for the addition of the exterior mounting pads to the exposed pins 212. In this manner pins 212 can be maintained in the correct orientation to allow for the stacked substrates to be assembled thereon. The appropriate spacing between the substrates is discussed later herein in more detail, with regard to later figures. Examples include using spacers or separators.

[0053] FIG. 4A depicts an enlarged side view of a module / component 400 comprising a populated substrate 202 according to embodiment, similar to those depicted in FIG. 2B. Again, for ease of depiction purposes, FIG. 4A illustrates two die 203 a / b that are electrically attached to the substrate 202 by attaching the conductive pads 213 on the die 203a / b to traces 211 and vias 214 in and on the substrate 202 through conductive attachment pads 210 on the exterior surface of the substrate 202. An individual surface trace 211 connected to an attachment pad 210 may be directly connected to a respective opening in the substrate 222. In FIG. 4A there are two die 203a / b attached to the interposer substrate 202. In other embodiments, such as depicted in FIG. 4B there may be multiple die attached to one or both sides of the populated substrate 202. In addition, other components such as packaged components, passive devices, optical and non-silicon devices may also be attached to “populate” a stack substrate 202. In embodiments, FIG. 4B depicts an enlarged side view of another populated substrate 202, like those depicted in FIG. 2B, but with multiple die and other components thereon. In this embodiment - and others - the substrate 202 may be considered an interposer. FIG. 4B illustrates three die 403a / b / c that are electrically attached tosubstrate 202 by attaching the pads 213 on the die 403a / b / c to traces 21 la / b and vias 214 in and on the substrate 202 through conductive attachment pads 210 on the exterior of the substrate 202. According to some embodiments, a surface trace may be directly connected to a respective hole 222, or the surface trace may be routed to traces and vias inside the substrate 202 that make interconnections with other components on the substrate exterior, and then come back to a surface trace that is attached to the connecting and structural holes 222 in the substrate 202. Although not shown, other components such as, for example, mechanical and optical devices, may also be included. In this example, the exterior traces 211b are attached to the connecting holes 222 in substrate 202 through which the connection pins 212 are electrically and mechanically attached. Each populated substrate 202 may be a portion of an overall circuit or a separate circuit in embodiments.

[0054] Referring now to FIG. 5, a side view of an end portion of substrate stack 221, such as that shown in FIG. 2B, is provided. In this example, the stack is mounted on a HI device or SiP base substrate 201 to form a system or sub-module 500. FIG. 5 illustrates the physical and electrical interconnections of pins 212 with two populated stacked substrates 202a / b. The two depicted stack substrates 202 a / b each have two die, 203 a / b and 203 c / d respectively, attached via conductive pads 210 a / b / c / d of die 203 a / b / c / d to connective pads and traces on exterior surfaces of respective substrates. The two stack substrates are electrically connected to stack pins 212 through one or more traces 211 a / b / c / d, as previously depicted in FIG. 2B. In embodiments, one end 227 of stack pins 212 may extend up to and through the top 226 of a device package for optional external connections, or optionally mounting of and connection to other components.

[0055] According to embodiments, the spacing between substrates 202 can be controlled. For instance, the size of the pin may be adjusted to hold substrates (e.g., with different size holes) in a given location. For instance, in embodiments, the size of the pin is graduated (i.e. gets larger at the top / bottom) and the holes in substrates 2021, 202b vary to determine the placement of the substrate along the pin. In other embodiments, non -conductive spacers could be used.

[0056] Continuing to refer to FIG. 5, internal to the stack substrates 202 a / b there may be traces and vias needed to properly connect the die 203 a / b / c / d to other components on that same substrate, or using the stack pins 212 and traces 211 associated with stack substrates 202 a / b to connect to components on a different stack substrate via stack pins 212 and traces 211 a / b / c / d. Device base substrate 201 illustrates the internal traces and vias needed to properly and operationally connectcomponents mounted thereon and may include surface traces as well; stack substrates may also include such surface traces, and internal traces and vias, for component interconnections. By way of example, active device 207 is mounted on the substrate 201 and may interconnect with other components mounted on the device substrate 201 (not depicted), as well as components mounted on substrates 202 a / b. Again, for ease of depiction purposes, FIG. 5 depicts only two die (e.g., 203 a / b on substrate 202 a, and 203 c / d on substrate 202 b) attached to populated stacked substrates 202 a / b, although there may be multiple other die, and active and passive devices attached to each substrate, as earlier depicted in FIG. 4B. These active and passive devices may be, for example, processors (analog, digital or mixed signal), memories (analog or digital), power management devices, communications devices (wired, wireless, optical), sensors, and interface controllers (analog, digital, optical); such devices may be packaged or bare die. Further, conductive stack pins 212 may be part of an array of conductive pins (see FIG. 3) allowing for power, ground, and I / O signals to be operationally passed between components mounted on multiple different stack substrates, such as stacked substrates 202a / b, the device’s base substrate 201, and the SiP’s top surface 226.

[0057] FIGs. 6A and 6B depict side views of a partially assembled and assembled stack substrate component or module 600 employing a stack of multiple stacked substrates, each of which are populated by various components (not fully depicted for ease of depiction purposes), respectively. According to embodiments, FIG. 6A depicts a side view of the stack and two substrates 202a / b, each with two die attached 203a / b and 203c / d, respectively, and that are electrically and mechanically connected by stack pins 212 detachably attached to a base mount 301. In embodiments, the base mount 301 and associated pins 212 may be inverted to attach the stacked substrates 202a / b both mechanically and electronically to stack pins 212. FIG. 6B depicts a side view of an assembled stack (item 221 in FIG. 2B) employing a stack of multiple stack substrates 202a / b each of which is fully populated by various components and attached to SiP base substrate 201 which is also populated by various components 207 and depicts a portion of the top surface of a SiP package 226. In this view of an embodiment, the ends 227 of the array of stack pins 212 protrude through the top surface 226 of the SiP package. Note that mounting base 301 for stack pins 212 (depicted in FIG. 3) has been removed in FIG. 6B. In a similar manner, although the SiP base substrate 201 is populated by various active components 207, it may also include multiple other components. Although the length of each of the stacked substrates 202 a / b in FIG. 6B is thesame as the length of the base substrate 201 , the length (and width) of each of the stack of substrates in a stack is typically the same, each stack substrate of a stack may be any convenient length (and width) that fits within a SiP package, or any convenient size if the stack is intended to be a standalone device.

[0058] FIGs. 7A and 7B depict, respectively, side views of a HI device (like a SiP) containing the fully assembled stack 300 of substrates mounted in a device 700 / 720 that has been encapsulated by encapsulant 225. The device includes various active components 207, passive components 208 and assembled stack of stack substrates 300 attached to the device substrate 201 along with external connectors 204 on the bottom of the substrate 201. Encapsulant 225 completely covers the mounting base 300 for stack pins 212 in substrate stack 300 in FIG. 7A. Referring to FIG. 7B, the device of FIG. 7A is depicted after the encapsulant 225 has been partially removed to remove the mounting header 301 for the stack pins 212 and expose the stack pins 212 of the assembled substrate stack 300 to the top surface 226 of the package for the SiP. Referring now to FIG. 7A, a side view of a device containing stack 300 of stack substrates that has been encapsulated by encapsulant 225 and attached to device base substrate 201 is provided. The device may include various active components 207, passive components 208 and stack of stack substrates 300 attached to the SiP base substrate 201 along with external connectors 204 on the bottom of the SiP base substrate 201 in some embodiments. Again, as noted earlier, encapsulant 225 completely covers the mounting header 301 for stack pins 212 in substrate stack 300 when used (it may be optional).

[0059] According to some embodiments, in FIG. 7A the header 301 for pins 212, including the stacked substrates, is attached to the base substrate 201 before encapsulant 225 is applied to package the device. Accordingly, the device base substrate 201 has a portion of its upper exterior surface with a selected area reserved for the connections associated with the array of stack pins 212 mounting on and connecting to a set of conductive pads in that reserved surface space. In more detail, stack pins 212 when connected to the conductive pads on the surface of the base substrate 201 form a series of conductive risers on which stacked substrates are physically mounted and electrically interconnected. This array of risers allows for the operational interconnection of components on various stack substrates included in the device and desired for functional operations by the device. The HI device is encapsulated after any remaining components are mounted and connected. Following encapsulation, a portion of encapsulant 225 over base mount 301 is removed by grinding, or any other suitable means, to allow for removal of the base mount 301. Afterremoval of the base mount 301 , the ends of the stack pins 212 may remain exposed for further connections and modified to be suitable for such connections, or the package may be re- encapsulated to cover and protect the exposed ends of the stack pins 212.

[0060] Some embodiments use connection balls in lieu of stack pins 212, including examples shown in FIGs. 8A, 8B, 8C, 8D and 8E. These examples depict alternative embodiments of stacked substrates where the physical, mechanical and electrical interconnects between stacked substrates 202 are BGA type solder balls, rather than mechanical and conductive stack pins 212.

[0061] Referring now to FIG. 8A, a side view of an end portion of a stack substrate system 800 (like the view depicted in FIG. 2B) is shown. The two stack substrates 202a / b each have two die, 203a / b and 203c / d respectively, attached via conductive bumps 210a / b / c / d on die 203a / b / c / d, respectively, and associated traces 211a / b / c / d / e. The two stack substrates are then electrically connected to the balls 312a / b / c through traces 211a / b / c / d / e. Internal to stack substrates 202a / b there may be, although not depicted in this figure, additional traces and vias needed to properly connect the die 203a / b / c / d to the stack substrate 202a / b, and to the balls 312a / b / c. Ball 312a is available on the top surface 226 of the package (note that ball 312a slightly protrudes 227 through the top surface of the package 226), and ball 312c is connected to the device substrate 201. In embodiments, ball 312a is an optional BGA ball, and may not be needed in certain instances. Although in this figure, only two die (e.g., 203a / b) are attached to each stack substrate 202a, there may also be multiple active and passive devices attached to each stack substrate. These active and passive devices may be, for example, processors (analog, digital or mixed signal), memories (analog or digital), power management devices, communications devices (wired, wireless, optical), sensors, and interface devices (analog, digital, optical), and may be bare die or packaged. The conductive balls 312 may be viewed as an array of conductive posts (see FIG. 8E) allowing for power, ground, and I / O signals to be passed between multiple stack substrates, such as 202a / b, the device’ s substrate 201 and the top surface 227, using vias or through vias in the stack substrates.

[0062] FIG. 8B depicts a view of an embodiment of a populated stack substrate module 820. In more detail, two die 203a / b may be electrically attached to stack substrate 202 by attaching the connective pads 213 of the die 203a / b to the traces 211 and vias 214 in and on the stack substrate 202 through conductive attachment balls 210 on the exterior surface of a stack substrate 202. The traces 211 are attached to the connecting conductive balls 312. In FIG. 8B and subsystem 840, there are two die 203a and 203b attached to stack substrate 202. In other embodiments there maybe multiple die attached to each side of the stack substrate 202. In addition, other components such as passives, optical, and non-silicon devices may be attached.

[0063] FIG. 8C depicts a side view of an embodiment of a populated stack substrate subsystem module 840. One die 203b is electrically attached to the stack substrate 202 by attaching the external connector pads 213 of the die 203b to the traces 211 and vias 214 in and on the stack substrate 202b through attachment balls 210 on the surface of the stack substrate. The traces 211 are attached to connective balls 312. In this example, there is one die 203b attached to the bottom surface of stack substrate 202. In other embodiments there may be multiple die attached to each side of stack substrate 202. In addition, other components such as passives, optical, and nonsilicon devices may be attached.

[0064] FIG. 8D depicts a side view of another populated stack substrate module 860. One die 203a is electrically attached to stack substrate 202 by attaching the external connector pads 213 of the die 203a to the traces 211 and vias 214 in and on the stack substrate through attachment balls 210. The traces 211 are attached to balls 312. Again, in other embodiments there may be multiple die attached to each side of the stack substrate 202. In addition, other components such as passives, optical, and non-silicon devices may be attached to either, or both, exterior surfaces of a stack substrate.

[0065] FIG. 8E depicts a side view of an exemplary embodiment of a stack substrate module 880. In this example, the array of balls 312 a / b / c in a stack may be seen. Each ball 312 a / b / c is attached to either the top or bottom surface of a stack substrate; conductive ball 312 a may be attached to the top surface 226 of the SiP 880 (and exposed 227 on the top surface), and conductive ball 312c may be attached to the SiP substrate 201 via a conductive landing pad 21 le on the SiP substrate 201. Although illustrate with multiple balls in each layer, according to embodiments, one or more of the balls may be removed / unnecessary. A benefit of this embodiment is that it may not be necessarily to have connections going all the way up and down the stack. The BGA balls can have different signals moving between layers, and one may not need to fully populate all BGA balls to provide connections between layers.

[0066] According to embodiments, FIGs. 9A, 9B, 9C, and 9D illustrate a stack substrate component / module 900, where physical stack separators and spacers are used to stack the stack substrates physically. The terms separator and spacer may be used interchangeably in some embodiments. In some embodiments, the spacers further electrically connect them together, to thedevice substrate, and optionally to the top surface of the device. In some embodiments, the separator is electrically active (c.g., with a narrow substrate) and a spacer is a passive device.

[0067] FIG. 9A depicts a side view of an end portion of a stack substrate system, like that shown in FIG. 2B, constructed using substrate separators and spacers 412a / b / c. The two stack substrates 202 a / b each have two die, 203a / b and 203c / d respectively, attached via conductive bumps 210 a / b / c / d and traces 211a / b / c / d. The two stack substrates are then electrically connected to the separators and spacers 412 through traces 211 a / b / c / d. Internal to the stack substrates 202 a / b there may be additional traces and vias (not shown in this figure) needed to properly connect the die 213 a / b / c / d to the stack substrate 202 a / b to the separators 412. Although only two die (e.g., 203 a / b) are attached to each stack substrate (e.g., 202a), there may be multiple active and passive devices attached to each stack substrate, as noted earlier in FIG.4B. These active and passive devices may be, for example, processors (analog, digital or mixed signal), memories (analog or digital), power management, communications (wired, wireless, optical), sensors, and interfaces (analog, digital, optical). In FIG. 9A, the separators I spaces are all the same size; however, in embodiments they can have different heights between layers, so that thermal vs density tradeoffs can be addressed.

[0068] According to some embodiments, the separators and spacers 412a / b / c are a group of separators allowing for power, ground, and I / O signals to be passed between any of multiple stack substrates, such as 202 a / b, while maintaining physical and electrical integrity of the stack substrate system. Further, a separator and spacer 412a can be connected through 227 to the top surface 226 of SiP package, while the bottom separator and spacer 412c is connected to device’s substrate 201 via a trace 21 le. Further, although not shown, additional separators and spacers may be placed between the attached components such as between devices 203b and 203c. These additional separators and spacers may be used to, for instance, electrically isolate the components on adjacent stack substrates, as part of the structure, or as heat sinks.

[0069] FIG. 9B depicts one embodiment of a populated stack substrate for use in a stack substrate module or component 920. In this depiction two die 203a / b are electrically attached to stack substrate 202 by attaching the pads 213 of the die 203 to the traces 211 and vias 214 in and on the stack substrate to separators and spacers 412a / b. The traces 211 are attached to the separators and spacers 412a / b on the stack substrate via traces 211. Again, as noted earlier herein, the appropriate spacing between the substrates is discussed later herein in more detail, with regard to later figures but using simple spacers or separators. In this example 920, there are two die 203a and 203battached to the substrate 202. In other embodiments (see Fig. 4B) there may be multiple die attached to each side of substrate 202. In addition, other components such as passives, optical and non-silicon devices may be attached. In this example the two separators 412a / b are shown on opposite ends and sides of the substrate to demonstrate a variation of configurations of the populated substrate subsystem.

[0070] FIG. 9C depicts a side view of an interposer stack module or component 940 using substrate separators and spacers. In this embodiment, the stack of separators and spacers 412a / b / c can be seen attached to the stack substrates 202a / b with separator and spacers 412a attached and protruding through 227 the surface 226 of the SiP 940. The die 203 a / b / c / d are not visible in this view but can be attached to the stack substrates as shown in FIG. 9A.

[0071] FIG. 9D depicts a completed device 960 after the encapsulate 225 has been shaved to expose external connection and spacer pads 227 of the assembled stack substrate system 361 on the top surface 226 of the SiP 960. The die 203 a / b / c / d are not visible in this view but are attached to the stacked substrates as shown in FIG. 9A.

[0072] According to embodiments, a process 1000 is provided according to embodiments. In certain aspects, FIG. 10 depicts a method for assembling the individual populated stack substrates into a stack, and then assembling the stack on an HI device. This could be, for example, a System in Package (SiP) device. Although depicted as a single figure, this method may be broken into two different methods in embodiments. The first method 1011 is for the assembly of a set of stack substrates into a system / module, and the second method 1012 is for assembling such a system / module onto the SiP substrate to create a SiP device.

[0073] The assembly 1011 of each of the populated stack substrates into a module has four steps. The first step slOOl is to assemble and test each of the substrates. Although the three examples depicted in the previous figures (FIGs. 2 - 9) each show only one or two active components on each stack substrate, multiple active and passive components may be attached to each of the stack substrates. Once each of the individual stack substrates are assembled and tested in step slOOl, the substrates are physically stacked and interconnected together in step sl002, optionally encapsulated s 1003 and tested s 1004 as a module. In embodiments, and depending on the use case of the HI device, a stack substrate module may not be encapsulated. The second assembly process 1012 electrically and mechanically attaches the stack module to the substrate in step 1005. Once attached, the device is optionally encapsulated and tested in step sl006.

[0074] According to embodiments, the process 1000 discussed with respect FIG. 10 may use any of the interconnection systems described herein, including: using connection pins (FIGs. 2 - 7), BGA balls (FIG. 8), separators and spacers (FIG. 9), or any other interconnection systems. The different interconnection systems may also be used together in any combination.

[0075] FIGs. 11A, 11B and 11C depict a front, side and partially transparent top view, respectively, of a stack substrate module (SSM) according to some embodiments. FIG. 11 A depicts the front view of stack 1120. In this embodiment stack 1120 comprises three stack substrate subassemblies, such as described with respect to FIG. 12G, where each stack substrate has a stack substrate 202 with two die 203 attached to its top and bottom surfaces. The two die 203 are electrically connected to the substrate via contacts 210 (see FIG. 2). In embodiments, each stack substrate is electrically interconnected internally with traces 211 and vias 214 (see FIG. 4). Optional spacers 1101 are attached to give stability, proper separation, and structural integrity to the stack substrate module. Connection balls 312 are attached for electrical interconnection between individual substrates 211. When necessary for structural integrity, spacer support structures 1111 are attached. FIG. 1 IB depicts the side view 1140 of the module. As in FIG.11 A, stack substrate 202 has two die 203 electrically attached. Connection balls 312 are attached to electrically interconnect the stack substrate. Optional spacers 1101 are included where needed along with the spacer support structures 1111. The spacers 1101 and spacer support structures may be non-conductive or may be individually electrically interconnected via appropriate conductive traces to provide power, ground or signals to stack substrates 202. For simple spacers as noted earlier herein, they may be smaller and non-conductive and just used for maintaining proper spaceing between substrates. FIG. 11C, depicts the top view 1160 of the stack substrate module. Depicted in this view are stack substrate 202 with the top die 203, spacer 1101 and spacer support structures 1111. In this example only one die 203 is depicted, but it should be understood that other layouts (not depicted) may include, for example, multiple active devices, passive devices, or optical devices attached to various individual stack substrates 202 in the stack 1100. In these examples, connections on two sides of the stack. However, in embodiments, connections can exist on all sides of the substrates and potentially in the middle of the substrate.

[0076] FIGs. 12A-12M depict steps of a method for assembling an SSM / SSC and attaching it to a System in Package (SiP) device. FIG. 12A depicts the starting point of the method with the interposer substrate 202 with the internal and external traces 211 and vias 214. FIG. 12B depictsthe attachment of the first die 203, which may have passives as part of its manufacture, and any other dcviccs / componcnts, to this side of interposer substrate 202. FIG. 12C depicts flipping over of the partially completed subassembly. FIG. 12D depicts the attachment of the second die 203 and any other devices / components to the interposer substrate. Although for this example the assembly method depicts only one die 203 being attached to the interposer substrate, there may be, for example, multiple active, multiple passive devices, optical devices, and mechanical devices attached to either or both sides of the interposer substrate, and being operationally electrically interconnected using the traces 211 and vias 214 in substrate 202. FIG. 12E depicts the attachment of two balls 312 to the interposer substrate 202. The balls 312 are used for both electrical interconnection between interposer substrates but also for structural integrity of the stack. FIG. 12F depicts adding a spacer 1101. FIG. 12G depicts an SSM / SSC 1250 ready to be stacked and a flipped subassembly. FIG. 12H depicts stacking the subassemblies 1250 and FIG. 121 depicts attaching the spacer support structure 1111. Note the spacer support structure may be used to mechanically and / or electrically attach to the device (not shown) and / or to the top surface of the device package. FIG. 12K depicts adding the two top balls 313 when stacking additional components on the top surface 226 of the device package 1260 (when necessary). Also depicted is the die stack 1255 attached to the HI device’s 1260 substrate 201. Not shown are the traces and vias on and in the substrate 201 used to interconnect the die stack 1250 to other components 207 (see FIG. 8E) and to the external connectors 204 of the HI device 1260. FIG. 12L depicts a side view of a SiP (or HI device) 1260 with the SSM 1255 included. FIG. 12M depicts a top view of a SiP (or HI device) 1260 with the SSM 1255 included.

[0077] FIG. 13 illustrates a process 1300 according to some embodiments. The process may be used, for instance, to make one or more of the devices / components shown with respect to FIGs. 12A-12M. Likewise, the process 1300 may be used with respect to any of the structures shown in FIGs. 2-9 and FIG. 11. In certain aspects, FIG. 13 lists steps 12 for assembling interposers / modules into a stack. According to embodiments, the process starts with the interposer substrate at step s 1301. Next the first die (sl302) is attached to the substrate. The subassembly is then flipped over at sl303, which may be optional. Next a second die (sl304) is attached to the substrate. Balls are then attached to the substrate at step si 305. This followed by optionally attaching spacer(s) at step sl306. In step sl307, the subassembly is flipped over (which again, may be optional). Next the subassemblies are stacked in step sl308. Then a spacer support structure(si 309) may be attached. This is followed by attaching balls at the top, if necessary, in step 1310.

[0078] Aspects of the disclosure combine three concepts to stack integrated circuit devices in die form: (1) Through Silicon Vias (TSV) or other through-substrate vias; (2) unused die edge area or the related scribe streets of a wafer; and (3) Re-Distribution Layers (RDLs). All these operations may be performed when die are still in a wafer form. An added opportunity according to some embodiments is to also integrate other active and passive devices into / onto the die stack. Moreover, stacked die subsystems may also be used as components in a stacked substrate subsystem. In embodiments, stacks may be made of known good die that have been processed in wafer form. And once created, these die stacks may be included in devices, such as for example an HI device or SiP device.

[0079] In some embodiments, the “dead” real estate in a wafer of die is used. For instance, the scribe street between the die in a wafer that is normally only used to singulate each die in a wafer can be effectively utilized. One example uses TSVs in the scribe street to make connections from the top surface of a die to its bottom surface, by using RDL layers on the top and bottom surfaces of the die that are connected to the TSVs. The RDL layers are connected via TSVs at the edges of the die outside of the active area of the die, and allow for signals / information to be passed from the top surface of the die to the bottom surface of the die and in the reverse direction as well. The top RDL layer is connected to the external connectors located on the top surface of the die. Both RDL layers may also have external connectors and may extend across the entire surface of the die. By using the external connectors of the RDL layers, a die so configured may be stacked and use the TSVs as a structural element to provide stability to a vertical arrangement of multiple die creating a die stack. In certain aspects, The use of the edge TSVs is to provide electrically connectable points on sides of a die for stacking die, leads to the use of similar electrically conductive rails or pins in the form of a scaffold, to provide a physically stable structure for stacking substrates; the rails are connected to each substrate at its edges which are normally not used and may employ an RDL like layer on the bottom of the substrate to provide an alternate set of external connectors for stacking a second substrate below a first substrate. There may also be an conductors in addition to RDL on the top surface of the substrate, as well, to provide the interconnection between the substrate and the power rails.

[0080] According to some embodiments, FIG. 14 depicts a tested semiconductor wafer 1400 of die ready for further processing. A finished substrate 1401 comprises a plurality of good die readyto be cut into individual die 1411. As shown in expanded view 1420, four die (die 1421 , 1422, 1423, 1424) arc located in the center the wafer 1400. For illustration purposes, the following describes performing wrap-around RDL (WA-RDL) for this block of four die, rather than all the die in a wafer. However, embodiments are applicable to processing all die (or a larger subset of die) on the wafer

[0081] FIGs. 15A and 15B depict the placement of through silicon vias (TSVs) 1501 in the saw / scribe street 1502 between adjacent die according to some embodiments (e.g., in a processed and tested semiconductor wafer 1400, 1500). In FIG. 15A, the TSVs 1501 are shown placed in the scribe streets 1502 surrounding the four die (1421, 1422, 1423, 1424) while the other die designated by 1411 are not shown with TSVs 1501 in order to simplify the depiction and discussion. Depending on the width of the saw street 1502 the TSVs 1501 may vary in size and shape. Further the TSVs may be, for instance, various staggered arrangements from one side of the saw street to the other side, be placed side by side within the saw street, or various combinations of different size, quantity, and staggering. This illustrates that the TSVs are located outside the active area of the die, so no modification of the design of the die is needed to accommodate the TSVs, unlike current usage of TSVs. Accordingly, this process may be used with any die while in wafer form. FIG. 15B depicts a top view of only the four die 1421, 1422, 1423, 1424 of FIG. 15A after the insertions of the TSVs 1501, the RDL added to both the top and back side of the four die while still in the wafer, and then the die cut apart 1552. In this example, due to the cutting, partial TSV portion 1551 remain at the outer edges of the die 1421-1424. That is FIG. 15B depicts a top view 1550 of a four modified singulated die. Additional aspects of the RDL process are illustrated, for instance, with respect to FIGs. 19A and 19B. While TSVs are used as an example, other through- wafer vias and material systems may be used in embodiments.

[0082] According to embodiments, aspects of the disclosure provide apparatuses and methods for stacking semiconductor components. This may include, for instance, creating WA-RDL die in a wafer for making a stack of die from known good die in a wafer. In embodiments, one or processes described herein begin with known good die in a wafer manufactured by current standard high volume semiconductor manufacturing processes and techniques.

[0083] FIGs. 16A-16F and 17A-17F illustrate aspects of a manufacturing processes. These processes may be used, for instance, to make singulated stackable die (e.g., having through- substrate vias and one or more RDLs). According to some embodiments, FIGs. 16A (1600), 16B(1610), 16C (1620), and 16D (1630), 16E (1640), and 16F (1650) depict a side view cut away 1510 focused on two adjacent half TSVs 1661a / b, an RDL on the top surface 1665a / b, an RDL on the backside 1666a / b, and the saw street 1502 between die 1421 and 1422. FIG. 16A depicts the starting view while FIG. 16F depicts the completed process. FIGs. 17A (1700), 17B (1610), 17C (1720), and 17D (1730), 17E (1740), and 17F (1750) depict a side view cut away 1510 depicting two adjacent TSVs 361a / b, an RDF on the top surface 365a / b, an RDF on the backside 366a / b, and the saw street 1502 between die 1421 and 1422. FIG. 17A depicts the starting view while FIG. 17F depicts the completed process.

[0084] FIG. 16A depicts a cut away side view of a segment of a processed wafer 1400 according to some embodiments, which is made up of the wafer 1651 with the active portion and circuitry of two adjacent good electrical die (GEDs) 1421, 1422 including the seal rings 1621 / 1622, with a saw street 1502 between the edges 1623 of the two die 1421, 1422. A saw street is typically 60 to 100 microns in width. In this example, 1651 is the silicon substrate on which the active and passive components of the die have been created and operatively interconnected. Although not depicted in FIG. 16A, each of the die 1421 and 1422 can have external connectors for connecting the die to other semiconductor devices or components. While silicon and TSVs are used in examples, other through-substrate vias and materials can be used according to embodiments. In some instance, the seal rings are regions surrounding the active or functional regions of the die (e.g., marking the edge of the active part of the die).

[0085] FIG. 16B shows the laser drilling or masked etching of a hole 1664 for the through silicon via (TSV). In embodiments, the hole 1664 is generally about 40 to 60 microns in diameter and does not penetrate the backside or bottom of the wafer 1651. This step may use conventional semiconductor manufacturing processes to create the hole in the die while still in the wafer.

[0086] FIG. 16C depicts a view of a partially completed TSV 1661 with multiple layers 1662, 1663, and 1664. These layers may be, for example, an oxide layer 1662, a liner 1663 (e.g., TA- CU), and copper, or other suitable conductive metal in the hole 1664 to form the via. In some embodiments, this step can use conventional semiconductor manufacturing processes such as, for example, masked chemical vapor deposition (CVD) to create the oxide layer and TA-CU liner and electro-plating copper or a Cu seed in the hole in the die while still in the wafer. Other known semiconductor manufacturing processes and techniques may be employed to create the insulating and barrier layers and place other metals than copper in the hole 1664. Similarly, the top first RDFlayer 1665 depicted may be created before or after creation of the TSV. However, the RDL layers on the top and backside of the die may be placed before the TSVs arc created.

[0087] FIG. 16D depicts the wafer 1651 after back- grinding exposes the TSV 1661 on the backside or bottom of the wafter 1631.

[0088] FIG. 16E depicts the wafer after the second redistribution layer (RDL) 1666 is applied to the backside or bottom 1631 of the wafer. In some embodiments, the RDL layers are patterned to match up with external connectors of a first die on the top surface, and the backside RDL is patterned to match up and interface with the topside RDL of a second die to be stacked below the first die. In addition, some TSVs may extend from the top RDL of the topmost die in a stack to the TSVs of the bottommost die in a stack to provide power, ground and signals to all the die in the stack.

[0089] FIG. 16F depicts the two die 1421 and 1422, which have separated 1602 using a singulation technique (e.g., a saw or other dicing process). In this embodiment, each die 1421 and 1422 have half of the TSV 1661a / b connected to the RDL on both their top surfacesl665a / b and backside or bottom surfaces 1666a / b. However, in other embodiments, sawing / singulating may be arranged such that fully TSV structures remain.

[0090] In summary, FIGs. 16A, 16B, 16C, and 16D, 16E and 16F depict side cut away views 1510 focused on two adjacent die 1421 and 1422 in the wafer and the addition of half TSVs 1661a, b, RDL on the top surface 1665a / b, RDL on the bottom 1666a / b, and the saw street 1502 between die 1421 and 1422. FIG. 16A depicts the starting step of two adjacent die in a wafer while FIG. 16F depicts the completed process where the die are singulated and illustrates the WA-RDL of those two die. According to embodiments, the TSVs are located in the saw / scribe street and do not impact the design of the circuitry for the die.

[0091] FIG. 17A depicts a segment of a processed wafer 1400 made up of the wafer 1651 with the active circuitry of two adjacent good electrical die (GEDs) 1421, 1422 including the seal rings 1621 / 2, with a saw street 1502, typically 60 to 100 microns in width, between the edges 1622 of the two die 1421, 1422. In many aspects, FIG. 17A is similar to FIG. 16A, and the following steps in FIGs. 17B-17F are similar to those in FIGs. 16B-16F, but deal with two TSVs rather than one. In embodiments, the saw / scribe street may be wide enough that it is preferred to use two TSVs rather than one large TSV. FIG. 17B shows the addition of the two holes 1664a / b for the through silicon vias (TSV). In embodiments, the holes 1664a / b are generally about 40 to 60 microns indiameter and do not penetrate the back side of the wafer! 631. FIG. 17C depicts a view of a completed TSVs 1761a / b showing the oxide layer 1662, the TA-CU liner 1663, and the copper via 1661a / b. FIG. 17D depicts the wafer after back-grinding exposes the TSVs 1761a / b on the bottom of the wafer 1631. FIG. 17E depicts the wafer after the redistribution layers (RDL) are applied to the top surface 1765 and bottom 1766 of the wafer 1651a / b / c. In summary, FIGs. 17A, 17B, 17C, and 17D, 17E and 17F depict cut away side views 1510 depicting two adjacent TSVs 361a / b, RDL on the top surface 365a / b, RDL on the bottom 366a / b, and the saw street 1502 between die 1421 and 1422. FIG. 17A depicts the starting step while FIG. 17F depicts the completed process where the die are singulated and illustrates the WA-RDL of those two die. Again, the TSVs are located in the saw / scribe street and do not impact the design of the circuitry for the die, e.g. they avoid the active area of the die.

[0092] FIGs. 18A and 18B depict a top and side view of four adjacent semiconductor die found in the center of a wafer, according to some embodiments. In the example of FIG. 18A, four die 1421, 1422, 1423, 1424 with the portion of the TSV 1802 attached to each of them are shown. In the example of FIG. 18B, a side view is provided of the four die 1421, 1422, 1423, 1424 in FIG. 18A, with the TSVs 1802 attached to each of the die. FIGs. 19A and 19B show a top and side view of an individual die (1421 in this example) with the attached portion of the TSVs 1802a / b with top surface RDL 1665 and backside or bottom 1666 RDL, after being singulated. According to embodiments, the die is ready to be stacked.

[0093] According to embodiments, the use of the edge TSVs (or other through- wafer vias) is to provide electrically connectable points on sides of a die for stacking die. Embodiments can also use similar electrically conductive rails or pins in the form of a scaffold to provide a physically stable structure for stacking substrates. In some embodiments, the rails are connected to each substrate at its edges which are normally not used and may employ an RDL like layer on the bottom of the substrate to provide an alternate set of external connectors for stacking a second substrate below a first substrate. There may also be one or more conductors in addition to RDL on the top surface of the substrate, as well, to provide the interconnection between the substrate and the power rails.

[0094] EIGs. 20A, 20B, and 20C show three different embodiments of die stacks. In these examples, the die each have TSV and RDL interconnects.

[0095] In EIG. 20A four die 1421, 1422, 1423, 1424 from a wafer 1400 are stacked together 2000.For example, die 1421 and 1422 are interconnected via the TSVs 1802 of each of the two die and the top surface RDLs 1665 a / b of both die 1421 andl422 and the back side (bottom) RDL 1666 a of die 1421. In this embodiment, the top surface RDL 1665 of die 1421 may not have the same interconnect as the top surface RDL 1665 b of die 1422. The stack is mounted on a base substrate 2001 for a system that employs the die stack. Substrate 2001 includes multiple layers of conductive traces insulated from each other appropriately interconnected with vias between layers and used for operationally interconnecting the components mounted on the base substrate. These layers and vias are depicted in FIG. 1.

[0096] In FIG. 20B a different embodiment 2050 is depicted. In this embodiment, a die 2051 with a smaller size is attached through the bottom RDL 1666 of die 2051 and the top surface RDL 1665 of die 1422. The two die 1422 and 2051 may be, for example, from two different wafers with different die sizes. Other example arrangements are possible with each die in the stack being of a different size. Alternatively, as shown in FIG. 20A, all die may be the same size in embodiments.

[0097] In FIG. 20C a different embodiment 2075 is depicted. In this embodiment, a die 2051 with a smaller size is attached through the bottom RDL 1666 of die 2051 and the top surface RDL 1665 of die 1422. Again, this example may result from the two die 1422 and 2051 being from two different wafers with different die sizes. Other exemplary arrangements may be possible with each die in the stack being of a different size. Also depicted are various components located on the top surface of the top surface RDL 1665 of die 2051 and the top surface RDL 1665b of die 1422. Also depicted are several bond wires connecting the external connectors of the top surface RDL of dies 2051 and 1422 and the base substrate 2001. According to embodiments, one can connect down to the base substrate from the top / sides of the stack. Additionally, the die in the lower stack could be any size to allow for wire bond connections to be used for lower die. Die 2052 may also be of a smaller size. In some embodiments, various components 207,208 may be located on the top surface of the top surface RDL 1665 of die 2051 and the top surface RDL 1665b of die 1422. Also depicted are several bond wires 2082, 2083, 2084, 2085 connecting respectively: (1) the top surface RDL 1665c of device 1422 to the SiP substrate 2001, (2) the top surface RDL 1665d of die 2051 to the top surface RDL 1665c of die 1422, (3) the top surface RDL1665d of the die 2051 to device 207, and (4) the top surface RDL of die 1424 to the SiP substrate 2001. An additional connection method using ball attach 2081 is shown connecting the device 207 to the top surface RDL 1665d of the top die 2051 in the stack.

[0098] Referring back to FIG. 20A, depending on the layout of the top surface RDL 1665d and the bottom RDL 1666d, the die 1424 could be electrically connected to the substrate 2001 via the bottom RDL 1666d, as depicted, or electrically connected via the topside RDL 1665d and TSV 1802d. Further, die 1421-1424, depending on the RDL placed on their top surfaces or bottoms and the TSV connections 1802 between the two RDL surfaces could be stacked in multiple ways such as (1) bottom to bottom, (2) top surface to top surface, (3) top surface to bottom with the top surface on the top of the stack, or (4) bottom to top surface with either the remaining bottom or top surface on top of the stack.

[0099] According to embodiments, FIGs. 21 A-21H depict different views of completed die ready to be stacked and interconnected. According to embodiments, these die may be used as a subcomponent of a larger stacked device or system.

[0100] FIGs. 21 A and 21B show a side and top view of a die stacking device 2100 after all the WA-RDL post processing of the present disclosure has been completed. FIG. 21A depicts a side view of the finished die 1421. It is made up of a stack, which has, from top to bottom, a top surface redistribution layer 1665 made up of an array of connecting bumps 2103, traces 2101, and vias 2102. Below the top layer redistribution layer 1665 is device 1421 with multiple through silicon vias (TSVs) 1802 a / b / c on one or more edges of the device. In this example, one of the TSVs 1802a is arranged to be connected to TSVs in the same physical location as in the die above and below creating a structural element, for a signal, power, or ground rail though the die stack. Below device 1421 is the bottom redistribution layer (RDL) 1666. As in the top surface RDL 1665, the bottom RDL 1666 has an array of connecting bumps 2103, traces 2101, and vias 2102. The top surface RDL provides external connectors 2103 for other connections and makes connections with the external connectors of the device 1421 and forwards to and receives signals from the external connectors 2103 and similarly forwards to and receives signals from TSVs that are connected to the RDL. The TSVs also provide and receive signals from the bottom redistribution layer (RDL) 1666. FIG. 21B depicts the top view 2150 of the finished die 1421. The active region of the die is identified by the dashed box 2121. In this example, the vias 1802 are located outside of the active region.

[0101] FIGs. 21C, 21D, 21E, 21F, 21G and 21H depict side views of a singulated die encased with top and bottom redistribution layers (RDL) 1665, the surfaces interconnected by TSVs 1802 in the scribe street, for instance, as discussed with respect to FIG. 18 A.

[0102] FIG. 21 C depicts a die 1421 that has been singulated from a wafer 1400 after through silicon vias (TSVs) 1802 have been placed in the scribe street outside the active areas of each of the die, and a redistribution layer (RDL) has been applied to the top and bottom surfaces of the die on the wafer. In embodiments, both the applications of the TSVs and RDL are performed while the die are in the wafer prior to being singulated. The substrate uses traces 211 and vias 214.

[0103] FIGs. 2 ID and 2 IE depict an embodiment where two die 1421 and 1422 are stacked on a base substrate 201 having redistribution layers (RDL) 1665 on both the top and bottom layers of the die and through silicon vias (TSVs) 1802 on the edges of the die. This arrangement allows for a device 207 to be attached to the top surface 1665 of the top die 1422. This can be connected to the SiP substrate 201 through the electrical path created by the top surface RDL 1665 on the top die 1422 to its TSV 1802 to the RDL on its bottom surface, connected to the top surface RDL on the bottom die 1421, connected to its bottom surface RDL through its TSV, and connected through bumps 2103 to the top surface of the base substrate 201. Finally, the electrical path can continue through the substrate 201 using traces 211 and vias 214 to an external connection ball 204. However, the path may use the RDL at any die to make other connections.

[0104] FIG. 21F depicts an example of three die 1421, 1422, 2051 stacked on a substrate 201. In this embodiment, a third die 2051 is attached to die 1422. As in FIG. 21E, the three die 1421, 1422, and 2051 are stacked on a base substrate 201 and have redistribution layers (RDL) 1665 on both the top and bottom layers of the die and through silicon vias (TSVs) 1802 on the edges of the die. This arrangement allows for a bump on the top surface RDL 1665 of the top die 2051 to be electrically connected to the top surface RDL1665 of die 1422 through its (2051) bottom surface RDL 1665 via the bumps 2103 between die 2051 and 1422. Next, the top surface RDL of die 1422 is connected to its bottom surface RDL through its TSV 1802. Die 1422 is connected to die 1421 through the bottom surface RDL of die 1422 to the top surface RDL of die 1421. then the top surface RDL is connected to the bottom surface RDL of die 1421 through its TSVs 1802. Finally it is connected to the base substrate 201 through the bottom surface RDL of die 1421. The electrical path created begins on a bump on the top surface RDL 1665 on the top die 2051 to its TSV 1802 to the RDL on its bottom surface, connected to the top surface RDL, TSV and bottom surface RDL on the middle die 1422, connected to the top surface RDL of the bottom die 1421, connected to the TSV 1802 of the bottom die 1421 and its bottom surface RDL on die 1421. It is then connected through bumps 2103 to the top surface of the SiP substrate 201. Finally, the electrical path cancontinue through the substrate 201 using traces 21 1 and vias 214 to an external connection ball 204.

[0105] FIG. 21G depicts a special case of using TSVs 1802 and RDL 1665 to selectively add structure to the die stacking process. In this example the edges of the two die 1421 and 1422 have one or more TSVs placed in the scribe street of the two die. Also, RDL segments are placed in the same locations of the die on the top and bottom surfaces of the die. In the assembly of the die stack, connection bumps 2361 are used to mechanically and electrically attach the two die 1421 / 2 together. These attachment points on the stack of die may be used as 1) structural components, 2) power rail distribution, or signal distribution on one or more of the die in the stack. It should be noted that for simplicity of description the RDL segments may be isolated from other RDL segments on each of the surfaces of the die in the stack or may be interconnected with other RDL segments on the surfaces to the extent of covering the whole die surfaces. Also note that the traces and vias in the RDL are not shown in this example. In addition, in embodiments, the space between the RDL on the first and second die may be zero, and the RDL may provide additional interconnections between components that may be located on an RDL layer on one (or more) of the die. In some embodiments, connection bumps 2361 may be omitted, as shown in FIG. 21H. In effect, a single via may run between multiple die providing one or more of electrical connection and / or mechanical support to the stack / sub-assembly.

[0106] FIG. 22 depicts a process 2200 according to some embodiments. The process may be used, for instance, for creating die ready for stacking, as illustrated with respect to any of FIGs. 14-21. In certain aspects, process 2200 is for stacking semiconductor devices using through silicon vias (TSV), redistribution layers (RDL), and one or more singulation techniques. In some embodiments, the process 2200 starts with a finished and tested wafer in step s2201. Next, in step s2202, an array of through silicon vias (TSVs) are inserted into scribe street between die. A redistribution layer (RDL) is added to the top surface of the wafer in step s2203, followed by a RDL added to the bottom of the wafer in step s2204. Finally, the die in the wafer are sawed apart in step s2205. In embodiments, the steps s2203 and s2204 of applying RDL to the top surface and back side of the wafer can be done in either top surface first or backside or bottom first.

[0107] FIG. 23 depicts a process 2300 according to some embodiments. The process may be used, for instance, for creating die ready for stacking, as illustrated with respect to any of FIGs. 14-21. In some embodiments, the process 2300 begins with step s2301, which comprises obtaininga wafer with a plurality of die / devices and scribe streets between the die / devices. Tn steps s2302 and s2303, which may be optional in some embodiments (c.g., where such processing has already been performed on the obtained wafer), top and bottom RDLs are applied. In step s2304, through- waver vias, such as TSVs, are fabricated in at least one of the scribe streets. In step s2305, which may be optional, the wafer is diced (e.g., sawed, singulated, etc.) along the scribe streets.

[0108] According to embodiments, techniques - including structures and processes - described with respect to stacks of interposer substrates and their interconnections are similar to those used for stacked die described herein, and vice-versa. That is, the unused edges of a substrate may be used for interconnecting and structurally supporting stacks of substrates using conductive rods or pins and RDL at least on the edges of a substrate. The same is true for stacks of die in certain aspects. Embodiments use the edges of a substrate for performing functions that arc not typically associated with a substrate’s edge.

[0109] Summary of Embodiments

[0110] Al. A method of manufacturing a semiconductor device, comprising: obtaining a w after having a plurality of die (or devices) and scribe streets between the die (or devices); fabricating through-wafer vias in at least one scribe street; and dicing (e.g., sawing, singulation, etc.) the wafer along the scribe streets.

[0111] A2. The method of Al, wherein the dicing (or sawing, singulating, etc.) is performed through a plurality of the through-wafer vias to form a plurality of partial vias.

[0112] A3. The method of Al, wherein the dicing (or sawing, singulating, etc.) is performed between two adjacent thro ugh- wafer vias in a scribe street.

[0113] A4. The method of any of A1-A3, further comprising one or more of: forming a first redistribution layer (RDL) on a top surface of the wafer; and / or forming a second redistribution layer (RDL) on a bottom surface of the wafer.

[0114] A5. The method of any of A1-A4, wherein obtaining the wafer comprises processing the wafer (e.g., fabricating one or more of the plurality of die and / or scribe streets).

[0115] A6. The method of any of A1-A5, wherein the dicing (or sawing, singulating, etc.) forms a plurality of devices according to any of C1-C8.

[0116] A7. The method of any of A1-A6, wherein the wafer is a silicon wafer and the vias are through- silicon- vias (TSVs).

[0117] A8. The method of any of A1-A7, wherein fabricating through-wafer vias comprises oneor more of:(i) laser drilling holes for the vias in the top side of the wafer;(ii) mask etching holds for the vias in the top side of the wafer; and / or(iii) depositing one or more of an oxide layer, liner, and / or conductor in the holes.

[0118] A9. The method of any of A1-A8, wherein the fabricated vias do not penetrate fully through the wafer.

[0119] A10. The method of any of A1-A9, further comprising: back-grinding the wafer to expose the vias on the bottom side of the wafer.

[0120] All. The method of any of Al -A 10 comprising performing any of the methods on a wafer according to any of B1-B5.

[0121] Bl. A semiconductor device, comprising: a substrate (e.g., wafer), wherein a plurality of devices (e.g., die) are formed in / on the substrate; a plurality of scribe streets are provided between the plurality of devices (e.g., between adjacent die); and a plurality of vias that extend through the substrate, wherein the plurality of vias are located in the scribe streets.

[0122] B2. The device of Bl, wherein the substrate is a silicon wafer and the vias are through- silicon-vias (TSVs).

[0123] B3. The device of Bl or B2, further comprising one or more of: a first redistribution layer (RDL) on a top surface of the substrate; and / or a second redistribution layer (RDL) on a bottom surface of the substrate.

[0124] B4. The device of any of B1-B3, wherein the plurality of vias are arranged in a single line in each of the scribe streets.

[0125] B5. The device of any of B1-B3, wherein the plurality of vias are arranged pair- wise in two lines in each of the scribe streets.

[0126] Cl. A semiconductor device, comprising: a substrate, wherein an active region of the device is provided on an upper surface of the substrate; and a least one via extending through the substrate, wherein the via is located outside of the active region.

[0127] C2. The device of Cl, wherein the at least via is located on an outer edge of the device.

[0128] C3. The device of Cl or C2, wherein the device comprises a plurality of vias and a first via is located on a first edge of the device and a second via is located on a second edge of the device (e.g., where the first and second edges are on opposite sides of the device).

[0129] C4. The device of any of C1-C3, further comprising: a first redistribution layer (RDL)on a top side of the device.

[0130] C5. The device of C4, further comprising: a second redistribution layer (RDL) on a bottom side of the device.

[0131] C6. The device of C4 or C5, wherein the first and / or second RDL comprises of one or more of bumps, traces, and / or vias.

[0132] C7. The device of any of C1-C6, wherein the vias comprise a plurality of layers.

[0133] C8. The device of C7, wherein the layers comprise one or more of an oxide layer, liner, and / or conductor layer.

[0134] DI. A system comprising: a first semiconductor device according to any of C1-C8; and a second semiconductor device according to any of C1-C8, wherein the first device is stacked on the second device.

[0135] D2. The system of DI, further comprising: a base substrate (e.g., where the first and second devices are stacked on the base substrate).

[0136] D3. The system of DI or D2, wherein:(i) the first and second die are interconnected using their respective vias; and / or(ii) the first and second die are interconnected using a bottom RDL of the first device and a top RDL of the second device.

[0137] D4. The system of any of D1-D3, wherein the first device has first functionality and the second device has second, different functionality.

[0138] D5. The system of any of D1-D4, further comprising: a third device (e.g., having a different functionality than the first and / or second device) that is stacked on the first device.

[0139] D6. The system of D5, wherein the third device is interconnected to the second device.

[0140] D7. The system of D6, wherein the second and third device are interconnected:(i) using at least one via of the first device; and / or(ii) using bond wires.

[0141] D8. The system of any of D1-D7, further comprising: one or more passives arranged on an uppermost device of the system (e.g., interconnected to the upper most die using its top RDL).

[0142] D9. The system of any of D1-D8, wherein the stacked devices and the base substrate are encapsulated to form a System-in-Package (SiP).

[0143] D10. The system of any of D1-D9, wherein the at least one of the devices is a processor, at least one of the devices is a memory, and / or at least one of the devices is a power managementdevice.

[0144] Dl l. The system of any of D1-D10, wherein the first and second die have different sizes.

[0145] D12. The system of any of Dl-Dl l, wherein at least one of the first, second, or third device is connected to the base substrate using a bond wire.

[0146] D13. The system of any of DI -DI 2, wherein the vias of multiple devices in the stack are connected to form a structural element or to a carry a common signal (e.g., to the base substrate).

[0147] D14. The system of D13, wherein the common signal is an operational signal of the system, power, or ground.

[0148] El. A method comprising: mounting a first semiconductor device according to any of C1-C8 onto a base substrate; and stacking a second semiconductor device according to any of Cl- C8 onto the first device.

[0149] E2. The method of El, comprising forming the first or second device according to any of the methods of A1-A14.

[0150] Fl. A connection device comprising: an array of conductive pins; and a mounting header; wherein the conductive pins are all attached to the mounting header.

[0151] F2. The device of Fl, wherein the pins are removably attached to the header.

[0152] Gl. A method, comprising: mounting a plurality of substrates / interposers to the connection device of Fl or F2.

[0153] G2. The method of Gl, further comprising: removing the mounting header.

[0154] G3. The method of G2, wherein the mounting comprises inserting the conductive pins through corresponding holes of the plurality of substrates / interposers (e.g., at the edges).

[0155] G4. The method of any of G2 or G3, wherein the conductive pins provide both electrical connection and mechanical support between a plurality of the substrates / interposes.

[0156] Hl. A device (module, component), comprising: a substrate (e.g., with a plurality of vias and internal traces); at least one die mounted on a first surface of the substrate; and at least one connection element at an outer edge of the substrate, wherein the connection element is one or more of a pin, spacer, and / or ball.

[0157] H2. The device of Hl, further comprising: a second die mounted on a second, opposite surface of the substrate.

[0158] JI. A system, comprising: a first device according to Hl or H2; and a second device according to H 1 or H2, wherein the first device is stacked on the second device and the first andsecond device are interconnected using the connection element(s).

[0159] KI. A method, comprising one or more of:(a) obtaining an interposer substrate;(b) attaching a first die to a first surface of the interposer substrate to form a sub-assembly;(c) flipping the sub-assembly;(d) attaching a second die to a second, opposite surface of the interposer substrate;(e) attaching one or more balls (e.g., to the substrate);(f) attaching at least one spacer (e.g., to the first die) to form an updated sub-assembly; and / or(g) flipping the updated sub-assembly.

[0160] K2. The method of KI, further comprising:(h) repeating any of steps (a)-(g) to form first and second sub-assemblies OR obtaining first and second sub-assemblies (e.g., according to Hl, H2, or JI); and(i) stacking the first and second sub-assemblies to form a module.

[0161] K3. The method of KI or K2, further comprising:(j) adding a support structure to the module; and / or(k) adding top balls to the module.

[0162] K4. The method of any of K1-K3, further comprising: attaching the module to a system substrate (e.g., with one or more additional passive / active components) to form a system (e.g., SiP); and / or encapsulating the module (e.g., along with the other system components).

[0163] LI. A semiconductor device (e.g., a SiP), comprising: a plurality of active and passive components, a base substrate comprising a plurality of layers with etched conductive paths and a plurality of vias associated therewith for making operative interconnections between said plurality of components, and a plurality of areas on the surface of said substrate for mounting components, wherein each of said plurality of areas on the surface of said substrate for mounting components is configured / arranged for mounting components of said plurality of components, a plurality of interposer substrates aligned in a vertical manner / arrangement wherein each interposer substrate comprises a plurality of layers with etched conductive paths and a plurality of vias associated therewith for making operative interconnections between components mounted thereon, a plurality of areas on the surface of each of said interposer substrate, for mounting components, and a plurality of input / output pads at one or more edges of each one of said plurality of interposersubstrates for interconnections, and / or a plurality of power, ground, and input / output connectors interconnecting with the input / output pads at the edges of each interposer substrate of said plurality of interposer substrates to interconnect with each other and with the base substrate of said SiP, wherein said substrates and components are optionally encapsulated (or a lid is added) to cover and protect the plurality of components mounted on said substrates.

[0164] L2. The device of LI, wherein each of said interposer substrates includes at least one die / component / device / structure mounted on a surface of the substrate.

[0165] L3. The device of L2, wherein each die is a memory device or stack.

[0166] L4. The device of any of L1-L3, further comprising interconnecting the base substrate to the package top surface.

[0167] L5. The device of any of L1-L4, further comprising: at least a first group of said plurality of components are operatively mounted on said substrate in one of said plurality of areas and operatively interconnected using said vias and conductive paths; and / or a third group (or up to an Nth group) of plurality of said plurality of components are operatively mounted on said substrate in a third one (or Nth one) of said plurality of areas and operatively interconnected using said vias and conductive paths.

[0168] L6. The device of any of L1-L5, further comprising a plurality of shared or common interconnects between stacked interposer substrates for power, ground, control signals, and input / output signals.

[0169] Ml. A packaged System in a Package (SiP), comprising: a SiP substrate comprising multiple layers with etched conductive paths, multiple vias associated therewith for making interconnections, conductive pads for additional interconnections, and exterior connectors, a plurality of components mounted on said substrate and operatively interconnected using said vias and etched conductive paths, and an area of said substrate suitable for operatively connecting a riser structure having a plurality of interconnecting pins for making a plurality of connections to said SiP substrate, wherein the riser structure comprises a plurality of structural conductive paths for operative interconnections between a series of stacked substrates operatively connected to said structural conductive paths, said SiP substrate and said exterior connectors located on said exterior surface of said SiP package.

[0170] Nl. A Device Stack Module (DSM), comprising: one or more substrates each populated with multiple components, electrically interconnected using traces and vias on and in each of thesubstrates and on one or more of its surfaces, a stacking structure to rigidly attach mechanically and operatively interconnect electrically the substrates together at the edge of each substrate, the one or more substrates are electrically interconnected using electrical conductors in the stacking structure, the stacking structure capable of electrically and mechanically connecting to a heterogeneous integrating device’s (System in Package’s) substrate and, optionally, top surface.

[0171] N2. The device stack module of Nl, where the substrates are connected using a. Connection Pins (conduits, rods) b. Connection Balls c. Separators

[0172] 01. A system in package device, comprising: one or more substrates populated with various passive and active components; and one or more Device Stack Modules, wherein the Device Stack Modules are attached to the one or more substrates.

[0173] Pl. A SiP where a DSM stacking structure protrudes the top surface of the SiP package allowing for external connections with external components.

[0174] QI. A method for assembling a system in package with a device stack module, comprising: populating a substrate; encapsulating; and shaving the top surface to reveal DSM connectors

[0175] Rl. A SiP device, comprising: at least two substrates each populated with components operationally interconnected and mounted thereon, wherein the components on each of the substrates are operationally interconnected with traces and vias associated with each substrate (each respective substrate), electrical interconnectors operationally connected with traces on an external surface of a substrate of said at least two substrates and arranged to space / arrange the at least two substrates in a horizontally layered manner and such that components on one substrate may be operationally interconnected by the electrical interconnectors to components of a different substrate, a SiP substrate for mounting the spaced apart at least two substrates and their associated individual components in an operational manner with components on the SiP substrate using the electrical interconnectors, and mounting external connectors on an exterior surface of the SiP substrate.

[0176] SI. A two surface contact die, comprising: a bare die having an active area with active and passive components located therein and thereon with external connectors located thereon, a first RDL layer connecting to the external connectors of the die and providing a first set of exteriorconnectors, a plurality of through silicon via (TSVs) aligned along the edges of the die outside the active area of the die and interconnected with the first set of exterior connectors of the first RDL layer, and a second RDL layer on a face of the die opposite that of the first RDL, interconnected with the first RDL layer via the TSVs and having a second set of exterior connectors.

[0177] Tl. A semiconductor device, comprising: a plurality of layers of semiconductor components vertically aligned and arranged in a vertical column, wherein each layer includes at least active and passive devices operably interconnected in and on each layer using a set of insulatingly spaced apart patterned conductive traces and vias in each layer and wherein each layer includes at least one set of external connectors, a plurality of conductive traces located at the edges of each layer and operably interconnecting the layers using external connectors, and a plurality of exterior connectors operably connected to selected conductive traces and external connectors.

[0178] While various embodiments of the present disclosure are described herein, it should be understood that they have been presented by way of example only, and not by way of any limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the herein above-described exemplary embodiments. Moreover, any combination of herein abovedescribed elements in all possible variations thereof is encompassed by the disclosure unless otherwise indicated herein or otherwise clearly contradicted by context. Accordingly, other embodiments, variations, and improvements not described herein are not excluded from the scope of the present disclosure. Such variations include but are not limited to new substrate material, different kinds of devices attached to the substrate not discussed, or new packaging concepts.

[0179] Additionally, while the processes described above and illustrated in the drawings are shown as a sequence of steps, this was done solely for the sake of illustration. Accordingly, it is contemplated that some steps may be added, some steps may be omitted, the order of the steps may be re-arranged, and some steps may be performed in parallel.

[0180] Systems and methods for vertically integrating semiconductor devices are provided. A device substrate has an active region of the device and at least one via that extends through the substrate, where the via is located outside of the active region. Such devices can be stacked on top of each other to form an integrated system. During processing of wafers used to form the devices, the vias can be located in scribe streets.

Claims

CLAIMS:

1. A method of manufacturing a semiconductor device, comprising: obtaining (s2301) a wafer having a plurality of devices and scribe streets between the devices; fabricating (s2304) through-wafer vias in at least one scribe street; and dicing (s2305) the wafer along the scribe streets.

2. The method of claim 1, wherein at least one of the plurality of devices is a semiconductor die provided in or on the wafer.

3. The method of claim 1, wherein the dicing comprises singulating individual devices by sawing the wafer along the scribe streets.

4. The method of claim 1, wherein the dicing is performed through a plurality of the through- wafer vias to form a plurality of partial vias.

5. The method of claim 1, wherein the dicing is performed between two adjacent through-wafer vias in a scribe street.

6. The method of claim 1, further comprising at least one of: forming (s2303) a first redistribution layer (RDL) on a top surface of the wafer; or forming (s2304) a second redistribution layer (RDL) on a bottom surface of the wafer.

7. The method of claim 1, wherein obtaining the wafer comprises processing the wafer to fabricate one or more of the plurality of devices or scribe streets.

8. The method of claim 1, wherein the dicing forms a plurality of singulated devices each comprising a substrate, wherein an active region of the device is provided on an upper surface of the substrate, and a least one of the vias via extends through the substrate, wherein the via is located outside of the active region.

9. The method of claim 1, wherein the wafer is a silicon wafer and the vias are through-silicon-vias (TSVs).

10. The method of claim 1, wherein fabricating through-wafer vias comprises one or more of:(i) laser drilling holes for the vias in the top side of the wafer;(ii) mask etching holds for the vias in the top side of the wafer; or(iii) depositing one or more of an oxide layer, liner, or conductor in the holes.

11. The method of claim 1 , wherein the fabricated vias do not penetrate fully through the wafer.

12. The method of claim 11, further comprising: back-grinding the wafer to expose the vias on a bottom side of the wafer.

13. A semiconductor device, comprising: a substrate (1400, 1500), wherein a plurality of devices (1421-1424) are formed in or on the substrate; a plurality of scribe streets (1502) that are provided between the plurality of devices; and a plurality of vias (1501) that extend through the substrate, wherein the plurality of vias are located in the scribe streets.

14. The semiconductor device of claim 13, where the substrate is a wafer.

15. The semiconductor device of claim 13, wherein a plurality of the devices are die and at least one scribe street is provided between adjacent die.

16. The semiconductor device of claim 13, wherein the substrate is a silicon wafer and the vias are through- silicon- vias (TSVs).

17. The semiconductor device of claim 13, further comprising at least one of: a first redistribution layer (RDL) on a top surface of the substrate; or a second redistribution layer (RDL) on a bottom surface of the substrate.

18. The semiconductor device of claim 13, wherein the plurality of vias are arranged in a single line in each of the scribe streets, or wherein the plurality of vias arc arranged pair-wise in two lines in each of the scribe streets.

19. A semiconductor device (1421, 2100, 2150), comprising: a substrate, wherein an active region (2121) of the device is provided on an upper surface of the substrate; and a least one via (1802) extending through the substrate, wherein the via is located outside of the active region and is located on an outer edge of the device.

20. The semiconductor device of claim 19, wherein the device is a singulated device.

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