Display substrate and display device

Abstract

A display substrate, comprising: a base (10), a plurality of sub-pixels (PX), a plurality of first traces, and a compensation electrode plate (36). The base (10) comprises a display region (A1) and a peripheral region located on at least one side of the display region (A1). The plurality of sub-pixels (PX) are disposed on one side of the base (10) and are located in the display region (A1). The plurality of first traces are located in the peripheral region and are electrically connected to the plurality of sub-pixels (PX). The compensation electrode plate (36) is located in the peripheral region, and at least one insulating layer is provided between the compensation electrode plate (36) and the plurality of first traces. The orthographic projection of the compensation electrode plate (36) on the base (10) partially overlaps the orthographic projection of the plurality of first traces on the base (10). The compensation electrode plate (36) has a hollowed-out structure, and the orthographic projection of the hollowed-out structure on the base (10) partially overlaps the orthographic projection of at least one first trace on the base (10).

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost.

[0003] SUMMARY

[0004] The subject matter of the present text is outlined in this summary. This summary is not intended to limit the scope of protection of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] In one aspect, the present embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first wires, and a compensation plate. The substrate comprises a display area and a peripheral area located at least one side of the display area. The plurality of sub-pixels are arranged on one side of the substrate and located in the display area. The plurality of first wires are located in the peripheral area and electrically connected to the plurality of sub-pixels. The compensation plate is located in the peripheral area, and at least one insulating layer is arranged between the compensation plate and the plurality of first wires. The compensation plate has a hollow structure, and the hollow structure is partially overlapped with at least one of the plurality of first wires in the projection of the substrate.

[0007] In some example embodiments, the substrate further comprises: a hole region, the peripheral area comprises a winding region located between the hole region and the display area; and the plurality of first wires and the compensation plate are located in the winding region.

[0008] In some example embodiments, the hollow structure has at least one first hollow edge, the extension direction of the at least one first hollow edge is parallel to the extension direction of at least one of the plurality of first wires, and the projection of the at least one first hollow edge on the substrate is located within the projection of the at least one of the plurality of first wires on the substrate.

[0009] In some example embodiments, the compensation plate is located on the side of the plurality of first wires close to the substrate.

[0010] In some example embodiments, the plurality of first traces are alternatively arranged in a first gate metal layer and a second gate metal layer, the second gate metal layer is located on a side of the first gate metal layer away from the substrate, and adjacent first traces in the plurality of first traces do not overlap in the orthographic projection of the substrate; and the compensation electrode plate is located in a bottom light shielding metal layer, the bottom light shielding metal layer is located on a side of the first gate metal layer close to the substrate.

[0011] In some example embodiments, the plurality of first traces include a plurality of straight trace segments extending in the same direction; and the hollow structure of the compensation electrode plate includes a plurality of first hollow portions, at least one first hollow portion in the plurality of first hollow portions has a first edge, the extension direction of the first edge is parallel to the extension direction of the plurality of straight trace segments, and one first edge of a single first hollow portion is located in the orthographic projection of the substrate within the orthographic projection range of one straight trace segment.

[0012] In some example embodiments, the orthographic projection of the at least one first hollow portion on the substrate is rectangular, the at least one first hollow portion further has a second edge, the extension direction of the second edge is perpendicular to the extension direction of the first edge, and the orthographic projection of the second edge on the substrate partially overlaps with the orthographic projection of at least two straight trace segments in the plurality of straight trace segments on the substrate.

[0013] In some example embodiments, the plurality of first hollow portions are arrayed along the extension direction of the plurality of straight trace segments, and adjacent first hollow portions are arranged in alignment in the extension direction of the plurality of straight trace segments.

[0014] In some example embodiments, the plurality of first hollow portions are arrayed along the extension direction of the plurality of straight trace segments, and at least two adjacent first hollow portions are arranged in misalignment in the extension direction of the plurality of straight trace segments.

[0015] In some example embodiments, the plurality of first hollow portions arrayed along the extension direction of the plurality of straight trace segments are a row of first hollow portions, the row of first hollow portions includes a first group of hollow portions and a second group of hollow portions arranged in alternation, the plurality of first hollow portions in the first group of hollow portions are arranged in alignment, the plurality of first hollow portions in the second group of hollow portions are arranged in alignment, and the first group of hollow portions and the second group of hollow portions are arranged in misalignment.

[0016] In some example embodiments, the plurality of first hollowed-out portions arranged along the extension direction of the plurality of straight wire segments is a row of first hollowed-out portions, the row of first hollowed-out portions comprises: a third group of hollowed-out portions and a fourth group of hollowed-out portions arranged alternately, the plurality of first hollowed-out portions in the third group of hollowed-out portions are arranged staggeredly, the plurality of first hollowed-out portions in the fourth group of hollowed-out portions are arranged staggeredly; at least one first hollowed-out portion in the third group of hollowed-out portions is arranged in alignment with at least one first hollowed-out portion in the fourth group of hollowed-out portions.

[0017] In some example embodiments, the plurality of first hollowed-out portions arranged along the extension direction of the plurality of straight wire segments is a row of first hollowed-out portions, the row of first hollowed-out portions comprises: a plurality of fifth groups of hollowed-out portions arranged sequentially, the plurality of first hollowed-out portions in the fifth group of hollowed-out portions are arranged staggeredly, adjacent fifth groups of hollowed-out portions are arranged in alignment.

[0018] In some example embodiments, the plurality of first wires comprises: a plurality of arc wire segments with the same extension direction; the hollowed-out structure of the compensation electrode plate comprises: a plurality of second hollowed-out portions; the plurality of second hollowed-out portions are arranged along the extension direction of the plurality of arc wire segments; at least one second hollowed-out portion in the plurality of second hollowed-out portions has a third edge, the extension direction of the third edge is parallel to the extension direction of the plurality of arc wire segments, the third edge of a single second hollowed-out portion is located within the orthographic projection range of an arc wire segment on the substrate in the orthographic projection of the substrate.

[0019] In some example embodiments, the hollowed-out structure of the compensation electrode plate comprises: at least one third hollowed-out portion; the at least one third hollowed-out portion extends along at least part of the edge of the hole region; the length of the first wire with the orthographic projection of the at least one third hollowed-out portion on the substrate is greater than the length of the first wire without the orthographic projection of the at least one third hollowed-out portion on the substrate.

[0020] In some example embodiments, the plurality of first wires comprises: a first group of first wires bypassing the hole region from one side of the hole region, and a second group of first wires bypassing the hole region from the other side of the hole region; the hollowed-out structure of the compensation electrode plate comprises: at least one third hollowed-out portion with the orthographic projection of the first group of first wires on the substrate, and at least one third hollowed-out portion with the orthographic projection of the second group of first wires on the substrate.

[0021] In some example embodiments, at least part of the edge of the at least one third hollow part is in the orthographic projection of the substrate in a step shape; the step shape comprises: a plurality of step structures connected in sequence, each step structure comprising a first step and a second step connected to each other; the first step and the second step are straight line segments with different extension directions; the first step of each step structure is in the orthographic projection of the substrate within the orthographic projection range of a first trace, and the second step is in the orthographic projection of the substrate overlapping with the orthographic projection of at least two adjacent first traces.

[0022] In some example embodiments, the step shape further comprises: a step connecting segment connecting adjacent step structures, the step connecting segment being an arc segment.

[0023] In another aspect, the embodiments provide a display device comprising the display substrate as described above.

[0024] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings.

[0025] SUMMARY

[0026] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0027] FIG. 1 is a schematic view of a display substrate according to at least one embodiment of the present disclosure;

[0028] FIG. 2 is a schematic view of a gate line in FIG. 1;

[0029] FIG. 3A is a schematic view of a partial cross section of a display area of a display substrate according to at least one embodiment of the present disclosure;

[0030] FIG. 3B is another schematic view of a partial cross section of a display area of a display substrate according to at least one embodiment of the present disclosure;

[0031] FIG. 4 is a schematic view of a partial cross section along the direction of Q-Q' in FIG. 2;

[0032] FIG. 5 is a schematic view of the position of a first straight line connecting segment of a gate connecting trace and a plurality of first hollow parts of a compensation plate according to at least one embodiment of the present disclosure;

[0033] FIG. 6A is a schematic view of a partial enlargement of region S1 in FIG. 1;

[0034] FIG. 6B is a schematic view of a first straight line connecting segment of a plurality of gate connecting traces in FIG. 6A;

[0035] FIG. 6C is a schematic view of a compensation plate in FIG. 6A;

[0036] FIG. 7 is another position view of the first straight connection segment of the gate connection wire and the plurality of first hollowed-out portions of the compensation electrode plate according to at least one embodiment of the present disclosure;

[0037] FIG. 8 is another position view of the first straight connection segment of the gate connection wire and the plurality of first hollowed-out portions of the compensation electrode plate according to at least one embodiment of the present disclosure;

[0038] FIG. 9 is another position view of the first straight connection segment of the gate connection wire and the plurality of first hollowed-out portions of the compensation electrode plate according to at least one embodiment of the present disclosure;

[0039] FIG. 10A is another partial enlarged view of region S1 in FIG. 1;

[0040] FIG. 10B is a view of the first straight connection segment of the plurality of gate connection wires in FIG. 10A;

[0041] FIG. 10C is a view of the compensation electrode plate in FIG. 10A;

[0042] FIG. 11A is a partial enlarged view of region S2 in FIG. 1;

[0043] FIG. 11B is a view of the plurality of arc-shaped connection segments in FIG. 11A;

[0044] FIG. 11C is a view of the compensation electrode plate in FIG. 11A;

[0045] FIG. 12 is a view of the compensation electrode plate of the winding region according to at least one embodiment of the present disclosure;

[0046] FIG. 13A is a partial view of the edge of the third hollowed-out portion according to at least one embodiment of the present disclosure;

[0047] FIG. 13B is another partial view of the edge of the third hollowed-out portion according to at least one embodiment of the present disclosure;

[0048] FIG. 14 is another view of the compensation electrode plate of the winding region according to at least one embodiment of the present disclosure;

[0049] FIG. 15 is another view of the compensation electrode plate of the winding region according to at least one embodiment of the present disclosure;

[0050] FIG. 16 is another view of the compensation electrode plate of the winding region according to at least one embodiment of the present disclosure;

[0051] FIG. 17 is another view of the compensation electrode plate of the winding region according to at least one embodiment of the present disclosure;

[0052] FIG. 18 is another view of the gate connection wire of the winding region according to at least one embodiment of the present disclosure;

[0053] FIG. 19 is a schematic view of a position of a broken line connection section of a gate connection wire and a first hollowed portion of a compensation electrode plate according to an embodiment of the present disclosure;

[0054] FIG. 20 is another schematic view of a position of a broken line connection section of a gate connection wire and a first hollowed portion of a compensation electrode plate according to an embodiment of the present disclosure;

[0055] FIG. 21 is a schematic view of a display device according to an embodiment of the present disclosure.

[0056] DETAILED DESCRIPTION

[0057] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. The embodiments can be implemented in various forms. It is readily apparent to those skilled in the art that the embodiments and the contents can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. Embodiments in the present disclosure and features in the embodiments can be arbitrarily combined so far as there is no contradiction in combination.

[0058] In the drawings, the size, the thickness, or the region of one or more constituent elements shown in the drawings can be exaggerated for clarity. Thus, one embodiment of the present disclosure should not be construed as being limited to the size, the shape, and the relative arrangement of one or more constituent elements illustrated in the drawings. The embodiments of the present disclosure are schematically shown in the drawings, and the shapes and the values are not limited to those shown in the drawings.

[0059] In this specification, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among constituent elements, and are not used to describe the quantities of the constituent elements. "A plurality of" in the present disclosure means two or more.

[0060] In this specification, in order to facilitate the description of the present specification and simplify the description, words of specification indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are used to describe the positional relationship of the constituent elements with reference to the drawings, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the constituent elements described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0061] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connected" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances.

[0062] In this specification, "electrically connected" includes the case where the constituent elements are connected together through an element having some electrical effect. The "element having some electrical effect" is not particularly limited as long as it can perform transmission of electrical signals between the connected constituent elements. Examples of the "element having some electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0063] In this specification, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region where current flows mainly.

[0064] In this specification, the first electrode can be a drain, and the second electrode can be a source, or the first electrode can be a source, and the second electrode can be a drain. In the case of using a transistor having opposite polarity, or in the case where the direction of current flow is changed in the operation of a circuit, the functions of the "source" and the "drain" are sometimes interchanged with each other. Therefore, the "source" and the "drain" can be interchanged with each other in this specification. In addition, the gate can be referred to as a control electrode.

[0065] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, for example, including a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, for example, including a state in which the angle is 85° or more and 95° or less.

[0066] In this specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly, and can be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, etc. There can be some small deformations due to tolerances, for example, there can be a fillet, an arc edge, and a deformation, etc.

[0067] In the present disclosure, "about" and "approximately" mean not strictly limited boundaries, allowing for a range of process and measurement errors. In the present disclosure, "the same" means a difference of 10% or less in the numerical value, for example, including a difference of 5% or less in the numerical value.

[0068] In the present disclosure, A extending along the direction of B means that A can include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a bar-shaped body, the main part extends along the direction of B, and the length of the main part extending along the direction of B is greater than the length of the secondary part extending along other directions. In the present disclosure, "A extends along the direction of B" means "the main part of A extends along the direction of B".

[0069] In the present disclosure, "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. In the present disclosure, "the shape of A" means the shape of the orthographic projection of A on the substrate.

[0070] With the development of display technology, there is an increasing demand for full-screen and narrow-frame. In order not to lose the effect of taking pictures, the display substrate needs to be specially designed to meet the purpose of exposing the rear camera. Among them, the display area through hole (AA hole) design is one of the main solutions for full-screen. Since no sub-pixel is arranged in the display area through hole, the originally passing through the display area through hole The wire needs to bypass the display area through hole to connect the sub-pixels on both sides of the display area through hole, therefore, for the wires transmitting the same signal, the signal load of the wire bypassing the display area through hole and the signal load of the wire not needing to bypass the display area through hole will be different, thereby causing display defects (Mura) and the like.

[0071] The embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first wires, and a compensation plate. The substrate comprises a display area and a peripheral area located on at least one side of the display area. The plurality of sub-pixels are arranged on one side of the substrate and located in the display area. The plurality of first wires are located in the peripheral area and electrically connected with the plurality of sub-pixels. The compensation plate is located in the peripheral area, and at least one insulating layer is arranged between the compensation plate and the plurality of first wires. The orthographic projection of the compensation plate on the substrate partially overlaps with the orthographic projection of the plurality of first wires on the substrate. The compensation plate has a hollow structure, and the orthographic projection of the hollow structure on the substrate partially overlaps with the orthographic projection of at least one first wire on the substrate.

[0072] In some examples, the positive projection of the compensation electrode plate on the substrate can cover the positive projection of at least one first trace on the substrate; or the positive projection of the compensation electrode plate on the substrate partially overlaps the positive projection of each of the plurality of first traces on the substrate. The positive projection of the hollow structure of the compensation electrode plate on the substrate partially overlaps the positive projection of one or more first traces on the substrate. The positive projection of the hollow structure of the compensation electrode plate on the substrate can not overlap the positive projection of at least one first trace on the substrate.

[0073] In some examples, the hollow structure of the compensation electrode plate can be located inside the compensation electrode plate, for example, can include a plurality of openings or slots independently arranged inside the compensation electrode plate. The edge of the hollow structure can not be in communication with the outer edge of the compensation electrode plate. In other examples, the hollow structure can be located at the outer edge of the compensation electrode plate, so that at least part of the edge of the hollow structure can be in communication with the outer edge of the compensation electrode plate, for example, the edge of the hollow structure can be part of the outer edge of the compensation electrode plate. The outer edge of the compensation electrode plate in the present example can be irregularly shaped.

[0074] The display substrate provided by the present embodiment can compensate the first traces by the compensation electrode plate overlapping the positive projection of the first traces on the substrate, so as to compensate the load of the first traces. Moreover, the compensation electrode plate has a hollow structure, and the overlapping area of the plurality of first traces and the compensation electrode plate on the substrate can be adjusted by the hollow structure, so as to compensate the different first traces.

[0075] In some example embodiments, the substrate can further include a hole region. The peripheral region can include a winding region between the hole region and the display region, and the plurality of first traces and the compensation electrode plate can be located in the winding region. In the present example, the compensation electrode plate arranged in the winding region can compensate the first traces winding around the hole region, so as to improve the load difference of the traces caused by the hole region.

[0076] In some example embodiments, the hollow structure can have at least one first hollow edge, the extension direction of the at least one first hollow edge is parallel to the extension direction of the at least one first trace, and the positive projection of the at least one first hollow edge on the substrate can be located in the range of the positive projection of the at least one first trace on the substrate. In the present example, the first hollow edge of the hollow structure on the substrate is covered by the positive projection of the first trace on the substrate, so as to improve the film forming effect of the upper insulating layer affected by the edge of the hollow structure, and further affect the existence of material residues (Remain) or the trace defects of the upper conductive layer.

[0077] In some example embodiments, the plurality of first traces can include a plurality of straight trace segments extending in the same direction. The hollow structure of the compensation electrode plate can include a plurality of first hollow portions. At least one of the first hollow portions can have a first edge, the first edge can extend in a direction parallel to the plurality of straight trace segments, and a projection of the first edge of the single first hollow portion on the substrate can be within a projection of one of the straight trace segments on the substrate. In this example, the first hollow edges of the hollow structure can include the first edges of the plurality of first hollow portions. In some examples, the first hollow portions can be openings provided in the compensation electrode plate. For example, the projection of the first hollow portions on the substrate can be rectangular. However, the present embodiments are not limited thereto. For example, the projection of the first hollow portions on the substrate can be annular or other shapes. This example can improve the situation of material residue or trace failure of the conductive layer above the edge of the hollow structure by providing a plurality of first hollow portions and the straight trace segments of the first traces can cover the first edges of the first hollow portions on the substrate.

[0078] In some example embodiments, the plurality of first traces can include a plurality of arcuate trace segments extending in the same direction. The hollow structure of the compensation electrode plate can include a plurality of second hollow portions. The plurality of second hollow portions can be arranged along the extending direction of the plurality of arcuate trace segments. At least one of the second hollow portions can have a third edge, the third edge can extend in a direction parallel to the plurality of arcuate trace segments, and a projection of the third edge of the single second hollow portion on the substrate can be within a projection of one of the arcuate trace segments on the substrate. In this example, the first hollow edges of the hollow structure can include the third edges of the plurality of second hollow portions. In some examples, the second hollow portions can be openings provided in the hollow electrode plate. For example, the projection of the second hollow portions on the substrate can be rectangular. However, the present embodiments are not limited thereto. For example, the projection of the second hollow portions on the substrate can be annular or other shapes. This example can improve the situation of material residue or trace failure of the conductive layer above the edge of the hollow structure by providing a plurality of second hollow portions and the arcuate trace segments of the first traces can cover the third edges of the second hollow portions on the substrate.

[0079] In some example embodiments, the hollowed structure of the compensation electrode plate can include at least one third hollowed part, and the at least one third hollowed part can extend along at least part of the edge of the hole region. The length of the first traces that have overlap with the orthographic projection of the at least one third hollowed part on the substrate can be greater than the length of the first traces that have no overlap with the orthographic projection of the at least one third hollowed part on the substrate. In some examples, the orthographic projection of the third hollowed part on the substrate can be an arc-shaped hollowed groove provided on the compensation electrode plate. However, the present embodiments are not limited thereto. For example, the third hollowed part can be a ring-shaped hollowed groove. The present example can achieve differentiated load compensation for the plurality of first traces by providing the third hollowed part extending along the edge of the hole region.

[0080] In some example embodiments, the orthographic projection of at least part of the edge of the at least one third hollowed part on the substrate can be a stepped shape. The stepped shape can include a plurality of stepped structures connected in sequence, and each stepped structure can include a first step and a second step connected to each other, and the first step and the second step can be straight line segments with different extension directions. The orthographic projection of the first step of each stepped structure on the substrate can be located within the orthographic projection range of a first trace on the substrate, and the orthographic projection of the second step on the substrate can have overlap with the orthographic projection of at least two adjacent first traces on the substrate. In the present example, the first hollowed edge of the hollowed structure can include the first steps of the plurality of stepped structures. The present example can achieve differentiated load compensation for the plurality of first traces by providing the part of the edge of the third hollowed part extending along the edge of the hole region to be a stepped shape, and can also improve the situation that the edge of the hollowed structure affects the material residue or trace failure of the conductive layer above.

[0081] The scheme of the present embodiments will be illustrated below by some examples.

[0082] FIG. 1 is a schematic view of a display substrate according to at least one embodiment of the present disclosure. FIG. 2 is a schematic view of a gate line in FIG. 1. In some examples, as shown in FIGS. 1 and 2, the display substrate can include a hole region A2, a display region A1 located at least one side of the hole region A2, and a peripheral region BB located at least one side of the display region A1. The peripheral region BB can include a winding region B5 located between the hole region A2 and the display region A1, a first peripheral region B1 and a fourth peripheral region B4 located on both sides of the display region A1 along a second direction Y, and a second peripheral region B2 and a third peripheral region B3 located on both sides of the display region A1 along a first direction X. The first peripheral region B1 can be in communication with the second peripheral region B2 and the third peripheral region B3, and connected with the display region A1; the fourth peripheral region B4 can be in communication with the second peripheral region B2 and the third peripheral region B3, and connected with the display region A1. The first peripheral region B1, the second peripheral region B2, the third peripheral region B3, and the fourth peripheral region B4 can surround the display region A1 after being in communication. For example, the first peripheral region B1 can be a lower bezel region of the display substrate, the second peripheral region B2 can be a left bezel region of the display substrate, the third peripheral region B3 can be a right bezel region of the display substrate, and the fourth peripheral region B4 can be an upper bezel region of the display substrate. However, the present embodiments are not limited thereto.

[0083] In some examples, no sub-pixels can be disposed in the hole region A2, and the hole region A2 can not be used for display; in other words, the hole region A2 can be a non-display region. No sub-pixels can be disposed in the winding region B5, and the winding region B5 can not be used for display.

[0084] In some examples, a shape of a projection of the hole region A2 can be a circle, for example, a diameter of the hole region A2 can range from 6 mm to 20 mm, for example, can be about 12 mm. However, the present embodiments are not limited thereto. In other examples, the shape of the projection of the hole region A2 can be a rectangle, a rounded rectangle, an ellipse, a semicircle, a pentagon, or a hexagon, etc.

[0085] In some examples, an edge of the hole region A2 can be an inner edge of the winding region B5, and an outer edge of the winding region B5 can be connected with the display region A1. For example, a shape of a projection of the hole region A2 can be a circle, and a shape of a projection of the winding region B5 can be a circular ring. However, the present embodiments are not limited thereto. In other examples, a shape of a projection of the winding region can match a shape of the hole region; for example, a shape of a projection of the hole region is a rectangle, and a shape of a projection of the winding region can be a rectangular ring; or a shape of a projection of the hole region is an ellipse, and a shape of a projection of the winding region can be an elliptical ring.

[0086] In some examples, the hole region A2 can be located at a middle position of the display region A1, such that the display region A1 can surround the hole region A2. However, the present embodiment is not limited thereto. In other examples, the hole region can be adjacent to an upper edge or a lower edge of the display region, such that the display region can surround at least the left side and the right side of the hole region.

[0087] In some examples, the display region A1 can include a plurality of sub-pixels PX constituting a pixel array, which can be configured to display dynamic pictures or still images. For example, the display substrate can employ a flexible substrate, and thus the display substrate can be deformable, such as being crimped, bent, folded, or rolled up.

[0088] In some examples, the display region A1 can include a plurality of gate lines and a plurality of data lines. The plurality of gate lines can extend along a first direction X and be arranged along a second direction Y; the plurality of data lines can extend along the second direction Y and be arranged along the first direction X. The plurality of gate lines and the plurality of data lines can intersect to form a plurality of sub-pixel regions in the orthographic projection of the substrate, each sub-pixel region being configured to have one sub-pixel PX. The plurality of data lines can be electrically connected to the plurality of sub-pixels PX and configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines can be electrically connected to the plurality of sub-pixels PX and configured to provide gate driving signals to the plurality of sub-pixels PX. For example, the gate driving signals can include scan signals, or can include scan signals and light-emitting control signals, or can include scan signals, reset control signals, and light-emitting control signals. In some examples, the second direction Y can be the extension direction of the data lines in the display region A1; the first direction X can be the extension direction of the gate lines in the display region A1. The first direction X and the second direction Y can intersect each other, such as being perpendicular to each other.

[0089] In some examples, the plurality of gate lines can include a plurality of first-type gate lines 311 and a plurality of second-type gate lines 312. Each gate line can be connected to a plurality of sub-pixels arranged along the first direction X. Since the hole region A2 is not provided with sub-pixels, the number of sub-pixels connected to at least one first-type gate line 311 can be less than the number of sub-pixels connected to at least one second-type gate line 312. The signal load of at least one first-type gate line 311 can be less than the signal load of at least one second-type gate line 312.

[0090] In some examples, the plurality of second-type gate lines 312 can extend along the first direction X and be arranged along the second direction Y. For example, the plurality of second-type gate lines 312 can be divided into two groups arranged along the second direction Y, and the plurality of first-type gate lines 311 can be located between the two groups of second-type gate lines 312 in the second direction Y.

[0091] In some examples, as shown in FIG. 2, the plurality of first type gate lines 311 are truncated by the aperture area A2 in the first direction X. The first type gate lines 311 can include a first gate extension 311-1 and a second gate extension 311-2 located in the display area A1. The first gate extension 311-1 and the second gate extension 311-2 can be connected by a gate connection wire 33 located in the wire winding area B5. The gate connection wire 33 can be wound along the aperture area A2.

[0092] In some examples, the first gate extension 311-1 and the second gate extension 311-2 of the first type gate lines 311 and the gate connection wire 33 can be an integrated structure connected to each other; or the first gate extension 311-1 and the second gate extension 311-2 can be located in the same conductive layer, and the conductive layer where the gate connection wire 33 is located can be different from the conductive layer where the first gate extension 311-1 is located.

[0093] In some examples, at least one gate connection wire 33 located in the wire winding area B5 can include a first straight connection segment 331, a second straight connection segment 332, and an arc-shaped connection segment 333. The first straight connection segment 331 and the second straight connection segment 332 can extend along the first direction X and be located on both sides of the aperture area A2 along the first direction X. The arc-shaped connection segment 333 can be connected between the first straight connection segment 331 and the second straight connection segment 332. The first straight connection segment 331 can be connected to the first gate extension 311-1, and the second straight connection segment 332 can be connected to the second gate extension 311-2. For example, the first straight connection segment 331, the second straight connection segment 332, and the arc-shaped connection segment 333 can be an integrated structure connected to each other.

[0094] In some examples, the plurality of data lines can include a plurality of first type data lines 321 and a plurality of second type data lines 322. Each data line can be connected to a plurality of sub-pixels arranged along the second direction Y. Since the aperture area A2 does not have sub-pixels arranged thereon, the number of sub-pixels connected by at least one first type data line 321 can be less than the number of sub-pixels connected by at least one second type data line 322, and the signal load of the at least one first type data line 321 can be less than the signal load of the at least one second type data line 322.

[0095] In some examples, the plurality of second type data lines 322 can extend along the second direction Y and be arranged along the first direction X. For example, the plurality of second type data lines 322 can be divided into two groups arranged along the first direction X, and the plurality of first type data lines 321 can be located between the two groups of second type data lines 322 along the first direction X.

[0096] In some examples, the plurality of first-type data lines 321 are cut off by the hole region A2 in the second direction Y. The first-type data lines 321 can include a first data connection segment 321-1 and a second data connection segment 321-2 located in the display region A1. The first data connection segment 321-1 and the second data connection segment 321-2 can be connected by a data connection wire 34 located in the winding region B5. The data connection wire 34 can be wound along the hole region A2.

[0097] In some examples, the first data connection segment 321-1 and the second data connection segment 321-2 of the first-type data lines 321 and the data connection wire 34 can be an integrated structure connected to each other, or the first data connection segment 321-1 and the second data connection segment 321-2 can be located in the same conductive layer, and the conductive layer where the data connection wire 34 is located can be different from the conductive layer where the first data connection segment 321-1 is located.

[0098] In some examples, one pixel unit of the display region A1 can include three sub-pixels, which can be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, the present embodiment is not limited thereto. In some examples, one pixel unit can include four sub-pixels, which can be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For example, one pixel unit can include four sub-pixels, which can include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0099] In some examples, one sub-pixel PX can include a pixel circuit and a light emitting element electrically connected to the pixel circuit. The pixel circuit can include a plurality of transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, and the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit can include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel circuit can be P-type transistors or can be N-type transistors, and the use of the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0100] In some examples, the shape of the light emitting element of a sub-pixel can be rectangular, rhombic, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light emitting elements of the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner. When a pixel unit includes four sub-pixels, the light emitting elements of the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square manner. However, the present embodiments are not limited thereto.

[0101] In some examples, the light emitting element can be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light emitting element can be an OLED, which can emit red light, green light, blue light, white light, etc. under the driving of the corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined as needed. In some examples, the light emitting element can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element can be electrically connected to the corresponding pixel circuit. However, the present embodiments are not limited thereto.

[0102] FIG. 3A is a schematic view of a partial cross-section of a display area of a display substrate according to at least one embodiment of the present disclosure. In FIG. 3A, the structure of one sub-pixel of the display area is taken as an example for illustration. In the present example, the transistor types of the plurality of pixel transistors in the pixel circuit can be different, for example, can include low-temperature polysilicon thin film transistors and oxide thin film transistors.

[0103] In some examples, as shown in FIG. 3A, in a direction perpendicular to the display substrate, the display area of the display substrate can include a substrate 10, and a circuit structure layer 12, a light emitting structure layer 13, and an encapsulation structure layer 14 sequentially arranged on the substrate 10. The circuit structure layer 12 can at least include the pixel circuit of a plurality of sub-pixels, and each sub-pixel can include a plurality of transistors and at least one capacitor. The light emitting structure layer 13 can at least include the light emitting element of a plurality of sub-pixels. In other examples, the display substrate can further include a touch structure layer on the side of the encapsulation structure layer away from the substrate. For example, the touch structure layer can include at least one touch conductive layer.

[0104] In some examples, one first transistor 21, one second transistor 22 and one capacitor 23 are included in each sub-pixel in FIG. 3A. The transistor types of the first transistor 21 and the second transistor 22 can be different. Among them, the first transistor 21 can be a low-temperature polysilicon thin-film transistor, and the second transistor 22 can be an oxide thin-film transistor. Alternatively, the first transistor 21 can be an oxide thin-film transistor, and the second transistor 22 can be a low-temperature polysilicon thin-film transistor.

[0105] In some examples, the circuit structure layer 12 of the display area can include a bottom shielding metal layer (BSM), a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer and a second source-drain metal layer, which are arranged on the substrate 10. The first insulating layer 101, which can also be referred to as a buffer layer, can be arranged between the bottom shielding metal layer and the first semiconductor layer. The second insulating layer 102 can be arranged between the first semiconductor layer and the first gate metal layer. The third insulating layer 103 can be arranged between the first gate metal layer and the second gate metal layer. The fourth insulating layer 104 can be arranged between the second gate metal layer and the second semiconductor layer. The fifth insulating layer 105 can be arranged between the second semiconductor layer and the third gate metal layer. The second insulating layer 102 to the fifth insulating layer 105 can also be referred to as a gate insulating layer. The sixth insulating layer 106, which can also be referred to as an interlayer insulating layer, can be arranged between the third gate metal layer and the first source-drain metal layer. The seventh insulating layer 107 and the eighth insulating layer 108 can be arranged between the first source-drain metal layer and the second source-drain metal layer. The eighth insulating layer 108 can be located on the side of the seventh insulating layer 107 away from the substrate 10. The ninth insulating layer 109 can be arranged on the side of the second source-drain metal layer away from the substrate 10. The seventh insulating layer 107 can also be referred to as a passivation layer. The eighth insulating layer 108 can also be referred to as a first planarization layer. The ninth insulating layer 109 can also be referred to as a second planarization layer. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105 and the sixth insulating layer 106 can be inorganic insulating layers. The eighth insulating layer 108 and the ninth insulating layer 109 can be organic insulating layers. However, the present embodiment is not limited thereto. In other examples, a buffer layer can also be arranged on the side of the bottom shielding metal layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the inside of the display substrate, and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, the seventh insulating layer can be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the eighth insulating layer can be arranged between the first source-drain metal layer and the second source-drain metal layer.

[0106] In some examples, as shown in FIG. 3A, the light-shielding metal layer at the bottom of the display region can include at least: a light-shielding block 25. The light-shielding block 25 can be configured to at least partially cover the active layer of the transistor of the pixel circuit to avoid the influence of external light on the performance of the transistor. For example, the light-shielding block 25 can be electrically connected with the constant voltage signal line of the peripheral region, such as the light-shielding block 25 can be configured to receive the first power signal. The first semiconductor layer of the display region can include at least: the first active layer 210 of the first transistor 21. The first active layer 210 of the first transistor 21 can include: a first region 2101, a second region 2102, and a channel region 2100 between the first region 2101 and the second region 2102. The first gate metal layer can include at least: the first gate 213 of the first transistor 21, and the first plate 231 of the capacitor 23. The first gate 213 of the first transistor 21 can cover the channel region 2100 of the first active layer 210 in the orthographic projection of the substrate 10. The second gate metal layer can include at least: the second plate 232 of the capacitor 23. The second plate 232 and the first plate 231 of the capacitor 23 can at least partially overlap in the orthographic projection of the substrate 10, for example, the two can coincide. The second semiconductor layer can include at least: the second active layer 220 of the second transistor 22. The third gate metal layer can include at least: the second gate 223 of the second transistor 22. The second gate 223 of the second transistor 22 can partially overlap with the second active layer 220 in the orthographic projection of the substrate 10.

[0107] In some examples, as shown in FIG. 3A, the first source-drain metal layer can at least include: the first source 211 and the first drain 212 of the first transistor 21, the second source 221 and the second drain 222 of the second transistor 22. The sixth insulating layer 106 can be provided with a plurality of pixel vias (for example, including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The sixth insulating layer 106, the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 in the first pixel via can be removed to expose at least part of the surface of the first region 2101 of the first active layer 210; the sixth insulating layer 106, the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 in the second pixel via can be removed to expose at least part of the surface of the second region 2102 of the first active layer 210. The sixth insulating layer 106 and the fifth insulating layer 105 in the third pixel via and the fourth pixel via can be removed to expose at least part of the surface of both ends of the second active layer 220. The first source 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can at least include: the first transfer electrode 241. The first transfer electrode 241 can be electrically connected to the first drain 212 of the first transistor 21 of the pixel circuit through the fifth pixel via provided by the eighth insulating layer 108 and the seventh insulating layer 107. The present example can realize electrical connection between the pixel circuit and the light emitting element through the first transfer electrode 241.

[0108] In some examples, as shown in FIG. 3A, the light-emitting structure layer 13 can include a pixel definition layer 134 and a plurality of light-emitting elements. For example, each light-emitting element can include a first electrode 131, an organic light-emitting layer 132, and a second electrode 133 stacked. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be electrically connected to the first transfer electrode 241 through a sixth pixel via hole formed in the ninth insulating layer 109 and disposed on the ninth insulating layer 109. The pixel definition layer 134 is disposed on the first electrode 131 and the ninth insulating layer 109, and the pixel definition layer 134 can be provided with a plurality of pixel openings, and each pixel opening can expose at least part of the surface of the corresponding first electrode 131. At least part of the organic light-emitting layer 132 can be disposed in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0109] In some examples, the organic light-emitting layer 132 of the light-emitting element can include an emitting layer (EML) and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting element can emit light according to the required gray scale by utilizing the light-emitting property of the organic material.

[0110] In some examples, the light-emitting layers of the light-emitting elements of different colors can be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer located on one side of the light-emitting layer can adopt a common layer, and the electron injection layer and the electron transport layer located on the other side of the light-emitting layer can adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by one process (one evaporation process or one inkjet printing process), and isolation can be achieved by forming a film layer surface step difference or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be prepared by evaporation using a fine metal mask (FMM) or an open mask, or by using an inkjet process.

[0111] In some examples, as shown in FIG. 3A, the encapsulation structure layer 14 can include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. The first encapsulation layer 141 and the third encapsulation layer 143 can be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic materials have high density and can prevent the invasion of water, oxygen, etc. The second encapsulation layer 142 can be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external water vapor from entering the light-emitting element. The second encapsulation layer 142 can be made of organic materials, such as a high polymer material containing a desiccant or a high polymer material that can block water vapor, etc., or a high polymer resin, etc. to planarize the surface of the display substrate, and can relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and can also include a water-absorbing material such as a desiccant to absorb water, oxygen, etc. that invade the inside. However, the present embodiment is not limited thereto. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0112] FIG. 3B is another partial cross-sectional view of a display area of a display substrate according to at least one embodiment of the present disclosure. In the present example, the transistor types of the plurality of pixel transistors in the pixel circuit can be the same, for example, all can be low-temperature polysilicon thin film transistors. In FIG. 3B, a first transistor 21 and a capacitor 23 included in each sub-pixel are taken as examples for illustration.

[0113] In some examples, as shown in FIG. 3B, the circuit structure layer 12 of the display area can include a bottom light shielding metal layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 10. A first insulating layer 101 can be disposed between the bottom light shielding metal layer and the first semiconductor layer, a second insulating layer 102 can be disposed between the first semiconductor layer and the first gate metal layer, a third insulating layer 103 can be disposed between the first gate metal layer and the second gate metal layer, a fourth insulating layer 104 can be disposed between the second gate metal layer and the first source-drain metal layer, a seventh insulating layer 107 and an eighth insulating layer 108 can be disposed between the first source-drain metal layer and the second source-drain metal layer, and a ninth insulating layer 109 can be disposed on a side of the second source-drain metal layer away from the substrate 10. The eighth insulating layer 108 and the ninth insulating layer 109 can be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can be inorganic insulating layers. The remaining structures of the display area of the display substrate of the present example can refer to the description of the embodiment shown in FIG. 3A, and thus will not be described here.

[0114] In some examples, the pixel circuit can include eight pixel transistors (i.e., a first pixel transistor to an eighth pixel transistor) and one storage capacitor. The second pixel transistor can be an oxide thin film transistor, and the first pixel transistor, the third pixel transistor to the eighth pixel transistor can be low-temperature polysilicon thin film transistors.

[0115] In some examples, the gate of the third pixel transistor is electrically connected with the first node, the first electrode of the third pixel transistor is electrically connected with the second node, and the second electrode of the third pixel transistor is electrically connected with the third node. The gate of the fourth pixel transistor is electrically connected with the first scan line, the first electrode of the fourth pixel transistor is electrically connected with the data line, and the second electrode of the fourth pixel transistor is electrically connected with the second node. The gate of the second pixel transistor is electrically connected with the second scan line, the first electrode of the second pixel transistor is electrically connected with the third node, and the second electrode of the second pixel transistor is electrically connected with the first node. The gate of the fifth pixel transistor is electrically connected with the light-emitting control line, the first electrode of the fifth pixel transistor is electrically connected with the first power supply line, and the second electrode of the fifth pixel transistor is electrically connected with the second node. The gate of the sixth pixel transistor is electrically connected with the light-emitting control line, the first electrode of the sixth pixel transistor is electrically connected with the third node, and the second electrode of the sixth pixel transistor is electrically connected with the fourth node. The gate of the first pixel transistor is electrically connected with the first reset control line, the first electrode of the first pixel transistor is electrically connected with the first initial signal line, and the second electrode of the first pixel transistor is electrically connected with the third node. The first pixel transistor can be configured to reset the third node. The gate of the seventh pixel transistor is electrically connected with the second reset control line, the first electrode of the seventh pixel transistor is electrically connected with the second initial signal line, and the second electrode of the seventh pixel transistor is electrically connected with the fourth node. The seventh pixel transistor can be configured to reset the fourth node. The gate of the eighth pixel transistor is electrically connected with the second reset control line, the first electrode of the eighth pixel transistor is electrically connected with the third initial signal line, and the second electrode of the eighth pixel transistor is electrically connected with the second node. The eighth pixel transistor can be configured to reset the second node. The first electrode of the storage capacitor is electrically connected with the first node, and the second electrode of the storage capacitor is electrically connected with the first power supply line.

[0116] In some examples, taking the film layer structure of the display substrate shown in FIG. 3A as an example, the plurality of gate lines can be located in the first gate metal layer and the second gate metal layer, and the plurality of data lines can be located in the first source-drain metal layer and the second source-drain metal layer. For example, the plurality of gate lines can include a plurality of first scan lines, a plurality of second scan lines, a plurality of light-emitting control lines, a plurality of first reset control lines, and a plurality of second reset control lines; wherein the plurality of first scan lines and the plurality of first reset control lines can be disposed in the first gate metal layer, and the plurality of second scan lines, the plurality of light-emitting control lines, and the plurality of second reset control lines can be disposed in the second gate metal layer.

[0117] In some examples, the plurality of gate connection wires located in the winding area can be alternatively arranged in the first gate metal layer and the second gate metal layer. For example, the gate connection wires connected with the first scan lines can be located in the first gate metal layer, the gate connection wires connected with the first reset control lines can be located in the first gate metal layer, the gate connection wires connected with the second scan lines can be located in the second gate metal layer, the gate connection wires connected with the light-emitting control lines can be located in the second gate metal layer, and the gate connection wires connected with the second reset control lines can be located in the second gate metal layer. The plurality of data connection wires located in the winding area can be alternatively arranged in the first source-drain metal layer and the second source-drain metal layer. However, the present embodiment is not limited thereto.

[0118] In some examples, the plurality of first wires located in the winding area can include a first group of first wires winding around the hole area A2 from one side of the hole area A2 and a second group of first wires winding around the hole area A2 from the other side of the hole area A2. For example, the plurality of first wires located in the winding area can include the plurality of gate connection wires 33. The hole area A2 can have a first center line extending through a center point of the hole area A2 along the first direction X. The first group of first wires can include the plurality of gate connection wires 33 located on one side of the first center line along the second direction Y, such as the plurality of gate connection wires 33 winding around the hole area A2 from the top side, and the second group of first wires can include the plurality of gate connection wires 33 located on the other side of the first center line along the second direction Y, such as the plurality of gate connection wires 33 winding around the hole area A2 from the bottom side.

[0119] FIG. 4 is a schematic view of a partial cross section along the direction Q-Q’ in FIG. 2. In some examples, as shown in FIGS. 2 and 4, the plurality of gate connection wires 33 located in the winding area B5 can include gate connection wires 33a located in the first gate metal layer and gate connection wires 33b located in the second gate metal layer. The plurality of gate connection wires 33a and the plurality of gate connection wires 33b can be alternatively arranged, and adjacent gate connection wires 33a and 33b can not overlap in the orthographic projection of the substrate 10. The plurality of data connection wires 34 located in the winding area B5 can include data connection wires 34a located in the first source-drain metal layer and data connection wires 34b located in the second source-drain metal layer. Adjacent data connection wires 34a and 34b can not overlap in the orthographic projection of the substrate 10.

[0120] In some examples, the winding region B5 may be provided with a compensation plate 36. The compensation plate 36 may be configured to receive a constant voltage signal, such as a first power signal provided by a first power line, or a second power signal provided by a second power line. The compensation plate 36 may be located in the bottom light-shielding metal layer, and the orthographic projection of the compensation plate 36 onto the substrate 10 may at least partially overlap with the orthographic projections of the multiple gate connection traces 33a and 33b onto the substrate 10. For example, the orthographic projection of the compensation plate 36 onto the substrate 10 may cover a portion of the orthographic projections of the gate connection traces onto the substrate 10, and may partially overlap with another portion of the orthographic projections of the gate connection traces onto the substrate 10; or, the orthographic projection of the compensation plate 36 onto the substrate 10 may partially overlap with the orthographic projections of all the gate connection traces onto the substrate 10. This example demonstrates that by setting a compensation plate 36 in the bottom light-shielding metal layer, capacitance compensation can be performed on the gate connection traces located in the first and second gate metal layers within the winding area B5. This results in load compensation for the first type of gate lines connected to the gate connection traces, ensuring that the load of the first type of gate lines after compensation is approximately the same as that of the second type of gate lines, thereby guaranteeing the display effect.

[0121] In some examples, a compensation electrode 36 can be provided in the winding region B5. The orthographic projection of the compensation electrode 36 onto the substrate can be an annular shape with a hollow structure. The outer edge of the compensation electrode 36 can be approximately the same shape as the edge of the winding region B5. In this example, by providing a large-area compensation electrode, it is possible to avoid setting thin lines in the bottom light-shielding metal layer, thereby preventing the bottom light-shielding metal layer from affecting the wiring of the upper conductive layer.

[0122] In some examples, the compensation electrode plate 36 can have a hollow structure, and a projection of the substrate and a projection of at least one gate connection wire on the substrate can partially overlap. By arranging the hollow structure, the present example can avoid the peeling problem caused by a large-area compensation electrode plate. Moreover, by arranging the hollow structure, the overlapping area of the compensation electrode plate and different gate connection wires can be adjusted, thereby facilitating differential capacitance compensation for different gate connection wires. However, at the edge position of the compensation electrode plate (for example, the edge position of the hollow structure), the film forming effect of the inorganic film layer above the compensation electrode plate will be poor, for example, narrow gaps or recessed positions are generated, so that the conductive layer above the inorganic film layer will have a remaining condition, which is easy to cause wire defects and the like, thereby affecting the display effect of the display substrate. For example, taking the film layer structure of the display substrate shown in FIG. 3B as an example, the compensation electrode plate can be located at the bottom light shielding metal layer, and the plurality of gate connection wires can be located at the first gate metal layer and the second gate metal layer. The film forming effect of the inorganic insulating layer (for example, including the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104) above the edge position of the compensation electrode plate will be poor, thereby causing the first source-drain metal layer to easily generate metal residues, wire defects, and the like at the area corresponding to the edge position of the compensation electrode plate. By designing the hollow structure of the compensation electrode plate, and covering part of the edge of the hollow structure of the compensation electrode plate by the first gate metal layer and the second gate metal layer, the present example can improve the metal residues or wire defects of the conductive film layer above the edge position of the hollow structure of the compensation electrode plate.

[0123] FIG. 5 is a schematic view of the position relationship between the first straight connection segment of the gate connection wire and the plurality of first hollow parts of the compensation electrode plate according to at least one embodiment of the present disclosure. In the present example, the hollow structure of the compensation electrode plate can have a plurality of first hollow parts, and the plurality of straight wire segments of the plurality of first wires can include the first straight connection segment and the second straight connection segment of the plurality of gate connection wires. FIG. 5 illustrates the position relationship between the first straight connection segment and the first hollow part as an example, and the position relationship between the second straight connection segment and the first hollow part can refer to the position relationship between the first straight connection segment and the first hollow part, which will not be described here.

[0124] In some examples, as shown in FIG. 5, the first straight connection segment 331 of the plurality of gate connection wires 33 can extend along the first direction X and be arranged along the second direction Y in sequence. The plurality of first straight connection segments 331 can be located at the same conductive layer (for example, the first gate metal layer or the second gate metal layer), or can be alternately arranged at the first gate metal layer and the second gate metal layer. The present embodiment is not limited in this regard.

[0125] In some examples, as shown in FIG. 5, the hollow structure of the compensation electrode plate can have a plurality of first hollows 41. The plurality of first hollows 41 can be arranged in an array along the first direction X and the second direction Y. A row of first hollows in the present example can include a plurality of first hollows 41 arranged along the first direction X, and a column of first hollows can include a plurality of first hollows 41 arranged along the second direction Y. A row of first hollows can be arranged in alignment along the first direction X. A column of first hollows can be arranged in alignment along the second direction Y.

[0126] In some examples, the first hollow 41 can be an opening provided on the compensation electrode plate. The orthographic projection of the first hollow 41 on the substrate can be rectangular. The first hollow 41 can have a first edge 411 and a second edge 412 arranged in parallel with each other, and a second edge 413 and a fourth edge 414 arranged in parallel with each other. The first edge 411, the second edge 413, the first edge 412 and the second edge 414 can be connected in sequence. The extension direction of the first edge 411 can be perpendicular to the extension direction of the second edge 413. The extension direction of the first edge 411 and the second edge 412 can be parallel to the extension direction of the plurality of first straight connection segments 331, and the extension direction of the second edge 413 and the fourth edge 414 can be perpendicular to the extension direction of the plurality of first straight connection segments 331.

[0127] In some examples, the orthographic projection of the first edge 411 of the first hollow 41 on the substrate can be located within the orthographic projection range of one of the first straight connection segments 331 on the substrate, and the orthographic projection of the first edge 412 on the substrate can be located within the orthographic projection range of another of the first straight connection segments 331 on the substrate. In some examples, the orthographic projection of the first edge 411 on the substrate can be located at the middle position of the orthographic projection of one of the first straight connection segments 331 on the substrate along the second direction Y. The orthographic projection of the first edge 412 on the substrate can be located at the middle position of the orthographic projection of another of the first straight connection segments 331 on the substrate along the second direction Y. For example, the orthographic projection of the first edge 411 on the substrate can coincide with the middle line of the orthographic projection of one of the first straight connection segments 331 on the substrate along the second direction Y. The orthographic projection of the first edge 412 on the substrate can coincide with the middle line of the orthographic projection of another of the first straight connection segments 331 on the substrate along the second direction Y.

[0128] In some examples, the first straight connection segment 331 on which the orthographic projection of the first edge 411 on the substrate is located and the first straight connection segment 331 on which the orthographic projection of the first edge 412 on the substrate is located can not have an adjacent, and at least one first straight connection segment (for example, two first straight connection segments) can be provided between the two first straight connection segments 331.

[0129] In some examples, the second edges 413 and 414 of the first hollowed parts 41 can be partially overlapped with the projections on the substrate of the plurality of first straight connection segments 331 (e.g., four or three first straight connection segments 331). The lengths of the second edges 413 and 414 can be the same, and the length of the second edge 413 can be greater than the line width of at least two first straight connection segments 331. The length of the first edge 411 can be the same as or different from the length of the second edge 413. The present embodiment is not limited in this regard.

[0130] In some examples, the projection on the substrate of a first straight connection segment 331 can cover the projection on the substrate of the first edges 411 of the plurality of first hollowed parts 41 in a row of first hollowed parts, or can cover the projection on the substrate of the first edges 412 of the plurality of first hollowed parts 41 in a row of first hollowed parts.

[0131] The arrangement of the first hollowed parts in the present example can improve the influence of the boundary position of the compensation electrode plate (e.g., the edge position of the first hollowed part) on the upper inorganic film layer and the conductive layer (e.g., the first source / drain metal layer), and can prevent material residue and wire disconnection of the conductive layer.

[0132] FIG. 6A is a partial enlarged view of the region S1 in FIG. 1. FIG. 6B is a schematic view of the first straight connection segments of the plurality of gate connection wires in FIG. 6A. FIG. 6C is a schematic view of the compensation electrode plate in FIG. 6A. FIGS. 6A-6C schematically show the partial overlap between the first straight connection segments of the gate connection wires and the compensation electrode plate.

[0133] In some examples, as shown in FIGS. 6A-6C, the first straight connection segments 331a of the gate connection wires 33a in the first gate metal layer can extend along the first direction X, and the first straight connection segments 331b of the gate connection wires 33b in the second gate metal layer can extend along the first direction X. The first straight connection segments 331a of the plurality of gate connection wires 33a and the first straight connection segments 331b of the plurality of gate connection wires 33b can be alternately arranged along the second direction Y. The projections on the substrate of the first straight connection segments 331a and 331b can not overlap. The line widths of the first straight connection segments 331a and 331b can be the same.

[0134] In some examples, the compensation electrode plate 36 can be located in the bottom light shielding metal layer. The compensation electrode plate 36 can have a plurality of first hollowed parts 41 arranged in an array along the first direction X and the second direction Y. The plurality of first hollowed parts 41 can be arranged in alignment along the first direction X and the second direction Y.

[0135] In some examples, the first hollow part 41 can have a rectangular shape in the orthographic projection of the substrate. The first hollow part 41 can have first edges 411 and 412 arranged in parallel, and second edges 413 and 414 arranged in parallel. The first edges 411 and 412 can extend along the first direction X. The extending direction of the first edges 411 and 412 can be the same as the extending direction of the first straight connection segments 331a and 331b. The extending direction of the second edges 413 and 414 can be perpendicular to the extending direction of the first straight connection segments 331a and 331b. The orthographic projection of the first edge 411 (or 412) of the first hollow part 41 in the substrate can be within the orthographic projection of a first straight connection segment 331a (or 331b) in the substrate. The orthographic projection of the second edge 413 (or 414) of the first hollow part 41 in the substrate can overlap with the orthographic projection of a plurality of first straight connection segments (for example, four or three first straight connection segments) in the substrate. The length of the second edge 413 (or 414) can be greater than the line width of at least two first straight connection segments.

[0136] The present example can improve the compensation of the influence of the boundary position of the compensation electrode plate (for example, the edge position of the first hollow part) on the upper inorganic film layer and the conductive layer by arranging a plurality of first hollow parts along the extending direction of the first straight connection segments, and the orthographic projection of the plurality of first straight connection segments in the substrate can cover the orthographic projection of the first edges of the plurality of first hollow parts in the substrate. The present example can prevent material residues and poor wiring of the upper conductive layer (for example, the first source / drain metal layer).

[0137] FIG. 7 is another schematic view of the first straight connection segments of the gate connection wiring and the plurality of first hollow parts of the compensation electrode plate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 7, the compensation electrode plate can have a plurality of first hollow parts 41. The plurality of first hollow parts 41 can be arranged in an array along the first direction X and the second direction Y. The plurality of first hollow parts 41 can be arranged in alignment in the second direction Y; along the first direction X, at least two adjacent first hollow parts 41 can be arranged in a staggered manner. For example, a plurality of adjacent first hollow parts 41 (for example, six first hollow parts) in a row of first hollow parts can be arranged in a stepped manner. For example, each first hollow part 41 can have a center line passing through the center point and extending along the first direction X, and the center lines of the six adjacent first hollow parts 41 in a row of first hollow parts can be arranged in sequence along the second direction Y, and the minimum distance between the center lines of any two adjacent first hollow parts 41 can be the same. The present embodiment is not limited in this regard.

[0138] In some examples, as shown in FIG. 7, the first hollow part 41 can have a rectangular shape in the orthographic projection of the substrate. The first edges 411 and 412 of the first hollow part 41 can extend in parallel to the first direction X, and the orthographic projection of the first edges 411 and 412 can be located within the orthographic projection range of two different first straight connection segments 331. The second edges 413 and 414 of the first hollow part 41 can extend in parallel to the second direction Y, and the orthographic projection of the second edges 413 and 414 can overlap with the orthographic projection of a plurality of (for example, four) first straight connection segments 331.

[0139] The present example can achieve the same load of the plurality of first straight connection segments after compensation of the compensation electrode plate by staggered arrangement of the plurality of first hollow parts, thereby achieving differential load compensation of the plurality of gate connection traces.

[0140] FIG. 8 is another position diagram of the first straight connection segment of the gate connection trace and the plurality of first hollow parts of the compensation electrode plate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 8, the plurality of first hollow parts 41 of the compensation electrode plate can be arranged along the first direction X and the second direction Y. The plurality of first hollow parts 41 can be arranged in alignment along the second direction Y. The plurality of first hollow parts X can be arranged staggered along the first direction X. One row of first hollow parts can include a first group of hollow parts 41a and a second group of hollow parts 41b arranged alternately along the first direction X, and the number of first hollow parts included in the first group of hollow parts 41a and the second group of hollow parts 41b can be the same. However, the present embodiment is not limited thereto. For example, the number of first hollow parts included in the first group of hollow parts 41a and the second group of hollow parts 41b can be different. For example, the number of first hollow parts included in the first group of hollow parts 41a can be greater than the number of first hollow parts included in the second group of hollow parts 41b.

[0141] In some examples, the first group of hollow parts 41a can include a plurality of first hollow parts 41 (for example, three first hollow parts) arranged in alignment along the first direction X; and the second group of hollow parts 41b can include a plurality of first hollow parts 41 (for example, three first hollow parts) arranged in alignment along the first direction X. The center lines of the plurality of first hollow parts 41 in the first group of hollow parts 41a in parallel to the first direction X can coincide, and the center lines of the plurality of first hollow parts 41 in the second group of hollow parts 41b in parallel to the first direction X can coincide.

[0142] In some examples, the first group of hollow parts 41a and the second group of hollow parts 41b can be arranged staggered along the first direction X. For example, the center line of the first group of hollow parts 41a in parallel to the first direction X can be located on one side of the center line of the second group of hollow parts 41b in parallel to the first direction X along the second direction Y.

[0143] In the example, the first straight connection segment 331 of the plurality of gate connection wires 33 can have different overlapping areas with the compensation electrode plate in the substrate. In some examples, the first straight connection segment (e.g., the first straight connection segment 331-1) that overlaps with both the first set of hollow parts 41a and the second set of hollow parts 41b in the substrate can have a smaller overlapping area with the compensation electrode plate than the first straight connection segment (e.g., the first straight connection segment 331-2 or 331-3) that overlaps with only the first set of hollow parts 41a or the second set of hollow parts 41b in the substrate. The compensation electrode plate can have a smaller compensation capacitance for the first straight connection segment 331-1 than for the first straight connection segment 331-2 or 331-3. In this way, the compensation electrode plate can focus on signal compensation for the first straight connection segments 331-2 and 331-3, thereby achieving differential compensation for different gate connection wires. The edge of the single first hollow part and the projection of the first straight connection segment in the substrate can be the same as described in the foregoing embodiments, and thus will not be described here.

[0144] FIG. 9 is another position diagram of the first straight connection segment of the gate connection wire and the plurality of first hollow parts of the compensation electrode plate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 9, the plurality of first hollow parts 41 of the compensation electrode plate can be arranged along the first direction X and the second direction Y. The plurality of first hollow parts 41 can be arranged in alignment along the second direction Y. The plurality of first hollow parts 41 can be arranged staggered along the first direction X. A row of first hollow parts can include the third set of hollow parts 41c and the fourth set of hollow parts 41d arranged alternately along the first direction X. The third set of hollow parts 41c and the fourth set of hollow parts 41d can include the same number of first hollow parts 41. However, the present embodiment is not limited thereto. For example, the third set of hollow parts 41c and the fourth set of hollow parts 41d can include different numbers of first hollow parts. For example, the third set of hollow parts 41c can include a larger number of first hollow parts than the fourth set of hollow parts 41d.

[0145] In some examples, the third group of hollow parts 41c can include a plurality of first hollow parts 41 (such as three first hollow parts) arranged staggered along the first direction X, and the fourth group of hollow parts 41d can include a plurality of first hollow parts 41 (such as three first hollow parts) arranged staggered along the first direction X. The center lines of the plurality of first hollow parts 41 in the third group of hollow parts 41c, which are parallel to the first direction X, can be sequentially arranged along the opposite direction of the second direction Y, and the minimum distance between the center lines of any two adjacent first hollow parts 41 in the third group of hollow parts 41c, which are parallel to the first direction X, can be the same. The center lines of the plurality of first hollow parts 41 in the fourth group of hollow parts 41d, which are parallel to the first direction X, can be sequentially arranged along the second direction Y. The minimum distance between the center lines of any two adjacent first hollow parts 41 in the fourth group of hollow parts 41d, which are parallel to the first direction X, can be the same.

[0146] In some examples, at least one first hollow part in the third group of hollow parts 41c and at least one first hollow part in the fourth group of hollow parts 41d can be arranged in alignment along the first direction X. For example, the third group of hollow parts 41c and the fourth group of hollow parts 41d can be symmetrically arranged about the midline of both groups, which is parallel to the second direction Y. However, the present embodiment is not limited thereto.

[0147] In the present example, the first straight connection segments 331 of the plurality of gate connection wires 33 can have different overlapping areas with the compensation electrode plate in the substrate. In some examples, the overlapping area of the first straight connection segment (for example, the first straight connection segment 331-5 or 331-6) that overlaps with the compensation electrode plate can be greater than the overlapping area of the first straight connection segment (for example, the first straight connection segment 331-4) that only overlaps with part of the first hollow parts in the first group of hollow parts 41a and the second group of hollow parts 41b in the substrate. The compensation capacitance of the compensation electrode plate to the first straight connection segment 331-4 can be greater than the compensation capacitance to the first straight connection segment 331-5 or 331-6. In this way, the compensation electrode plate can focus on signal compensation for the first straight connection segment 331-4, thereby achieving differential compensation for different gate connection wires. The relationship between the edge of a single first hollow part and the projection of the first straight connection segment in the present example can refer to the description of the foregoing embodiments, and will not be described here again.

[0148] FIG. 10A is another partial enlarged schematic view of the region S1 in FIG. 1. FIG. 10B is a schematic view of the first straight connection segments of the plurality of gate connection wires in FIG. 10A. FIG. 10C is a schematic view of the compensation electrode plate in FIG. 10A. FIGS. 10A to 10C show a partial overlapping schematic view of the first straight connection segments of the gate connection wires and the compensation electrode plate.

[0149] In some examples, the compensation electrode plate 36 can be located in the bottom light shielding metal layer. The compensation electrode plate 36 can have a plurality of first hollows 41 arranged in the first direction X and the second direction Y. The plurality of first hollows 41 can include a plurality of fifth groups of hollows 41e arranged in the first direction X and the second direction Y. The plurality of first hollows 41 can be arranged in alignment along the second direction Y and staggered along the first direction X.

[0150] In some examples, the fifth group of hollows 41e can include six first hollows 41 staggered along the first direction X. The center lines of the six first hollows 41 in the fifth group of hollows 41e parallel to the first direction X can be sequentially arranged along the second direction Y, and the minimum distance between the center lines of any two adjacent first hollows 41 parallel to the first direction X can be the same. Adjacent fifth groups of hollows 41e arranged along the first direction X can be arranged in alignment along the first direction X. For example, the first first hollow in the fifth group of hollows 41e and the first first hollow in the adjacent fifth group of hollows 41e along the first direction X can be arranged in alignment along the first direction X. The remaining positional relationships of the first hollows in this example and the first straight connection segments can refer to the descriptions of the previous embodiments, and will not be described here.

[0151] By staggering the plurality of first hollows along the extension direction of the first straight connection segments, the present example can adjust the overlapping area of the plurality of first straight connection segments and the normal projection of the compensation electrode plate on the substrate, thereby realizing differential compensation of the plurality of gate connection traces.

[0152] FIG. 11A is a partial enlarged schematic view of region S2 in FIG. 1. FIG. 11B is a schematic view of the plurality of arc-shaped connection segments in FIG. 11A. FIG. 11C is a schematic view of the compensation electrode plate in FIG. 11A. In the present example, the arc-shaped connection segments of the plurality of first traces can include the arc-shaped connection segments 333 of the plurality of gate connection traces 33.

[0153] In some examples, as shown in FIGS. 11A-11C, the plurality of arc-shaped connection segments 333 of the plurality of gate connection wires 33 can extend along the arc-shaped edges of the hole region B5. The plurality of arc-shaped connection segments 333 can be located in the same conductive layer (e.g., the first gate metal layer or the second gate metal layer), or can be alternatively arranged in the first gate metal layer and the second gate metal layer. For example, the arc-shaped connection segments 333a of the gate connection wires 33a located in the first gate metal layer can extend along the edges of the hole region B5, and the arc-shaped connection segments 333b of the gate connection wires 33b located in the second gate metal layer can extend along the edges of the hole region B5. The plurality of arc-shaped connection segments 333a of the gate connection wires 33a and the plurality of arc-shaped connection segments 333b of the gate connection wires 33b can be alternatively arranged in a direction away from the hole region B5. The orthographic projections of the arc-shaped connection segments 333a and 333b on the substrate can not overlap. The line widths of the arc-shaped connection segments 333a and 333b can be the same. For example, the arc-shaped connection segments 333a or 333b can be arc segments with the center of the hole region B5 as the center.

[0154] In some examples, the compensation electrode plate 36 can include a plurality of second hollow portions 42, which can be arranged in a direction along which the arc-shaped connection segments 333a and 333b extend. For example, the plurality of second hollow portions 42 can be arranged in a row in the direction along which the arc-shaped connection segments 333a and 333b extend, and a plurality of rows of second hollow portions can be arranged in a direction away from the hole region B5. The spacing between adjacent second hollow portions 42 in a row of second hollow portions close to the hole region B5 can be smaller than the spacing between adjacent second hollow portions 42 in a row of second hollow portions away from the hole region B5. For example, the plurality of second hollow portions 42 can be arranged in a radial manner with the center of the hole region A2 as the center.

[0155] In some examples, the orthographic projection of the second hollow portion 42 on the substrate can be rectangular. The second hollow portion 42 can have a third edge 421 and a fourth edge 422 arranged in parallel, and a fourth edge 423 and a fourth edge 424 arranged in parallel. The extension direction of the third edge 421 and the fourth edge 422 can be parallel to the extension direction of the arc-shaped connection segments 333a and 333b, and the extension direction of the fourth edge 423 and the fourth edge 424 can be perpendicular to the extension direction of the arc-shaped connection segments 333a and 333b. The orthographic projection of the third edge 421 (or 422) on the substrate can be located within the orthographic projection range of an arc-shaped connection segment 333a (or 333b) on the substrate. The orthographic projection of the fourth edge 423 (or 424) on the substrate can overlap with the orthographic projection of a plurality of arc-shaped connection segments (e.g., three or four arc-shaped connection segments) on the substrate. The length of the fourth edge 423 (or 424) can be greater than the line width of at least two arc-shaped connection segments. The arrangement direction of the plurality of second hollow portions 42 can change with the change in the angle of the circular arc of the arc-shaped connection segments, so as to ensure that the third edge of the second hollow portion 42 in the orthographic projection on the substrate can be located within the orthographic projection range of the arc-shaped connection segment on the substrate.

[0156] The present example can improve the influence of the boundary position of the compensation electrode plate (e.g., the edge position of the second hollow part) on the upper inorganic film layer and the conductive layer, and can prevent material residues and poor wiring of the upper conductive layer (e.g., the first source / drain metal layer) by arranging a plurality of second hollow parts along the extension direction of the arc-shaped connection segments, and the projection of the plurality of arc-shaped connection segments on the substrate can cover the third edge of the plurality of second hollow parts in the projection of the substrate. The remaining description of the compensation electrode plate of the present example can refer to the description of the foregoing embodiments, and thus will not be described here.

[0157] FIG. 12 is a schematic view of a compensation electrode plate of a winding area according to at least one embodiment of the present disclosure. In FIG. 12, the dashed line in the winding area B5 divides the winding area B5 into a first region close to the hole area A2 and a second region away from the hole area A2, wherein the first region is the arrangement region of the arc-shaped connection segments of the gate connection wire 33 in the winding area B5, and the second region is the arrangement region of the first and second straight connection segments of the gate connection wire 33.

[0158] In some examples, as shown in FIG. 12, the hole area A2 can have a first center line O1 extending along the first direction X and a second center line O2 extending along the second direction Y. The first center line O1 and the second center line O2 can divide the winding area B5 into four regions (such as the upper left region, the upper right region, the lower left region, and the lower right region). The plurality of gate connection wires can include a first group of gate connection wires located on one side of the first center line O1 in the second direction Y and a second group of gate connection wires located on the opposite side of the first center line O1 in the second direction Y. For example, the first group of gate connection wires and the second group of gate connection wires can be symmetrically arranged about the first center line O1. In the present example, the first group of first wires passing through the hole area A2 from one side of the hole area A2 can include the first group of gate connection wires, and the second group of first wires passing through the hole area A2 from the other side of the hole area A2 can include the second group of gate connection wires.

[0159] In some examples, as shown in FIG. 12, the compensation electrode plate 36 located in the winding area B5 can have a third hollow part 43a located in the upper left region and a third hollow part 43b located in the lower right region. The projection of the third hollow part 43a on the substrate can overlap the projection of the first group of gate connection wires on the substrate, and the projection of the third hollow part 43b on the substrate can overlap the projection of the second group of gate connection wires on the substrate.

[0160] In some examples, the third hollowed parts 43a and 43b each has an overlap with the projections on the substrate of the plurality of gate connection wires arranged close to the hole region A2, and can have no overlap with the projections on the substrate of the plurality of gate connection wires arranged away from the hole region A2. The plurality of gate connection wires arranged close to the hole region A2 can have a length greater than the plurality of gate connection wires arranged away from the hole region A2. The present example can reduce the capacitance compensation for the gate connection wires with a greater length, and increase the capacitance compensation for the gate connection wires with a shorter length, so as to keep the loads of the plurality of gate connection wires the same after compensation.

[0161] In some examples, the third hollowed parts 43a and 43b can each be an arc-shaped hollowed groove extending along the edge of the hole region A2. Take the structure of the third hollowed part 43a as an example for illustration. The third hollowed part 43a can have a fifth edge 431, a sixth edge 432, a seventh edge 433, and an eighth edge 434. The fifth edge 431, the seventh edge 433, the sixth edge 432, and the eighth edge 433 can be connected in sequence. The fifth edge 431 and the sixth edge 432 can have the same extension direction, for example, can extend along the extension direction of the plurality of arc-shaped connection segments. The projections on the substrate of the fifth edge 431 and the sixth edge 432 can at least partially overlap with the projections on the substrate of the plurality of arc-shaped connection segments. For example, the projection on the substrate of an arc-shaped connection segment can cover the projection on the substrate of the fifth edge 431 (or the sixth edge 432). The seventh edge 433 and the eighth edge 434 can have an extension direction perpendicular to the extension direction of the arc-shaped connection segment. For example, the extension line of the seventh edge 433 or the eighth edge 434 can pass through the intersection of the first center line O1 and the second center line O2. However, the present embodiment is not limited thereto.

[0162] FIG. 13A is a partial schematic view of the edge of a third hollowed part according to at least one embodiment of the present disclosure. In some examples, at least part of the edge of the third hollowed part can have a stepped shape in the projection on the substrate. For example, the seventh edge 433 and the eighth edge 434 of the third hollowed part 43a can have a stepped shape in the projection on the substrate. The stepped shape can include a plurality of stepped structures 430 connected in sequence. Each stepped structure 430 can include a first step 430-1 and a second step 430-2 connected to each other. The first step 430-1 and the second step 430-2 are straight line segments with different extension directions. For example, the extension direction of the first step 430-1 can be perpendicular to the extension direction of the second step 430-2.

[0163] In some examples, the first stage 430-1 can have an extension direction parallel to the extension direction of a local segment (e.g., a straight connection segment or an arc connection segment) of the gate connection wire. The orthographic projection of the first stage 430-1 on the substrate can be within the orthographic projection range of a gate connection wire 33 (e.g., an arc connection segment 333 of the gate connection wire 33) on the substrate. The orthographic projection of the second stage 430-2 on the substrate can overlap with the orthographic projection of at least two adjacent gate connection wires 33 on the substrate. For example, the orthographic projection of the first stage 430-1 of the adjacent step structure on the substrate can be within the orthographic projection range of different two gate connection wires on the substrate. However, the present embodiment is not limited thereto. The edge arrangement of the third hollow portion of the present example can not only facilitate the differential compensation of the compensation plate to different gate connection wires, but also improve the influence of the boundary position (e.g., the edge position of the third hollow portion) of the compensation plate on the upper inorganic film layer and the conductive layer (e.g., the first source-drain metal layer), and prevent material residues and wire defects of the conductive layer.

[0164] FIG. 13B is another partial schematic view of the edge of the third hollow portion according to at least one embodiment of the present disclosure. In some examples, at least part of the edge of the third hollow portion can have a step shape in the orthographic projection on the substrate. For example, the seventh edge 433 and the eighth edge 434 of the third hollow portion 43a can have a step shape in the orthographic projection on the substrate. The step shape can include a plurality of step structures 430 connected in sequence. The adjacent step structures 430 can be connected by a step connection segment 430-3. The step connection segment 430-3 can be an arc segment. Each step structure 430 can include a first stage 430-1 and a second stage 430-2 connected to each other. The first stage 430-1 and the second stage 430-2 are straight segments with different extension directions. For example, the extension direction of the first stage 430-1 can be perpendicular to the extension direction of the second stage 430-2. At least part of the edge of the third hollow portion of the present example can have a circular arc gradual boundary. The edge arrangement of the third hollow portion of the present example can not only facilitate the differential compensation of the compensation plate to different gate connection wires, but also improve the influence of the boundary position (e.g., the edge position of the third hollow portion) of the compensation plate on the upper inorganic film layer and the conductive layer (e.g., the first source-drain metal layer), and prevent material residues and wire defects of the conductive layer. Other descriptions of the edge of the present example can be referred to the descriptions of the foregoing embodiments, which will not be repeated here.

[0165] FIG. 14 is another schematic view of a compensation pad of a winding area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 14, the compensation pad 36 located at the winding area B5 can have third hollowed parts 43a and 43c located at the upper left region and third hollowed parts 43b and 43d located at the lower right region. The third hollowed parts 43a and 43c overlap the first set of gate connection traces in the orthographic projection of the substrate, and the third hollowed parts 43b and 43d overlap the second set of gate connection traces in the orthographic projection of the substrate.

[0166] In some examples, as shown in FIG. 14, the third hollowed parts 43a, 43b, 43c and 43d can each be an arc-shaped hollowed slot extending along the edge of the hole area A2. The third hollowed part 43c can be located on the side of the third hollowed part 43a away from the hole area A2, and the third hollowed part 43d can be located on the side of the third hollowed part 43b away from the hole area A2. The length of the third hollowed part 43c can be less than the length of the third hollowed part 43a, and the length of the third hollowed part 43d can be less than the length of the third hollowed part 43b.

[0167] The edge arrangement of the third hollowed part of the present example can not only facilitate the compensation pad to achieve differentiated compensation for different gate connection traces, but also improve the influence of the boundary position of the compensation pad (e.g., the edge position of the third hollowed part) on the upper inorganic film layer and the conductive layer (e.g., the first source-drain metal layer), and prevent material residues and trace defects of the conductive layer. The remaining structures of the third hollowed part of the present example can refer to the descriptions of the foregoing embodiments, and will not be described here.

[0168] FIG. 15 is another schematic view of a compensation pad of a winding area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 15, the compensation pad 36 located at the winding area B5 can have third hollowed parts 43a and 43c located at the upper left region and third hollowed parts 43e and 43f located at the lower left region. The third hollowed parts 43a and 43c overlap the first set of gate connection traces in the orthographic projection of the substrate, and the third hollowed parts 43e and 43f overlap the second set of gate connection traces in the orthographic projection of the substrate.

[0169] In some examples, as shown in FIG. 15, the third hollowed parts 43a, 43c, 43e and 43f can each be an arc-shaped hollowed groove extending along the edge of the hole region A2. The third hollowed part 43c can be located on the side of the third hollowed part 43a away from the hole region A2, and the third hollowed part 43f can be located on the side of the third hollowed part 43e away from the hole region A2. The length of the third hollowed part 43c can be less than the length of the third hollowed part 43a, and the length of the third hollowed part 43f can be less than the length of the third hollowed part 43e. For example, the third hollowed parts 43a and 43e can be substantially symmetrical about the first center line O1, and the third hollowed parts 43c and 43f can be substantially symmetrical about the first center line O1. However, the present embodiment is not limited thereto.

[0170] The edge arrangement of the third hollowed part of the present example can not only be beneficial to compensate for the implementation differences of the different gate connection traces by the plate, but also can improve the influence of the boundary position (e.g., the edge position of the third hollowed part) of the compensation plate on the upper inorganic film layer and the conductive layer (e.g., the first source / drain metal layer), and can prevent material residues and trace defects of the conductive layer. The remaining structures of the third hollowed part of the present example can refer to the descriptions of the foregoing embodiments, and will not be described here again.

[0171] FIG. 16 is another schematic view of a compensation plate of a winding region according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 16, the compensation plate 36 located in the winding region B5 can have third hollowed parts 43a and 43c located in the upper left region, third hollowed parts 43e and 43f located in the lower left region, third hollowed parts 43g and 43h located in the upper right region, and third hollowed parts 43b and 43d located in the lower right region. The third hollowed parts 43a, 43c, 43g and 43h have an overlap between the orthographic projection of the first group of gate connection traces on the substrate and the orthographic projection of the third hollowed parts on the substrate, and the third hollowed parts 43e, 43f, 43b and 43d have an overlap between the orthographic projection of the second group of gate connection traces on the substrate and the orthographic projection of the third hollowed parts on the substrate.

[0172] In some examples, as shown in FIG. 16, the third hollowed parts 43a, 43b, 43c, 43d, 43e, 43f, 43g and 43h can each be an arc-shaped hollowed groove extending along the edge of the hole region A2. The third hollowed part 43c can be located on the side of the third hollowed part 43a away from the hole region A2, the third hollowed part 43f can be located on the side of the third hollowed part 43e away from the hole region A2, the third hollowed part 43d can be located on the side of the third hollowed part 43b away from the hole region A2, and the third hollowed part 43h can be located on the side of the third hollowed part 43g away from the hole region B5. For example, the third hollowed parts 43a and 43e can be substantially symmetrical about the first center line O1, and the third hollowed parts 43g and 43a can be substantially symmetrical about the second center line O2. However, the present embodiment is not limited thereto.

[0173] The edge arrangement of the third hollowed part of the present example can not only facilitate the compensation of different gate connection traces, but also improve the influence of the boundary position of the compensation electrode plate (e.g. the edge position of the third hollowed part) on the upper inorganic film layer and the conductive layer (e.g. the first source / drain metal layer), and prevent material residue and trace defects of the conductive layer. The remaining structures of the third hollowed part of the present example can refer to the descriptions of the foregoing embodiments, and will not be described here again.

[0174] In other examples, the third hollowed parts 43a, 43g, 43b and 43e can be connected to form a ring-shaped hollowed groove to reduce the load compensation on the plurality of gate connection traces close to the hole area A2. In other examples, the third hollowed parts 43c, 43h, 43d and 43f can be connected to form a ring-shaped hollowed groove to reduce the load compensation on the plurality of gate connection traces close to the hole area A2.

[0175] FIG. 17 is another schematic view of the compensation electrode plate of the winding area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 17, the compensation electrode plate 36 located in the winding area B5 can have a third hollowed part 43i located in the upper left area and a third hollowed part 43j located in the lower right area. The third hollowed parts 43i and 43j can be connected to the edge of the compensation electrode plate 36 close to the hole area A2. The edges of the third hollowed parts 43i and 43j can be part of the edge of the compensation electrode plate 36. For example, the third hollowed parts 43i and 43j are not independently arranged inside the compensation electrode plate 36, but are arranged at the boundary position of the compensation electrode plate 36 close to the hole area A2, so that the boundary position of the compensation electrode plate 36 can form a notch recessed away from the hole area A2. In this way, the overlapping area of the compensation electrode plate and the gate connection traces arranged close to the hole area in the orthographic projection of the substrate can be smaller than the overlapping area of the compensation electrode plate and the gate connection traces arranged away from the hole area in the orthographic projection of the substrate, thereby increasing the load compensation on the gate connection traces arranged away from the hole area.

[0176] In some examples, the edge shape of the compensation electrode plate close to the hole area can adopt a stepped boundary as shown in FIG. 13A, or a circular arc gradual change boundary as shown in FIG. 13B. The edge arrangement of the compensation electrode plate can not only facilitate the compensation of different gate connection traces, but also improve the influence of the boundary position of the compensation electrode plate (e.g. the edge position of the third hollowed part) on the upper inorganic film layer and the conductive layer (e.g. the first source / drain metal layer), and prevent material residue and trace defects of the conductive layer. The remaining structures of the compensation electrode plate of the present example can refer to the descriptions of the foregoing embodiments, and will not be described here again.

[0177] FIG. 18 is another schematic view of the gate connection wire of the winding region according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 18, the gate connection wire 33 of the winding region B5 can include a first straight connection segment 331, a second straight connection segment 332, and a zigzag connection segment 334. The zigzag connection segment 334 can be connected between the first straight connection segment 331 and the second straight connection segment 332. The zigzag connection segment 334 can include a plurality of sub-straight line segments connected in different extension directions. Further descriptions of the gate connection wire according to the present example can be referred to the descriptions of the foregoing embodiments, and thus will not be repeated here.

[0178] FIG. 19 is a schematic view of the position of the zigzag connection segment of the gate connection wire and the first hollow part of the compensation electrode plate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 19, the plurality of straight line segments of the plurality of first wires according to the present example can include a plurality of first straight connection segments 331 with the same extension direction, a plurality of second straight connection segments 332 with the same extension direction, and a plurality of sub-straight line segments of a plurality of zigzag connection segments 334 with the same extension direction. The hollow structure of the compensation electrode plate can include a plurality of first hollow parts 41. The plurality of first hollow parts 41 can be arranged in an array along the extension direction of the plurality of sub-straight line segments of the plurality of zigzag connection segments 334. The edges (e.g., the first edges 411 and 412) of the first hollow part 41 with the same extension direction as the sub-straight line segments of the zigzag connection segment 334 can be located within the projection range of the corresponding sub-straight line segments on the substrate in the orthographic projection of the substrate, and the edges (e.g., the second edges 413 and 414) of the first hollow part 41 perpendicular to the extension direction of the sub-straight line segments can overlap with the projection of the plurality of sub-straight line segments on the substrate in the orthographic projection of the substrate. Further descriptions of the compensation electrode plate according to the present example can be referred to the descriptions of the foregoing embodiments, and thus will not be repeated here.

[0179] FIG. 20 is another schematic view of the position of the zigzag connection segment of the gate connection wire and the first hollow part of the compensation electrode plate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 20, the hollow structure of the compensation electrode plate can include a plurality of first hollow parts 41. The plurality of first hollow parts 41 can be arranged divergently along the direction of the radial line passing through the center point of the hole region. For example, the center lines of the plurality of first hollow parts 41 arranged in the direction away from the hole region A2 can coincide and be perpendicular to the extension direction of the sub-straight line segments of the plurality of zigzag connection segments 334. Further descriptions of the compensation electrode plate according to the present example can be referred to the descriptions of the foregoing embodiments, and thus will not be repeated here.

[0180] In some examples, when the first routing line in the winding region only has a straight line segment, the hollow structure of the compensation electrode plate can include a plurality of first hollow parts, and the straight line segment can cover part of the edge of the first hollow part in the orthographic projection of the substrate; when the first routing line in the winding region has a straight line segment and an arc line segment, the hollow structure of the compensation electrode plate can include a plurality of first hollow parts and a plurality of second hollow parts, or the hollow structure can include a plurality of first hollow parts and at least one third hollow part; wherein the straight line segment can cover part of the edge of the first hollow part in the orthographic projection of the substrate, and the arc line segment can cover part of the edge of the second hollow part or the third hollow part in the orthographic projection of the substrate. The present embodiment is not limited in this regard.

[0181] In other examples, a plurality of compensation electrode plates can be provided in the winding region. For example, the winding region B5 can be divided into four regions according to the first center line O1 and the second center line O2, and one compensation electrode plate can be provided in each of the four regions, and the compensation electrode plates in adjacent regions can be independently provided. Alternatively, one compensation electrode plate can be independently provided in each of the two regions divided according to the first center line (or the second center line). The hollow structure of each compensation electrode plate can be as described in the foregoing embodiments, and thus will not be described again.

[0182] In other examples, the film layer structure of the display substrate can be as shown in FIG. 3A, and the compensation electrode plate can be located in the third gate metal layer. The compensation electrode plate located in the third gate metal layer is provided by overlapping the orthographic projection of the gate connection routing line located in the first gate metal layer and the second gate metal layer on the substrate, to compensate for the load of the first type of gate line connected by different gate connection routing lines. Alternatively, the compensation electrode plate located in the third gate metal layer is provided by overlapping the orthographic projection of the data connection routing line located in the first source-drain metal layer and the second source-drain metal layer on the substrate, to compensate for the load of the first type of data line connected by different data connection routing lines.

[0183] In other examples, the peripheral region can further include a first corner region (which can also be referred to as a lower left corner region) connected between the first peripheral region and the second peripheral region, and a second corner region (which can also be referred to as a lower right corner region) connected between the first peripheral region and the third peripheral region. The orthographic projection of the routing line located in the bottom light shielding metal layer in the first corner region and the second corner region can not overlap with the orthographic projection of the routing line located in the first gate metal layer and the second gate metal layer in the region. In other words, in the first corner region and the second corner region, the routing line of the bottom light shielding metal layer can be arranged away from the routing line of the first gate metal layer and the second gate metal layer, to avoid the unevenness of the upper inorganic layer caused by the boundary of the bottom light shielding metal layer, and to avoid the material residue and routing line defects of the conductive layer.

[0184] FIG. 21 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 21, the display panel 910 can be an OLED display panel. The display device 91 can be any product or component with display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like. However, the present embodiment is not limited thereto.

[0185] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "an example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. Furthermore, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, without contradiction.

[0186] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary, and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A display substrate, comprising: The substrate includes a display area and a peripheral area located on at least one side of the display area; Multiple sub-pixels are disposed on one side of the substrate and located in the display area; Multiple first traces are located in the surrounding area, and the multiple first traces are electrically connected to the multiple sub-pixels; A compensation electrode plate is located in the surrounding area, and at least one insulating layer is provided between the compensation electrode plate and the plurality of first traces; The orthographic projection of the compensation electrode on the substrate overlaps with the orthographic projection of the plurality of first traces on the substrate; the compensation electrode has a hollow structure, and the orthographic projection of the hollow structure on the substrate overlaps with the orthographic projection of at least one of the plurality of first traces on the substrate.

2. The display substrate according to claim 1, wherein, The substrate further includes: a hole region, and the peripheral region includes a winding region located between the hole region and the display region; the plurality of first traces and the compensation electrode are all located in the winding region.

3. The display substrate according to claim 1 or 2, wherein, The hollow structure has at least one first hollow edge, the extension direction of the at least one first hollow edge is parallel to the extension direction of at least one of the plurality of first traces, and the orthographic projection of the at least one first hollow edge on the substrate is located within the orthographic projection range of the at least one first trace on the substrate.

4. The display substrate according to any one of claims 1 to 3, wherein, The compensation plate is located on the side of the plurality of first traces that is close to the substrate.

5. The display substrate according to claim 4, wherein, The plurality of first traces are alternately disposed in the first gate metal layer and the second gate metal layer, the second gate metal layer being located on the side of the first gate metal layer away from the substrate, and the orthographic projections of adjacent first traces in the plurality of first traces on the substrate do not overlap. The compensation electrode is located in the bottom light-shielding metal layer, which is located on the side of the first gate metal layer near the substrate.

6. The display substrate according to any one of claims 1 to 5, wherein, The plurality of first routing lines include: a plurality of straight routing line segments extending in the same direction; The hollow structure of the compensation electrode plate includes: a plurality of first hollow portions; At least one of the plurality of first cutout portions has a first edge, the extension direction of the first edge being parallel to the extension direction of the plurality of straight line segments; the orthographic projection of a first edge of a single first cutout portion onto the substrate lies within the orthographic projection range of a straight line segment onto the substrate.

7. The display substrate according to claim 6, wherein, The at least one first cutout portion has a rectangular orthographic projection onto the substrate. The at least one first cutout portion also has a second edge, the extension direction of which is perpendicular to the extension direction of the first edge. The orthographic projection of the second edge onto the substrate overlaps with the orthographic projection portions of at least two of the plurality of straight line segments onto the substrate.

8. The display substrate according to claim 6, wherein, The plurality of first hollow portions are arranged in an array along the extension direction of the plurality of straight line segments, and adjacent first hollow portions are aligned in the extension direction of the plurality of straight line segments.

9. The display substrate according to claim 6, wherein, The plurality of first hollow portions are arranged in an array along the extension direction of the plurality of straight line segments, and at least two adjacent first hollow portions are staggered in the extension direction of the plurality of straight line segments.

10. The display substrate according to claim 9, wherein, Multiple first cutouts arranged along the extension direction of the multiple straight line segments constitute a row of first cutouts. The row of first cutouts includes: an alternately arranged first group of cutouts and a second group of cutouts. Multiple first cutouts in the first group of cutouts are aligned, multiple first cutouts in the second group of cutouts are aligned, and the first group of cutouts and the second group of cutouts are staggered.

11. The display substrate according to claim 9, wherein, Multiple first cutouts arranged along the extension direction of the multiple straight line segments constitute a row of first cutouts. The row of first cutouts includes: an alternately arranged third group of cutouts and a fourth group of cutouts. Multiple first cutouts in the third group of cutouts are staggered, and multiple first cutouts in the fourth group of cutouts are staggered. At least one first cutout in the third group of cutouts is aligned with at least one first cutout in the fourth group of cutouts.

12. The display substrate according to claim 9, wherein, Multiple first hollow sections arranged along the extension direction of the multiple straight line segments constitute a row of first hollow sections. The row of first hollow sections includes multiple fifth groups of hollow sections arranged sequentially. Multiple first hollow sections in the fifth group of hollow sections are staggered, and adjacent fifth groups of hollow sections are aligned.

13. The display substrate according to any one of claims 1 to 5, wherein, The plurality of first routing lines include: a plurality of arc routing line segments with the same extension direction; The hollow structure of the compensation electrode plate includes: a plurality of second hollow portions; the plurality of second hollow portions are arranged along the extension direction of the plurality of arc-shaped lines; At least one of the plurality of second cutouts has a third edge, the extension direction of which is parallel to the extension direction of the plurality of arc traces, and the orthographic projection of the third edge of a single second cutout onto the substrate is located within the orthographic projection range of an arc trace onto the substrate.

14. The display substrate according to claim 2, wherein, The hollow structure of the compensation electrode plate includes: at least one third hollow portion; the at least one third hollow portion extends along at least a portion of the edge of the hole area; The length of the first trace that overlaps with the orthographic projection of the at least one third cutout portion on the substrate is greater than the length of the first trace that does not overlap with the orthographic projection of the at least one third cutout portion on the substrate.

15. The display substrate according to claim 14, wherein, The plurality of first traces include: a first set of first traces that bypasses the hole area from one side of the hole area, and a second set of first traces that bypasses the hole area from the other side of the hole area; The hollow structure of the compensation electrode plate includes at least one third hollow portion that overlaps with the orthographic projection of the first group of first traces on the substrate, and at least one third hollow portion that overlaps with the orthographic projection of the second group of first traces on the substrate.

16. The display substrate according to claim 14, wherein, At least a portion of the edge of the at least one third cutout portion has a stepped shape when projected onto the substrate; the stepped shape includes: a plurality of stepped structures connected in sequence, each stepped structure including a first stage and a second stage connected to each other; the first stage and the second stage are straight segments with different extension directions; The orthographic projection of the first stage of each stepped structure onto the substrate lies within the orthographic projection range of a first trace onto the substrate, and the orthographic projection of the second stage onto the substrate overlaps with the orthographic projections of at least two adjacent first traces onto the substrate.

17. The display substrate according to claim 16, wherein, The step shape also includes: a step connecting segment that connects adjacent step structures, wherein the step connecting segment is an arc segment.

18. A display device comprising a display substrate as claimed in any one of claims 1 to 17.

Images