Array substrate, display panel, and display device
By using 1P8D pixel design and specific electrode pattern blocks and slit structure, the problems of insufficient transmittance, dark lines, and vertical crosstalk in UV2A and SUVA LCD panels were solved, achieving higher transmittance and better display effect.
Patent Information
- Application Number
- PCT/CN2024/084486
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-03-28
- Publication Date
- 2026-01-02
AI Technical Summary
Existing UV2A and SUVA LCD panel technologies have limitations in improving transmittance and reducing dark lines, especially when 8-domain alignment is used, the transmittance improvement is insufficient and the number of dark lines increases, and there is also a problem of longitudinal crosstalk.
The design employs a 1P8D pixel design. By placing a brighter second sub-pixel electrode between a darker first sub-pixel electrode in the sub-pixel electrode and introducing a slit extending along the first direction in the sub-pixel electrode, combined with a specific electrode pattern block and slit design, the proportion of dark lines is reduced and longitudinal crosstalk is decreased.
It improves the transmittance of the LCD panel, reduces the appearance of dark lines, improves the longitudinal crosstalk problem, and enhances the display effect and brightness uniformity.
Smart Images
Figure CN2024084486_02012026_PF_FP_ABST
Abstract
Description
Array substrate, display panel and display device TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular to an array substrate, a display panel and a display device. BACKGROUND
[0002] The name of UV2A comes from the multiplication of ultraviolet (UV) and the VA mode of liquid crystal panel. This technology can precisely control the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.
[0003] The key of UV2A is to use a special polymer material as an alignment film to control the tilt of liquid crystal molecules along the direction of ultraviolet light with high precision. The precision unit is picometer (one millionth of a meter). The advantage of UV2A is that the liquid crystal panel is a simple structure without protrusions and slits. This "dream of liquid crystal technicians" has been explored for more than 30 years. Today, with the three conditions of new materials, production equipment and perfect processing process, this dream has come true. The simple structure of the liquid crystal panel not only improves the production efficiency, but also has many advantages in picture quality.
[0004] SUMMARY
[0005] Embodiments of the present disclosure provide an array substrate, a display panel and a display device. The array substrate comprises:
[0006] a substrate;
[0007] a plurality of gate lines located on one side of the substrate and extending along a first direction;
[0008] a plurality of data lines located on the same side of the substrate as the gate lines and extending along a second direction intersecting the first direction;
[0009] a plurality of sub-pixel electrodes located on the same side of the substrate as the gate lines, at least one of the plurality of sub-pixel electrodes comprising two first sub-pixel electrodes arranged in sequence along the first direction and a second sub-pixel electrode located between the two first sub-pixel electrodes; the light output brightness of the area where the second sub-pixel electrode is located is greater than the light output brightness of the area where the first sub-pixel electrode is located;
[0010] wherein the sub-pixel electrode comprises at least a first slit extending along the first direction, and the first slit passes through the central area of the sub-pixel electrode.
[0011] In a possible implementation, the first slit is located in the first sub-pixel electrode.
[0012] In a possible implementation, the first slit comprises a plurality of first sub-slits extending along the first direction and arranged along the second direction.
[0013] In a possible implementation, the second sub-pixel electrode comprises a plurality of electrode pattern blocks arranged along the second direction, and an electrode connecting portion connecting adjacent pattern blocks.
[0014] The first sub-slit further comprises a first sub-slit portion extending along the first direction and arranged along the first direction, and a second sub-slit portion; the first sub-slit portion and the second sub-slit portion are located at different sides of the electrode connecting portion.
[0015] In a possible implementation, the first sub-pixel electrode further comprises a first sub-pixel electrode portion, and a second sub-pixel electrode portion.
[0016] The first sub-slit portion and the second sub-slit portion are arranged along the second direction.
[0017] In a possible implementation, an end of the first sub-slit portion away from the electrode connecting portion is in a closed structure; an end of the second sub-slit portion away from the electrode connecting portion is in a closed structure.
[0018] In a possible implementation, the sub-pixel electrode further comprises a second slit extending along the second direction, and an extension line of the second slit passes through a central region of the sub-pixel electrode.
[0019] In a possible implementation, the electrode pattern block comprises a first pattern portion extending along the second direction, and two second pattern portions connected to the first pattern portion; the two second pattern portions are respectively located at two sides of the first pattern portion along the first direction.
[0020] The second slit is located between the first pattern portion and the second pattern portion.
[0021] In a possible implementation, the electrode pattern block further comprises a pattern connecting portion located between the first pattern portion and the second pattern portion; the first pattern portion and the second pattern portion are electrically connected through the pattern connecting portion.
[0022] In a possible implementation, the first pattern portion and the second pattern portion have two pattern connecting portions, the two pattern connecting portions are respectively located at two end positions of an outer edge of the second pattern portion along the second direction, and connect the second pattern portion and the first pattern portion at the end positions.
[0023] The second slit is located between two of the pattern connection portions.
[0024] In one possible implementation, the first pattern portion and the second pattern portion have one pattern connection portion therebetween, the pattern connection portion is connected to the second pattern portion at a middle position of an outer edge of the second pattern portion along the second direction, and connects the second pattern portion and the first pattern portion at the middle position.
[0025] The second slit is located between the first pattern portion and the second pattern portion, and on both sides of the pattern connection portion along the second direction.
[0026] In one possible implementation, the array substrate further comprises a first common wire on one side of the gate line, and a transfer electrode; the transfer electrode has an overlapping area with the first common wire in the orthographic projection of the substrate.
[0027] The array substrate further comprises a pixel circuit; the pixel circuit comprises a first transistor, a second transistor, and a third transistor,
[0028] The first transistor comprises a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor comprises a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; and the third transistor comprises a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode.
[0029] The first transistor control electrode is multiplexed with the gate line, the first transistor first electrode is multiplexed with the data line, and the first transistor second electrode is electrically connected with the second sub-pixel electrode.
[0030] The second transistor control electrode is multiplexed with the gate line, the second transistor first electrode is multiplexed with the first transistor first electrode, and the second transistor second electrode is electrically connected with the first sub-pixel electrode.
[0031] The third transistor control electrode is multiplexed with the gate line, the third transistor first electrode is multiplexed with the second transistor second electrode, and the third transistor second electrode is electrically connected with the transfer electrode.
[0032] In one possible implementation, a part of the orthographic projection of the second sub-pixel electrode overlaps with the orthographic projection of the gate line and the first common wire.
[0033] In one possible implementation, the array substrate further comprises a pixel circuit; the pixel circuit comprises a first transistor, a second transistor, a third transistor, and a first signal line.
[0034] The first transistor comprises a first transistor control electrode, a first transistor first electrode and a first transistor second electrode; the second transistor comprises a second transistor control electrode, a second transistor first electrode and a second transistor second electrode; the third transistor comprises a third transistor control electrode, a third transistor first electrode and a third transistor second electrode;
[0035] The first transistor control electrode multiplexes the gate line, the first transistor first electrode multiplexes the data line; and the first transistor second electrode is electrically connected to the second sub-pixel electrode;
[0036] The second transistor control electrode multiplexes the gate line, the second transistor first electrode multiplexes the first transistor first electrode; and the second transistor second electrode is electrically connected to the first sub-pixel electrode;
[0037] The third transistor control electrode multiplexes the gate line, the third transistor first electrode multiplexes the second transistor second electrode; and the third transistor second electrode multiplexes the first signal line.
[0038] The display panel provided by the embodiment of the present disclosure comprises the array substrate provided by the embodiment of the present disclosure, and further comprises an opposite substrate arranged opposite to the array substrate; the opposite substrate comprises a common electrode layer.
[0039] The display device provided by the embodiment of the present disclosure comprises the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS
[0040] FIG. 1 is a schematic diagram of sub-pixel distribution of 1P4D;
[0041] FIG. 2A is a schematic diagram of an array substrate provided by the embodiment of the present disclosure;
[0042] FIG. 2B is a schematic diagram of a single film layer of a gate line layer in FIG. 2A;
[0043] FIG. 2C is a schematic diagram of a single film layer of a data line layer in FIG. 2A;
[0044] FIG. 2D is a schematic diagram of a single film layer of an active layer in FIG. 2A;
[0045] FIG. 2E is a schematic diagram of a single film layer of a first insulating layer in FIG. 2A;
[0046] FIG. 2F is a schematic diagram of a single film layer of a pixel electrode layer in FIG. 2A;
[0047] FIG. 2G is a schematic diagram of a corresponding black matrix layer of FIG. 2A;
[0048] FIG. 2H is a schematic diagram of a corresponding light efficiency of FIG. 2A;
[0049] Fig. 2I is a schematic diagram of an equivalent circuit corresponding to Fig. 2A;
[0050] Fig. 3A is a schematic diagram of an array substrate from a second aspect of the present disclosure;
[0051] Fig. 3B is a schematic diagram of a single film layer of the pixel electrode layer in Fig. 2A;
[0052] Fig. 3C is a schematic diagram of a light effect corresponding to Fig. 3A;
[0053] Fig. 4A is a schematic diagram of an array substrate from a third aspect of the present disclosure;
[0054] Fig. 4B is a schematic diagram of a single film layer of the pixel electrode layer in Fig. 4A;
[0055] Fig. 5A is a schematic diagram of an array substrate from a fourth aspect of the present disclosure;
[0056] Fig. 5B is a schematic diagram of a single film layer of the gate line layer in Fig. 5A;
[0057] Fig. 5C is a schematic diagram of a single film layer of the data line layer in Fig. 5A;
[0058] Fig. 5D is a schematic diagram of a single film layer of the active layer in Fig. 5A;
[0059] Fig. 5E is a schematic diagram of a single film layer of the first insulating layer in Fig. 5A;
[0060] Fig. 5F is a schematic diagram of a single film layer of the pixel electrode layer in Fig. 5A;
[0061] Fig. 5G is a schematic diagram of an equivalent circuit corresponding to Fig. 5A;
[0062] Fig. 6 is a schematic diagram of an array substrate from a fifth aspect of the present disclosure;
[0063] Fig. 7 is a schematic diagram of an array substrate from a sixth aspect of the present disclosure;
[0064] Fig. 8 is a schematic diagram of an array substrate from a seventh aspect of the present disclosure;
[0065] Fig. 9 is a schematic diagram of various crosstalk images. DETAILED DESCRIPTION
[0066] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort fall within the scope of protection of the present disclosure.
[0067] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The words "first", "second", and similar words do not necessarily denote any order, quantity, or importance, but are used to distinguish one element from another, and the words "comprise", "comprising", and similar words do not exclude the presence of elements or items other than those listed. The words "connected" or "coupled" do not necessarily denote a direct connection or coupling, but can include an indirect connection or coupling through one or more intervening elements. The words "upper", "lower", "left", "right", and the like describe relative positions for ease of description and can only change when the absolute positions of the described objects change.
[0068] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art to which the discussion pertains and which is associated with the measurement of the particular quantity, i.e., limitations of the measurement system. For example, "about" can mean within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the stated value.
[0069] In the drawings, the thicknesses of layers, films, panels, regions, etc., can be exaggerated for clarity. Descriptive terminology such as "above", "below", "left", "right", "upper", "lower", etc., is used for clarity in the description of the implementations to provide an example embodiment and is in no way intended to limit the scope of the disclosure. Accordingly, the embodiments described herein should not be construed as limited to the particular form set forth herein, but rather can be implemented using any number of variations within the scope of the disclosure. For example, the sequence of steps can be changed, other steps can be added, or other steps can be left out. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive.
[0070] In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and configurations incorporated herein will be omitted.
[0071] Compared with the UV2A pixel design, the super fine light alignment (SUVA) is an upgraded version of the UV2A, as shown in FIG. 1, which is a SUVA pixel design of 1P4D (4 domains in one sub-pixel), compared with the UV2A pixel design, the SUVA pixel design can effectively reduce the dark lines of the pixel, but the SUVA alignment has obvious transmittance improvement for 4-domain alignment, and the number of dark lines increases and the transmittance improvement is insufficient when the 8-domain alignment is used.
[0072] Therefore, the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 2A-2F, comprises:
[0073] a substrate 1;
[0074] a plurality of gate lines 2 located on one side of the substrate 1 and extending along a first direction X;
[0075] a plurality of data lines 3 located on the same side of the substrate 1 as the gate lines 2 and extending along a second direction Y intersecting the first direction X;
[0076] a plurality of sub-pixel electrodes 4 located on the same side of the substrate 1 as the gate lines 2, at least one of the plurality of sub-pixel electrodes 4 comprising: two first sub-pixel electrodes 41 arranged in sequence along the first direction X, and a second sub-pixel electrode 42 located between the two first sub-pixel electrodes 41, and optionally, the two first sub-pixel electrodes 41 in the same sub-pixel electrode 4 are electrically connected; the light output brightness of the region where the second sub-pixel electrode 42 is located is greater than the light output brightness of the region where the first sub-pixel electrode 41 is located;
[0077] wherein the sub-pixel electrode 4 comprises at least a first slit F1 extending along the first direction X, and the first slit F1 passes through the central region of the sub-pixel electrode 4.
[0078] In the embodiments of the present disclosure, the sub-pixel electrode 4 comprises: two first sub-pixel electrodes 41, and a second sub-pixel electrode 42 located between the two first sub-pixel electrodes 41; the light output brightness of the region where the second sub-pixel electrode 42 is located is greater than the light output brightness of the region where the first sub-pixel electrode 41 is located; the sub-pixel electrode 4 comprises at least a first slit F1 extending along the first direction X, and the first slit F1 passes through the central region of the sub-pixel electrode 4, that is, by setting the brighter second sub-pixel electrode 42 between the two darker first sub-pixel electrodes 41 in the 1P8D structure design, and adopting the first slit F1 extending along the first direction X in the sub-pixel electrode 4, the position of the sub-pixel transverse dark line is approximately coincident, the design of the pixel structure forming the dark line in the light alignment can be compressed, the proportion of the dark line is reduced, the liquid crystal efficiency is improved, and the color cast is also improved by adopting the 1P8D pixel design.
[0079] In addition, in the embodiment of the present disclosure, by arranging the brighter second sub-pixel electrode 42 between the two darker first sub-pixel electrodes 41 in the 1P8D structure design, that is, the brighter second sub-pixel 42 is located in the middle, and the darker first sub-pixel 41 is arranged on both sides, due to voltage suppression, longitudinal crosstalk does not occur.
[0080] In the liquid crystal display panel, various wirings are densely arranged, and there is a large coupling capacitance, which causes various crosstalk problems. The type of crosstalk is greatly related to the row inversion / column inversion / point inversion of the liquid crystal display panel. In combination with FIG. 9, the crosstalk problem includes horizontal crosstalk, vertical crosstalk, and the like. The horizontal crosstalk is related to the coupling capacitance between the data line and the common electrode. The vertical crosstalk is related to the coupling capacitance between the data line and the pixel electrode on the one hand, and is also related to the transistor drain current Ioff on the other hand.
[0081] In the conventional 8Domain sub-pixel design, the dark pixel is not bright at low gray level, and only the bright pixel is bright. In the embodiment of the present disclosure, by arranging the brighter second sub-pixel 42 in the middle of the sub-pixel 4, the distance between the brighter second sub-pixel 42 and the data line is far, and the coupling capacitance Cpd between the sub-pixel electrode and the data line is about 0. Therefore, when the low gray level changes the picture, the pixels of different gray levels on both sides are difficult to be affected by the different voltages of the data lines on both sides, so it is difficult to occur longitudinal crosstalk (that is, vertical crosstalk), and the problem of longitudinal crosstalk can be improved. That is, the arrangement of arranging the brighter second sub-pixel 42 in the middle of the sub-pixel 4 has good performance in low gray level longitudinal crosstalk.
[0082] It should be noted that brighter means more backlight transmission, and darker means less backlight transmission, that is, when the voltage applied to different regions is different, the pressure difference formed with the common electrode of the opposite substrate is different. The greater the pressure difference, the stronger the ability to drive the liquid crystal to rotate, the more the backlight transmission, and the brighter the region. Conversely, the smaller the pressure difference, the weaker the ability to drive the liquid crystal to rotate, the less the backlight transmission, and the darker the region.
[0083] Specifically, the array substrate can further include a pixel circuit. The brightness of the region where the second sub-pixel electrode 42 is located is greater than the brightness of the region where the first sub-pixel 41 is located. It can be understood that under the driving of the pixel circuit, the brightness of the second sub-pixel 42 is greater than the brightness of the first sub-pixel 41.
[0084] It should be noted that the main difference between the structure shown in FIG. 3A and the structure shown in FIG. 2A is the difference in the sub-pixel electrode pattern, therefore, the array substrate corresponding to FIG. 3A mainly shows the pattern of the sub-pixel electrode layer shown in FIG. 3B, and the patterns of the gate line layer, the data line layer, the active layer, the first insulating layer, and the black matrix layer corresponding to FIG. 3A can be referred to FIGS. 2B-2E, and the embodiments of the present disclosure will not be repeated; the rest of the drawings are similar.
[0085] FIG. 2H is a light efficiency diagram of the pixel structure corresponding to FIG. 2A, and FIG. 3C is a light efficiency diagram of the pixel structure corresponding to FIG. 3A. By comparing the light efficiency diagrams of FIG. 2H and FIG. 3C, it can be seen that the pixel structure of FIG. 2A can be thinner than that of FIG. 3A, which can increase the transmittance; in the structure of FIG. 3A, there will be a bending of the dark lines at the middle position of the electrode pattern block P0, and the effect of improving the transmittance is not as good as that of the structure shown in FIG. 2A.
[0086] In a possible implementation, as shown in FIG. 2F, the first slit F1 is located at the first sub-pixel electrode 41. In this way, the position of the pixel structure in the center area of the sub-pixel is adapted to generate horizontal dark lines, thereby reducing the proportion of the dark lines and improving the liquid crystal efficiency.
[0087] In a possible implementation, as shown in FIG. 2F, the first slit F1 includes a plurality of first sub-slits F11 extending along the first direction X and arranged along the second direction Y. In a possible implementation, as shown in FIG. 2G, the first slit F1 includes two first sub-slits F11 extending along the first direction X and arranged along the second direction Y. In this way, while reducing the proportion of the dark lines, the influence on the sub-pixel electrode 4 in normal display is reduced. Alternatively, three first slits or more first slits can also be provided in the present case, and the slits can be straight lines, or can be wavy or zigzag, etc., which are not limited here.
[0088] In a possible implementation, as shown in FIG. 2F, the second sub-pixel 42 electrode includes a plurality of electrode pattern blocks P0 arranged along the second direction Y, and an electrode connecting portion P1 connecting adjacent pattern blocks P0; the first sub-slit F11 further includes a first sub-slit portion FA extending along the first direction X and arranged along the first direction X, and a second sub-slit portion FB; the first sub-slit portion FA and the second sub-slit FB are located at different sides of the electrode connecting portion P1, for example, as shown in FIG. 2G, the first sub-slit portion FA is located at the left side of the electrode connecting portion P1, and the second sub-slit portion FB is located at the right side of the electrode connecting portion P1. That is, the first sub-slit F11 is disconnected at the position of the second sub-pixel electrode 42 to avoid affecting the structure of the second sub-pixel electrode 42.
[0089] In a possible implementation, as shown in FIG. 2F, the first sub-pixel electrode 41 further includes: a first sub-pixel electrode part 41A, and a second sub-pixel electrode part 41B; the first sub-pixel electrode part 41A is arranged between two first sub-slit parts FA adjacent in the second direction Y; the second sub-pixel electrode part 41B is arranged between two second sub-slit parts FB adjacent in the second direction Y. Optionally, the part of the first sub-pixel electrode 41 between the two first sub-slit parts FA can be taken as the first sub-pixel electrode part 41A, and the part of the first sub-pixel electrode 41 between the two second sub-slit parts FB can be taken as the second sub-pixel electrode part 41B.
[0090] In a possible implementation, as shown in FIG. 2F, the first sub-slit part FA is in a closed structure away from one end of the electrode connection part P1; the second sub-slit part F2 is in a closed structure away from one end of the electrode connection part P1. In this way, the first sub-pixel electrode 41 can be prevented from being broken in the second direction Y when the first slit F1 penetrates the first sub-pixel electrode 41 in the first direction X, and the problem of display failure can be avoided.
[0091] In a possible implementation, as shown in FIG. 2F, FIG. 3B, FIG. 4B, FIG. 6, FIG. 7 and FIG. 8, the sub-pixel electrode 4 further includes: a second slit F2 extending in the second direction Y, and the extension line of the second slit F2 passes through the center region of the sub-pixel electrode 4. In the embodiments of the present disclosure, the sub-pixel electrode 4 further includes: a second slit F2 extending in the second direction Y, and the extension line of the second slit F2 passes through the center region of the sub-pixel electrode 4 and substantially coincides with the position of the sub-pixel longitudinal dark line, which can compress the design of the pixel structure in the light orientation in the second direction Y to form a dark line, reduce the proportion of the dark line in the second direction Y, improve the liquid crystal efficiency, and at the same time, the 1P8D pixel design can improve the color cast.
[0092] In a possible implementation, as shown in FIG. 2F, the electrode pattern block P0 includes: a first pattern part P01 extending in the second direction Y, and two second pattern parts P02 connected with the first pattern part P01. Optionally, the orthographic projection of the first pattern part P01 on the substrate 1 can be a vertical bar, and the orthographic projection of the second pattern part P02 on the substrate 1 can be a triangle; the two second pattern parts P02 are respectively located on the two sides of the first pattern part P01 in the first direction X; the second slit F2 is located between the first pattern part P01 and the second pattern part P02. Optionally, as shown in FIG. 2G, each second pattern part P02 can form a second slit F2 extending in the second direction Y with the first pattern part P01, and one electrode pattern block P0 can have two second slits F2.
[0093] In a possible implementation, as shown in FIG. 2F, the electrode pattern block P0 further comprises: a pattern connecting portion P03 located between the first pattern portion P01 and the second pattern portion P02, for example, as shown in FIG. 2G, the pattern connecting portion P03 is located at the end of the second pattern portion P02; the first pattern portion P01 and the second pattern portion P02 are electrically connected through the pattern connecting portion P03.
[0094] In a possible implementation, as shown in FIG. 2F, the first pattern portion P01 and the second pattern portion P02 have two pattern connecting portions P03, the two pattern connecting portions P03 are respectively located at two end positions of the second pattern portion P02 along the outer edge of the second direction Y, and connect the second pattern portion P02 and the first pattern portion P01 at the end positions; the second slit F2 is located between the two pattern connecting portions P03.
[0095] In a possible implementation, as shown in FIG. 3A and FIG. 3B, the first pattern portion P01 and the second pattern portion P02 have one pattern connecting portion P03, the pattern connecting portion P03 is connected to the middle position of the second pattern portion P02 along the outer edge of the second direction Y, and connects the second pattern portion P02 and the first pattern portion P01 at the middle position; the second slit F2 is located between the first pattern portion P01 and the second pattern portion P02, and is located on both sides of the pattern connecting portion P03 along the second direction Y.
[0096] In a possible implementation, as shown in FIG. 2F, the two second pattern portions P02 are symmetrical about the first pattern portion P01. In a possible implementation, as shown in FIG. 5B, the second pattern portion P02 is a triangle in the orthographic projection pattern of the substrate 1, and optionally, the second pattern portion P02 is a right-angled triangle in the orthographic projection pattern of the substrate 1, and the two second pattern portions P02 of the right-angled triangle are arranged in a way that the hypotenuses face each other; and optionally, the second pattern portion P02 of the right-angled triangle is arranged in a way that the hypotenuse faces the second slit F2.
[0097] In a possible implementation, as shown in FIG. 2F, the second slits F2 of two adjacent electrode pattern blocks P0 are not connected. In this way, the two second pattern portions P02 on the left and right sides in the same electrode pattern block P0 are electrically connected at the upper and lower ends respectively, so as to ensure that the two second pattern portions P02 in the same electrode pattern block P0 also have better connectivity when the second slit F2 is arranged.
[0098] In a possible implementation, as shown in FIG. 2F, the orthogonal projection of the electrode pattern block P0 on the substrate 1 includes a rhombus. One of the sides of the rhombus can form an angle of 30°-60° with the first direction X, and specifically, for example, can form an angle of 45° with the first direction X; the other of the sides of the rhombus can form an angle of 130°-160° with the first direction X, and specifically, for example, can form an angle of 145° with the first direction X. In a possible implementation, as shown in FIG. 2F, one of the diagonals of the rhombus can be parallel to the first direction X, and the other of the diagonals of the rhombus can be parallel to the second direction Y.
[0099] In a possible implementation, the width of the rhombus-shaped electrode pattern block P0 in the first direction X can be one-fifth to four-fifths of the width of the sub-pixel electrode 4 in the first direction X; in a possible implementation, the width of the rhombus-shaped electrode pattern block P0 in the first direction X can be one-half of the width of the sub-pixel electrode 4 in the first direction X. In a possible implementation, the length of the rhombus-shaped electrode pattern block P0 in the second direction Y can be one-fifth to four-fifths of the length of the sub-pixel electrode 4 in the second direction Y; in a possible implementation, the length of the rhombus-shaped electrode pattern block P0 in the second direction Y can be one-fourth of the length of the sub-pixel electrode 4 in the second direction Y; in a possible implementation, the length of the rhombus-shaped electrode pattern block P0 in the second direction Y can be one-half of the length of the sub-pixel electrode 4 in the second direction Y; in a possible implementation, the length of the rhombus-shaped electrode pattern block P0 in the second direction Y can be equal to the length of the sub-pixel electrode 4 in the second direction Y.
[0100] In a possible implementation, the four corners of the rhombus can all be right angles, as shown in FIG. 2F.
[0101] In a possible implementation, in combination with FIG. 2F, the first sub-pixel electrode 41 can be a pattern complementary to the pattern of the second sub-pixel electrode 42, that is, the pattern of the two first sub-pixel electrodes 41 is obtained by removing the pattern of the second sub-pixel electrode 42 from the sub-pixel electrode 4.
[0102] In a possible implementation, at least one electrode pattern block P0 is distributed in the same sub-pixel electrode 4, that is, the area of the electrode pattern block P0 can be small, and one or more electrode pattern blocks P0 can be distributed in one sub-pixel electrode 4, as shown in FIGS. 2A, 3A, 4A, 5A, and 6. In a possible implementation, as shown in FIG. 2A, two electrode pattern blocks P0 can be distributed in one sub-pixel electrode P; in a possible implementation, as shown in FIG. 7, one electrode pattern block P0 can be distributed in one sub-pixel electrode P.
[0103] In another possible implementation, the at least one electrode pattern block P0 is distributed in two adjacent sub-pixel electrodes 4, that is, the area of the electrode pattern block P0 can be larger, and a part of an electrode pattern block P0 can be distributed in one sub-pixel electrode 4, that is, one electrode pattern block P0 can be in multiple sub-pixel electrodes 4 respectively, as shown in FIG. 8.
[0104] In a possible implementation, referring to FIG. 8, the electrode pattern block P0 includes: a first sub-pattern block PX1 distributed along the second direction Y, and a second sub-pattern block PX2; the first sub-pattern block PX1 is a triangle in the orthographic projection of the substrate 1, and the second sub-pattern block PX2 is a triangle in the orthographic projection of the substrate 1; the orthographic projection of the second sub-pattern block PX2 of a second sub-pixel electrode 42 on the substrate 1 combines with the orthographic projection of the first sub-pattern block PX1 of an adjacent second sub-pixel electrode 42 on the substrate 1 to form a rhombus; in the same second sub-pixel electrode 42, the first sub-pattern block PX1 and the second sub-pattern block PX2 are distributed with opposite apex angles.
[0105] In a possible implementation, in combination with FIGS. 2A-2F and 2I, where FIG. 2I can be the equivalent circuit diagram corresponding to FIG. 2A, the array substrate further includes: a first common wire 51 located on one side of the gate line 2, and a switching electrode PC; the orthographic projection of the switching electrode PC on the substrate 1 has an overlapping area with the orthographic projection of the first common wire 51 on the substrate 1.
[0106] The array substrate further includes: a pixel circuit; the pixel circuit includes: a first transistor T1, a second transistor T2, and a third transistor T3; the first transistor T1 includes: a first transistor control electrode T1A, a first transistor first electrode T1B, and a first transistor second electrode T1C; the second transistor T2 includes: a second transistor control electrode T2A, a second transistor first electrode T2B, and a second transistor second electrode T2C; the third transistor T3 includes: a third transistor control electrode T3A, a third transistor first electrode T3B, and a third transistor second electrode T3C.
[0107] The first transistor control electrode T1A multiplexes the gate line 2, and the first transistor first electrode T1B multiplexes the data line 3; the first transistor second electrode T1C is electrically connected with the second sub-pixel electrode 42;
[0108] The second transistor control electrode T2A multiplexes the gate line 2, the second transistor first electrode T2B multiplexes the first transistor first electrode T1B; the second transistor second electrode T2C is electrically connected with the first sub-pixel electrode 41;
[0109] The third transistor control electrode T3A multiplexes the gate line 2, the third transistor first electrode T3B multiplexes the second transistor second electrode T2C; and the third transistor second electrode T3C is electrically connected with the first common wire 51 through the switching electrode PC.
[0110] In a possible implementation, in combination with FIGS. 2A-2F and FIG. 2I, the array substrate further includes: a second common wire 52 located on the other side of the gate line 2; and the pixel circuit further includes: a first liquid crystal capacitor Cpx1, a second liquid crystal capacitor Cpx2, a first capacitor C1, and a second capacitor C2, wherein the first liquid crystal capacitor Cpx1 can be formed by the first sub-pixel electrode 41 and the common electrode layer of the opposite substrate, the second liquid crystal capacitor Cpx2 can be formed by the second sub-pixel electrode 42 and the common electrode layer of the opposite substrate, the first capacitor C1 can be formed by the first sub-pixel electrode 41 and the second common wire 52, and the second capacitor C2 can be formed by the second sub-pixel electrode 42 and the first common wire 51.
[0111] In the embodiment of the application, the first sub-pixel electrode 41 can be electrically connected to the gate line 2 and the data line 3 through the first transistor T1, the second sub-pixel electrode 42 can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2, and the third transistor second electrode T3C is electrically connected to the first common wire 51, so that part of the charge in the second capacitor C2 corresponding to the second sub-pixel electrode P2 can be released to the first common wire 51 through the third transistor T3, and the brightness of the first sub-pixel electrode 41 can be greater than the brightness of the second sub-pixel electrode 42, so that different bright and dark pixels are realized in the same sub-pixel electrode 4, and the display effect of 8 domains is realized.
[0112] In a possible implementation, referring to FIGS. 2A-2F, the orthogonal projection of the transfer electrode PC on the substrate 1 has an overlapping area with the orthogonal projection of the first common wire 51 on the substrate 1, and has an overlapping area with the orthogonal projection of the third transistor second electrode T3C on the substrate 1, the third transistor second electrode T3C is electrically connected to the first common wire 51 through the transfer electrode PC in the overlapping area through the third via hole K3; the third via hole K3 can be a half via hole design, the third via hole K3 partially exposes the first common wire 51 and partially exposes the third transistor second electrode T3C, the transfer electrode PC partially contacts the first common wire 51 and partially contacts the third transistor second electrode T3C at the third via hole K3, so that the first common wire 51 and the third transistor second electrode T3C are electrically connected through the transfer electrode PC. Specifically, the third via hole K3 is a half via hole design, which can form a step structure inside the third via hole K3 to guide the flow of the alignment liquid, thereby avoiding the technical effect of moire phenomenon in the picture.
[0113] In a possible implementation, referring to FIG. 2B, the first common wire 51 and the second common wire 52 can be of the same layer and the same material as the gate line 2, so that the first common wire 51 and the second common wire 52 can be formed at the same time as the gate line 2 is formed, thereby simplifying the manufacturing process of the array substrate.
[0114] In a possible implementation, referring to FIG. 2F, the transfer electrode PC can be of the same layer and material as the sub-pixel electrode 4, and thus the transfer electrode PC can be formed at the same time as the sub-pixel electrode 4, thereby simplifying the manufacturing process of the array substrate.
[0115] In a possible implementation, referring to FIG. 2B, the array substrate can further include a third common wire group extending along the second direction Y, and the third common wire group includes two third common wires 53. The two third common wires 53 of the same third common wire group are located on both sides of the data line 3 in the orthographic projection of the substrate 1.
[0116] In a possible implementation, referring to FIGS. 2A-2F, a part of the orthographic projection of the second sub-pixel electrode 42 on the substrate 1 overlaps the orthographic projection of the gate line 2 and the first common wire 51 on the substrate 1. Optionally, the second sub-pixel electrode 42 can include a pixel extension P04, and optionally, a part of the orthographic projection of the pixel extension P04 on the substrate 1 overlaps the orthographic projection of the gate line 2 and the first common wire 51 on the substrate 1. The pixel extension P04 can protrude outward from the sub-pixel electrode and overlap the orthographic projection of the second electrode T1C of the first transistor T1, and be electrically connected in the overlapping area, thereby achieving electrical connection between the first transistor T1 and the second sub-pixel electrode 42.
[0117] In a possible implementation, referring to FIGS. 5A-5G, wherein FIG. 5G can be the equivalent pixel circuit diagram corresponding to FIG. 5A, the array substrate further includes a pixel circuit, and the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a first signal line 6.
[0118] The first transistor T1 includes a first transistor control electrode T1A, a first transistor first electrode T1B, and a first transistor second electrode T1C. The second transistor T2 includes a second transistor control electrode T2A, a second transistor first electrode T2B, and a second transistor second electrode T2C. The third transistor T3 includes a third transistor control electrode T3A, a third transistor first electrode T3B, and a third transistor second electrode T3C.
[0119] The first transistor control electrode T1A multiplexes the gate line 2, and the first transistor first electrode T1B multiplexes the data line 3. The first transistor second electrode T1C is electrically connected to the second sub-pixel electrode 42.
[0120] The second transistor control electrode T2A multiplexes the gate line 2, and the second transistor first electrode T2B multiplexes the first transistor first electrode T1B. The second transistor second electrode T2C is electrically connected to the first sub-pixel electrode 41.
[0121] The third transistor control electrode T3A multiplexes the gate line 2, the third transistor first electrode T3B multiplexes the second transistor second electrode T2C, and the third transistor second electrode T1C multiplexes the first signal line 6.
[0122] In a possible implementation, referring to FIGS. 5A-5G, the array substrate further includes a first common wire 51 on one side of the gate line 2 and a second common wire 52 on the other side of the gate line 2; and the pixel circuit further includes a first liquid crystal capacitor Cpx1, a second liquid crystal capacitor Cpx2, a first capacitor C1, and a second capacitor C2, wherein the first liquid crystal capacitor Cpx1 can be formed by the first sub-pixel electrode 41 and the common electrode layer of the opposite substrate, the second liquid crystal capacitor Cpx2 can be formed by the second sub-pixel electrode 42 and the common electrode layer of the opposite substrate, the first capacitor C1 can be formed by the first sub-pixel electrode 41 and the second common wire 52, and the second capacitor C2 can be formed by the second sub-pixel electrode 42 and the first common wire 51.
[0123] In the embodiment of the present application, the first sub-pixel electrode 41 can be electrically connected to the gate line 2 and the data line 3 through the first transistor T1, the second sub-pixel electrode 42 can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2, and the third transistor second electrode T3C is electrically connected to the first signal line 6. Part of the charge in the second capacitor C2 corresponding to the second sub-pixel electrode 42 can be released to the first signal line 6 through the third transistor T3, so that the brightness of the first sub-pixel electrode P1 is greater than the brightness of the second sub-pixel electrode 42, and the same sub-pixel electrode 4 has different bright and dark pixels, and the 8-domain display effect is realized.
[0124] In a possible implementation, in combination with FIGS. 5A-5G, the first signal line 6 passes through the center area of the substrate 1 in the orthographic projection of the electrode pattern block P0. In this way, the display panel has fewer dark lines and the transmittance of the display panel can be improved.
[0125] In a possible implementation, in combination with FIGS. 2A-2G, the array substrate can be sequentially provided with a gate line layer as shown in FIG. 2B, a data line layer as shown in FIG. 2C, an active layer as shown in FIG. 2D, a first insulating layer as shown in FIG. 2E, and a sub-pixel electrode layer as shown in FIG. 2F on one side of the substrate 1.
[0126] The active layer can include an active pattern 71 corresponding to the transistor.
[0127] The first insulating layer can have a first via K1, a second via K2, and a third via K3; and the first insulating layer can be a first passivation layer or an organic ORG layer.
[0128] Based on the same inventive concept, the embodiment of the present disclosure further provides a display panel, wherein the display panel comprises the array substrate provided by the embodiment of the present disclosure, and further comprises a counter substrate arranged opposite to the array substrate; the counter substrate comprises a common electrode layer.
[0129] Specifically, the counter substrate can comprise a counter substrate, and the common electrode layer located on the side of the counter substrate facing the array substrate. Specifically, the counter substrate can further comprise a black matrix layer as shown in FIG. 2G, and the black matrix layer can comprise a black matrix pattern 81 and a black matrix opening.
[0130] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, wherein the display device comprises the display panel provided by the embodiment of the present disclosure.
[0131] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the present application.
[0132] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.
Claims
1. An array substrate, wherein, The application relates to a display panel, comprising: a substrate; a plurality of gate lines located on one side of the substrate and extending along a first direction; a plurality of data lines located on the same side of the substrate as the gate lines and extending along a second direction intersecting the first direction; a plurality of sub-pixel electrodes located on the same side of the substrate as the gate lines, at least one of the sub-pixel electrodes comprising two first sub-pixel electrodes arranged in sequence along the first direction and a second sub-pixel electrode located between the two first sub-pixel electrodes; the light-emitting brightness of the area where the second sub-pixel electrode is located is greater than the light-emitting brightness of the area where the first sub-pixel electrode is located; wherein the sub-pixel electrode comprises at least a first slit extending along the first direction, and the first slit passes through the central area of the sub-pixel electrode.
2. The array substrate of claim 1, wherein, The first slit is located in the first sub-pixel electrode.
3. The array substrate of claim 1 or 2, wherein, The first slit comprises a plurality of first sub-slits extending along the first direction and arranged along the second direction.
4. The array substrate of claim 3, wherein, The second sub-pixel electrode comprises a plurality of electrode pattern blocks arranged along the second direction and an electrode connecting portion connecting adjacent pattern blocks. The first sub-slit further comprises a first sub-slit portion and a second sub-slit portion extending along the first direction and arranged along the first direction; the first sub-slit portion and the second sub-slit portion are located on different sides of the electrode connecting portion.
5. The array substrate of claim 4, wherein, The first sub-pixel electrode further comprises a first sub-pixel electrode portion and a second sub-pixel electrode portion. The first sub-pixel electrode portion is arranged between two adjacent first sub-slits along the second direction; the second sub-pixel electrode portion is arranged between two adjacent second sub-slits along the second direction. The end of the first sub-slit portion away from the electrode connecting portion is a closed structure; the end of the second sub-slit portion away from the electrode connecting portion is a closed structure.
6. The array substrate of claim 4 or 5, wherein, The sub-pixel electrode further comprises a second slit extending along the second direction, and the extension line of the second slit passes through the central area of the sub-pixel electrode.
7. The array substrate of any one of claims 4-6, wherein, The electrode pattern block comprises a first pattern portion extending along the second direction and two second pattern portions connected with the first pattern portion; the two second pattern portions are respectively located on both sides of the first pattern portion along the first direction; 8. The array substrate of claim 7, wherein, The second slit is located between the first pattern portion and the second pattern portion. The electrode pattern block further comprises a pattern connecting portion located between the first pattern portion and the second pattern portion; the first pattern portion and the second pattern portion are electrically connected through the pattern connecting portion.
9. The array substrate of claim 8, wherein, The first pattern portion and the second pattern portion have two pattern connecting portions, and the two pattern connecting portions are respectively located at two end portions of the outer edge of the second pattern portion along the second direction and connect the second pattern portion and the first pattern portion at the end portions; 10. The array substrate of claim 9, wherein, The second slit is located between the two pattern connecting portions. 11. The array substrate of claim 9, wherein, The first pattern portion and the second pattern portion are connected by a pattern connecting portion, the pattern connecting portion being connected to a middle portion of an outer edge of the second pattern portion in the second direction and connecting the second pattern portion and the first pattern portion at the middle portion; The second slit is located between the first pattern portion and the second pattern portion and on both sides of the pattern connecting portion in the second direction.
12. The array substrate of any of claims 1-11, wherein, The array substrate further comprises a first common wire on one side of the gate line and a transfer electrode; the transfer electrode has an overlapping area with the first common wire in the orthographic projection of the substrate. The array substrate further comprises a pixel circuit; the pixel circuit comprises a first transistor, a second transistor, and a third transistor, The first transistor comprises a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor comprises a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor comprises a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode; The first transistor control electrode is multiplexed with the gate line, and the first transistor first electrode is multiplexed with the data line; the first transistor second electrode is electrically connected with the second sub-pixel electrode; The second transistor control electrode is multiplexed with the gate line, and the second transistor first electrode is multiplexed with the first transistor first electrode; the second transistor second electrode is electrically connected with the first sub-pixel electrode; The third transistor control electrode is multiplexed with the gate line, and the third transistor first electrode is multiplexed with the second transistor second electrode; the third transistor second electrode is electrically connected with the transfer electrode.
13. The array substrate of claim 12, wherein, Part of the orthographic projection of the second sub-pixel electrode overlaps with the orthographic projection of the gate line and the first common wire in the substrate.
14. The array substrate of any one of claims 1-11, wherein, The array substrate further comprises a pixel circuit; the pixel circuit comprises a first transistor, a second transistor, a third transistor, and a first signal line; The first transistor comprises a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor comprises a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor comprises a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode; The first transistor control electrode is multiplexed with the gate line, and the first transistor first electrode is multiplexed with the data line; the first transistor second electrode is electrically connected with the second sub-pixel electrode; The second transistor control electrode is multiplexed with the gate line, and the second transistor first electrode is multiplexed with the first transistor first electrode; the second transistor second electrode is electrically connected with the first sub-pixel electrode; The third transistor control electrode is multiplexed with the gate line, and the third transistor first electrode is multiplexed with the second transistor second electrode; the third transistor second electrode is multiplexed with the first signal line.
15. A display panel, wherein, The array substrate comprises a counter substrate arranged opposite to the array substrate; the counter substrate comprises a common electrode layer.
16. A display device comprising: The display panel as claimed in claim 15 is included.