Transistor, driving backplane, preparation method, and display device

Abstract

A transistor, a driving backplane, a preparation method, and a display device. The transistor comprises a first active portion, a first source, a first drain, and a first gate. The first active portion comprises a first source region, a first drain region, and a first channel region; the first channel region is arranged between the first source region and the first drain region; and the material of the first active portion comprises a first semiconductor material, and the first drain region further comprises a first ion. The first source is arranged on one side of the first active portion in a first direction and is in contact with the first source region, and the material of the first source comprises a second semiconductor material, wherein the second semiconductor material is different from the first semiconductor material, and the first direction is perpendicular to the first active portion. The first drain is arranged on one side of the first active portion in the first direction and is in contact with the first drain region. The first gate is arranged on one side of the first active portion in the first direction, and the orthographic projection of the first gate on the first active portion overlaps the first channel region.

Description

Transistor, driving backplane, manufacturing method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a transistor, a driving backplane, a manufacturing method thereof, and a display device. Background Art

[0002] With the development of display technology, display devices (such as mobile phones, laptops, and tablets) are increasingly used in people's lives. Among them, organic light-emitting diode (OLED) displays have attracted widespread attention due to their advantages such as active illumination, wide viewing angle, high contrast, fast response, low power consumption, and ultra-thinness.

[0003] Summary of the Invention

[0004] In one aspect, a transistor is provided. The transistor includes a first active portion, a first source, a first drain, and a first gate. The first active portion includes a first source region, a first drain region, and a first channel region; the first channel region is disposed between the first source region and the first drain region; the material of the first active portion includes a first semiconductor material, and the first drain region also includes first ions. The first source is disposed on one side of the first active portion along a first direction and in contact with the first source region. The material of the first source includes a second semiconductor material; the second semiconductor material is different from the first semiconductor material; wherein the first direction is perpendicular to the first active portion. The first drain is disposed on one side of the first active portion along the first direction and in contact with the first drain region. The first gate is disposed on one side of the first active portion along the first direction, and its orthographic projection on the first active portion overlaps with the first channel region.

[0005] In some embodiments, one of the first semiconductor material and the second semiconductor material includes an oxide semiconductor material, and the other includes a silicon-based semiconductor material.

[0006] In some embodiments, the material of the first source region further includes second ions, and the concentration of the second ions is 1×10^19 ions / cm^3 to 6×10^20 ions / cm^3; and / or, the material of the first source region further includes third ions, and the concentration of the third ions is 1×10^17 ions cm^3 to 1×10^22 ions / cm^3.

[0007] In some embodiments, the first gate is disposed on a side of the first active portion away from the first source, and its orthographic projection on the first active portion covers the first source region; the first drain is disposed on a side of the first active portion close to the first gate.

[0008] In another aspect, a driving backplane is provided. The driving backplane includes a substrate and a plurality of first-type transistors. The plurality of first-type transistors are disposed on one side of the substrate; wherein the first-type transistors are the transistors described in any of the above embodiments.

[0009] In some embodiments, the first source of the first type of transistor is disposed on a side of the first active portion of the first type of transistor away from the substrate, and the first drain of the first type of transistor is disposed on a side of the first source closer to the first active portion. The driver backplane further comprises a plurality of second type of transistors disposed on a side of the substrate closer to the first type of transistor. The second type of transistor includes a second active portion. The first active portion is made of low-temperature polysilicon, and the second active portion is made of an oxide semiconductor.

[0010] In some embodiments, the material of the first source electrode and the material of the second active portion are the same and are provided in the same layer.

[0011] In some embodiments, a material of the first source electrode includes indium tin oxide, and a material of the second active portion includes indium gallium zinc oxide.

[0012] In some embodiments, the driver backplane further comprises a plurality of light shielding blocks. The plurality of light shielding blocks are disposed between the substrate and the second active portion; the orthographic projection of one light shielding block on the substrate overlaps the orthographic projection of one second active portion on the substrate. The light shielding blocks are made of the same material and disposed on the same layer as the first active portion or the first source electrode.

[0013] In some embodiments, the second type of transistor further includes a second gate; and the light shielding block is multiplexed as the second gate.

[0014] In some embodiments, the second type of transistor further includes a third gate, which is disposed on a side of the second active portion away from the substrate. The third gate is made of the same material and is disposed in the same layer as the first drain in the first type of transistor.

[0015] In some embodiments, the first source in the first type of transistor is arranged on a side of the first active portion close to the substrate; the first drain in the first type of transistor is arranged on a side of the first active portion away from the substrate; the first gate in the first type of transistor is arranged on a side of the first active portion away from the first source, and its orthographic projection on the substrate covers the orthographic projection of the first source region in the first type of transistor on the substrate; the driving backplane also includes a plurality of first adapter blocks, the first adapter blocks and the first source electrodes are made of the same material and are arranged in the same layer, the first adapter blocks are connected to the first source electrodes, and the orthographic projection of the first adapter blocks on the substrate and the orthographic projection of the first type of transistor on the substrate are at least partially staggered; the first adapter block also includes a fourth ion, and the doping concentration of the fourth ion is 5×10^14ions / cm^2 to 5×10^15ions / cm^2.

[0016] In another aspect, a display device is provided, comprising the transistor or the driving backplane according to any one of the above embodiments.

[0017] In another aspect, a method for preparing a driving backplane is provided. The method includes forming a first type of transistor on a substrate; the first type of transistor includes a first active portion, a first source, a first drain, and a first gate; the first active portion includes a first source region, a first drain region, and a first channel region; the first channel region is disposed between the first source region and the first drain region; the material of the first active portion includes a first semiconductor material, and the first drain region also includes a first ion; the first source electrode is disposed on one side of the first active portion along a first direction and contacts the first source region, the material of the first source electrode includes a second semiconductor layer material; the second semiconductor material is different from the first semiconductor material; wherein the first direction is perpendicular to the first active portion; the first drain electrode is disposed on one side of the first active portion along the first direction and contacts the first drain region; the first gate is disposed on one side of the first active portion along the first direction, and its orthographic projection on the first active portion overlaps with the first channel region.

[0018] In some embodiments, forming the first type of transistor on the substrate includes forming a first semiconductor layer on the substrate; the first semiconductor layer includes the first active portion; forming a second semiconductor layer on a side of the first semiconductor layer away from the substrate; the second semiconductor layer includes a first source electrode;

[0019] In some embodiments, the second semiconductor layer further includes a second active portion; after forming the second semiconductor layer on a side of the first semiconductor layer away from the substrate, the preparation method further includes: forming a second conductive layer on a side of the second semiconductor layer away from the substrate; the second conductive layer includes a third gate, and the orthographic projection of the third gate on the substrate overlaps with the orthographic projection of the second active portion on the substrate.

[0020] In some embodiments, the second semiconductor layer further includes a second gate; after forming the second semiconductor layer on a side of the first semiconductor layer away from the substrate, the preparation method further includes: forming a third semiconductor layer on a side of the second semiconductor layer away from the substrate; the third semiconductor layer includes a second active portion, and the orthographic projection of the second active portion on the substrate overlaps with the orthographic projection of the second gate on the substrate.

[0021] In some embodiments, the first type of transistor formed on the substrate includes: forming a fourth semiconductor layer on the substrate; the fourth semiconductor layer includes a first source; forming a fifth semiconductor layer on a side of the fourth semiconductor layer away from the substrate; the fifth semiconductor layer includes the first active portion; forming a third conductive layer on a side of the fifth semiconductor layer away from the substrate; the third conductive layer includes the first gate; the orthographic projection of the first gate on the substrate overlaps with a portion of the first active portion that contacts the first source; forming a fourth conductive layer on a side of the third conductive layer away from the substrate; the fourth conductive layer includes a first drain.

[0022] In some embodiments, during the process of forming the first type of transistor on the substrate, an insulating layer is formed on a side of the first source and the first source region that is away from the substrate, and ions are doped into the first source and the first source region that is away from the substrate.

[0023] In some embodiments, the first active portion is disposed on a side of the first source electrode away from the substrate;

[0024] The forming of an insulating layer on a side of one of the first source and the first source region away from the substrate includes: forming a second insulating layer on a side of the first active layer away from the substrate; forming a first via and doping second ions into the first source region; the orthographic projection of the first via on the substrate overlaps with the orthographic projection of a portion of the first source region in contact with the first source on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0026] FIG1 is a structural diagram of a display device according to some embodiments;

[0027] FIG2 is another structural diagram of a display device according to some embodiments;

[0028] FIG3 is a cross-sectional view along section line AA in FIG1 ;

[0029] FIG4 is another cross-sectional view along section line AA in FIG1 ;

[0030] FIG5 is a structural diagram of a driving backplane according to some embodiments;

[0031] FIG6 is another structural diagram of a driving backplane according to some embodiments;

[0032] FIG7 is another structural diagram of a driving backplane according to some embodiments;

[0033] FIG8 is another structural diagram of a driving backplane according to some embodiments;

[0034] FIG9 is another structural diagram of a driving backplane according to some embodiments;

[0035] FIG10 is another structural diagram of a driving backplane according to some embodiments;

[0036] FIG11 is another structural diagram of a driving backplane according to some embodiments;

[0037] FIG12 is another structural diagram of a driving backplane according to some embodiments;

[0038] FIG13 is a diagram showing the relationship between the saturation current, drain voltage, and gate voltage of a transistor in the related art;

[0039] FIG14 is a diagram illustrating the relationship between the saturation current, drain voltage, and gate voltage of a transistor according to some embodiments;

[0040] FIG15 is a flow chart of a method for preparing a driving backplane according to some embodiments;

[0041] FIG16 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0042] 17 to 19 are diagrams showing steps for preparing a driving backplane according to some embodiments;

[0043] FIG20 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0044] 21 and 22 are diagrams showing another step of preparing a driving backplane according to some embodiments;

[0045] FIG23 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0046] 24 and 25 are diagrams showing another step of preparing a driving backplane according to some embodiments;

[0047] FIG26 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0048] FIG27 is a diagram illustrating another step of preparing a driving backplane according to some embodiments;

[0049] FIG28 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0050] 29 to 31 are diagrams showing another step of preparing a driving backplane according to some embodiments;

[0051] FIG32 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0052] FIG33 is a diagram illustrating another step of preparing a driving backplane according to some embodiments;

[0053] FIG34 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0054] 35 to 38 are diagrams showing another step of preparing a driving backplane according to some embodiments;

[0055] FIG39 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0056] FIG40 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0057] FIG41 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0058] 42 and 43 are diagrams showing another step of preparing a driving backplane according to some embodiments;

[0059] FIG44 is a flow chart of another method for preparing a driving backplane according to some embodiments;

[0060] 45 and 46 are diagrams showing another step of preparing a driving backplane according to some embodiments. DETAILED DESCRIPTION

[0061] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0062] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0063] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0064] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0065] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0066] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0067] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0068] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0069] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0070] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0071] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0072] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0073] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0074] Some embodiments of the present disclosure provide a display device 1000. As shown in FIG1 , the display device 1000 may be any product or component with a display function, such as a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, or a car central control screen.

[0075] The display device 1000 may be a liquid crystal display (LCD), an organic light-emitting display (OLED), a quantum dot light-emitting display (QLED), a micro light-emitting diode (Micro LED), a sub-millimeter light-emitting diode (Mini LED), or an active-matrix organic light-emitting diode (AMOLED) display.

[0076] It should be noted that Micro LED refers to an LED with a size (such as length) less than 50 μm, and Mini LED refers to an LED with a size (such as length) of 50 μm to 200 μm.

[0077] In some embodiments, the display device 1000 may be an OLED display device. As shown in FIG. 2 , the display device 1000 includes a driving backplane 100 , a light-emitting device 200 , and an encapsulation layer 300 , which are sequentially stacked.

[0078] The light emitting device 200 includes an anode 210, a light emitting functional layer 220, and a cathode 230. The anode 210 and the cathode 230 respectively inject holes and electrons into the light emitting functional layer 220. When the holes and electrons combine to generate excitons, they transition from an excited state to a ground state, generating light emission.

[0079] The encapsulation layer 300 is disposed on a side of the light-emitting device 200 away from the driver backplane 100. The encapsulation layer 300 may be an encapsulation film. The number of layers of encapsulation film included in the encapsulation layer 300 is not limited. In some embodiments, the encapsulation layer 300 may include a single layer of encapsulation film, or may include two or more layers of encapsulation film stacked together. For example, the encapsulation layer 300 includes three layers of encapsulation film stacked in sequence.

[0080] When the encapsulation layer 300 includes three layers of encapsulation films stacked in sequence, the encapsulation film in the middle layer is made of an organic material, while the encapsulation films on both sides are made of an inorganic material. The organic material may be, for example, polymethyl methacrylate (PMMA) or PI.

[0081] In other embodiments, the display device 1000 may be a liquid crystal display device (LCD) or a mini / micro light emitting display device (MLED), which is not specifically limited in the embodiments of the present disclosure.

[0082] As shown in FIG. 3 , when the display device 1000 is a liquid crystal display device, the liquid crystal display device includes a backlight module 110 and a display panel 120 .

[0083] The backlight module 110 has an emitting side 1101 and a non-emitting side 1102. The emitting side 1101 refers to the side of the backlight module 110 that can emit light (the upper side of the backlight module 110 in FIG3 ), and the non-emitting side 1102 refers to the side opposite the emitting side 1101 (the lower side of the backlight module 110 in FIG3 ). The display panel 120 is located on the display side of the backlight module 110.

[0084] The backlight module 110 is used to provide backlight for the display panel 120 . The display panel 120 can adjust the intensity (gray scale) of light passing through the display panel 120 , thereby realizing image display.

[0085] 3 , the backlight module 110 includes a driving backplane 100 and a light emitting device 200. The light emitting device 200 is disposed on one side of the driving backplane 100. The light emitting device 200 may include, for example, Micro LED and / or Mini LED.

[0086] In some embodiments, as shown in FIG. 3 , the backlight module further includes an optical film 400 . The optical film 400 is located on a side of the light emitting device 200 away from the driving backplane 100 .

[0087] The light emitting device 200 can directly emit white light, which is then homogenized by the multiple optical films 400 and then emitted toward the display panel 120. Alternatively, the light emitting device 200 can also emit light of other colors (e.g., blue light), which is then color-converted and homogenized by the multiple optical films 400 and then emitted toward the display panel 120.

[0088] As shown in FIG. 4 , when the display device 1000 is a micro-luminescent display device, the micro-luminescent display device includes a display panel 120 , and the display panel 120 includes a driving backplane 100 and a light-emitting device 200 .

[0089] The light emitting device 200 can emit light of multiple colors (eg, red light, blue light, and green light) to achieve full-color display.

[0090] In the following embodiments, the display device 1000 is an OLED display device as an example to schematically illustrate some embodiments of the present disclosure. However, the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical concept is applied.

[0091] In some embodiments, as shown in FIG. 2 , the driving backplane 100 includes a substrate 10 and a driving circuit stack 20 .

[0092] The substrate 10 may be a flexible substrate 10 or a rigid substrate 10. The material used for the substrate 10 may include a polymer resin or glass. For example, the substrate 10 may be flexible, and the material used for the substrate 10 may include a polymer resin, such as one of polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate two formal acid glycol ester (PEN), polyethylene terephthalate (PET), polyphenylene sulfide granule (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). Exemplarily, the substrate 10 may be rigid, and the material of the substrate 10 includes glass containing SiO 2 as a main component.

[0093] It should be noted that the substrate 10 can be a single-layer structure or a multi-layer structure. For example, in the case of a multi-layer structure, the substrate 10 can include a base and a buffer layer provided on the base. The buffer layer is provided on the base. The material used for the buffer layer can include inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON) and silicon oxide (SiOx, x>0). The buffer layer is used to provide a good foundation for the formation of thin films when thin films are formed on the substrate 10.

[0094] As shown in FIG. 2 , the driving circuit stack 20 is disposed on the substrate 10 . The driving circuit stack 20 includes a plurality of transistors 21 (Thin-Film Transistors, TFTs for short) and at least one storage capacitor 22 (Capacitor, C for short).

[0095] In some embodiments, the structure of the driving circuit stack 20 includes various structures, which can be selected according to actual needs. For example, the structure of the driving circuit stack 20 may include "2T1C", "3T1C", "6T1C", "7T1C", "8T1C", "6T2C", or "7T2C". Where "T" represents the transistor 21, and the number before "T" represents the number of transistors 21. "C" represents the storage capacitor 22, and the number before "C" represents the number of storage capacitors 22.

[0096] The transistor 21 provided in the embodiments of the present disclosure can be a P-type transistor or an N-type transistor. In the following embodiments, the transistor 21 is a P-type transistor as an example to schematically illustrate some embodiments of the present disclosure. However, the embodiments of the present disclosure are not limited thereto, and N-type transistors can also be considered, as long as the same technical concept is applied.

[0097] In the related art, the power consumption of transistors is relatively large, which results in relatively large power consumption of the display device.

[0098] In order to solve the above technical problems, as shown in Figures 5, 6, 7, 8, 9, 10, 11 and 12, some embodiments of the present disclosure provide a transistor 21, which includes a first active portion 211, a first source 212, a first drain 213 and a first gate 214.

[0099] The first active portion 211 includes a first source region 2111, a first drain region 2112, and a first channel region 2113. The first channel region 2113 is disposed between the first source region 2111 and the first drain region 2112. The first drain region 2112 further includes first ions. The first ions include at least one of boron ions, phosphorus ions, fluorine ions, helium ions, neon ions, argon ions, krypton ions, xenon ions, and radon ions.

[0100] It can be understood that the higher doping concentration of the first ions can make the first drain region 2112 conductive, so that the properties of the first drain region 2112 (eg, conductivity) are substantially the same as those of a conductor.

[0101] Exemplarily, the doping concentration of the first ion is 5×10^14 ions / cm^2 to 5×10^15 ions / cm^2. Exemplarily, the doping concentration of the first ion is 5×10^14 ions / cm^2, 8×10^14 ions / cm^2, 1×10^15 ions / cm^2, 3×10^15 ions / cm^2, or 5×10^15 ions / cm^2.

[0102] The first source electrode 212 is disposed on one side of the first active portion 211 along the first direction X and contacts the first source region 2111 . The first source electrode 212 is made of the second semiconductor material. The first direction X is perpendicular to the first active portion 211 .

[0103] The first drain electrode 213 is disposed on one side of the first active portion 211 along the first direction X and contacts the first drain region 2112. The first drain electrode 213 is formed of a metal. This arrangement forms an ohmic contact between the first drain electrode 213 and the first drain region 2112. For example, the first drain electrode 213 is formed of titanium or molybdenum.

[0104] The first gate 214 is disposed on one side of the first active portion 211 along the first direction X, and an orthographic projection of the first gate 214 on the first active portion 211 overlaps with the first channel region 2113 .

[0105] The second semiconductor material is different from the first semiconductor material, that is, the work function of the second semiconductor material is different from the work function of the first semiconductor material, and the Fermi level of the first source electrode 212 is different from the Fermi level of the first source region 2111. After the first source electrode 212 contacts the first source region 2111, the Fermi level of the first source electrode 212 and the Fermi level of the first source region 2111 reach equilibrium, that is, the Fermi level of the first source electrode 212 is equal to the Fermi level of the first source region 2111. At this time, a built-in electric field is formed between the first source electrode 212 and the first source region 2111, that is, a heterojunction barrier is formed between the first source electrode 212 and the first source region 2111. When a positive voltage is applied to the first gate 214, electrons in the first channel region 2113 accumulate in the first active portion 211 near the interface of the first gate 214, thereby opening the channel in the first active portion 211. At the same time, the first drain 213 is connected to a negative voltage, and the first source 212 is connected to a positive voltage. In this way, the heterojunction barrier is reduced. As the voltage of the first drain 213 increases, the heterojunction barrier gradually decreases until it is reverse biased. When the heterojunction barrier is reverse biased, electrons in the first source region 2111 flow toward the first source 212, that is, current can flow from the first source 212 to the first drain 213. As the voltage of the first drain 213 increases, the depletion layer in the first source region 2111 extends away from the first source 212. When the depletion layer extends to the surface of the first active portion 211 away from the first source 212, the current flowing from the first source 212 to the first drain 213 remains unchanged, that is, the current is saturated.

[0106] Based on the above structure, compared to related technologies, some embodiments of the present disclosure provide transistors 21 with a lower saturation voltage, as shown in Figures 13 and 14. In other words, applying a lower voltage to the first drain 213 of the transistor 21 of the present disclosure can place the transistor 21 in a saturation region, thereby enabling the transistor 21 to operate normally. This lower voltage can reduce the power consumption of the transistor 21, thereby reducing the power consumption of the display device 1000.

[0107] Generally, in order to reduce the power consumption of the transistor 21 , the voltage applied to the first drain 213 is equal to the saturation voltage of the transistor 21 .

[0108] It is understood that the voltage signal received by the first gate 214 is a timing signal. When the display device 1000 displays a black screen or is off, the voltage received by the first gate 214 is 0, the first gate 214 does not operate, and the power consumption of the first gate 214 is 0. When the display device 1000 is emitting light, the voltage received by the first gate 214 is an operating voltage (the operating voltage refers to the voltage that can turn on the transistor 21), the first gate 214 operates, and the power consumption of the first gate 214 is not 0.

[0109] The voltage signal received by the first drain electrode 213 is a DC signal. Therefore, when the display device 1000 displays a black screen, is off, or emits light, the first drain electrode 213 is working and the power consumption of the first drain electrode 213 is not zero.

[0110] Due to the above reasons, the operating time of the first gate 214 is shorter than the operating time of the first drain 213. Therefore, the power consumption of the transistor 21 is less correlated with the voltage at the first gate 214 and more correlated with the voltage at the first drain 213. In other words, increasing the voltage at the first gate 214 results in a smaller increase in the power consumption of the transistor 21, while increasing the voltage at the first drain 213 results in a larger increase in the power consumption of the transistor 21.

[0111] As shown in Figures 13 and 14, when the first gate voltage is the same and the first gate voltage 214 is increased by the same amount, the saturation voltage of the transistor 21 in the present disclosure increases less than that in the related art. Therefore, when the first gate voltage 214 is increased by the same amount, the power consumption of the transistor 21 in the present disclosure increases less.

[0112] For example, when the voltage of the first gate 214 increases from 6 V to 8 V, the saturation voltage of the transistor 21 in the related art increases from 3.8 V to 5.4 V, i.e., the saturation voltage increases by 1.6 V. The saturation voltage of the transistor 21 in the present disclosure increases from 1.4 V to 1.8 V, i.e., the saturation voltage increases by 0.4 V.

[0113] In some embodiments, a smaller saturation voltage results in a smaller saturation current of transistor 21 , while in some cases, transistor 21 requires a larger saturation current. As shown in FIG14 , the saturation current of transistor 21 can be increased by increasing the voltage of first gate 214 .

[0114] As shown in Figures 13 and 14, under the same saturation current, compared with the related art, the saturation voltage of the transistor 21 in the present disclosure is smaller, that is, the voltage at the first drain 213 is smaller, and the voltage at the first gate 214 is larger. The smaller voltage at the first drain 213 can reduce the power consumption of the transistor 21. Although the voltage of the first gate 214 is larger, the power consumption of the transistor 21 is less related to the voltage at the first gate 214. Therefore, increasing the voltage of the first gate 214 will increase the power consumption of the transistor 21 less. In summary, under the same saturation current, compared with the related art, the power consumption of the transistor 21 in the present disclosure is smaller.

[0115] In some embodiments, one of the first semiconductor material and the second semiconductor material comprises an oxide semiconductor material, and the other comprises a silicon-based semiconductor material. In this manner, the first semiconductor material and the second semiconductor material can be different.

[0116] Exemplarily, the first semiconductor material includes an oxide semiconductor material, and the second semiconductor material includes a silicon-based semiconductor material. Alternatively, exemplary, the first semiconductor material includes a silicon-based semiconductor material, and the second semiconductor material includes an oxide semiconductor material.

[0117] In some embodiments, the first semiconductor material includes at least one of indium tin oxide, indium zinc oxide, gallium zinc oxide, indium gallium tin oxide, or indium tin zinc oxide, and the silicon-based semiconductor material includes at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon.

[0118] In some embodiments, the material of the first source region 2111 further includes second ions, the concentration of which is 1×10^19 ions / cm^3 to 6×10^20 ions / cm^3; and / or the material of the first source region 212 further includes third ions, the concentration of which is 1×10^17 ions / cm^3 to 1×10^22 ions / cm^3. Arranged in this manner, the size of the heterojunction barrier can be adjusted, thereby adjusting the saturation current of the transistor 21 and increasing the applicability of the transistor 21. The second ions can include at least one of boron ions, phosphorus ions, fluorine ions, helium ions, neon ions, argon ions, krypton ions, xenon ions, and radon ions. The second ions are the same as the first ions, for example, both the second ions and the first ions include boron ions or phosphorus ions. Alternatively, the second ions are different from the first ions, for example, the second ions include one of boron ions and phosphorus ions, and the first ions include the other of boron ions and phosphorus ions.

[0119] The third ion may also include at least one of a boron ion, a phosphorus ion, a fluorine ion, a helium ion, a neon ion, an argon ion, a krypton ion, a xenon ion, and a radon ion. The third ion is the same as the first ion, for example, both the third ion and the first ion include a boron ion or a phosphorus ion. Alternatively, the third ion is different from the first ion, for example, the third ion includes one of a boron ion and a phosphorus ion, and the first ion includes the other of the boron ion and the phosphorus ion.

[0120] Illustratively, the concentration of the second ions is 1×10^19 ions / cm^3, 2×10^19 ions / cm^3, 5×10^19 ions / cm^3, 8×10^19 ions / cm^3, 1×10^20 ions / cm^3, 3×10^20 ions / cm^3, or 6×10^20 ions / cm^3.

[0121] The concentration of the third ion is 1×10^17 ions / cm^3, 5×10^17 ions / cm^3, 8×10^17 ions / cm^3, 1×10^18 ions / cm^3, 4×10^18 ions / cm^3, 7×10^18 ions / cm^3, 1×10^19 ions / cm^3, 5×10^19 ions / cm^3, 9×10^19 ions / cm^3, 1×10^20 ions / cm^3, 8×10^20 ions / cm^3, 1×10^21 ions / cm^3, 9×10^21 ions / cm^3 or 1×10^22 ions / cm^3.

[0122] In some embodiments, as shown in Figures 5, 6, 7, 8, 9, and 10, the first source electrode 212 and the first drain electrode 213 are located on the same side of the first active portion 211 along the first direction X. Alternatively, as shown in Figures 11 and 12, the first source electrode 212 and the first drain electrode 213 are located on both sides of the first active portion 211.

[0123] 11 and 12 , the first gate 214 is disposed on a side of the first active portion 211 away from the first source 212, and its orthographic projection on the first active portion 211 covers the first source region 2111. The first drain 213 is disposed on a side of the first active portion 211 close to the first gate 214.

[0124] In this manner, when doping the first ions into the first active portion 211 , the first gate 214 can serve as a mask, thus eliminating the need to manufacture a separate mask plate, thereby reducing manufacturing costs.

[0125] In some embodiments, as shown in FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , FIG. 10 , FIG. 11 and FIG. 12 , the driving circuit stack 20 includes a plurality of first-type transistors 201 , which are the transistors 21 of any of the above embodiments.

[0126] In some embodiments, as shown in Figures 5, 6, 7, 8, 9 and 10, the first source 212 of the first type transistor 201 is arranged on a side of the first active portion 211 of the first type transistor 201 away from the substrate 10, and the first drain 213 of the first type transistor 201 is arranged on a side of the first source 212 close to the first active portion 211.

[0127] On this basis, the driving circuit stack 20 further includes a plurality of second-type transistors 202 . The plurality of second-type transistors 202 are disposed on a side of the substrate 10 close to the first-type transistors 201 , and the second-type transistors 202 include a second active portion 2021 .

[0128] The first active portion 211 is made of low-temperature polysilicon, meaning the first type of transistor 201 is a low-temperature polysilicon transistor. The second active portion 2021 is made of an oxide semiconductor material, meaning the second type of transistor 202 is an oxide thin-film transistor. In this way, the warm polysilicon transistor and the oxide transistor are integrated on a single driver backplane 100.

[0129] Based on the advantages of low-temperature polysilicon transistors such as high mobility and fast charging, and the advantages of oxide transistors such as low leakage current, integrating low-temperature polysilicon transistors and oxide transistors on a driving backplane can reduce the power consumption of the driving backplane 100 and improve the display quality of the display device 1000.

[0130] In some embodiments, as shown in Figures 5, 6, 7, 8, 9, and 10, the second type transistor 202 further includes a second source 2022, a second drain 2023, and a third gate 2024. The second source 2022 contacts the second source region in the second active portion 2021, and the second drain 2023 contacts the second drain region in the second active portion 2021. The second source 2022 and the second drain 2023 are made of the same material and are disposed in the same layer. The third gate 2024 is disposed between the second source 2022 and the second active portion 2021, and its orthographic projection on the substrate 10 overlaps with the orthographic projection of the second channel region of the second active portion 2021 on the substrate 10.

[0131] In some embodiments, as can be seen from the above, when the material of the first active portion 211 includes low-temperature polysilicon material, the material of the first source 212 includes oxide semiconductor material, and the material of the second active portion also includes oxide semiconductor material, so the material of the first source 212 can be made the same or different as needed.

[0132] 5, 6, 7, and 8, the first source 212 is made of the same material as the second active portion 2021 and is disposed in the same layer. In this manner, the first source 212 and the second active portion 2021 can be formed through a single patterning process.

[0133] Here, "A and B" being arranged in the same layer means that, along the thickness direction of the substrate, the film layers adjacent to A and B are the same film layer. For example, the side of A close to the substrate directly contacts the first film layer, and the side away from the substrate directly contacts the second film layer. Similarly, the side of B close to the substrate directly contacts the first film layer, and the side away from the substrate directly contacts the second film layer. A and B can be formed by the same or different processes.

[0134] In other examples, as shown in FIG. 9 and FIG. 10 , the material of the first source electrode 212 is different from the material of the second active portion 2021 .

[0135] For example, the material of the first source electrode 212 includes indium tin oxide. Indium tin oxide has a relatively low sheet resistance, which can improve the conductivity of the first source electrode 212.

[0136] For example, the sheet resistance of ITO is 20Ω to 80Ω. For example, the sheet resistance of ITO is 20Ω, 25Ω, 32Ω, 37Ω, 40Ω, 45Ω, 51Ω, 58Ω, 62Ω, 69Ω, 72Ω, 76Ω, or 80Ω.

[0137] The material of the second active portion 2021 includes indium gallium zinc oxide, which has a relatively large sheet resistance, thereby reducing leakage current in the second active portion 2021 .

[0138] For example, the sheet resistance of indium gallium zinc oxide is 2000Ω to 8000Ω. For example, the sheet resistance of indium tin oxide is 2000Ω, 2500Ω, 3200Ω, 3700Ω, 4000Ω, 4500Ω, 5100Ω, 5800Ω, 6200Ω, 6900Ω, 7200Ω, 7600Ω, or 8000Ω.

[0139] On this basis, as shown in FIG9 , the first source electrode 212 and the second active portion 2021 are provided in the same layer, which is beneficial to reducing the number of insulating layers in the driving circuit stack 20 and lowering the manufacturing cost.

[0140] In some embodiments, as shown in Figures 8 and 10, on the basis that the material of the second active portion 2021 includes an oxide semiconductor material, the driver circuit stack 20 further includes a plurality of light shielding blocks 2001, which are disposed between the substrate 10 and the second active portion 2021. The orthographic projection of one light shielding block 2001 on the substrate 10 overlaps with the orthographic projection of one second active portion 2021 on the substrate 10. In this arrangement, light emitted from the substrate 10 toward the second active portion 2021 is blocked by the light shielding blocks 2001 and prevents the light from reaching the second active portion 2021, thereby reducing the risk of threshold voltage shift of the second-type transistor 202.

[0141] On this basis, the light shielding block 2001 and the first active portion 211 or the first source electrode 212 are made of the same material and are disposed on the same layer. In this way, the light shielding block 2001 and the first active portion 211 or the first source electrode 212 can be formed through a single patterning process, thereby reducing manufacturing costs.

[0142] 8 , the second active portion 2021 and the first source electrode 212 are disposed on the same layer, and the light shielding block 2001 and the first active portion 211 are made of the same material and disposed on the same layer. In this case, the light shielding block 2001 and the first active portion 211 can be formed through a single patterning process.

[0143] In other embodiments, as shown in Figure 10, the second active portion 2021 is arranged on the side of the first active portion 211 away from the substrate 10, and the light-shielding block 2001 and the first source 212 are made of the same material and are arranged in the same layer. In this way, the light-shielding block 2001 and the first source 212 can be formed by a single patterning process.

[0144] In some embodiments, as shown in FIG. 8 and FIG. 10 , the second type transistor 202 further includes a second gate 2025 , and the light shielding block 2001 can be reused as the second gate 2025 .

[0145] It should be noted that, when the light shielding block 2001 is reused as the second gate 2025 , the light shielding block 2001 needs to be made conductive.

[0146] In some embodiments, as shown in Figures 5, 6, 7, 8, 9, and 10, the driver circuit stack 20 further includes a plurality of second adapter blocks 23. The second adapter blocks 23 and the second source electrode 2022 are made of the same material and are disposed on the same layer. The second adapter blocks 23 are connected to the first source electrode 212 through vias.

[0147] As shown in FIG5 , the first drain 213 and the first source 212 are arranged in the same layer, and the driving circuit stack 20 further includes a plurality of third adapter blocks 24. The third adapter blocks 24 and the second source 2022 are made of the same material and arranged in the same layer, and the third adapter blocks 24 are connected to the first drain 213 through vias.

[0148] Alternatively, as shown in FIG6 , the first drain electrode 213 and the third gate electrode 2024 are made of the same material and are disposed on the same layer, and the driving circuit stack 20 further includes a plurality of third adapter blocks 24. The third adapter blocks 24 are made of the same material and are disposed on the same layer as the second source electrode 2022, and are connected to the first drain electrode 213 through vias.

[0149] Alternatively, as shown in FIG. 7 , the first drain electrode 213 and the second source electrode 2022 are made of the same material and are provided in the same layer.

[0150] In some embodiments, as shown in Figures 11 and 12, the first source 212 in the first type of transistor 201 is arranged on a side of the first active portion 211 close to the substrate 10, the first drain 213 is arranged on a side of the first active portion 211 away from the substrate 10, and the first gate 214 in the first type of transistor 201 is arranged on a side of the first active portion 211 away from the first source 212, and its orthographic projection on the substrate 10 covers the orthographic projection of the first source region 2111 on the substrate 10.

[0151] On this basis, as shown in Figures 11 and 12, the driver circuit stack 20 further includes a plurality of first adapter blocks 25. The first adapter blocks 25 and the first source electrode 212 are made of the same material and are disposed in the same layer. The first adapter blocks 25 are connected to the first source electrode 212, and the orthographic projections of the first adapter blocks 25 on the substrate 10 and the orthographic projections of the first type transistor 201 on the substrate 10 are at least partially staggered. The first adapter blocks 25 further include fourth ions, which include boron ions, phosphorus ions, fluorine ions, helium ions, neon ions, argon ions, krypton ions, xenon ions, or radon ions.

[0152] It is understandable that the doping concentration of the fourth ion is relatively high, so that the fourth ion can make the first transfer block 25 conductive, thereby making the properties of the first transfer block 25 (eg, conductivity) substantially the same as those of a conductor.

[0153] Exemplarily, the doping concentration of the fourth ion is 5×10^14 ions / cm^2 to 5×10^15 ions / cm^2. Exemplarily, the doping concentration of the fourth ion is 5×10^14 ions / cm^2, 8×10^14 ions / cm^2, 1×10^15 ions / cm^2, 3×10^15 ions / cm^2, or 5×10^15 ions / cm^2.

[0154] In some embodiments, as shown in FIG11 , the driving circuit stack 20 further includes a plurality of fourth transfer blocks 26 . The fourth transfer blocks 26 and the first drain electrode 213 are made of the same material and are disposed in the same layer. The fourth transfer blocks 26 are connected to the first transfer blocks 25 through vias.

[0155] In some embodiments, as shown in Figure 12, the driving circuit stack 20 also includes a plurality of fifth adapter blocks 27. The fifth adapter blocks 27 and the first gate 214 are made of the same material and are arranged in the same layer. The fifth adapter blocks 27 are connected to the first adapter blocks 25 through vias, and the fourth adapter blocks 26 are connected to the fifth adapter blocks 27 through vias.

[0156] Some embodiments of the present disclosure further provide a method for preparing a driving backplane 100 . As shown in FIG. 15 , the preparation method includes S100 .

[0157] As shown in FIG. 15 , S100 : forming a first type transistor 201 on a substrate 10 .

[0158] In the above steps, as shown in FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , FIG. 10 , FIG. 11 and FIG. 12 , the first type of transistor 21 includes a first active portion 211 , a first source 212 , a first drain 213 and a first gate 214 .

[0159] The first active portion 211 includes a first source region 2111, a first drain region 2112 and a first channel region 2113. The first channel region 2113 is arranged between the first source region 2111 and the first drain region 2112. The material of the first active portion 211 includes a first semiconductor material, and the first drain region 2112 also includes a first ion. Among them, the first ion includes boron ions, phosphorus ions, fluorine ions, helium ions, neon ions, argon ions, krypton ions, xenon ions or radon ions. The type of the first ion is selected according to actual conditions. The concentration of the first ion is high, so that the first drain region 2112 can be made conductive. That is, the properties of the first drain region 2112 after doping with the first ion (for example, conductivity) are roughly the same as the properties of the conductor.

[0160] Exemplarily, the doping concentration of the first ion is 5×10^14 ions / cm^2 to 5×10^15 ions / cm^2. Exemplarily, the doping concentration of the first ion is 5×10^14 ions / cm^2, 8×10^14 ions / cm^2, 1×10^15 ions / cm^2, 3×10^15 ions / cm^2, or 5×10^15 ions / cm^2.

[0161] The first source electrode 212 is disposed on one side of the first active portion 211 along the first direction X and contacts the first source region 2111 . The material of the first source electrode 212 includes the second semiconductor layer material.

[0162] The first direction X is perpendicular to the first active portion 211. The first drain electrode 213 is disposed on one side of the first active portion 211 along the first direction X and contacts the first drain region 2112. The first drain electrode 213 is made of a metal, for example, titanium or molybdenum. This arrangement forms an ohmic contact between the first drain electrode 213 and the first drain region 2112.

[0163] The first gate 214 is disposed on one side of the first active portion 211 along the first direction X, and an orthographic projection of the first gate 214 on the first active portion 211 overlaps with the first channel region 2113 .

[0164] The second semiconductor material is different from the first semiconductor material. In this way, a heterojunction barrier is formed between the first source 212 and the first source region 2111 , thereby reducing the saturation voltage of the first type of transistor 201 and further reducing the power consumption of the first type of transistor 201 .

[0165] As shown in FIG. 16 , S100 includes S110 and S120 .

[0166] As shown in FIG. 17 , S110 , a first semiconductor layer 1 is formed on a substrate 10 .

[0167] In the above steps, the first semiconductor layer 1 can be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The first semiconductor layer 1 includes a first active portion 211 .

[0168] As shown in FIG. 18 and FIG. 19 , S120 , a second semiconductor layer 2 is formed on a side of the first semiconductor layer 1 away from the substrate 10 .

[0169] The second semiconductor layer 2 may be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The second semiconductor layer 2 includes a first source electrode 212 .

[0170] In some embodiments, as shown in FIG. 20 , between S110 and S120 , S100 further includes S111 to S112 .

[0171] As shown in FIG. 21 , S111 : forming a third insulating layer 103 on a side of the first semiconductor layer 1 away from the substrate 10 .

[0172] In the above steps, the third insulating layer 103 may be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process, and the third insulating layer 103 is configured to block ions from passing through.

[0173] Exemplarily, the material of the third insulating layer 103 includes photoresist.

[0174] As shown in FIG. 22 , S112 : forming a second via hole 1002 , and doping the first active portion 211 with first ions.

[0175] In the above steps, the orthographic projection of the second via 1002 on the substrate 10 overlaps with the orthographic projection of the first drain region 2112 on the substrate 10. In this way, the first ions can pass through the second via 1002 to reach the first source region 2111, thereby making the first drain region 2112 conductive.

[0176] It is understandable that after the first drain region 2112 is doped with the first ions, the third insulating layer 103 needs to be removed.

[0177] In some embodiments, as shown in Fig. 18 , the second semiconductor layer 2 further includes a second active portion 2021. As shown in Fig. 23 , after S120, the preparation method further includes S200 to S300.

[0178] As shown in FIG. 24 , S200 : forming a second conductive layer 3 on a side of the second semiconductor layer 2 away from the substrate 10 .

[0179] In the above steps, the second conductive layer 3 can be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The second conductive layer 3 includes a third gate 2024, and the orthographic projection of the third gate 2024 on the substrate 10 overlaps with the orthographic projection of the second active portion 2021 on the substrate 10.

[0180] As shown in FIG. 25 , S300 : forming a fifth conductive layer 4 on a side of the second conductive layer 3 away from the substrate 10 .

[0181] The fifth conductive layer 4 can be formed by at least one of a thin film deposition process, an electroplating process, and an electroless plating process. The fifth conductive layer 4 includes a second source electrode 2022 and a second drain electrode 2023. The second source electrode 2022 contacts the second source region 2022 in the second active portion 2021, and the second drain electrode 2023 contacts the second drain region 2023 in the second active portion 2021. The second active portion 2021, the third gate 2024, the second source electrode 2022, and the second drain electrode 2023 form the second type transistor 202.

[0182] In some embodiments, as shown in FIG. 26 , between S120 and S200 , S100 further includes S130 .

[0183] As shown in FIG. 27 , S130 : forming a first drain electrode 213 on a side of the first semiconductor layer 1 away from the substrate 10 .

[0184] In the above steps, the first drain electrode 213 can be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The first drain electrode 213 and the first source electrode 212 are disposed in the same layer, which helps reduce the number of insulating layers in the driver circuit stack, thereby reducing the manufacturing cost.

[0185] In other embodiments, as shown in FIG6 , the second conductive layer 3 further includes a first drain electrode 213 , that is, the first drain electrode 213 and the third gate electrode 2024 are made of the same material and are disposed in the same layer. In this way, the first drain electrode 213 and the third gate electrode can be formed through a single patterning process, thereby reducing the manufacturing cost.

[0186] On this basis, the driving circuit stack 20 further includes a third adapter block 24. The third adapter block 24 and the second drain electrode 2023 are made of the same material and are provided in the same layer. The third adapter block 24 is connected to the first drain electrode 213 through a via.

[0187] In some other embodiments, as shown in FIG7 , the fifth conductive layer 4 includes a first drain electrode 213 , that is, the first drain electrode 213 and the second drain electrode 2023 are made of the same material and are disposed in the same layer. In this way, the first drain electrode 213 and the second drain electrode 2023 can be formed by a single patterning process.

[0188] In some embodiments, as shown in Figure 19, the second semiconductor layer 2 further includes a second gate 2025. As shown in Figure 28, after S120, the preparation method further includes S400 to S600.

[0189] As shown in FIG. 29 , S400 : forming a third semiconductor layer 5 on a side of the second semiconductor layer 2 away from the substrate 10 .

[0190] In the above steps, the third semiconductor layer 5 can be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The third semiconductor layer 5 includes a second active portion 2021, and the orthographic projection of the second active portion 2021 on the substrate 10 overlaps with the orthographic projection of the second gate 2025 on the substrate 10.

[0191] As shown in FIG. 30 , S500 : forming a second conductive layer 3 on a side of the second active portion 2021 away from the substrate 10 .

[0192] In the above steps, the second conductive layer 3 can be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The second conductive layer 3 includes a third gate 2024, and the orthographic projection of the third gate 2024 on the substrate 10 overlaps with the orthographic projection of the second active portion 2021 on the substrate 10.

[0193] As shown in FIG. 31 , S600 : forming a fifth conductive layer 4 on a side of the second conductive layer 3 away from the substrate 10 .

[0194] The fifth conductive layer 4 can be formed by at least one of a thin film deposition process, an electroplating process, and an electroless plating process. The fifth conductive layer 4 includes a second source electrode 2022 and a second drain electrode 2023. The second source electrode 2022 contacts the second source region 2022 in the second active portion 2021, and the second drain electrode 2023 contacts the second drain region 2023 in the second active portion 2021. The second active portion 2021, the second source electrode 2022, the second drain 2023, the third gate electrode 2024, and the second gate electrode 2025 form the second type transistor 202.

[0195] In some embodiments, as shown in FIG. 32 , between S120 and S400 , S100 further includes S140 .

[0196] As shown in FIG. 33 , S140 : forming a first drain electrode 213 on a side of the first semiconductor layer 1 away from the substrate 10 .

[0197] In the above steps, the first drain electrode 213 can be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The first drain electrode 213 and the first source electrode 212 are disposed in the same layer, which helps reduce the number of insulating layers in the driver circuit stack, thereby reducing the manufacturing cost.

[0198] 10 , the driving circuit stack 20 further includes a third adapter block 24 , which is made of the same material and provided on the same layer as the second drain electrode 2023 . The third adapter block 24 is connected to the first drain electrode 213 through a via.

[0199] In other embodiments, as shown in FIG6 , the second conductive layer 3 further includes a first drain electrode 213 , that is, the first drain electrode 213 and the third gate electrode 2024 are made of the same material and are disposed in the same layer. In this way, the first drain electrode 213 and the third gate electrode can be formed through a single patterning process, thereby reducing the manufacturing cost.

[0200] On this basis, the driving circuit stack further includes a third adapter block 24. The third adapter block 24 and the second drain electrode 2023 are made of the same material and are provided in the same layer. The third adapter block 24 is connected to the first drain electrode 213 through a via.

[0201] In some other embodiments, as shown in FIG7 , the fifth conductive layer 4 includes a first drain electrode 213 , that is, the first drain electrode 213 and the second drain electrode 2023 are made of the same material and are disposed in the same layer. In this way, the first drain electrode 213 and the second drain electrode 2023 can be formed by a single patterning process.

[0202] In some embodiments, as shown in FIG. 34 , S100 includes S150 to S180 .

[0203] As shown in FIG. 35 , S150 : forming a fourth semiconductor layer 6 on the substrate 10 .

[0204] The fourth semiconductor layer 6 can be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The fourth semiconductor layer 6 includes a first source electrode 212 .

[0205] As shown in FIG. 36 , at S160 , a fifth semiconductor layer 7 is formed on a side of the fourth semiconductor layer 6 away from the substrate 10 .

[0206] The fifth semiconductor layer 7 may be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The fifth semiconductor layer 7 includes a first active portion 211 .

[0207] As shown in FIG. 37 , at S170 , a third conductive layer 8 is formed on a side of the fifth semiconductor layer 7 away from the substrate 10 .

[0208] The third conductive layer 8 can be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The third conductive layer 8 includes a first gate electrode 214. The orthographic projection of the first gate electrode 214 on the substrate 10 overlaps with the portion of the first active portion 211 that contacts the first source electrode 212.

[0209] As shown in FIG. 38 , at S180 , a fourth conductive layer 9 is formed on a side of the third conductive layer 8 away from the substrate 10 .

[0210] The fourth conductive layer 9 can be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process. The fourth conductive layer 9 includes a first drain electrode 213 .

[0211] In some embodiments, as shown in FIG. 39 , between S170 and S180 , S100 further includes S171 .

[0212] S171: Using the first gate 214 as a mask, the first drain region 2112 is conductive.

[0213] In some embodiments, as shown in FIG. 40 , S100 further includes S1100 and S1200 .

[0214] S1100 : forming an insulating layer on a side of one of the first source 212 and the first source region 2111 away from the substrate 10 .

[0215] In the above steps, the insulating layer may be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process, and the insulating layer covers the first source electrode 212 .

[0216] S1200 : doping ions into the first source 212 or the first source region 2111 , the one farther from the substrate 10 .

[0217] In this manner, the size of the heterojunction barrier between the first source 212 and the first source region 2111 can be adjusted, thereby adjusting the saturation current of the first type of transistor 201 and increasing the use range of the first type of transistor 201.

[0218] In some embodiments, the first source 212 is disposed on a side of the first active portion 211 away from the substrate 10 . As shown in FIG. 41 , S1100 includes S1110 , and S1200 includes S1210 .

[0219] As shown in FIG. 42 , S1110 : forming a first insulating layer 101 on a side of the first active portion 211 away from the substrate 10 .

[0220] In the above steps, the first insulating layer 101 may be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process, and the first insulating layer 101 covers the first source electrode 212 .

[0221] Exemplarily, the material of the first insulating layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0222] As shown in FIG. 43 , S1210 : doping the first source region 2111 with third ions.

[0223] In some other embodiments, the first active portion 211 is disposed on a side of the first source 212 away from the substrate 10. As shown in Figure 44, S1100 includes S1120, and S1200 includes S1220.

[0224] As shown in FIG. 45 , S1120 : forming a second insulating layer 102 on a side of the first active layer away from the substrate 10 .

[0225] In the above steps, the second insulating layer 102 can be formed by at least one of a thin film deposition process, an electroplating process, and a chemical plating process, and the second insulating layer 102 covers the first active portion 211. The second insulating layer 102 is configured to block ions from passing through.

[0226] Exemplarily, the material of the second insulating layer 102 includes photoresist.

[0227] As shown in FIG. 46 , S1220 : forming a first via hole 1001 , and doping the first source region 2111 with second ions.

[0228] In the above steps, the orthographic projection of the first via 1001 on the substrate 10 overlaps with the orthographic projection of the portion of the first source region 2111 that contacts the first source electrode 212 on the substrate 10. With this arrangement, ions can pass through the first via 1001 and reach the first source region 2111, thereby changing the work function of the first source region 2111 and, in turn, the size of the heterojunction barrier between the first source region 2111 and the first source electrode 212.

[0229] It is understandable that after the first source region 2111 is doped with the second ions, the second insulating layer 102 needs to be removed.

[0230] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0231] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A transistor comprising: a first active portion comprising a first source region, a first drain region, and a first channel region; the first channel region being disposed between the first source region and the first drain region; The material of the first active portion includes a first semiconductor material, and the first drain region further includes first ions; a first source electrode disposed on one side of the first active portion along a first direction and in contact with the first source region, wherein the first source electrode is made of a second semiconductor material; the second semiconductor material is different from the first semiconductor material; wherein the first direction is perpendicular to the first active portion; a first drain electrode, disposed on one side of the first active portion along the first direction and in contact with the first drain region; The first gate is disposed on one side of the first active portion along the first direction, and an orthographic projection of the first gate on the first active portion overlaps with the first channel region.

2. The transistor according to claim 1, wherein One of the first semiconductor material and the second semiconductor material includes an oxide semiconductor material, and the other includes a silicon-based semiconductor material.

3. The transistor according to claim 1 or 2, wherein: The material of the first source region also includes second ions, and the concentration of the second ions is 1×10^19 ions / cm^3 to 6×10^20 ions / cm^3; and / or, the material of the first source region also includes third ions, and the concentration of the third ions is 1×10^17 ions cm^3 to 1×10^22 ions / cm^3.

4. The transistor according to any one of claims 1 to 3, wherein The first gate is arranged on a side of the first active portion away from the first source, and its orthographic projection on the first active portion covers the first source region; the first drain is arranged on a side of the first active portion close to the first gate.

5. A driving backplane, comprising: substrate; A plurality of first-type transistors are arranged on one side of the substrate; wherein the first-type transistors are the transistors according to any one of claims 1 to 4.

6. The driving backplane according to claim 5, wherein: The first source of the first type of transistor is arranged on a side of the first active portion of the first type of transistor away from the substrate, and the first drain of the first type of transistor is arranged on a side of the first source close to the first active portion; The driving backplane further includes: A plurality of second-type transistors are arranged on a side of the substrate close to the first-type transistors; the second-type transistors include a second active portion; the material of the first active portion includes low-temperature polysilicon material, and the material of the second active portion includes oxide semiconductor material.

7. The driving backplane according to claim 6, wherein: The first source electrode and the second active portion are made of the same material and are provided in the same layer.

8. The driving backplane according to claim 6, wherein: A material of the first source electrode includes indium tin oxide, and a material of the second active portion includes indium gallium zinc oxide.

9. The driving backplane according to any one of claims 6 to 8, further comprising: a plurality of light shielding blocks, disposed between the substrate and the second active portion; An orthographic projection of one of the light shielding blocks on the substrate overlaps with an orthographic projection of one of the second active portions on the substrate; The light shielding block and the first active portion or the first source electrode are made of the same material and are provided in the same layer.

10. The driving backplane according to claim 9, wherein: The second type of transistor also includes a second gate; the light shielding block is multiplexed as the second gate.

11. The driving backplane according to any one of claims 5 to 10, wherein: The second type of transistor further includes a third gate, which is arranged on a side of the second active portion away from the substrate. The third gate is made of the same material and is arranged in the same layer as the first drain in the first type of transistor.

12. The driving backplane according to claim 5, wherein: The first source of the first type of transistor is arranged on a side of the first active portion close to the substrate; the first drain of the first type of transistor is arranged on a side of the first active portion away from the substrate; the first gate of the first type of transistor is arranged on a side of the first active portion away from the first source, and its orthographic projection on the substrate covers the orthographic projection of the first source region of the first type of transistor on the substrate; The driving backplane also includes a plurality of first adapter blocks, the first adapter blocks and the first source electrode are made of the same material and are arranged in the same layer, the first adapter blocks are connected to the first source electrode, and the orthographic projection of the first adapter block on the substrate and the orthographic projection of the first type of transistor on the substrate are at least partially staggered; the first adapter block also includes a fourth ion, and the doping concentration of the fourth ion is 5×10^14ions / cm^2~5×10^15ions / cm^2.

13. A display device comprising the transistor according to any one of claims 1 to 4, or the driving backplane according to any one of claims 5 to 12.

14. A method for preparing a driving backplane, comprising: A first type of transistor is formed on a substrate; the first type of transistor includes a first active portion, a first source, a first drain and a first gate; the first active portion includes a first source region, a first drain region and a first channel region; the first channel region is arranged between the first source region and the first drain region; the material of the first active portion includes a first semiconductor material, and the first drain region also includes a first ion; the first source is arranged on one side of the first active portion along the first direction and contacts the first source region, and the material of the first source includes a second semiconductor layer material; the second semiconductor material is different from the first semiconductor material; wherein the first direction is perpendicular to the first active portion; the first drain is arranged on one side of the first active portion along the first direction and contacts the first drain region; the first gate is arranged on one side of the first active portion along the first direction, and its positive projection on the first active portion overlaps with the first channel region.

15. The preparation method according to claim 14, wherein The first type of transistor formed on the substrate includes: forming a first semiconductor layer on the substrate; the first semiconductor layer includes the first active portion; A second semiconductor layer is formed on a side of the first semiconductor layer away from the substrate; the second semiconductor layer includes the first source electrode.

16. The preparation method according to claim 15, wherein The second semiconductor layer further includes a second active portion; After forming a second semiconductor layer on a side of the first semiconductor layer away from the substrate, the preparation method further includes: forming a second conductive layer on a side of the second semiconductor layer away from the substrate; The second conductive layer includes a third gate, and an orthographic projection of the third gate on the substrate overlaps with an orthographic projection of the second active portion on the substrate.

17. The preparation method according to claim 15, wherein The second semiconductor layer further includes a second gate; After forming a second semiconductor layer on a side of the first semiconductor layer away from the substrate, the preparation method further includes: A third semiconductor layer is formed on a side of the second semiconductor layer away from the substrate; the third semiconductor layer includes a second active portion, and an orthographic projection of the second active portion on the substrate overlaps with an orthographic projection of the second gate on the substrate.

18. The preparation method according to claim 14, wherein The first type of transistor formed on the substrate includes: forming a fourth semiconductor layer on the substrate; the fourth semiconductor layer including the first source electrode; forming a fifth semiconductor layer on a side of the fourth semiconductor layer away from the substrate; the fifth semiconductor layer includes the first active portion; forming a third conductive layer on a side of the fifth semiconductor layer away from the substrate; the third conductive layer includes the first gate; an orthographic projection of the first gate on the substrate overlaps with a portion of the first active portion that contacts the first source electrode; A fourth conductive layer is formed on a side of the third conductive layer away from the substrate; the fourth conductive layer includes a first drain.

19. The preparation method according to any one of claims 14 to 18, wherein In the process of forming the first type of transistor on the substrate, an insulating layer is formed on the side of the first source and the first source region that is away from the substrate, and ions are doped into the side of the first source and the first source region that is away from the substrate.

20. The manufacturing method according to claim 19, wherein the first active portion is disposed on a side of the first source electrode away from the substrate; The forming of an insulating layer on a side of one of the first source electrode and the first source region that is away from the substrate and away from the substrate comprises: forming a second insulating layer on a side of the first active layer away from the substrate; A first via is formed, and second ions are doped into the first source region; an orthographic projection of the first via on the substrate overlaps with an orthographic projection of a portion of the first source region in contact with the first source on the substrate.

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