Display substrate and display device

Abstract

A display substrate, comprising a first frame area (B1) and a second frame area (B2) which are communicated with each other, wherein the first frame area (B1) comprises a bending area (B02) located on one side of a display area (AA) in a first direction (D1). The display substrate comprises: a base (10); a plurality of sub-pixels (PX) arranged on the base (10) and located in the display area (AA); a plurality of gate driving circuits located in the second frame area (B2); and at least one first peripheral control line (L1) and a plurality of second peripheral control lines (L2, L3) located in the first frame area (B1). The potential of a signal transmitted by each first peripheral control line (L1) is lower than the potential of a signal transmitted by each second peripheral control line (L2, L3). In the bending area (B02), at least one second peripheral control line (L2) is located between at least one first peripheral control line (L1) and the boundary of the display substrate.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, and in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility and low cost.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] The present embodiment provides a display substrate and a display device.

[0006] In one aspect, the present embodiment provides a display substrate, comprising: a display area and a frame area located around the display area, the frame area comprising: a first frame area and a second frame area which are in communication with each other, the first frame area comprising at least: a bending area located on one side of the display area along a first direction. The display substrate comprises: a substrate, a plurality of sub-pixels provided on one side of the substrate and located in the display area, a plurality of gate driving circuits located in the second frame area, at least one first peripheral control line and a plurality of second peripheral control lines located in the first frame area. The plurality of gate driving circuits are electrically connected to the plurality of sub-pixels and configured to provide a plurality of pixel control signals to the plurality of sub-pixels. The at least one first peripheral control line is connected to the plurality of gate driving circuits. Some of the plurality of second peripheral control lines are connected to the plurality of gate driving circuits; the potential of the signal transmitted by each first peripheral control line is lower than the potential of the signal transmitted by each second peripheral control line. In the bending area, at least one second peripheral control line of the plurality of second peripheral control lines is located between the at least one first peripheral control line and the boundary of the display substrate.

[0007] In some example embodiments, the display substrate further comprises: a plurality of peripheral data lines located in the first frame area, the plurality of peripheral data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; in a second direction, the plurality of second peripheral control lines and the at least one first peripheral control line are located between the plurality of peripheral data lines and the boundary of the display substrate; and the second direction intersects the first direction.

[0008] In some example embodiments, in the bending area, a minimum distance between the at least one first perimeter control line and the boundary of the display substrate is greater than or equal to 1250 microns.

[0009] In some example embodiments, the at least one first perimeter control line is configured to transmit a constant voltage signal, and a potential of the constant voltage signal is less than or equal to -6V.

[0010] In some example embodiments, at least one of the plurality of sub-pixels includes a pixel circuit and a light emitting element connected to the pixel circuit. The pixel circuit includes at least a driving transistor, a data writing transistor, and a compensation transistor. A gate of the data writing transistor is connected to a first scan line, a first electrode of the data writing transistor is connected to a data line, and a second electrode of the data writing transistor is connected to a first electrode of the driving transistor. A gate of the driving transistor is connected to a second electrode of the compensation transistor, a second electrode of the driving transistor is connected to a first electrode of the compensation transistor, and a gate of the compensation transistor is connected to a second scan line. The plurality of gate driving circuits includes at least one first scan driving circuit configured to provide a first scan signal to the first scan line and at least one second scan driving circuit configured to provide a second scan signal to the second scan line. The plurality of second perimeter control lines includes at least a second start signal line and a second scan driving output line connected to the at least one second scan driving circuit. The at least one first perimeter control line is located between the second start signal line and the second scan driving output line.

[0011] In some example embodiments, the pixel circuit further includes a first reset transistor. A gate of the first reset transistor is connected to a first reset control line, a first electrode of the first reset transistor is configured to receive a first initial signal, and a second electrode of the first reset transistor is connected to the second electrode of the driving transistor. In the bending area, a second perimeter control line of the plurality of second perimeter control lines closest to the boundary of the display substrate is configured to transmit the first initial signal.

[0012] In some example embodiments, in the bending area, a minimum distance between the second perimeter control line of the plurality of second perimeter control lines closest to the boundary of the display substrate and the boundary of the display substrate is greater than or equal to 400 microns.

[0013] In some example embodiments, the first bezel area further comprises a first signal access area located at a side of the bending area away from the display area; the display substrate further comprises a plurality of first contact pads located at the first signal access area and arranged along a second direction; the second direction intersects the first direction; the plurality of first contact pads comprises at least one first control contact pad connected with the at least one first perimeter control line and a plurality of second control contact pads connected with the plurality of second perimeter control lines. In the second direction, at least one second control contact pad of the plurality of second control contact pads is located between the at least one first control contact pad and a boundary of the display substrate.

[0014] In some example embodiments, the at least one first perimeter control line is located between a first second perimeter control line and a second second perimeter control line; in the second direction, the at least one first control contact pad is located between a second control contact pad connected with the first second perimeter control line and a second control contact pad connected with the second second perimeter control line.

[0015] In some example embodiments, the at least one first perimeter control line is located between a first second perimeter control line and a second second perimeter control line; the first second perimeter control line is located at a side of the at least one first perimeter control line close to a boundary of the display substrate. In the second direction, the at least one first control contact pad is located at a side of a second control contact pad connected with the second second perimeter control line away from the boundary of the display substrate.

[0016] In some example embodiments, the first bezel area further comprises a first sub-area located at a side of the bending area close to the display area, the first sub-area being in communication with the second bezel area. The display substrate further comprises a plurality of electrostatic discharge circuits located at the first sub-area, the plurality of electrostatic discharge circuits being arranged adjacent to the plurality of gate drive circuits. The plurality of electrostatic discharge circuits are arranged as a plurality of rows along the first direction, each row of electrostatic discharge circuits comprising a plurality of electrostatic discharge circuits arranged along a second direction; the second direction intersects the first direction. The at least one first perimeter signal line is located between two adjacent rows of electrostatic discharge circuits.

[0017] In some example embodiments, the plurality of electrostatic discharge circuits are arranged as a first row of electrostatic discharge circuits, a second row of electrostatic discharge circuits and a third row of electrostatic discharge circuits in a direction away from the display area; the at least one first perimeter signal line is located between the first row of electrostatic discharge circuits and the second row of electrostatic discharge circuits.

[0018] In some example embodiments, the display substrate includes a plurality of first perimeter control lines, and the plurality of electrostatic discharge circuits are connected to one of the first perimeter control lines.

[0019] In some example embodiments, the plurality of gate driving circuits includes a first group of gate driving circuits and a second group of gate driving circuits located on two sides of the display area along a second direction, the second direction being perpendicular to the first direction. The first group of gate driving circuits is connected to at least one first perimeter control line, and the second group of gate driving circuits is connected to at least one first perimeter control line. The first group of gate driving circuits includes the same number of gate driving circuits as the second group of gate driving circuits.

[0020] In another aspect, the embodiments provide a display device including the display substrate as described above.

[0021] Other aspects can become apparent from a review of the drawings and detailed description.

[0022] SUMMARY

[0023] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0024] FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0026] FIG. 3 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0027] FIG. 4A is a schematic diagram of a partial cross-section of a display area according to at least one embodiment of the present disclosure;

[0028] FIG. 4B is another schematic diagram of a partial cross-section of a display area according to at least one embodiment of the present disclosure;

[0029] FIG. 5 is a schematic diagram of partial traces of a first frame area according to at least one embodiment of the present disclosure;

[0030] FIG. 6 is a schematic diagram of a partial cross-section of a first frame area according to at least one embodiment of the present disclosure;

[0031] FIG. 7 is a schematic diagram of a partial enlargement of region S1 in FIG. 6 according to at least one embodiment of the present disclosure;

[0032] FIG. 8 is another schematic diagram of partial traces of a first frame area according to at least one embodiment of the present disclosure;

[0033] FIG. 9 is another partial routing diagram of a first bezel region according to an embodiment of the present disclosure;

[0034] FIG. 10 is another partial routing diagram of a first bezel region according to an embodiment of the present disclosure;

[0035] FIG. 11 is another partial diagram of a first bezel region according to an embodiment of the present disclosure;

[0036] FIG. 12 is an equivalent circuit diagram of an electrostatic discharge circuit according to an embodiment of the present disclosure;

[0037] FIG. 13 is a partial enlarged diagram of region S2 in FIG. 6;

[0038] FIG. 14 is a diagram of a first semiconductor layer, a first gate metal layer, and a second gate metal layer in FIG. 13;

[0039] FIG. 15 is a diagram of a display device according to an embodiment of the present disclosure.

[0040] DETAILED DESCRIPTION

[0041] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. The embodiments can be implemented in various forms. It is readily apparent to those skilled in the art that the embodiments and features thereof can be changed or replaced without departing from the gist of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the following embodiments. The embodiments of the present disclosure and the features thereof can be arbitrarily combined with each other without conflict.

[0042] In the drawings, the size, the thickness, or the region of one or a plurality of constituent elements, a layer, or the region is sometimes exaggerated for the purpose of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to such a size, and the shape, the size, and the like of one or a plurality of components in the drawings do not reflect the actual ratio. Furthermore, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shape or the numerical value shown in the drawings.

[0043] The ordinal numbers "first", "second", "third", and the like in the present specification are used to avoid confusion among constituent elements and are not used to limit the number in the order. "A plurality of" in the present disclosure indicates two or more.

[0044] In this specification, terms of "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation of the specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is changed as appropriate according to the direction of the components described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0045] In this specification, unless explicitly stated and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the meaning of the above terms in the present disclosure can be understood according to the situation. Among them, "connected" can include "electrically connected", "electrically connected" can include the case where the components are connected together through elements having certain electrical effects. "Elements having certain electrical effects" are not particularly limited as long as they can transmit electrical signals between the connected components. Examples of "elements having certain electrical effects" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements with multiple functions, and the like.

[0046] In this specification, a transistor refers to an element including at least a gate (gate electrode), a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region where current mainly flows.

[0047] In this specification, the first electrode can be a drain, and the second electrode can be a source, or the first electrode can be a source, and the second electrode can be a drain. In addition, the gate can also be referred to as a control electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source" and "drain" are sometimes exchanged with each other. Therefore, in this specification, "source" and "drain" can be exchanged with each other.

[0048] In the present specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0049] In the present specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly so, and can be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, etc. There can be some small deformations due to tolerances, such as a fillet, an arc edge, and a deformation, etc.

[0050] In the present specification, "about", "approximately", etc. refer to not strictly limited boundaries, and allow for a range of process and measurement errors. In the present disclosure, "the same" includes a case in which the values differ by 10% or less, such as a case in which the values differ by 5% or less.

[0051] In the present specification, A extending along a direction of B means that A can include a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends along the direction of B, and the length of the main portion extending along the direction of B is greater than the length of the secondary portion extending along other directions. In the present specification, "A extending along the direction of B" means "the main portion of A extending along the direction of B".

[0052] In the present specification, "A and B are in the same layer structure" means that A and B are formed at the same time by one patterning process. "The same layer" does not always mean that the thickness or height of the layer is the same in the cross-sectional view. "The orthographic projection of A contains the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.

[0053] With the development of display technology, flexible display products are getting more and more attention. The lower frame of the display substrate of the flexible display product will be bent and narrowed in the bending area, and the edge wire of the bending area of the lower frame has a reliability corrosion problem, which is easy to cause display problems of the display product.

[0054] The embodiment provides a display substrate, comprising a display area and a frame area located around the display area, the frame area comprising a first frame area and a second frame area which are in communication with each other, and the first frame area at least comprising a bending area located on one side of the display area along a first direction. The display substrate comprises a substrate, a plurality of sub-pixels, a plurality of gate driving circuits, at least one first peripheral control line and a plurality of second peripheral control lines. The plurality of sub-pixels are arranged on one side of the substrate and located in the display area. The plurality of gate driving circuits are located in the second frame area and electrically connected to the plurality of sub-pixels, and are configured to provide a plurality of pixel control signals to the plurality of sub-pixels. The at least one first peripheral control line is located in the first frame area and connected to the plurality of gate driving circuits. The plurality of second peripheral control lines are located in the first frame area, and a part of the plurality of second peripheral control lines are connected to the plurality of gate driving circuits. The potential of the signal transmitted by each first peripheral control line is lower than the potential of the signal transmitted by each second peripheral control line. In the bending area, at least one second peripheral control line of the plurality of second peripheral control lines is located between the at least one first peripheral control line and the boundary of the display substrate. In other words, the at least one second peripheral control line is located on the side of the at least one first peripheral control line close to the boundary of the display substrate. The at least one first peripheral control line is not the wire closest to the boundary of the display substrate.

[0055] The display substrate provided by the embodiment can increase the distance between the first peripheral control line and the boundary of the display substrate by arranging the first peripheral control line with a lower transmission potential on the side of the at least one second peripheral control line with a higher transmission potential away from the boundary of the display substrate, thereby facilitating avoiding the reliability corrosion of the first peripheral control line.

[0056] In some example embodiments, the display substrate can further comprise a plurality of peripheral data lines located in the first frame area, the plurality of peripheral data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. In a second direction, the plurality of second peripheral control lines and the at least one first peripheral control line are located between the plurality of peripheral data lines and the boundary of the display substrate. The second direction intersects the first direction, for example, the second direction can be perpendicular to the first direction. In some examples, the plurality of second peripheral control lines can be located on both sides of the plurality of peripheral data lines in the second direction, and the at least one first peripheral control line can be located on the side of the plurality of peripheral data lines close to the at least one second peripheral control line. The embodiment is not limited in this regard.

[0057] In some example embodiments, the at least one first perimeter control line can be configured to transmit a constant voltage signal, and the constant voltage signal can have a potential less than or equal to -6V. In some examples, the signal transmitted by the at least one first perimeter control line can have a potential less than or equal to -6V and greater than or equal to -12V. For example, the signal transmitted by the first perimeter control line can have a potential ranging from -7V to -8V. The first perimeter control line of the present example can be the wire transmitting the lowest potential in the first bezel area. The present example can prevent the first perimeter control line from being susceptible to corrosion by arranging the first perimeter control line transmitting the lowest potential away from the boundary of the display substrate.

[0058] In some example embodiments, the first bezel area can further include a first signal access area located on a side of the bending area away from the display area. The display substrate can further include a plurality of first contact pads located in the first signal access area and arranged along a second direction. The plurality of first contact pads can include at least one first control contact pad connected to the at least one first perimeter control line and a plurality of second control contact pads connected to the plurality of second perimeter control lines. In the second direction, at least one second control contact pad of the plurality of second control contact pads can be located between the at least one first control contact pad and the boundary of the display substrate. In other words, in the second direction, at least one second control contact pad can be located between at least one first control contact pad close to the boundary of the display substrate. In some examples, the at least one first perimeter control line can be located between a first second perimeter control line and a second second perimeter control line; in the second direction, the at least one first control contact pad can be located between a second control contact pad connected to the first second perimeter control line and a second control contact pad connected to the second second perimeter control line. In other examples, the at least one first perimeter control line can be located between a first second perimeter control line and a second second perimeter control line; the first second perimeter control line is located on a side of the at least one first perimeter control line close to the boundary of the display substrate; in the second direction, the at least one first control contact pad can be located on a side of a second control contact pad connected to the second second perimeter control line away from the boundary of the display substrate. The present example can ensure signal transmission of the first perimeter control line and reasonable arrangement in the first bezel area by arranging the first control contact pad connected to the first perimeter control line away from the boundary of the display substrate.

[0059] In some example embodiments, the first bezel area can further include a first sub-area located at a side of the bending area close to the display area, the first sub-area being in communication with the second bezel area. The display substrate can further include a plurality of electrostatic discharge circuits located at the first sub-area, the plurality of electrostatic discharge circuits being arranged adjacent to the plurality of gate driving circuits. The plurality of electrostatic discharge circuits can be arranged in a plurality of rows along a first direction, each row of electrostatic discharge circuits including a plurality of electrostatic discharge circuits arranged along a second direction. The at least one first peripheral signal line can be located between two adjacent rows of electrostatic discharge circuits. The present example can reduce the length of the first peripheral signal line by arranging the first peripheral signal line between two adjacent rows of electrostatic discharge circuits, which is conducive to reducing the signal loading of the first peripheral signal line.

[0060] The scheme of the present embodiments is illustrated below by way of some examples.

[0061] FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 1, the display substrate can include a display area AA and a bezel area BB located around the display area AA. The bezel area BB can include a first bezel area B1 located at one side of the display area AA and a second bezel area B2 located at the remaining sides of the display area AA. For example, the first bezel area B1 can be located at one side of the display area AA along a first direction D1. The first bezel area B1 and the second bezel area B2 can be in communication. For example, the first bezel area B1 can be a lower bezel area of the display substrate, and the second bezel area B2 can include a left bezel area B21, a right bezel area B22, and an upper bezel area B23 of the display substrate.

[0062] In some examples, as shown in FIG. 1, the display area AA can be a flat area including a plurality of sub-pixels PX constituting a pixel array. The plurality of sub-pixels PX can be configured to display dynamic pictures or static images. The display area AA can be referred to as an active area. In some examples, the display area AA can be rectangular, for example, a rounded rectangular. However, the present embodiments are not limited thereto. For example, the display area can be circular, elliptical, or other shapes. In some examples, the display substrate can be a flexible substrate, and thus the display substrate can be deformable, for example, rolled, bent, folded, or rolled up.

[0063] In some examples, the display region AA can include a display structure layer disposed on the substrate, or can include a display structure layer and a touch structure layer disposed on the substrate in sequence. For example, the display substrate can integrate the touch structure, forming a Touch on Thin Film Encapsulation (Touch on TFE) structure. The Touch on TFE structure mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection, generally adopts two layers of metal to form a driving (Tx) electrode and a sensing (Rx) electrode, and a driving chip (IC) realizes touch action by detecting mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection, generally adopts a single layer of metal to form a touch electrode, and an integrated circuit realizes touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0064] In some examples, the display structure layer can include a plurality of sub-pixels PX, a plurality of gate lines GL and a plurality of data lines DL. The plurality of gate lines GL can extend along the second direction D2 and be arranged along the first direction D1, and the plurality of data lines DL can extend along the first direction D1 and be arranged along the second direction D2. The first direction D1 and the second direction D2 can intersect, for example, the first direction D1 can be perpendicular to the second direction D2. The orthogonal projection of the plurality of gate lines GL and the plurality of data lines DL on the substrate can intersect to form a plurality of sub-pixel regions. One sub-pixel PX can be disposed in one sub-pixel region. The plurality of data lines DL can be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL can be configured to provide a data signal to the plurality of sub-pixels PX. The plurality of gate lines GL can be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL can be configured to provide a pixel control signal to the plurality of sub-pixels PX. For example, the pixel control signal can include a scan signal, or can include a scan signal and a light-emitting control signal, or can include a scan signal, a reset control signal and a light-emitting control signal.

[0065] In some examples, one pixel unit of the display area AA can include three sub-pixels, which can be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light), respectively. However, the present embodiments are not limited thereto. In some examples, one pixel unit can include four sub-pixels, which can be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light, respectively. For another example, one pixel unit can include four sub-pixels, which can include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0066] In some examples, one sub-pixel PX can include a pixel circuit and a light emitting element electrically connected to the pixel circuit. The pixel circuit can include a plurality of transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit can include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel circuit can be P-type transistors or can be N-type transistors, and the use of the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0067] In some examples, the shape of the light emitting element of the sub-pixel can be rectangular, rhombic, pentagonal, or hexagonal. When one pixel unit includes three sub-pixels, the light emitting elements of the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner; when one pixel unit includes four sub-pixels, the light emitting elements of the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square manner. However, the present embodiments are not limited thereto.

[0068] In some examples, the light emitting element can be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light emitting element can be an OLED, which can emit red light, green light, blue light, white light, etc. under the driving of the corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined as needed. In some examples, the light emitting element can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element can be electrically connected to the corresponding pixel circuit. However, the present embodiments are not limited thereto.

[0069] FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of the present example is described by way of example of an 8T1C structure. In some examples, as shown in FIG. 2, the pixel circuit of the present example can include eight pixel transistors (i.e., first pixel transistor T1 to eighth pixel transistor T8) and one storage capacitor Cst. The first pixel transistor T1 can also be referred to as a first reset transistor, the second pixel transistor T2 can also be referred to as a compensation transistor, the third pixel transistor T3 can also be referred to as a drive transistor, the fourth pixel transistor T4 can also be referred to as a data write transistor, the fifth pixel transistor T5 can also be referred to as a first light emitting control transistor, the sixth pixel transistor T6 can also be referred to as a second light emitting control transistor, the seventh pixel transistor T7 can also be referred to as a second reset transistor, and the eighth pixel transistor T8 can also be referred to as a third reset transistor. The light emitting element EL can include an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.

[0070] In some examples, the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8 can be a first type of transistor, for example, can be a P-type transistor, and the second pixel transistor T2 can be a second type of transistor, for example, can be an N-type transistor. However, the present embodiments are not limited thereto. For example, the plurality of pixel transistors of the pixel circuit can all be P-type transistors, or can all be N-type transistors.

[0071] In some examples, the first type of transistors of the pixel circuit (e.g., including the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8) can employ low temperature poly-silicon thin film transistors, and the second type of transistors of the pixel circuit (e.g., including the second pixel transistor T2) can employ oxide thin film transistors. The active layer of the low temperature poly-silicon thin film transistor employs low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor employs oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature poly-oxide (LTPS+Oxide) display substrate, which can take advantage of both and can achieve low frequency driving, reduce power consumption, and improve display quality.

[0072] In some examples, as shown in FIG. 2, the pixel circuit can be electrically connected with a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line can be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0073] In some examples, as shown in FIG. 2, the gate of the third pixel transistor T3 is electrically connected with the first node N1, the first electrode of the third pixel transistor T3 is electrically connected with the second node N2, and the second electrode of the third pixel transistor T3 is electrically connected with the third node N3. The gate of the fourth pixel transistor T4 is electrically connected with the first scan line GL1, the first electrode of the fourth pixel transistor T4 is electrically connected with the data line DL, and the second electrode of the fourth pixel transistor T4 is electrically connected with the second node N2. The gate of the second pixel transistor T2 is electrically connected with the second scan line GL2, the first electrode of the second pixel transistor T2 is electrically connected with the third node N3, and the second electrode of the second pixel transistor T2 is electrically connected with the first node N1. The gate of the fifth pixel transistor T5 is electrically connected with the light-emitting control line EML, the first electrode of the fifth pixel transistor T5 is electrically connected with the first power supply line PL1, and the second electrode of the fifth pixel transistor T5 is electrically connected with the second node N2. The gate of the sixth pixel transistor T6 is electrically connected with the light-emitting control line EML, the first electrode of the sixth pixel transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth pixel transistor T6 is electrically connected with the fourth node N4. The gate of the first pixel transistor T1 is electrically connected with the first reset control line RST1, the first electrode of the first pixel transistor T1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first pixel transistor T1 is electrically connected with the third node N3. The first pixel transistor T1 can be configured to reset the third node N3. The gate of the seventh pixel transistor T7 is electrically connected with the second reset control line RST2, the first electrode of the seventh pixel transistor T7 is electrically connected with the second initial signal line INIT2, and the second electrode of the seventh pixel transistor T7 is electrically connected with the fourth node N4. The seventh pixel transistor T7 can be configured to reset the fourth node N4. The gate of the eighth pixel transistor T8 is electrically connected with the second reset control line RST2, the first electrode of the eighth pixel transistor T8 is electrically connected with the third initial signal line INIT3, and the second electrode of the eighth pixel transistor T8 is electrically connected with the second node N2. The eighth pixel transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected with the first node N1, and the second electrode of the storage capacitor Cst is electrically connected with the first power supply line PL1.

[0074] In the present example, the first node N1 is a connection point of the storage capacitor Cst, the second pixel transistor T2, and the third pixel transistor T3, the second node N2 is a connection point of the fifth pixel transistor T5, the fourth pixel transistor T4, the eighth pixel transistor T8, and the third pixel transistor T3, the third node N3 is a connection point of the first pixel transistor T1, the third pixel transistor T3, the second pixel transistor T2, and the sixth pixel transistor T6, and the fourth node N4 is a connection point of the sixth pixel transistor T6, the seventh pixel transistor T7, and the light-emitting element EL.

[0075] The working process of the pixel circuit shown in FIG. 2 is described below. Among them, the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8 of the pixel circuit are P-type transistors, and the second pixel transistor T2 is an N-type transistor.

[0076] In some examples, the working process of the pixel circuit in a frame display period can at least include: a first stage, a second stage, a third stage and a fourth stage.

[0077] The first stage is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, so that the seventh pixel transistor T7 and the eighth pixel transistor T8 are turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, so that the second pixel transistor T2 is turned on. The eighth pixel transistor T8 is turned on, so that the third initial signal provided by the third initial signal line INIT3 is provided to the second node N2. The seventh pixel transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4, and the fourth node N4 is initialized. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, so that the fourth pixel transistor T4, the first pixel transistor T1, the fifth pixel transistor T5 and the sixth pixel transistor T6 are disconnected. The light emitting element EL does not emit light in this stage.

[0078] The second stage is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, and the first pixel transistor T1 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second pixel transistor T2 is turned on. The first pixel transistor T1 and the second pixel transistor T2 are turned on, so that the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, and the first node N1 is initialized. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, so that the seventh pixel transistor T7, the eighth pixel transistor T8, the fourth pixel transistor T4, the fifth pixel transistor T5 and the sixth pixel transistor T6 are disconnected. The light emitting element EL does not emit light in this stage.

[0079] In the third stage, referred to as a data writing stage or threshold compensation stage, the first scan signal SCAN1 provided by the first scan line GL1 is a low level signal, and the fourth pixel transistor T4 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high level signal, and the second pixel transistor T2 is turned on. In this stage, the first electrode of the storage capacitor Cst is at a low level, and the third pixel transistor T3 is turned on. The second pixel transistor T2, the fourth pixel transistor T4 and the third pixel transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third pixel transistor T3, the third node N3 and the turned-on second pixel transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third pixel transistor T3 is charged to the storage capacitor Cst, so that the voltage of the first electrode (i.e. the first node N1) of the storage capacitor Cst is Vdata-|Vth|, wherein Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third pixel transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high level signal, and the emission control signal EM provided by the emission control line EML is a high level signal, so that the first pixel transistor T1, the seventh pixel transistor T7, the eighth pixel transistor T8, the fifth pixel transistor T5 and the sixth pixel transistor T6 are turned off.

[0080] In the fourth stage, the emission control signal EM provided by the emission control line EML can be switched from a high level signal to a low level signal, so that the fifth pixel transistor T5 and the sixth pixel transistor T6 are turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a low level signal, so that the second pixel transistor T2 is turned off. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1 and the second reset control signal RESET2 provided by the second reset control line RST2 are high level signals, so that the fourth pixel transistor T4, the first pixel transistor T1, the seventh pixel transistor T7 and the eighth pixel transistor T8 are turned off. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light emitting element EL through the turned-on fifth pixel transistor T5, the third pixel transistor T3 and the sixth pixel transistor T6, so as to drive the light emitting element EL to emit light.

[0081] In the driving process of the pixel circuit, the driving current flowing through the third pixel transistor T3 is determined by the voltage difference between the gate and the first electrode thereof. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third pixel transistor T3 is: I=K×(Vgs-Vth) 2= K x [(VDD - Vdata + |Vth|) - Vth] 2 = K x [VDD - Vdata] 2 ;

[0082] wherein I is the driving current flowing through the third pixel transistor T3, that is, the driving current of the light emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third pixel transistor T3, Vth is the threshold voltage of the third pixel transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0083] It can be seen from the above formula that the current flowing through the light emitting element is irrelevant to the threshold voltage of the third pixel transistor T3. Therefore, the pixel circuit of the present embodiment can compensate for the threshold voltage of the third pixel transistor T3. Moreover, the pixel circuit provided by the present embodiment can improve the display effect of the light emitting element and improve the display effect of the light emitting element.

[0084] FIG. 3 is a schematic diagram of the arrangement of the gate driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 3, the second frame area B2 can be provided with a plurality of gate driving circuits. For example, the plurality of gate driving circuits can include a first group of gate driving circuits and a second group of gate driving circuits, the first group of gate driving circuits can be located in the left frame area B21 of the second frame area B2, and the second group of gate driving circuits can be located in the right frame area B22 of the second frame area B2. The number of gate driving circuits in the first group of gate driving circuits can be the same as the number of gate driving circuits in the second group of gate driving circuits. However, the present embodiment is not limited thereto.

[0085] In some examples, as shown in FIG. 3, the plurality of gate driving circuits can include two first scan driving circuits 21a and 21b, two second scan driving circuits 22a and 22b, two first reset driving circuits 23a and 23b, two second reset driving circuits 24a and 24b, and two light emitting driving circuits 25a and 25b. The first group of gate driving circuits can include the first scan driving circuit 21a, the second scan driving circuit 22a, the first reset driving circuit 23a, the second reset driving circuit 24a, and the light emitting driving circuit 25a; and the second group of gate driving circuits can include the first scan driving circuit 21b, the second scan driving circuit 22b, the first reset driving circuit 23b, the second reset driving circuit 24b, and the light emitting driving circuit 25b. For example, within the left bezel area B21 of the second bezel area B2, the first scan driving circuit 21a, the second scan driving circuit 22a, the first reset driving circuit 23a, the second reset driving circuit 24a, and the light emitting driving circuit 25a can be sequentially arranged along a direction away from the display area AA; and within the right bezel area B22 of the second bezel area B2, the first scan driving circuit 21b, the second scan driving circuit 22b, the first reset driving circuit 23b, the second reset driving circuit 24b, and the light emitting driving circuit 25b can be sequentially arranged along a direction away from the display area AA.

[0086] In some examples, the plurality of pixel control signals provided by the plurality of gate driving circuits to the plurality of sub-pixels of the display area can include a first scan signal, a second scan signal, a first reset control signal, a second reset control signal, and a light emitting control signal. The first scan driving circuits 21a and 21b can be configured to provide the first scan signal to the plurality of pixel circuits of the display area AA. The second scan driving circuits 22a and 22b can be configured to provide the second scan signal to the plurality of pixel circuits of the display area AA. The light emitting driving circuits 25a and 25b can be configured to provide the light emitting control signal to the plurality of pixel circuits of the display area AA. The first reset driving circuits 23a and 23b can be configured to provide the first reset control signal to the plurality of pixel circuits of the display area AA. The second reset driving circuits 24a and 24b can be configured to provide the second reset control signal to the plurality of pixel circuits of the display area AA. In this example, the first scan signal, the second scan signal, the light emitting control signal, the first reset control signal, and the second reset control signal can all adopt double-side driving. However, the present embodiment is not limited thereto. In other examples, at least one of the first scan signal, the second scan signal, the light emitting control signal, the first reset control signal, and the second reset control signal can adopt single-side driving.

[0087] In some examples, the display region AA includes M rows of pixel circuits, where M is a positive integer. The rows of pixel circuits within the display region AA can be sequentially labeled as the 1st row to the Mth row along a direction from the upper border region B23 to the first border region B1.

[0088] In some examples, the first scan driving circuits 21a and 21b can each include a plurality of cascaded first scan driving units (e.g., including GP(1) to GP(4)). Each first scan driving unit can be configured to provide a first scan signal to a row of pixel circuits of the display region AA. For example, the first first scan driving unit GP(1) can be configured to provide a first scan signal to the 1st row of pixel circuits of the display region AA.

[0089] In some examples, the second scan driving circuits 22a and 22b can each include a plurality of cascaded second scan driving units (e.g., including GN(1) to GN(4)). Each second scan driving unit can be configured to provide a second scan signal to a row of pixel circuits of the display region AA. For example, the first second scan driving unit GN(1) can be configured to provide a second scan signal to the 1st row of pixel circuits of the display region AA. However, the present embodiments are not limited thereto. In other examples, each second scan driving unit can be configured to provide a second scan signal to two adjacent rows of pixel circuits of the display region.

[0090] In some examples, the light emitting driving circuits 25a and 25b can each include a plurality of cascaded light emitting driving units (e.g., including EM(1) to EM(4)). Each light emitting driving unit can be configured to provide a light emitting control signal to a row of pixel circuits of the display region AA. For example, the first light emitting driving unit EM(1) can be configured to provide a light emitting control signal to the 1st row of pixel circuits of the display region AA. However, the present embodiments are not limited thereto. In other examples, each light emitting driving unit can be configured to provide a light emitting control signal to two adjacent rows of pixel circuits of the display region.

[0091] In some examples, the first reset driving circuits 23a and 23b can each include a plurality of cascaded first reset driving units (e.g., including RP(1) to RP(4)). Each first reset driving unit can be configured to provide a first reset control signal to a row of pixel circuits of the display region AA. For example, the first first reset driving unit RP(1) can be configured to provide a first reset control signal to the 1st row of pixel circuits of the display region AA. However, the present embodiments are not limited thereto. In other examples, each first reset driving unit can be configured to provide a first reset control signal to two adjacent rows of pixel circuits of the display region.

[0092] In some examples, the second reset driving circuits 24a and 24b can each include a plurality of cascaded second reset driving units (e.g., including RH(1) to RH(4)). Each second reset driving unit can be configured to provide a second reset control signal to a row of pixel circuits of the display area AA. For example, the first second reset driving unit RH(1) can be configured to provide a second reset control signal to the first row of pixel circuits of the display area AA. However, the present embodiments are not limited thereto. In other examples, each second reset driving unit can be configured to provide a second reset control signal to two adjacent rows of pixel circuits of the display area.

[0093] FIG. 4A is a schematic diagram of a partial cross-section of a display area according to at least one embodiment of the present disclosure. In FIG. 4A, the structure of one sub-pixel of the display area is taken as an example. In the present example, the pixel circuit of each sub-pixel includes a low-temperature polysilicon thin film transistor and an oxide thin film transistor, as shown in FIG. 2.

[0094] In some examples, as shown in FIG. 4A, in a direction perpendicular to the display substrate, the display area of the display substrate can include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 arranged in sequence on the substrate 10. The circuit structure layer 12 can include at least: a plurality of pixel circuits of sub-pixels, each pixel circuit of a sub-pixel can include a plurality of transistors and at least one capacitor. The light-emitting structure layer 13 can include at least: a plurality of light-emitting elements of sub-pixels. In other examples, the display substrate can further include a touch structure layer on a side of the encapsulation structure layer away from the substrate.

[0095] In some examples, as shown in FIG. 4A, each sub-pixel includes one first type transistor 21, one second type transistor 22, and one capacitor 23. The first type transistor 21 can be a low-temperature polysilicon thin film transistor, and the second type transistor 22 can be an oxide thin film transistor.

[0096] In some examples, the circuit structure layer 12 of the display area can include a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 10. A first insulating layer 101 can be disposed between the first semiconductor layer and the first gate metal layer, a second insulating layer 102 can be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 can be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 can be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 can be disposed between the third gate metal layer and the first source-drain metal layer; a sixth insulating layer 106 (may also be referred to as a passivation layer) and a seventh insulating layer 107 (may also be referred to as a first planarization layer) can be disposed between the first source-drain metal layer and the second source-drain metal layer, the seventh insulating layer 107 can be located on a side of the sixth insulating layer 106 away from the substrate 10; an eighth insulating layer 108 (may also be referred to as a second planarization layer) can be disposed on a side of the second source-drain metal layer away from the substrate 10. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 can be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, the present embodiment is not limited thereto. In other examples, a buffer layer can also be disposed on a side of the first semiconductor layer close to the substrate, the buffer layer can prevent harmful substances in the substrate from invading the inside of the display panel, and also can increase the adhesion of the film layers in the display panel on the substrate. In other examples, a bottom shielding metal layer (BSM) can also be disposed on a side of the buffer layer close to the substrate, the bottom shielding metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to avoid the influence of external light on the performance of the transistor. In other examples, the sixth insulating layer can be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the seventh insulating layer can be disposed between the first source-drain metal layer and the second source-drain metal layer.

[0097] In some examples, as shown in FIG. 4A, the first semiconductor layer of the display region can include at least: a first active layer 210 of the first type transistor 21. The first active layer 210 of the first type transistor 21 can include: a first region 2101, a second region 2102, and a channel region 2100 between the first region 2101 and the second region 2102. The first gate metal layer can include at least: a first gate 213 of the first type transistor 21, and a first plate 231 of the capacitor 23. The first gate 213 of the first type transistor 21 can cover the channel region 2100 of the first active layer 210 in the orthographic projection of the substrate 10. The second gate metal layer can include at least: a second plate 232 of the capacitor 23, and a third gate 224 of the second type transistor 22. The second plate 232 and the first plate 231 of the capacitor 23 can at least partially overlap in the orthographic projection of the substrate 10, for example, the two can coincide. The second semiconductor layer can include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer can include at least: a second gate 223 of the second type transistor 22. The second gate 223 of the second type transistor 22 can partially overlap with the second active layer 220 in the orthographic projection of the substrate 10. The third gate 224 of the second type transistor 22 can partially overlap with the second active layer 220 in the orthographic projection of the substrate 10. The third gate 224 can be a bottom gate of the second type transistor 22, and the second gate 223 can be a top gate of the second type transistor 22.

[0098] In some examples, as shown in FIG. 4A, the first source-drain metal layer of the display area can at least include: the first source 211 and the first drain 212 of the first type transistor 21, the second source 221 and the second drain 222 of the second type transistor 22. The fifth insulating layer 105 can be provided with a plurality of pixel vias (for example, including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the first pixel via can be removed to expose at least part of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the second pixel via can be removed to expose at least part of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104, and the third insulating layer 103 in the third pixel via and the fourth pixel via can be removed to expose at least part of the surface of both ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can at least include: the first transfer electrode 241. The first transfer electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 of the pixel circuit through the fifth pixel via provided by the sixth insulating layer 106 and the seventh insulating layer 107. The present example can realize electrical connection between the pixel circuit and the light emitting element through the first transfer electrode 241.

[0099] In some examples, the gate lines of the display area can be located in the first gate metal layer and the third gate metal layer, for example, and the data lines of the display area can be located in the second source-drain metal layer, for example, and the first power supply lines of the display area can be located in the second source-drain metal layer, for example. The present embodiment is not limited in this regard.

[0100] In some examples, as shown in FIG. 4A, the light-emitting structure layer 13 can include a pixel definition layer 134 and a plurality of light-emitting elements. For example, each light-emitting element can include a first electrode 131, an organic light-emitting layer 132, and a second electrode 133 stacked. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be electrically connected to the first transfer electrode 241 through a sixth pixel via hole of the eighth insulating layer 108 provided on the eighth insulating layer 108. The pixel definition layer 134 is provided on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 can be provided with a plurality of pixel openings, and each pixel opening can expose at least part of the surface of the corresponding first electrode 131. At least part of the organic light-emitting layer 132 can be provided in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be provided on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0101] In some examples, the organic light-emitting layer 132 of the light-emitting element can include an emitting layer (EML) and at least one of a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 can emit light according to the required gray scale by utilizing the light-emitting characteristics of the organic material.

[0102] In some examples, the light-emitting layers of the light-emitting elements of different colors can be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer located on one side of the light-emitting layer can adopt a common layer, and the electron injection layer and the electron transport layer located on the other side of the light-emitting layer can adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by one process (one evaporation process or one inkjet printing process), and isolation can be achieved by forming a film layer surface step difference or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be prepared by evaporation using a fine metal mask (FMM) or an open mask, or by using an inkjet process.

[0103] In some examples, as shown in FIG. 4A, the encapsulation structure layer 14 can include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. The first encapsulation layer 141 and the third encapsulation layer 143 can be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic materials have high compactness and can prevent the invasion of water, oxygen, etc. The second encapsulation layer 142 can be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external water vapor from entering the light-emitting element. The second encapsulation layer 142 can be made of organic materials, such as a high polymer material containing a desiccant or a high polymer material capable of blocking water vapor, etc., or a high polymer resin, etc. to perform a planarization process on the surface of the display panel, and can relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and can also include a water-absorbing material such as a desiccant to absorb water, oxygen, etc. invading the inside. However, the present embodiment is not limited thereto. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0104] FIG. 4B is another partial cross-sectional view of a display area according to at least one embodiment of the present disclosure. In some examples, the transistor types of the plurality of pixel transistors in the pixel circuit can be the same, for example, all can be low-temperature polysilicon thin film transistors. In FIG. 4B, a first type of transistor 21 and a capacitor 23 included in each sub-pixel are taken as an example for illustration.

[0105] In some examples, as shown in FIG. 4B, the circuit structure layer 12 of the display area can include a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 10. A first insulating layer 101 can be disposed between the first semiconductor layer and the first gate metal layer, a second insulating layer 102 can be disposed between the first gate metal layer and the second gate metal layer, a third insulating layer 103 can be disposed between the second gate metal layer and the first source-drain metal layer, a sixth insulating layer 106 and a seventh insulating layer 107 can be disposed between the first source-drain metal layer and the second source-drain metal layer, and an eighth insulating layer 108 can be disposed on a side of the second source-drain metal layer away from the substrate 10. The seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 can be inorganic insulating layers. The remaining structures of the display area of the display substrate of the present example can be referred to the description of the embodiment shown in FIG. 4A, which will not be repeated here.

[0106] FIG. 5 is a schematic diagram of partial traces of a first bezel area according to at least one embodiment of the present disclosure. FIG. 5 illustrates an example of a region of the first bezel area close to the boundary XL of the left side of the display substrate. In some examples, as shown in FIG. 1 and FIG. 5, the first bezel area B1 can include a first sub-area B01, a bending area B02, and a second sub-area B03 arranged in sequence along a side away from the display area AA in the first direction D1. The first sub-area B01 can also be referred to as a first fan-out area. The first sub-area B01 can be in communication with the left bezel area B21 and the right bezel area B22 of the second bezel area B2, and connected to the display area AA. The bending area B02 can be connected between the first sub-area B01 and the second sub-area B03. The second sub-area B03 can include at least a first signal access area B034 and a second signal access area B035. The first signal access area B034 can be located on a side of the second signal access area B035 away from the bending area B02.

[0107] In some examples, the bending area B02 can be configured to bend the second sub-area B03 to the back of the display area AA. A plurality of bending connection lines extending in the first direction D1 can be disposed in the bending area B02 to achieve electrical connection between the traces transmitting the same signal in the first sub-area B01 and the second sub-area B03. The plurality of bending connection lines in the bending area B02 can be in a same layer structure, for example, can be located in the second source-drain metal layer. However, the present embodiment is not limited thereto. In other examples, the plurality of bending connection lines of the bending area can be located in the first source-drain metal layer.

[0108] In some examples, the first signal access area B034 can be provided with a plurality of first contact pads, which can be configured to be bonded with an external flexible printed circuit board (FPC). The second signal access area B035 can be provided with a plurality of second contact pads, which can be configured to connect a driving integrated circuit (IC). At least one first contact pad in the first signal access area B034 and at least one second contact pad in the second signal access area B035 can be connected by a wire.

[0109] In some examples, as shown in FIG. 5, the first bezel area B1 can be provided with a plurality of perimeter control lines. Each perimeter control line can include a first wire segment located at the first sub-area B01, a control bending line located at the bending area B02, and a second wire segment located at the second sub-area B03; wherein the control bending line can connect the first wire segment and the second wire segment. The first wire segment can extend at least along the first direction D1 and extend along the edge shape of the display area AA to the second bezel area B2. The control bending line and the second wire segment can extend along the first direction D1. Three perimeter control lines are taken as an example for illustration in FIG. 5.

[0110] In some examples, the plurality of perimeter control lines of the first bezel area B1 can include a first perimeter control line L1 and a plurality of second perimeter control lines (e.g. including a first second perimeter control line L2 and a second second perimeter control line L3). The first perimeter control line L1 can be configured to transmit a constant voltage signal. The potential of the signal transmitted by the first perimeter control line L1 can be lower than the potential of the signal transmitted by each second perimeter control line. For example, the potential of the signal transmitted by the first perimeter control line L1 can be the lowest potential of the signals transmitted by the plurality of perimeter control lines. For example, the potential of the signal transmitted by the first perimeter control line L1 can be less than or equal to -6V. The first second perimeter control line L2 and the second second perimeter control line L3 can be perimeter control lines adjacent to the first perimeter control line L1.

[0111] In some examples, as shown in FIG. 5, the first peripheral control line L1 can include a first routing segment 41-1 located at the first sub-region B01, a control bending line 42-1 located at the bending region B02, and a second routing segment 43-1 located at the second sub-region B03. The control bending line 42-1 can connect the first routing segment 41-1 and the second routing segment 43-1. The control bending line 42-1 and the second routing segment 43-1 can extend along the first direction D1. The second routing segment 43-1 can be connected with a third routing segment 44-1 extending substantially along the second direction D2, and the third routing segment 44-1 can be connected with a fourth routing segment 45-1 extending substantially along the first direction D1. For example, the second routing segment 43-1 and the third routing segment 44-1 can be an integrated structure connected with each other, for example, can be located at the first gate metal layer or the second gate metal layer; the fourth routing segment 45-1 and the third routing segment 44-1 can be located at different conductive layers, for example, the fourth routing segment 45-1 can be located at the first source-drain metal layer. However, the present embodiment is not limited thereto. For example, the second routing segment 43-1 and the third routing segment 44-1 can be located at different conductive layers.

[0112] In some examples, as shown in FIG. 5, the first peripheral control line L1 can include a first routing segment 41-1 located at the first sub-region B01, a control bending line 42-1 located at the bending region B02, and a second routing segment 43-1 located at the second sub-region B03. The control bending line 42-1 can connect the first routing segment 41-1 and the second routing segment 43-1. The control bending line 42-1 and the second routing segment 43-1 can extend along the first direction D1. The second routing segment 43-1 can be connected with a third routing segment 44-1 extending substantially along the second direction D2, and the third routing segment 44-1 can be connected with a fourth routing segment 45-1 extending substantially along the first direction D1. For example, the second routing segment 43-1 and the third routing segment 44-1 can be an integrated structure connected with each other, for example, can be located at the first gate metal layer or the second gate metal layer; the fourth routing segment 45-1 and the third routing segment 44-1 can be located at different conductive layers, for example, the fourth routing segment 45-1 can be located at the first source-drain metal layer. However, the present embodiment is not limited thereto. For example, the second routing segment 43-1 and the third routing segment 44-1 can be located at different conductive layers.

[0113] In some examples, as shown in FIG. 5, the second perimeter control line L3 can include a first routing segment 41-3 located in the first sub-region B01, a control bending line 42-3 located in the bending region B02, and a second routing segment 43-3 located in the second sub-region B03. The control bending line 42-3 can connect the first routing segment 41-3 and the second routing segment 43-3. The control bending line 42-3 and the second routing segment 43-3 can extend along the first direction D1. The second routing segment 43-3 can be connected with a third routing segment 44-3 extending substantially along the second direction D2, and the third routing segment 44-3 can be connected with a fourth routing segment 45-3 extending substantially along the first direction D1. For example, the second routing segment 43-3 and the third routing segment 44-3 can be an integrated structure connected with each other, for example, can be located in the first gate metal layer or the second gate metal layer; the fourth routing segment 45-3 and the third routing segment 44-3 can be located in different conductive layers, for example, the fourth routing segment 45-3 can be located in the first source-drain metal layer. However, the present embodiment is not limited thereto. For example, the second routing segment 43-3 and the third routing segment 44-3 can be located in different conductive layers.

[0114] In some examples, the first routing segment 41-1 of the first perimeter control line L1, the first routing segment 41-2 of the first second perimeter control line L2, and the first routing segment 41-3 of the second second perimeter control line L3 can be a same-layer structure, for example, can be located in the first gate metal layer, or can be located in the second gate metal layer, or can be a double-layer routing structure located in the first gate metal layer and the second gate metal layer.

[0115] In some examples, the control bending line 42-1 of the first perimeter control line L1, the control bending line 42-2 of the first second perimeter control line L2, and the control bending line 42-3 of the second second perimeter control line L3 can be a same-layer structure, for example, can be located in the first source-drain metal layer or the second source-drain metal layer.

[0116] In some examples, the second routing segment 43-1 of the first perimeter control line L1, the second routing segment 43-2 of the first second perimeter control line L2, and the second routing segment 43-3 of the second second perimeter control line L3 can be a same-layer structure, for example, can be located in the first gate metal layer or the second gate metal layer.

[0117] In some examples, the third routing segments 44-1, 44-2, and 44-3 can be a same-layer structure, for example, can be located in the first gate metal layer or the second gate metal layer. The fourth routing segments 45-1, 45-2, and 45-3 can be a same-layer structure, for example, can be located in the first source-drain metal layer.

[0118] In some examples, the first peripheral control line L1 may be located between the first second peripheral control line L2 and the second second peripheral control line L3, and the first second peripheral control line L2 may be located on the side of the first peripheral control line L1 closer to the boundary XL of the display substrate. The second second peripheral control line L3 may be located on the side of the first peripheral control line L1 away from the boundary XL of the display substrate.

[0119] In some examples, the plurality of first contact pads in the first signal access area B034 may include a plurality of control contact pads (e.g., first control contact pad 511, second control contact pad 512, and 513) arranged along the second direction D2. The first control contact pad 511, second control contact pad 512, and 513 may be arranged sequentially along the second direction D2. The first control contact pad 511 may be located on the side of the second control contact pad 512 closest to the boundary XL of the display substrate. For example, the first control contact pad 511 may be the contact pad closest to the boundary XL of the display substrate among the plurality of first contact pads.

[0120] In some examples, the second segment 43-1 of the first peripheral control line L1 can be connected to the first control contact pad 511 via the third segment 44-1 and the fourth segment 45-1. The second segment 43-2 of the first second peripheral control line L2 can be connected to the second control contact pad 512 via the third segment 44-2 and the fourth segment 45-2. The third segment 44-2 can also extend to the second signal access area B035 and connect to the second contact pad within the second signal access area B035. The second segment 43-3 of the second second peripheral control line L3 can be connected to the second control contact pad 513 via the third segment 44-3 and the fourth segment 45-3. The third segment 44-3 can also extend to the second signal access area B035 and connect to the second contact pad within the second signal access area B035. However, this embodiment is not limited to this. In other examples, the second peripheral control line adjacent to the first peripheral control line can be connected only to the first contact pad within the first signal access area.

[0121] In some examples, taking multiple peripheral control lines made of aluminum (Al) as an example, when the potential of the signal output by the traces near the boundary of the display substrate is low, the ambient H + High concentration, metallic Al and H + The reaction produces Al 3+ Al 3+ With F - / S 2- The reaction produces compounds, which can easily lead to corrosion of edge traces. Furthermore, for traces transmitting signals at high potentials, the presence of OH groups in the environment... - High concentration, metallic Al and OH- AlO 2- , cannot generate compounds, can effectively avoid the case of wire corrosion. The present example can increase the distance between the first peripheral control line and the boundary of the display substrate by arranging the first peripheral control line with the lowest transmission potential on the side away from the boundary of the display substrate of at least one second peripheral control line with a higher transmission potential, thereby preventing the first peripheral control line from being corroded.

[0122] FIG. 6 is a partial schematic view of a first bezel area according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 6, the second sub-area B03 can include, in the first direction D1, a second fan-out area B031, a circuit arrangement area B032, a third fan-out area B033, a second signal access area B035, and a first signal access area B034 arranged in sequence away from the bending area B02. However, the present embodiment is not limited thereto. In other examples, the second sub-area of the first bezel area can include, in the first direction, a second fan-out area, a first signal access area, and a second signal access area arranged in sequence away from one side of the bending area.

[0123] In some examples, the circuit arrangement area B032 can be configured to at least arrange a plurality of test circuits in the second direction D2. In other examples, a plurality of anti-static circuits can be arranged on the side of the plurality of test circuits close to the bending area B02, and a plurality of data selection circuits can be arranged on the side of the plurality of test circuits away from the bending area B02. However, the present embodiment is not limited thereto.

[0124] In some examples, the plurality of bending connection lines of the bending area B02 can include a plurality of data bending lines (e.g., including a first group of data bending lines 312a, a second group of data bending lines 312b, a third group of data bending lines 312c, and a fourth group of data bending lines 312d), a plurality of first power bending lines (e.g., including a first group of first power bending lines 321a, a second group of first power bending lines 321b, a third group of first power bending lines 321c), a plurality of second power bending lines (e.g., including a first group of second power bending lines 331a, a second group of second power bending lines 331b, a third group of second power bending lines 331c, and a fourth group of second power bending lines 331d), a plurality of control bending lines (e.g., including a first group of control bending lines 42a and a second group of control bending lines 42b), a plurality of touch bending lines (e.g., including a first group of touch bending lines 341a and a second group of touch bending lines 341b). Among them, the plurality of data bending lines can be configured to transmit data signals. The plurality of first power bending lines can be configured to transmit a first voltage signal VDD, and the plurality of second power bending lines can be configured to transmit a second voltage signal VSS. Each group of bending connection lines in the bending area B02 is schematically shown as a whole in FIG. 6.

[0125] In some examples, the first group of control bend lines 42a, the first group of second power bend lines 331a, the first group of touch bend lines 341a, the second group of second power bend lines 331b, the first group of data bend lines 312a, the first group of first power bend lines 321a, the second group of data bend lines 312b, the second group of first power bend lines 321b, the third group of data bend lines 312c, the third group of first power bend lines 321c, the fourth group of data bend lines 312d, the third group of second power bend lines 331c, the second group of touch bend lines 341b, the fourth group of second power bend lines 331d, and the second group of control bend lines 42b can be arranged in the second direction D2 in sequence. However, the present embodiment is not limited thereto. In other examples, the bend area can omit the plurality of touch bend lines; or the bend area can be provided with one or five groups of first power bend lines.

[0126] In some examples, the first bezel area B1 can be provided with a plurality of peripheral data lines. The plurality of peripheral data lines can include a plurality of first data fan-out lines (e.g., including the first group of first data fan-out lines 311a and the second group of first data fan-out lines 311b) located in the first sub-area B01, a plurality of second data fan-out lines (e.g., including the first group of second data fan-out lines 313a and the second group of second data fan-out lines 313b) located in the second fan-out area B031, a plurality of data bend lines (e.g., including the first group of data bend lines 312a, the second group of data bend lines 312b, the third group of data bend lines 312c, and the fourth group of data bend lines 312d) located in the bend area B02, and a plurality of third data fan-out lines (e.g., including the first group of third data fan-out lines 314a and the second group of third data fan-out lines 314b) located in the third fan-out area B03. The plurality of data bend lines, the plurality of first data fan-out lines, the plurality of second data fan-out lines, and the plurality of third data fan-out lines are schematically shown as a whole in FIG. 6, and the present example is not limited to the number of data bend lines, first data fan-out lines, second data fan-out lines, and third data fan-out lines.

[0127] In some examples, the plurality of first data fan-out lines can be connected with the plurality of data lines of the display area AA, for example, in a one-to-one correspondence. The first group of first data fan-out lines 311a can be connected with the first group of second data fan-out lines 313a through the first group of data bending lines 312a and the second group of data bending lines 312b, and the second group of first data fan-out lines 311b can be connected with the second group of second data fan-out lines 313b through the third group of data bending lines 312c and the fourth group of data bending lines 312d. For example, the plurality of first data fan-out lines can be connected with the plurality of data bending lines in a one-to-one correspondence, and the plurality of data bending lines can be connected with the plurality of second data fan-out lines in a one-to-one correspondence. The first group of second data fan-out lines 313a can be connected with the first group of third data fan-out lines 314a, and the second group of second data fan-out lines 313b can be connected with the second group of third data fan-out lines 314b. For example, one third data fan-out line can be connected with a plurality of second data fan-out lines. This embodiment is not limited thereto.

[0128] In some examples, the plurality of second contact pads of the second signal access area B035 can include a plurality of data contact pads 315. The plurality of third data fan-out lines can be electrically connected with the plurality of data contact pads 315 in the second signal access area B035.

[0129] In some examples, the first frame area B1 can be provided with a plurality of perimeter control lines extending at least along the first direction D1. The plurality of perimeter control lines can include a first group of perimeter control lines and a second group of perimeter control lines, and the first group of perimeter control lines and the second group of perimeter control lines can be located on both sides of the plurality of perimeter data lines along the second direction D2. In other words, the plurality of perimeter data lines can be located in the middle of the plurality of perimeter control lines along the second direction D2. Each perimeter control line can include a first wire segment located in the first sub-area B01, a control bending line located in the bending area B02, and a second wire segment located in the second sub-area B03.

[0130] In some examples, the plurality of first wire segments of the first sub-area B01 can include a first group of first wire segments 41a and a second group of first wire segments 41b. In FIG. 6, several first wire segments of the first sub-area B01 are taken as examples for illustration. The number of first wire segments is not limited in this embodiment. The first group of first wire segments 41a and the second group of first wire segments 41b can be located on both sides of the plurality of first data fan-out lines along the second direction D2. The first group of first wire segments 41a can be located on one side of the first group of first data fan-out lines 311a close to the boundary of the display substrate along the second direction D2, and the second group of first wire segments 41b can be located on one side of the second group of first data fan-out lines 311b close to the boundary of the display substrate along the second direction D2.

[0131] In some examples, the plurality of second trace segments of the second sub-region B03 can include a first group of second trace segments 43a and a second group of second trace segments 43b. FIG. 6 schematically illustrates a plurality of second trace segments of the second sub-region B03. The present embodiment is not limited to the number of second trace segments. The first group of second trace segments 43a and the second group of second trace segments 43b can be located on both sides of the plurality of second data fan-out lines and the plurality of third data fan-out lines in the second direction D2. The first group of second trace segments 43a can be located on a side of the first group of second data fan-out lines 313a and the first group of third data fan-out lines 314a close to the boundary of the display substrate in the second direction D2, and the second group of second trace segments 43b can be located on a side of the second group of second data fan-out lines 313b and the second group of third data fan-out lines 314b close to the boundary of the display substrate in the second direction D2.

[0132] In some examples, the first group of first trace segments 41a in the first sub-region B01 can be connected to the first group of second trace segments 43a in the second sub-region B03 through the first group of control bending lines 42a in the bending region B02; and the second group of first trace segments 41b in the first sub-region B01 can be connected to the second group of second trace segments 43b in the second sub-region B03 through the second group of control bending lines 42b in the bending region B02.

[0133] In some examples, the second sub-region B03 can further be provided with a plurality of third trace segments (e.g., including a first group of third trace segments 44a and a second group of third trace segments 44b) and a plurality of fourth trace segments (e.g., including a first group of fourth trace segments 45a and a second group of fourth trace segments 45b). The second trace segments of a portion of the plurality of perimeter control lines can be connected to the first contact pads in the second signal access region B035 through the third trace segments extending in the second direction D2, and can be connected to the first contact pads in the first signal access region B034 through the third trace segments extending in the second direction D2 and the fourth trace segments extending in the first direction D1. The second trace segments of another portion of the plurality of perimeter control lines can not be connected to the second contact pads in the second signal access region B035, but can be connected to the first contact pads in the first signal access region B034 through the third trace segments extending in the second direction D2 and the fourth trace segments extending in the first direction D1. For example, at least one of the perimeter control lines in the other portion can be further connected to the test circuit located in the circuit arrangement region through the third trace segments extending in the second direction D2.

[0134] In some examples, the arrangement of the plurality of gate driving circuits in the second bezel area B2 can be as shown in FIG. 3. The number and arrangement of the first group of gate driving circuits in the left bezel area B21 and the second group of gate driving circuits in the right bezel area B22 can be the same. Some of the first group of peripheral control lines can be connected to the first group of gate driving circuits, and some of the second group of peripheral control lines can be connected to the second group of gate driving circuits. The number and type of the first group of peripheral control lines and the second group of peripheral control lines on both sides of the plurality of peripheral data lines can be the same. For example, the first group of peripheral control lines and the second group of peripheral control lines can be arranged approximately symmetrically about the middle line of the first bezel area B1 parallel to the first direction D1. However, the present embodiment is not limited thereto. In other examples, when the number or type of gate driving circuits in the first group of gate driving circuits and the second group of gate driving circuits are different, the number or type of the first group of peripheral control lines and the second group of peripheral control lines can be different.

[0135] FIG. 7 is a partial enlarged view of the area S1 in FIG. 6. FIG. 7 illustrates the first group of peripheral control lines. The description of the second group of peripheral control lines can refer to the description of the first group of peripheral control lines, and thus is not repeated here.

[0136] In some examples, as shown in FIG. 7, the first group of peripheral control lines can include a first initial control line VI1, a second initial control line VI2, a third initial control line VI3, a fifth voltage control line VGH-N, a fourth voltage control line VGH, a light-emitting driving output line Eout, a fifth start signal line ESTV, a thirteenth clock signal line ECB, a twelfth clock signal line ECK, a fourteenth clock signal line ECX, a tenth clock signal line HCB, a ninth clock signal line HCK, a fourth start signal line HSTV, a second reset driving output line Hout, a first reset driving output line Pout, a third start signal line PSTV, a seventh clock signal line PCB, a sixth clock signal line PCK, an eighth clock signal line PCX, a fourth clock signal line NCB, a third clock signal line NCK, a second start signal line NSTV, a first voltage control line VGL1, a second voltage control line VGL2, a third voltage control line VGL3, a second scan driving output line Nout, a second clock signal line GCB, a first clock signal line GCK, a first start signal line GSTV, an eleventh clock signal line HCX, a fifth clock signal line NCX, a first scan driving output line Gout, a first panel detection line PCD1, and a second panel detection line PCD2.

[0137] In some examples, in the first sub-region, the first initial control line VI1, the second initial control line VI2, the third initial control line VI3, the fifth voltage control line VGH-N, the fourth voltage control line VGH, the fifth start signal line ESTV, the thirteenth clock signal line ECB, the twelfth clock signal line ECK, the fourteenth clock signal line ECX, the tenth clock signal line HCB, the ninth clock signal line HCK, the fourth start signal line HSTV, the third start signal line PSTV, the seventh clock signal line PCB, the sixth clock signal line PCK, the eighth clock signal line PCX, the fourth clock signal line NCB, the third clock signal line NCK, the second start signal line NSTV, the first voltage control line VGL1, the second voltage control line VGL2, the third voltage control line VGL3, the second clock signal line GCB, the first clock signal line GCK, the first start signal line GSTV, the eleventh clock signal line HCX, and the fifth clock signal line NCX can all adopt a double-layer routing design located in the first gate metal layer and the second gate metal layer. The light-emitting drive output line Eout, the second reset drive output line Hout, the first reset drive output line Pout, the second scan drive output line Nout, the first scan drive output line Gout, the first panel detection line PCD1, and the second panel detection line PCD2 can be single-layer routing located in the first gate metal layer.

[0138] In some examples, the first start signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, and the first scan drive output line Gout can be electrically connected with the first scan drive circuit 21a located in the left frame region B21. The first start signal line GSTV can be configured to provide a start signal to the first scan drive circuit 21a, the first clock signal line GCK and the second clock signal line GCB can be configured to provide a clock signal to the first scan drive circuit 21a, and the first scan drive output line Gout can be configured to be connected with the output end of the last-stage first scan drive unit of the first scan drive circuit 21a.

[0139] In some examples, the second start signal line NSTV, the third clock signal line NCK, the fourth clock signal line NCB, the fifth clock signal line NCX, and the second scan drive output line Nout can be electrically connected with the second scan drive circuit 22a located in the left frame region B21. The second start signal line NSTV can be configured to provide a start signal to the second scan drive circuit 22a, the third clock signal line NCK, the fourth clock signal line NCB, and the fifth clock signal line NCK can be configured to provide a clock signal to the second scan drive circuit 22a, and the second scan drive output line Nout can be configured to be connected with the output end of the last-stage second scan drive unit of the second scan drive circuit 22a.

[0140] In some examples, the third start signal line PSTV, the sixth clock signal line PCK, the seventh clock signal line PCB, the eighth clock signal line PCX and the first reset driving output line Pout can be electrically connected with the first reset driving circuit 23a in the left frame area B21. The third start signal line PSTV can be configured to provide a start signal for the first reset driving circuit 23a, the sixth clock signal line PCK, the seventh clock signal line PCB and the eighth clock signal line PCX can be configured to provide a clock signal for the first reset driving circuit 23a, and the first reset driving output line Pout can be configured to be connected with an output terminal of a last-stage first reset driving unit of the first reset driving circuit 23a.

[0141] In some examples, the fourth start signal line HSTV, the ninth clock signal HCK, the tenth clock signal HCB, the eleventh clock signal HCX and the second reset driving output line Hout can be electrically connected with the second reset driving circuit 24a in the left frame area B21. The fourth start signal line HSTV can be configured to provide a start signal for the second reset driving circuit 24a, the ninth clock signal HCK, the tenth clock signal HCB and the eleventh clock signal HCX can be configured to provide a clock signal for the second reset driving circuit 24a, and the second reset driving output line Hout can be configured to be connected with an output terminal of a last-stage second reset driving unit of the second reset driving circuit 24a.

[0142] In some examples, the fifth start signal line ESTV, the twelfth clock signal ECK, the thirteenth clock signal ECB, the fourteenth clock signal ECX and the light emitting driving output line Eout can be electrically connected with the light emitting driving circuit 25a in the left frame area B21. The fifth start signal line ESTV can be configured to provide a start signal for the light emitting driving circuit 25a, the twelfth clock signal ECK, the thirteenth clock signal ECB and the fourteenth clock signal ECX can be configured to provide a clock signal for the light emitting driving circuit 25a, and the light emitting driving output line Eout can be configured to be connected with an output terminal of a last-stage light emitting driving unit of the light emitting driving circuit 25a.

[0143] In some examples, the fifth voltage control line VGH-N can be electrically connected with the second scan driving circuit 22a in the left frame area B21, and configured to provide a seventh voltage signal for the second scan driving circuit 22a. The fourth voltage control line VGH can be electrically connected with the first scan driving circuit 21a, the first reset driving circuit 23a, the second reset driving circuit 24a and the light emitting driving circuit 25a in the left frame area B21, and configured to provide a sixth voltage signal. The fifth voltage signal and the sixth voltage signal can be constant voltage signals, and the sixth voltage signal can be different from the fifth voltage signal.

[0144] In some examples, the first voltage control line VGL1 can be electrically connected with the first scan driving circuit 21a, the first reset driving circuit 23a, the second reset driving circuit 24a and the light emitting driving circuit 25a in the left border area B21, and configured to provide a third voltage signal. The second voltage control line VGL2 can be electrically connected with the second scan driving circuit 22a in the left border area B21, and configured to provide a fourth voltage signal. The third voltage control line VGL3 can be electrically connected with the second scan driving circuit 22a in the left border area B21, and configured to provide a fifth voltage signal.

[0145] In some examples, the third voltage signal, the fourth voltage signal and the fifth voltage signal can be constant voltage signals, and the potentials of the third voltage signal, the fourth voltage signal and the fifth voltage signal can all be less than or equal to -6V. The third voltage signal provided by the first voltage control line VGL1 can be substantially the same as the fifth voltage signal provided by the third voltage control line VGL3, and the fourth voltage signal provided by the second voltage control line VGL2 can be different from the fifth voltage signal provided by the third voltage control line VGL3. For example, the potential of the fourth voltage signal can be less than or equal to the potential of the fifth voltage signal. In some examples, the potential range of the third voltage signal and the fifth voltage signal can both be -6V to -10V, and the potential range of the fourth voltage signal can be -6V to -12V. The present example can be beneficial to guarantee the performance of the second scan driving circuit by providing two low-potential constant voltage signals to the second scan driving circuit.

[0146] In some examples, the first initial control line VI1 can be configured to provide a first initial signal, the second initial control line VI2 can be configured to provide a second initial signal, and the third initial control line VI3 can be configured to provide a third initial signal. The first initial control line VI1 can be connected with a first initial signal line of the display area, and configured to provide the first initial signal to the first reset transistor of the pixel circuit. The second initial control line VI2 can be connected with a second initial signal line of the display area, and configured to provide the second initial signal to the second reset transistor of the pixel circuit. The third initial control line VI3 can be connected with a third initial signal line of the display area, and configured to provide the third initial signal to the third reset transistor of the pixel circuit.

[0147] In some examples, the first panel detection line PCD1 and the second panel detection line PCD2 can be configured to transmit a signal for detecting whether a crack exists in the periphery of the display substrate.

[0148] In some examples, the first initial control line VI1, the second initial control line VI2, the third initial control line VI3, the first panel detection line PCD1 and the second panel detection line PCD2 in the first group of peripheral control lines have no direct electrical connection with the plurality of gate driving circuits, and the rest of the wirings have electrical connection with the plurality of gate driving circuits.

[0149] In some examples, as shown in FIG. 7, the first initial control line VI1, the second initial control line VI2, the third initial control line VI3, the fifth voltage control line VGH-N, the fourth voltage control line VGH, the light-emitting driving output line Eout, the fifth start signal line ESTV, the thirteenth clock signal line ECB, the twelfth clock signal line ECK, the fourteenth clock signal line ECX, the tenth clock signal line HCB, the ninth clock signal line HCK, the fourth start signal line HSTV, the second reset driving output line Hout, the first reset driving output line Pout, the third start signal line PSTV, the seventh clock signal line PCB, the sixth clock signal line PCK, the eighth clock signal line PCX, the fourth clock signal line NCB, the third clock signal line NCK, the second start signal line NSTV, the first voltage control line VGL1, the second voltage control line VGL2, the third voltage control line VGL3, the second scan driving output line Nout, the second clock signal line GCB, the first clock signal line GCK, the first start signal line GSTV, the eleventh clock signal line HCK, the fifth clock signal line NCK, the first scan driving output line Gout, the first panel detection line PCD1 and the second panel detection line PCD2 can be arranged in sequence along a direction away from the boundary of the display substrate.

[0150] In the present example, the plurality of first peripheral control lines can include a first voltage control line VGL1, a second voltage control line VGL2, and a third voltage control line VGL3, and the rest of the peripheral control lines are the second peripheral control lines as described in the foregoing embodiments. In the present example, the first second peripheral control line can be the second start signal line NSTV, and the second second peripheral control line can be the second scan driving output line Nout. The three first peripheral control lines can be located between the second start signal line NSTV and the second scan driving output line Nout. The signals transmitted by the second start signal line NSTV and the second scan driving output line Nout are relatively stable, and have less influence on the signals transmitted by the three first peripheral control lines. However, the present embodiment is not limited thereto. In other examples, the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 can be located between the rest of the second peripheral control lines, for example, can be located between the first scan driving output line Gout and the first panel detection line PCD1, or can be located between the first reset driving output line Pout and the second reset driving output line Hout. In other examples, the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 can be located on the side of the plurality of second peripheral control lines close to the peripheral data line, for example, can be located on the side of the second panel detection line PCD2 away from the first panel detection line PCD1.

[0151] In some examples, the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 are sequentially arranged in a direction away from the boundary of the display substrate. The minimum distance between the plurality of first peripheral control lines of the present example and the boundary of the display substrate can be the minimum distance between the first voltage control line VGL1 and the boundary of the display substrate. The minimum distance W2 between the first voltage control line VGL1 and the boundary of the display substrate can be the distance between the edge of the first voltage control line VGL1 close to the boundary of the display substrate and the boundary of the display substrate. W2 can be greater than or equal to 1250 microns, for example, can be about 2067 microns.

[0152] In some examples, the wire closest to the boundary of the display substrate in the first group of peripheral control lines is the first initial control line VI1, and the minimum distance W1 between the first initial control line VI1 and the boundary of the display substrate can be the distance between the edge of the first initial control line VI1 close to the boundary of the display substrate and the boundary of the display substrate. W1 can be greater than or equal to 400 microns, for example, can be about 535 microns.

[0153] In some examples, the first initial control line VI1 transmits a signal with a potential higher than the potentials of signals transmitted by the first voltage control line VGL1, the second voltage control line VGL2 and the third voltage control line VGL3, for example, the potential of the signal transmitted by the first initial control line VI1 can range from -3V to -4V.

[0154] The present example can prevent the first peripheral control line from being subject to reliability corrosion by arranging the plurality of first peripheral control lines (including the first voltage control line VGL1, the second voltage control line VGL2 and the third voltage control line VGL3) away from the boundary of the display substrate, which is conducive to avoiding display problems such as black screen and yellow screen of the display substrate.

[0155] In other examples, at least two of the first voltage control line VGL1, the second voltage control line VGL2 and the third voltage control line VGL3 can be arranged between different second peripheral wires. For example, the second voltage control line VGL2 and the third voltage control line VGL3 can be arranged between the second starting signal line NSTV and the second scan driving output line Nout, and the first voltage control line VGL1 can be arranged between the first reset driving output line Pout and the second reset driving output line Hout. The present embodiment is not limited in this regard. As long as the first voltage control line VGL1, the second voltage control line VGL2 and the third voltage control line VGL3 are not arranged at the position closest to the boundary of the display substrate.

[0156] FIG. 8 is another partial wire layout diagram of the first bezel area according to at least one embodiment of the present disclosure. FIG. 8 illustrates an example in which the first bezel area is close to the boundary XL of the left side of the display substrate. In some examples, as shown in FIG. 8, the first peripheral control line L1 is connected to the first control contact pad 511, the first second peripheral control line L2 is connected to the second control contact pad 512, and the second second peripheral control line L3 is connected to the second control contact pad 513. In the first signal access area B034, the first control contact pad 511 can be arranged between the second control contact pads 512 and 513.

[0157] The present example can facilitate the arrangement of the first peripheral control line and the second peripheral control line by arranging the first control contact pad connected to the first peripheral control line between the second control contact pads connected to the adjacent second peripheral control lines. The remaining description of the present example can be referred to the description of the embodiment shown in FIG. 5, and thus will not be repeated here.

[0158] FIG. 9 is another partial routing diagram of the first bezel area according to at least one embodiment of the present disclosure. FIG. 9 illustrates an example in which the first bezel area is close to the boundary XL of the left side of the display substrate. In some examples, as shown in FIG. 9, the first peripheral control line L1 is connected to the first control contact pad 511, the first second peripheral control line L2 is connected to the second control contact pad 512, and the second second peripheral control line L3 is connected to the second control contact pad 513. In the first signal access area B034, the first control contact pad 511 can be located on the side of the second control contact pad 513 away from the boundary of the display substrate.

[0159] The present example can facilitate signal transmission of the first peripheral control line by arranging the first control contact pad connected to the first peripheral control line on the side of the second control contact pad connected to the adjacent second peripheral control line away from the boundary of the display substrate, thereby avoiding interference of the signal transmitted by the adjacent second peripheral control line with the signal transmitted by the first peripheral control line. The remaining description of the present example can refer to the description of the embodiment shown in FIG. 5, and thus will not be repeated here.

[0160] In other examples, the first control contact pad connected to the first peripheral control line in the first group of peripheral control lines can be located on the side of all the second control contact pads connected to the remaining second peripheral control lines away from the boundary of the display substrate. In other words, the first control contact pad can not be inserted into the plurality of second control contact pads, but can be located on the side of the plurality of second control contact pads connected to the first group of peripheral control lines away from the boundary of the display substrate.

[0161] FIG. 10 is another partial routing diagram of the first bezel area according to at least one embodiment of the present disclosure. FIG. 10 illustrates an example in which the first bezel area is close to the boundary XL of the left side of the display substrate. In some examples, as shown in FIG. 10, the third routing segment 44-3 connected to the first peripheral control line L1 can be located on the side of the third routing segment 44-3 connected to the second second peripheral control line L3 close to the bending area B02. The third routing segments 44-1, 44-3, and 44-2 can be arranged in a direction away from the bending area B02. The present example can facilitate connection of the first peripheral control line to the first control contact pad by adjusting the routing arrangement in the second sub-area, thereby avoiding interference of the signal transmitted by the second peripheral control line with the signal transmitted by the first peripheral control line. The remaining description of the present example can refer to the description of the embodiment shown in FIG. 9, and thus will not be repeated here.

[0162] FIG. 11 is another partial schematic view of the first bezel region according to at least one embodiment of the present disclosure. In some examples, the first sub-region B01 can be provided with a plurality of electrostatic discharge circuits. The plurality of electrostatic discharge circuits can be adjacent to the plurality of gate driving circuits in the second bezel region B2. For example, the first sub-region B01 can include a first corner region in communication with the left bezel region B21 and a second corner region in communication with the right bezel region B22. The plurality of electrostatic discharge circuits can be located in the first corner region and the second corner region. FIG. 11 illustrates an example of the arrangement of the plurality of electrostatic discharge circuits in the first corner region.

[0163] In some examples, as shown in FIG. 11, the plurality of electrostatic discharge circuits in the first sub-region B01 can be arranged in a plurality of rows along the first direction D1, and each row of electrostatic discharge circuits can include a plurality of electrostatic discharge circuits arranged along the second direction D2. For example, the plurality of electrostatic discharge circuits can be arranged in a first row of electrostatic discharge circuits 61a, a second row of electrostatic discharge circuits 61b, and a third row of electrostatic discharge circuits 61c. The first row of electrostatic discharge circuits 61a, the second row of electrostatic discharge circuits 61b, and the third row of electrostatic discharge circuits 61c can be sequentially arranged along a direction away from the display region.

[0164] In some examples, a first wire segment 41-1 of the first peripheral control line L1 located in the first sub-region B01 can be connected to the plurality of electrostatic discharge circuits. The first wire segment 41-1 of the first peripheral control line L1 can extend from the arc-shaped edge of the display region to the left bezel region B21 of the second bezel region. The first wire segment 41-1 of the first peripheral control line L1 can be located between the first row of electrostatic discharge circuits 61a and the second row of electrostatic discharge circuits 61b. Compared to the first peripheral control line bypassing from the same side of the plurality of rows of electrostatic discharge circuits, the wire arrangement of the first peripheral control line in the present example can be adapted to the position of the first peripheral control line away from the boundary of the display substrate, which can reduce the length of the first peripheral control line, thereby facilitating the reduction of the load.

[0165] Figure 12 is an equivalent circuit diagram of an electrostatic discharge circuit according to an embodiment of the present disclosure. In some examples, the electrostatic discharge circuit can be connected to a peripheral control line CL and configured to discharge electrostatic in the peripheral control line CL to which it is connected. The electrostatic discharge circuit can include a first discharge transistor ST1 to a fourth discharge transistor ST4. The first electrode of the first discharge transistor ST1 can be electrically connected to a third voltage control line VGL1, the gate electrode and the second electrode of the first discharge transistor ST1 can be electrically connected to the first electrode of the second discharge transistor ST2, the gate electrode and the second electrode of the second discharge transistor ST2 can be electrically connected to the peripheral control line CL corresponding to the first electrostatic discharge circuit, the first electrode of the third discharge transistor ST3 can be electrically connected to the peripheral control line CL corresponding to the first electrostatic discharge circuit, the gate electrode and the second electrode of the third discharge transistor ST3 can be electrically connected to the first electrode of the fourth discharge transistor ST4, and the gate electrode and the second electrode of the fourth discharge transistor ST4 can be electrically connected to a fourth voltage line VGH.

[0166] In an example, the electrostatic discharge circuit can prevent electrostatic accumulation in the peripheral control line from causing discharge breakdown and damage, discharge the electrostatic accumulated in the peripheral control line, and protect the peripheral control line.

[0167] In another example, the electrostatic discharge circuit can include two discharge transistors, each of which has one electrode connected to its own gate electrode, forming an equivalent diode connection. The signal line to be protected is connected between the two "diodes", and the other two ends of the two "diodes" are connected to the fourth voltage control line VGH and the first voltage control line VGL1, respectively. Thus, when a transient high voltage (e.g., 100V) occurs in the signal line due to the accumulation of positive charges, one of the "diodes" is turned on to discharge the positive charges in the signal line; when a transient low voltage (e.g., -100V) occurs in the signal line due to the accumulation of negative charges, the other "diode" is turned on to discharge the negative charges in the signal line.

[0168] Figure 13 is a partial enlarged view of the region S2 in Figure 6. Figure 14 is a schematic view of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in Figure 13. Figures 13 and 14 illustrate the arrangement of a plurality of electrostatic discharge circuits in the first corner region of the first sub-region.

[0169] In some examples, as shown in FIGS. 13 and 14, the plurality of electrostatic discharge circuits in the first sub-region includes a first row of electrostatic discharge circuits 61a, a second row of electrostatic discharge circuits 61b, and a third row of electrostatic discharge circuits 61c. The active layers of the discharge transistors of the plurality of electrostatic discharge circuits in the same row can be an integrated structure connected to each other. For example, the integrated structure can be a strip structure extending along the second direction D2. The active layers of the plurality of discharge transistors can be located in the first semiconductor layer. The arrangement order of the four discharge transistors of adjacent electrostatic discharge circuits in the same row can be reversed, for example, the first to fourth discharge transistors of the first electrostatic discharge circuit in the first row of electrostatic discharge circuits 61a are arranged along the second direction D2, and the fourth to first discharge transistors of the second electrostatic discharge circuit can be arranged along the second direction D2.

[0170] In some examples, as shown in FIGS. 13 and 14, the third voltage control line VGL3, the second voltage control line VGL2, and the first voltage control line VGL1 can be located between the first row of electrostatic discharge circuits 61a and the second row of electrostatic discharge circuits 61b, and can be arranged in the first direction D1 in the direction away from the first row of electrostatic discharge circuits 61a.

[0171] In some examples, the first row of electrostatic discharge circuits 61a, the second row of electrostatic discharge circuits 61b, and the third row of electrostatic discharge circuits 61c can be connected to the first voltage control line VGL1 through the first connection line 621, the second connection line 622, the third connection line 623, and the fourth connection line 624. The first connection line 621, the second connection line 622, the third connection line 623, and the fourth connection line 624 can extend along the first direction D1 and be arranged along the second direction D2. The fourth voltage control line VGH can be located on the side of the third row of electrostatic discharge circuits 61c away from the second row of electrostatic discharge circuits 61b, and can be electrically connected to the three rows of electrostatic discharge circuits through four connection lines extending along the first direction D1.

[0172] In some examples, the first row of electrostatic discharge circuits 61a can include six electrostatic discharge circuits, and the six electrostatic discharge circuits arranged along the second direction D2 can be sequentially connected to the second start signal line NSTV, the third clock signal line NCK, the second clock signal line GCB, the first clock signal line GCK, the first start signal line GSTV, and the eleventh clock signal line HCX, to play a role in electrostatic protection.

[0173] In some examples, the second row of static electricity release circuits 61b can include six static electricity release circuits, and the six static electricity release circuits of the second row of static electricity release circuits 61b can be arranged in alignment with the six static electricity release circuits of the first row of static electricity release circuits 61a in the first direction D1. The six static electricity release circuits of the second row of static electricity release circuits 61b arranged along the second direction D2 can be connected with the seventh clock signal line PCB, the sixth clock signal line PCK, the fourth clock signal line NCB, the eighth clock signal line PCX, the seventh clock signal line PCB, and the fourth start signal line HSTV in sequence, and play a role of static electricity protection.

[0174] In some examples, the third row of static electricity release circuits 61c can include seven static electricity release circuits, and six of the seven static electricity release circuits can be arranged in alignment with the six static electricity release circuits of the first row of static electricity release circuits 61a in the first direction D1. The seven static electricity release circuits of the third row of static electricity release circuits 61c arranged along the second direction D2 can be connected with the ninth clock signal line HCK, the twelfth clock signal line ECK, the tenth clock signal line HCB, the fourteenth clock signal line ECX, the thirteenth clock signal line ECB, the fifth start signal line ESTV, and the fifth clock signal line NCX in sequence, and play a role of static electricity protection.

[0175] In some examples, the first panel detection line PCD1 can be connected with the second detection connection line 631 located in the first gate metal layer through the first detection connection line 633 located in the first source-drain metal layer. The second panel detection line PCD2 can be connected with the fourth detection connection line 632 located in the first gate metal layer through the third detection connection line 634 located in the first source-drain metal layer.

[0176] In some examples, the first sub-region can further be provided with the second power frame line 342 located in the first source-drain metal layer, and the second power frame line 342 can be connected with the first group of second power bending lines 331a and the second group of second power bending lines 331b of the bending region, so as to be configured to transmit the second voltage signal VSS.

[0177] The structure of the second corner region of the first sub-region is similar to that of the first corner region, and thus will not be described here again.

[0178] FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 15, the display substrate 910 can be an OLED display substrate. The display device 91 can be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like. However, the present embodiment is not limited thereto.

[0179] In the description of the specification, the description using the terms "one embodiment", "some embodiments", "an example", "some examples" or the like means that the particular feature, structure, material or characteristic following the term is included in at least one embodiment or example of the application. The illustrative appearances of the above terms in various places in the specification are not necessarily referred to the same embodiment or example. Also, the particular features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples. Furthermore, in non-contradictory relation to each other, those skilled in the art can combine and combine the features described in the specification of different embodiments or examples and the features of different embodiments or examples.

[0180] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary, and are not to be interpreted as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A display substrate, comprising a display area and a bezel area located around the display area, the bezel area comprising: The first and second frame regions are in communication with each other, and the first frame region at least comprises a bending region located on one side of the display region in a first direction; The display substrate comprises: a substrate; a plurality of sub-pixels arranged on one side of the substrate and located in the display region; a plurality of gate driving circuits located in the second frame region and electrically connected to the plurality of sub-pixels, and configured to provide a plurality of pixel control signals to the plurality of sub-pixels; at least one first peripheral control line located in the first frame region and connected to the plurality of gate driving circuits; a plurality of second peripheral control lines located in the first frame region, and some of the plurality of second peripheral control lines are connected to the plurality of gate driving circuits; the potential of the signal transmitted by each first peripheral control line is lower than the potential of the signal transmitted by each second peripheral control line; In the bending region, at least one second peripheral control line of the plurality of second peripheral control lines is located between the at least one first peripheral control line and the boundary of the display substrate. 2.The display substrate of claim 1, further comprising: a plurality of peripheral data lines located in the first frame region, and the plurality of peripheral data lines are electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; In a second direction, the plurality of second peripheral control lines and the at least one first peripheral control line are located between the plurality of peripheral data lines and the boundary of the display substrate; the second direction intersects the first direction. 3.The display substrate of claim 1, wherein, In the bending region, the minimum distance between the at least one first peripheral control line and the boundary of the display substrate is greater than or equal to 1250 microns. 4.The display substrate of claim 1, wherein, The at least one first peripheral control line is configured to transmit a constant voltage signal, and the potential of the constant voltage signal is less than or equal to -6V. 5.The display substrate of claim 1, wherein, At least one sub-pixel of the plurality of sub-pixels comprises a pixel circuit and a light-emitting element connected to the pixel circuit; The pixel circuit at least comprises a driving transistor, a data writing transistor and a compensation transistor; The gate of the data writing transistor is connected to a first scan line, the first electrode of the data writing transistor is connected to a data line, and the second electrode of the data writing transistor is connected to the first electrode of the driving transistor; The gate of the driving transistor is connected to the second electrode of the compensation transistor, the second electrode of the driving transistor is connected to the first electrode of the compensation transistor, and the gate of the compensation transistor is connected to a second scan line; The plurality of gate driving circuits comprises at least one first scan driving circuit and at least one second scan driving circuit, the at least one first scan driving circuit is configured to provide a first scan signal to the first scan line, and the at least one second scan driving circuit is configured to provide a second scan signal to the second scan line; The plurality of second peripheral control lines at least comprises a second start signal line and a second scan driving output line connected to the at least one second scan driving circuit; The at least one first peripheral control line is located between the second start signal line and the second scan driving output line. 6.The display substrate of claim 5, wherein, The pixel circuit further comprises a first reset transistor, a gate of the first reset transistor is connected with a first reset control line, a first electrode of the first reset transistor is configured to receive a first initial signal, and a second electrode of the first reset transistor is connected with the second electrode of the driving transistor. In the bending area, a second perimeter control line closest to the boundary of the display substrate among the plurality of second perimeter control lines is configured to transmit the first initial signal. 7.The display substrate according to claim 1 or 6, wherein In the bending area, a minimum distance between the second perimeter signal line closest to the boundary of the display substrate among the plurality of second perimeter control lines and the boundary of the display substrate is greater than or equal to 400 microns. 8.The display substrate of claim 1, wherein, The first frame area further comprises a first signal access area located on a side of the bending area away from the display area. The display substrate further comprises a plurality of first contact pads arranged along a second direction in the first signal access area, and the second direction intersects the first direction. The plurality of first contact pads comprises at least one first control contact pad connected with the at least one first perimeter control line, and a plurality of second control contact pads connected with the plurality of second perimeter control lines. In the second direction, at least one second control contact pad among the plurality of second control contact pads is located between the at least one first control contact pad and the boundary of the display substrate. 9.The display substrate of claim 8, wherein, The at least one first perimeter control line is located between a first second perimeter control line and a second second perimeter control line. In the second direction, the at least one first control contact pad is located between a second control contact pad connected with the first second perimeter control line and a second control contact pad connected with the second second perimeter control line. 10.The display substrate of claim 8, wherein, The at least one first perimeter control line is located between a first second perimeter control line and a second second perimeter control line, and the first second perimeter control line is located on a side of the at least one first perimeter control line close to the boundary of the display substrate. In the second direction, the at least one first control contact pad is located on a side of the second control contact pad connected with the second second perimeter control line away from the boundary of the display substrate. 11.The display substrate of claim 1, wherein, The first frame area further comprises a first sub-area located on a side of the bending area close to the display area, and the first sub-area communicates with the second frame area. The display substrate further comprises a plurality of electrostatic discharge circuits located in the first sub-area, and the plurality of electrostatic discharge circuits are arranged adjacent to the plurality of gate drive circuits. The plurality of electrostatic discharge circuits are arranged as a plurality of rows along the first direction, and each row of electrostatic discharge circuits comprises a plurality of electrostatic discharge circuits arranged along a second direction, and the second direction intersects the first direction. The at least one first perimeter signal line is located between two adjacent rows of electrostatic discharge circuits. 12.The display substrate of claim 11, wherein, The plurality of electrostatic discharge circuits are arranged as a first row of electrostatic discharge circuits, a second row of electrostatic discharge circuits, and a third row of electrostatic discharge circuits in a direction away from the display area, and the at least one first perimeter signal line is located between the first row of electrostatic discharge circuits and the second row of electrostatic discharge circuits.

13. The display substrate according to claim 11 or 12, comprising a plurality of first peripheral control lines, and wherein the plurality of electrostatic discharge circuits are connected to one of the first peripheral control lines. 14.The display substrate of claim 1, wherein, The plurality of gate driving circuits comprises a first group of gate driving circuits and a second group of gate driving circuits located on two sides of the display area along a second direction, the second direction being perpendicular to the first direction. The first group of gate driving circuits is connected to at least one first peripheral control line, and the second group of gate driving circuits is connected to at least one first peripheral control line. The first group of gate driving circuits comprises the same number of gate driving circuits as the second group of gate driving circuits.

15. A display device comprising the display substrate according to any one of claims 1 to 14.

Images