Manufacturing method for back-contact solar cell, and solar cell and cell module

Abstract

A manufacturing method for a back-contact solar cell, and a solar cell and a cell module, relating to the technical field of solar cells. The manufacturing method comprises: sequentially forming a first functional layer and an insulating layer on a backlight surface of a semiconductor substrate, wherein the backlight surface of the semiconductor substrate is a polished surface; texturing a light receiving surface of the semiconductor substrate opposite to the backlight surface; sequentially forming a tunneling oxide layer, a doped polysilicon layer, and an anti-reflection layer on the textured light receiving surface of the semiconductor substrate; patterning the first functional layer and the insulating layer; forming a second functional layer on the side of the patterned first functional layer away from the semiconductor substrate; and forming electrode structures on the sides of the first functional layer and the second functional layer away from the semiconductor substrate.

Description

Preparation method of back contact solar cell, solar cell and battery assembly

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on and claims the priority of the Chinese patent application with application number: 2024103558121 and application date of March 27, 2024. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference. Technical Field

[0003] The present disclosure relates to the technical field of solar cells, and in particular to a method for preparing a back-contact solar cell, a solar cell, and a solar cell assembly. Background Art

[0004] Back-contact (BC) cells are a hot topic in industry research. Their most significant feature is that the metal electrode is located on the back surface of the cell, leaving the front surface unobstructed by the metal electrode. This improves light utilization, resulting in higher short-circuit current and conversion efficiency. Among various BC technologies, HBC (Hybrid Back Contact) technology has the highest photoelectric conversion efficiency. By adopting hybrid technology, passivation contact technology is applied to the back of the cell, forming an HBC cell.

[0005] HBC cells typically feature an amorphous silicon thin film on the front, which degrades more rapidly under UV (ultraviolet) radiation. Current solutions primarily involve the use of UV-blocking or UV-transfer films when packaging the cells into modules. However, these solutions present challenges such as reduced electrical performance, yellowing of the film, and increased costs. Furthermore, the photoelectric conversion efficiency of HBC cells remains to be improved. Furthermore, HBC cells do not utilize amorphous silicon produced using a low-temperature process, which complicates the manufacturing process and increases manufacturing costs.

[0006] Summary of the Invention

[0007] The present disclosure aims to solve at least one of the technical problems existing in the prior art. To this end, the present disclosure proposes a method for preparing a back-contact solar cell, a solar cell, and a cell assembly. The light-receiving surface of the substrate is provided with a tunneling oxide layer and a doped polysilicon layer, which has better passivation contact performance and can reduce UV attenuation. In addition, the backlight surface of the substrate is fully polished, so that the solar cell has a higher open-circuit voltage and photoelectric conversion efficiency. At the same time, by simultaneously completing the preparation of the tunneling oxide layer and the doped polysilicon layer on the light-receiving surface and the full polishing of the backlight surface, the process is simplified, and the first functional layer and the insulating layer covering the backlight surface of the semiconductor substrate can play a role in protecting the polished morphology of the backlight surface of the semiconductor substrate.

[0008] In a first aspect, the present disclosure provides a method for preparing a back-contact solar cell, comprising:

[0009] forming a first functional layer and an insulating layer in sequence on the backlight surface of the semiconductor substrate, wherein the backlight surface of the semiconductor substrate is a polished surface, the first functional layer completely covers the backlight surface, and the insulating layer completely covers the first functional layer;

[0010] Texturing the light-receiving surface of the semiconductor substrate opposite to the backlight surface;

[0011] A tunneling oxide layer, a doped polysilicon layer and an anti-reflection layer are sequentially formed on the light-receiving surface of the semiconductor substrate after texturing;

[0012] patterning the first functional layer and the insulating layer;

[0013] forming a second functional layer on a side of the patterned first functional layer away from the semiconductor substrate;

[0014] An electrode structure is formed on a side of the first functional layer and the second functional layer away from the semiconductor substrate.

[0015] According to the preparation method of the back-contact solar cell disclosed in the present invention, a tunneling oxide layer and a doped polysilicon layer are prepared on the light-receiving surface of the substrate. Compared with the amorphous silicon layer on the light-receiving surface of the conventional HBC cell substrate, the method has better passivation contact performance and can reduce UV attenuation. In addition, the backlight surface of the substrate is fully polished, which reduces the interface defects and carrier recombination in the heterojunction region of the backlight surface, so that the solar cell has a higher open-circuit voltage and photoelectric conversion efficiency. At the same time, the preparation process of the tunneling oxide layer and the doped polysilicon layer on the light-receiving surface and the full polishing preparation process of the backlight surface are combined in the process to complete the preparation of the two parts simultaneously, which simplifies the process. In addition, the first functional layer and the insulating layer covering the backlight surface of the semiconductor substrate can play a role in protecting the polishing morphology of the backlight surface of the semiconductor substrate.

[0016] According to one embodiment of the present disclosure, the remaining thickness of the anti-reflection layer after the step of forming an electrode structure on the side of the first functional layer and the second functional layer away from the semiconductor substrate is in a range of 20 nm to 150 nm.

[0017] According to one embodiment of the present disclosure, the anti-reflection layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and transparent conductive oxide.

[0018] According to one embodiment of the present disclosure, before sequentially forming the first functional layer and the insulating layer on the backlight surface of the semiconductor substrate, the method further includes:

[0019] providing a semiconductor substrate;

[0020] The light-receiving surface and the backlight surface of the semiconductor substrate are surface-polished.

[0021] According to one embodiment of the present disclosure, texturing is performed on a light-receiving surface of a semiconductor substrate opposite to a backlight surface, including:

[0022] Removing the insulating layer or oxide layer coated around the light-receiving surface of the semiconductor substrate opposite to the backlight surface;

[0023] The semiconductor substrate is immersed in a texturing solution to form a texturing morphology on the light-receiving surface of the semiconductor substrate.

[0024] According to one embodiment of the present disclosure, a first opening is formed in the patterned first functional layer, and the backlight surface of the semiconductor substrate is exposed by the first opening. A second functional layer is formed on a side of the patterned first functional layer away from the semiconductor substrate, including:

[0025] forming an intrinsic amorphous silicon layer on a side of the patterned first functional layer away from the semiconductor substrate, wherein the intrinsic amorphous silicon layer contacts the semiconductor substrate through the first opening;

[0026] forming a doped semiconductor layer on a side of the intrinsic amorphous silicon layer away from the semiconductor substrate;

[0027] The doping type of the doped semiconductor layer in the second functional layer is opposite to the doping type of the doped semiconductor layer in the first functional layer.

[0028] According to one embodiment of the present disclosure, an electrode structure is formed on a side of the first functional layer and the second functional layer away from the semiconductor substrate, including:

[0029] forming a second opening in the second functional layer, wherein an orthographic projection of the second opening on the semiconductor substrate is located within an orthographic projection of the patterned first functional layer on the semiconductor substrate, and the second opening exposes the patterned first functional layer;

[0030] forming a conductive layer on a side of the second functional layer away from the semiconductor substrate;

[0031] forming a third opening in the conductive layer to cut off the conductive layer, wherein the third opening is located between the first opening and the second opening;

[0032] A first electrode and a second electrode are formed on a side of the conductive layer away from the semiconductor substrate, the orthographic projection of the first electrode on the semiconductor substrate is located within the orthographic projection of the second opening on the semiconductor substrate, and the orthographic projection of the second electrode on the semiconductor substrate is located within the orthographic projection of the first opening on the semiconductor substrate.

[0033] According to one embodiment of the present disclosure, the material of the insulating layer includes at least one of phosphosilicate glass or borosilicate glass, silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon, microcrystalline silicon, and polycrystalline silicon.

[0034] In a second aspect, the present disclosure provides a back-contact solar cell, comprising:

[0035] A semiconductor substrate having a light-receiving surface and a backlight surface opposite to each other, wherein the backlight surface of the semiconductor substrate is a polished surface, the light-receiving surface of the semiconductor substrate is a velvet surface, and the backlight surface includes a first polarity region and a second polarity region alternately arranged along a first direction;

[0036] a first polarity structure disposed in the first polarity region, the first polarity structure comprising a first passivation layer, a first doped semiconductor layer, and a first electrode structure stacked in a direction away from the semiconductor substrate, wherein a surface of the first passivation layer facing the semiconductor substrate is a polished surface;

[0037] a second polarity structure disposed in the second polarity region, the second polarity structure comprising a second passivation layer, a second doped semiconductor layer, and a second electrode structure stacked in a direction away from the semiconductor substrate, wherein a surface of the second passivation layer facing the semiconductor substrate is a polished surface, and the doping type of the first doped semiconductor layer and the doping type of the second doped semiconductor layer are opposite;

[0038] A tunneling oxide layer is provided on the light-receiving surface of the semiconductor substrate;

[0039] a doped polysilicon layer, disposed on a side of the tunnel oxide layer away from the semiconductor substrate;

[0040] The anti-reflection layer is arranged on a side of the doped polysilicon layer away from the tunnel oxide layer.

[0041] According to the back-contact solar cell disclosed in the present invention, the light-receiving surface of the substrate is provided with a tunneling oxide layer and a doped polycrystalline silicon layer, which has better passivation contact performance than the amorphous silicon layer on the light-receiving surface of the conventional HBC cell substrate and can reduce UV attenuation. In addition, the backlight surface of the substrate is fully polished, which reduces the interface defects and carrier recombination in the heterojunction region of the backlight surface, so that the solar cell has a higher open-circuit voltage and photoelectric conversion efficiency, and the first functional layer and insulating layer covering the backlight surface of the semiconductor substrate can protect the polished morphology of the backlight surface of the semiconductor substrate.

[0042] According to one embodiment of the present disclosure, the thickness of the doped polysilicon layer is smaller than the thickness of the first doped semiconductor layer.

[0043] According to one embodiment of the present disclosure, the thickness of the tunnel oxide layer is in the range of 0.5 nm to 2.5 nm, and the thickness of the doped polysilicon layer is in the range of 3 nm to 100 nm.

[0044] According to one embodiment of the present disclosure, the first passivation layer includes a tunneling oxide, the thickness of the first passivation layer is in the range of 0.5nm-2.5nm, the first doped semiconductor layer includes doped polycrystalline silicon, the thickness of the first doped semiconductor layer is in the range of 10nm-250nm, the second passivation layer includes intrinsic amorphous silicon, the thickness of the second passivation layer is in the range of 1nm-15nm, the second doped semiconductor layer includes doped amorphous silicon and / or microcrystalline silicon, the thickness of the second doped semiconductor layer is in the range of 1nm-60nm.

[0045] According to one embodiment of the present disclosure, the second passivation layer at least partially extends to the first polarity region, and a first orthographic projection of the first doped semiconductor layer on the semiconductor substrate at least partially overlaps with a second orthographic projection of the second passivation layer on the semiconductor substrate;

[0046] There is direct contact between the first doped semiconductor layer and the second passivation layer; or

[0047] An insulating layer is provided between the first doped semiconductor layer and the second passivation layer. The material of the insulating layer includes at least one of phosphosilicate glass or borosilicate glass, silicon oxide, silicon nitride, and silicon oxynitride.

[0048] According to one embodiment of the present disclosure, the electrode structure includes a conductive layer and an electrode, wherein the conductive layer is located on a side of the doped semiconductor layer away from the passivation layer, and the electrode is located on a side of the conductive layer away from the doped semiconductor layer;

[0049] The material of the conductive layer includes at least one of zinc oxide, indium oxide and tin oxide, and the conductive layer is doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten and aluminum. The thickness of the conductive layer ranges from 10nm to 150nm.

[0050] In a third aspect, the present disclosure provides a battery assembly comprising a back-contact solar cell prepared according to the aforementioned preparation method, or comprising the aforementioned back-contact solar cell.

[0051] The battery assembly according to the present disclosure has better performance by adopting a back-contact solar cell with good passivation contact performance, low UV attenuation, high open circuit voltage and good photoelectric conversion efficiency.

[0052] Additional aspects and advantages of the present disclosure will be given in part in the description that follows and, in part, will be obvious from the description that follows, or will be learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The above and / or additional aspects and advantages of the present disclosure will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0054] FIG1 is a schematic flow chart of a method for preparing a back-contact solar cell according to an embodiment of the present disclosure;

[0055] FIG2 is a schematic diagram of a cross-sectional structure of a stage in a preparation method provided by an embodiment of the present disclosure;

[0056] FIG3 is a second schematic diagram of the cross-sectional structure of a stage in the preparation method provided by an embodiment of the present disclosure;

[0057] FIG4 is a third schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present disclosure;

[0058] FIG5 is a fourth schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present disclosure;

[0059] FIG6 is a fifth schematic diagram of the cross-sectional structure of a stage in the preparation method provided in an embodiment of the present disclosure;

[0060] FIG7 is a sixth schematic diagram of the cross-sectional structure of a stage in the preparation method provided by an embodiment of the present disclosure;

[0061] FIG8 is a seventh schematic diagram of a cross-sectional structure of a stage in the preparation method provided by an embodiment of the present disclosure;

[0062] FIG9 is an eighth schematic diagram of a cross-sectional structure of a stage in the preparation method provided by an embodiment of the present disclosure;

[0063] FIG10 is a ninth schematic diagram of a cross-sectional structure of a stage in a preparation method provided in an embodiment of the present disclosure;

[0064] FIG11 is a tenth schematic diagram of the cross-sectional structure of a stage in the preparation method provided by an embodiment of the present disclosure;

[0065] FIG12 is an eleventh schematic diagram of a cross-sectional structure of a stage in a preparation method provided by an embodiment of the present disclosure;

[0066] FIG13 is a schematic diagram of a cross-sectional structure of a back-contact solar cell according to an embodiment of the present disclosure;

[0067] FIG14 is a second schematic diagram of the cross-sectional structure of the back-contact solar cell provided in an embodiment of the present disclosure.

[0068] Reference numerals:

[0069] Semiconductor substrate 1, first functional layer 2, first passivation layer 2-1, first doped semiconductor layer 2-2, first substrate doped layer 3, insulating layer 4, second functional layer 5, second passivation layer 5-1, second doped semiconductor layer 5-2, third functional layer 6, tunneling oxide layer 6-1, doped polysilicon layer 6-2, second substrate doped layer 7, anti-reflection layer 8, conductive layer 9, first conductive layer 9-1, second conductive layer 9-2, first electrode 10, second electrode 11, first surface S1, second surface S2, third surface S3, first opening G1, second opening G2, third opening G3, first polarity region A, second polarity region B. DETAILED DESCRIPTION

[0070] Embodiments of the present disclosure are described in detail below, with examples of the embodiments illustrated in the accompanying drawings. In the accompanying drawings, the sizes of layers, regions, and components, as well as their relative sizes, may be exaggerated for clarity. The same or similar reference numerals throughout represent the same or similar components or components having the same or similar functions. The embodiments described below with reference to the accompanying drawings are illustrative and intended only to explain the present disclosure, and are not to be construed as limiting the present disclosure.

[0071] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that while the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another. Thus, without departing from the teachings of the present disclosure, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. Furthermore, when a second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present disclosure.

[0072] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0073] In the related art, the structure of HBC cells generally has an amorphous silicon thin film on the front. Since amorphous silicon thin films are more susceptible to damage from ultraviolet radiation and produce defects on the surface, they decay faster under UV radiation than other types of cells. The structure of HBC cells generally has a polished TOPCon (Tunnel Oxide Passivated Contact) area on the back, while the rear heterojunction area and the front have a suede morphology. The purpose of this is to make the process relatively simple. However, since the interface area of ​​the suede surface is larger than that of the polished surface, the interface defects and carrier recombination on the suede surface are more serious than those on the polished surface, resulting in the passivation of the rear heterojunction area not reaching the optimal level, thereby affecting the cell efficiency.

[0074] The present disclosure proposes a method for preparing a back-contact solar cell, a solar cell, and a cell module. By preparing a tunneling oxide layer and a doped polycrystalline silicon layer on the light-receiving surface of a substrate, compared with the amorphous silicon layer on the light-receiving surface of a conventional HBC cell substrate, the method has better passivation contact performance and can reduce UV attenuation. In addition, the backlight surface of the substrate is fully polished, which reduces interface defects and carrier recombination in the heterojunction region of the backlight surface, so that the solar cell has a higher open-circuit voltage and photoelectric conversion efficiency.

[0075] Furthermore, the general process for HBC backside fully polished structures is to provide a single-side textured and single-side polished silicon wafer before fabricating a TOPCon or HJT structure. This requires the wafer to undergo at least double-side textured, front-side masking, back-side polishing, and mask removal, or double-side polishing, back-side masking, front-side textured, and mask removal. The front-side doped polysilicon layer needs to be thinner than the back-side doped polysilicon layer in the TOPCon region to account for light absorption, necessitating separate fabrication of the front and back doped polysilicon layers, further increasing process complexity.

[0076] In the preparation method of the back-contact solar cell proposed in the present disclosure, the preparation process of the tunneling oxide layer and the doped polysilicon layer on the light-receiving side and the full polishing preparation process on the backlight side are combined in the process, and the preparation of the two parts is completed simultaneously, which simplifies the process. The first functional layer and the insulating layer covering the backlight side of the semiconductor substrate can protect the polishing morphology of the backlight side of the semiconductor substrate.

[0077] Referring to FIG1 , FIG1 illustrates a process for preparing a back-contact solar cell. In one embodiment of the present disclosure, a method for preparing a back-contact solar cell is provided. In this embodiment, the method for preparing a back-contact solar cell includes steps 10, 20, 30, 40, 50, and 60.

[0078] Step 10: forming a first functional layer 2 and an insulating layer 4 in sequence on the backlight surface of the semiconductor substrate 1, wherein the backlight surface of the semiconductor substrate 1 is a polished surface, the first functional layer 2 completely covers the backlight surface, and the insulating layer 4 completely covers the first functional layer 2;

[0079] Step 20: Texturing the light-receiving surface of the semiconductor substrate 1 opposite to the backlight surface;

[0080] Step 30: forming a tunneling oxide layer, a doped polysilicon layer and an anti-reflection layer 8 in sequence on the light-receiving surface of the semiconductor substrate 1 after texturing;

[0081] Step 40: patterning the first functional layer 2 and the insulating layer 4;

[0082] Step 50: forming a second functional layer 5 on a side of the patterned first functional layer 2 away from the semiconductor substrate 1;

[0083] Step 60 : forming an electrode structure on a side of the first functional layer 2 and the second functional layer 5 away from the semiconductor substrate 1 .

[0084] In some embodiments, the semiconductor substrate 1 may include single crystal silicon, germanium, gallium arsenide, etc. The doping type of the semiconductor substrate 1 may be N-type doping or P-type doping.

[0085] 2 , the backlight surface of the semiconductor substrate 1 is the first surface S1 , and the first surface S1 is a polished surface.

[0086] In some embodiments, before step 10, the following steps may be included: providing a semiconductor substrate 1; and performing surface polishing on the light-receiving surface and the backlight surface of the semiconductor substrate 1.

[0087] In this embodiment, semiconductor substrate 1 is first double-sided polished, resulting in a polished appearance on both the light-receiving and backlight-receiving sides of semiconductor substrate 1. For example, semiconductor substrate 1 is immersed in a polishing solution to achieve double-sided polishing. By simultaneously polishing both sides, the mask preparation and removal processes can be eliminated.

[0088] 3 , in some embodiments, a first functional layer 2 and an insulating layer 4 are formed on the backlight surface of the semiconductor substrate 1 after step 10. The first functional layer 2 may include a first passivation layer 2-1 and a first doped semiconductor layer 2-2. The first doped semiconductor layer 2-2 is located on the side of the first passivation layer 2-1 away from the semiconductor substrate 1. The material of the first passivation layer 2-1 may include a tunneling oxide, and its thickness may range from 0.5 nm to 2.5 nm, such as 0.5 nm, 1.5 nm, or 2.5 nm. The material of the first doped semiconductor layer 2-2 may include doped polysilicon, and its thickness may range from 10 nm to 300 nm, such as 10 nm, 50 nm, 150 nm, or 300 nm.

[0089] The first passivation layer 2-1 and the first doped semiconductor layer 2-2 can be formed by LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition). For example, in-situ doped amorphous / polycrystalline silicon is first formed on the side of the first passivation layer 2-1 away from the semiconductor substrate 1, and then crystallized by high temperature annealing; or after forming the intrinsic amorphous / polycrystalline silicon layer, doping and crystallization are performed by high temperature diffusion.

[0090] In this embodiment, while forming the first functional layer 2, the dopant elements in the first doped semiconductor layer 2-2 enter the backlit surface of the semiconductor substrate 1 through the first passivation layer 2-1 to form a first substrate doping layer 3. The doping type of the first substrate doping layer 3 is the same as that of the first doped semiconductor layer 2-2. The thickness of the first substrate doping layer 3 ranges from 5 nm to 200 nm, for example, 5 nm, 50 nm, 100 nm, or 200 nm.

[0091] After the first functional layer 2 is formed, an insulating layer 4 is formed on the side of the first functional layer 2 away from the semiconductor substrate 1. The insulating layer 4 is made of at least one of phosphosilicate glass or borosilicate glass, silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon, microcrystalline silicon, and polycrystalline silicon.

[0092] 4 , in step 20 , the light-receiving surface of the semiconductor substrate 1 is textured to obtain a third surface S3 .

[0093] It should be noted that when the semiconductor substrate 1 is textured, it usually needs to be immersed in the texture solution as a whole. Therefore, the first functional layer 2 and the insulating layer 4 covering the backlight surface of the semiconductor substrate 1 can protect the polishing morphology of the backlight surface of the semiconductor substrate 1.

[0094] In some embodiments, the specific process of step 20 can be: removing the insulating layer or oxide layer plated around the light-receiving surface of the semiconductor substrate 1 opposite to the backlight surface, for example, using a chain single-sided etching process; immersing the semiconductor substrate 1 in a texturing solution to form a texturing morphology on the light-receiving surface of the semiconductor substrate 1.

[0095] Referring to Figure 5 , a third functional layer 6 and an anti-reflection layer 8 are formed on the light-receiving surface of the semiconductor substrate 1. The third functional layer 6 includes a tunneling oxide layer 6-1 and a doped polysilicon layer 6-2. The doped polysilicon layer 6-2 is located on the side of the tunneling oxide layer 6-1 away from the semiconductor substrate 1. The thickness of the tunneling oxide layer 6-1 ranges from 0.5 nm to 2.5 nm, such as 0.5 nm, 1.5 nm, or 2.5 nm. The thickness of the doped polysilicon layer 6-2 ranges from 10 nm to 300 nm, such as 10 nm, 50 nm, 150 nm, or 300 nm.

[0096] In some embodiments, the first doped semiconductor layer 2-2 may also be a doped polysilicon layer. Considering the need for light absorption, the thickness of the doped polysilicon layer 6-2 is less than the thickness of the first doped semiconductor layer 2-2.

[0097] The tunnel oxide layer 6-1 and the doped polysilicon layer 6-2 can be formed by LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition). For example, in-situ doped amorphous / polysilicon can be formed on the side of the tunnel oxide layer 6-1 away from the semiconductor substrate 1, and then crystallized by high temperature annealing; or after forming the intrinsic amorphous / polysilicon layer, doping and crystallization can be performed by high temperature diffusion.

[0098] In this embodiment, while the third functional layer 6 is being formed, the dopant elements in the doped polysilicon layer 6-2 enter the light-receiving surface of the semiconductor substrate 1 through the tunneling oxide layer 6-1 to form a second substrate doped layer 7. The doping type of the second substrate doped layer 7 is the same as that of the doped polysilicon layer 6-2. The thickness of the second substrate doped layer 7 is in the range of 5 nm to 200 nm, for example, 5 nm, 50 nm, 100 nm, or 200 nm.

[0099] After the third functional layer 6 is formed, an anti-reflection layer 8 is formed on the side of the third functional layer 6 facing away from the semiconductor substrate 1. The material of the anti-reflection layer 8 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and a transparent conductive oxide. The anti-reflection layer 8 also serves as a mask to protect the third functional layer 6 from being etched during subsequent etching steps.

[0100] In some embodiments, after the step of forming an electrode structure on the side of the first functional layer 2 and the second functional layer 5 away from the semiconductor substrate 1, the remaining thickness of the anti-reflection layer 8 is in a range of 20 nm to 150 nm, for example, 20 nm, 100 nm, or 150 nm. That is, after the back-contact solar cell is fabricated, the remaining thickness of the anti-reflection layer 8 is in a range of 20 nm to 150 nm.

[0101] Referring to Figure 6 , the backlight surface of the semiconductor substrate 1 is patterned. Portions of the insulating layer 4, the first functional layer 2, and the first substrate doping layer 3 are removed to form spaced first openings G1, exposing the second surface S2. The distance between the first surface S1 and the third surface S3 is greater than the distance between the second surface S2 and the third surface S3, ensuring that no residue of the first substrate doping layer 3 remains.

[0102] As an example, the specific process of step 40 can be: first remove part of the insulating layer 4 by laser etching or ink printing; then remove the first doped semiconductor layer 2-2, the first passivation layer 2-1 and the first substrate doping layer 3 in the area without the insulating layer 4 by wet chemical etching.

[0103] The etching solution used in wet chemical etching may include an alkaline polishing solution, so that the second surface S2 can be polished while removing the first substrate doping layer 3, so that the etched second surface S2 forms a polished morphology to reduce surface defects.

[0104] Referring to Figure 7 , in some embodiments, it should be noted that after step 40, the insulating layer 4 on the side of the first doped semiconductor layer 2-2 away from the first passivation layer 2-1 can be completely removed. Because the insulating layer 4 is not easily etched, etching the first functional layer 2 may cause the edge of the insulating layer 4 to protrude and hang in the air. When the insulating layer 4 is completely removed, the protruding insulating layer 4 will not affect the formation of the second functional layer 5 and the passivation effect.

[0105] In some embodiments, step 50 may include: forming an intrinsic amorphous silicon layer on the side of the patterned first functional layer 2 away from the semiconductor substrate 1, and the intrinsic amorphous silicon layer is in contact with the semiconductor substrate 1 through the first opening G1; forming a doped semiconductor layer on the side of the intrinsic amorphous silicon layer away from the semiconductor substrate 1; wherein the doping type of the doped semiconductor layer in the second functional layer 5 is opposite to the doping type of the doped semiconductor layer in the first functional layer 2.

[0106] Referring to Figure 8 , a second functional layer 5 is formed on the backlit surface of the semiconductor substrate 1. The second functional layer 5 includes a second passivation layer 5-1 and a second doped semiconductor layer 5-2. The second doped semiconductor layer 5-2 is located on the side of the second passivation layer 5-1 away from the semiconductor substrate 1. The second passivation layer 5-1 comprises intrinsic amorphous silicon and has a thickness ranging from 1 nm to 15 nm, such as 1 nm, 10 nm, or 15 nm. The second doped semiconductor layer 5-2 comprises doped amorphous silicon and / or microcrystalline silicon and has a thickness ranging from 1 nm to 60 nm, such as 1 nm, 30 nm, or 60 nm. The doping type of the second doped semiconductor layer 5-2 is opposite to that of the first doped semiconductor layer 2-2. The second passivation layer 5-1 and the second doped semiconductor layer 5-2 can also be formed on the backlit surface of the semiconductor substrate 1 by LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition).

[0107] In some embodiments, step 60 may include: forming a second opening G2 in the second functional layer 5, the orthographic projection of the second opening G2 on the semiconductor substrate 1 is located within the orthographic projection of the patterned first functional layer 2 on the semiconductor substrate 1, and the second opening G2 exposes the patterned first functional layer 2; forming a conductive layer 9 on a side of the second functional layer 5 away from the semiconductor substrate 1; forming a third opening G3 in the conductive layer 9 to cut off the conductive layer 9, the third opening G3 is located between the first opening G1 and the second opening G2; forming a first electrode 10 and a second electrode 11 on a side of the conductive layer 9 away from the semiconductor substrate 1, the orthographic projection of the first electrode 10 on the semiconductor substrate 1 is located within the orthographic projection of the second opening G2 on the semiconductor substrate 1, and the orthographic projection of the second electrode 11 on the semiconductor substrate 1 is located within the orthographic projection of the first opening G1 on the semiconductor substrate 1.

[0108] 9 , a second opening G2 is formed on a side of the first functional layer 2 away from the semiconductor substrate 1. For example, the second functional layer 5 is removed by laser etching, and the insulating layer 4 and / or the laser oxidation layer are removed by wet chemical etching to expose the first doped semiconductor layer 2-2. The first doped semiconductor layer 2-2 may be removed to a certain thickness to ensure that no insulating layer 4 and / or the laser oxidation layer remain in the region of the second opening G2.

[0109] 10 , a conductive layer 9 is prepared. The conductive layer 9 covers the first functional layer 2 and the second functional layer 5. The conductive layer 9 can be prepared by physical vapor deposition (PVD) and chemical vapor deposition (CVD), and can be selected from reactive plasma deposition (RPD), magnetron sputtering, pulsed laser deposition (PLD), vacuum evaporation, atomic layer deposition (ALD), etc. The material of the conductive layer 9 includes at least one of zinc oxide, indium oxide, and tin oxide, which can be doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten, and aluminum. The thickness of the conductive layer 9 ranges from 10 nm to 150 nm, such as 10 nm, 50 nm, or 150 nm.

[0110] Referring to Figure 11 , a third opening G3 is formed. For example, the portion of the conductive layer 9 between the first opening G1 and the third opening G3 is removed by laser etching, ink printing, and / or wet chemical etching to form the third opening G3. The third opening G3 at least interrupts the conductive layer 9, exposing at most the first doped semiconductor layer 2-2. The conductive layer 9 is divided by the third opening G3 into a first conductive layer 9-1 and a second conductive layer 9-2. In the first direction D1, the first conductive layer 9-1 is located above the second opening G2 and extends to both sides. The second conductive layer 9-2 is located above the first opening G1 and extends to both sides.

[0111] Referring to Figure 12 , electrodes are prepared. A first electrode 10 is located on the side of the first conductive layer 9-1 away from the semiconductor substrate 1, and a second electrode 11 is located on the side of the second conductive layer 9-2 away from the semiconductor substrate 1. Methods for preparing the first and second electrodes 10, 11 include screen printing of silver paste, inkjet printing of silver paste, electroplating, and the like.

[0112] 13 and 14 , FIG13 shows the structure of a first back-contact solar cell, and FIG14 shows the structure of a second back-contact solar cell. One embodiment of the present disclosure further provides a back-contact solar cell.

[0113] In this embodiment, a back-contact solar cell includes a semiconductor substrate 1, a first polarity structure, a second polarity structure, a tunneling oxide layer, a doped polysilicon layer and an anti-reflection layer 8, wherein the semiconductor substrate 1 has a light-receiving surface and a back-light surface relative to each other, the back-light surface of the semiconductor substrate 1 is a polished surface, the light-receiving surface of the semiconductor substrate 1 is a velvet surface, and the back-light surface includes a first polarity region A and a second polarity region B alternately arranged along a first direction D1; the first polarity structure is arranged in the first polarity region A, and the first polarity structure includes a first passivation layer 2-1, a first doped semiconductor layer 2-2 and a first electrode structure stacked in a direction away from the semiconductor substrate 1, and the first passivation layer 2-1 faces One side surface of the semiconductor substrate 1 is a polished surface; the second polarity structure is arranged in the second polarity region B, and the second polarity structure includes a second passivation layer 5-1, a second doped semiconductor layer 5-2 and a second electrode structure stacked in a direction away from the semiconductor substrate, and the side surface of the second passivation layer 5-1 facing the semiconductor substrate 1 is a polished surface, and the doping type of the first doped semiconductor layer 2-2 and the doping type of the second doped semiconductor layer 5-2 are opposite; the tunneling oxide layer is arranged on the light-receiving surface of the semiconductor substrate 1; the doped polysilicon layer is arranged on the side of the tunneling oxide layer away from the semiconductor substrate 1; and the anti-reflection layer 8 is arranged on the side of the doped polysilicon layer away from the tunneling oxide layer.

[0114] In this embodiment, the light-receiving surface of semiconductor substrate 1 is provided with a third functional layer 6 and an anti-reflection layer 8, stacked in a direction away from semiconductor substrate 1. Third functional layer 6 comprises a tunneling oxide layer 6-1 and a doped polysilicon layer 6-2, with doped polysilicon layer 6-2 located on the side of tunneling oxide layer 6-1 away from semiconductor substrate 1. Compared to the amorphous silicon layer on the light-receiving surface of conventional HBC cell substrates, this design offers improved passivation contact performance and reduces UV attenuation. Furthermore, the backlight side of the substrate is fully polished, reducing interface defects and carrier recombination in the heterojunction region on this backlight side, resulting in a solar cell with higher open-circuit voltage and photoelectric conversion efficiency.

[0115] In a first direction D1, the first polarity region A and the second polarity region B are arranged adjacent to each other. A first opening G1 is formed on the light-receiving surface of the semiconductor substrate 1. The first opening G1 is used to form the second polarity region B. The surface of the first polarity region A is denoted as a first surface S1, the surface of the second polarity region B is denoted as a second surface S2, and the light-receiving surface of the semiconductor substrate 1 is denoted as a third surface S3.

[0116] In some embodiments, the distance between the first surface S1 and the third surface S3 of the first polarity region A is greater than the distance between the second surface S2 and the third surface S3 of the second polarity region B. This facilitates complete removal of the original film layer of the first polarity region A when forming the first opening G1.

[0117] The material of the first passivation layer 2-1 may include a tunneling oxide, and its thickness ranges from 0.5 nm to 2.5 nm, such as 0.5 nm, 1.5 nm, or 2.5 nm. The material of the first doped semiconductor layer 2-2 may include doped polysilicon, and its thickness ranges from 10 nm to 300 nm, such as 10 nm, 50 nm, 150 nm, or 300 nm.

[0118] While forming the first functional layer 2, the dopant elements in the first doped semiconductor layer 2-2 enter the backlit surface of the semiconductor substrate 1 through the first passivation layer 2-1 to form a first substrate doping layer 3. The doping type of the first substrate doping layer 3 is the same as that of the first doped semiconductor layer 2-2. The thickness of the first substrate doping layer 3 ranges from 5 nm to 200 nm, for example, 5 nm, 50 nm, 100 nm, or 200 nm.

[0119] The second passivation layer 5-1 comprises intrinsic amorphous silicon and has a thickness ranging from 1 nm to 15 nm, such as 1 nm, 10 nm, or 15 nm. The second doped semiconductor layer 5-2 comprises doped amorphous silicon and / or microcrystalline silicon and has a thickness ranging from 1 nm to 60 nm, such as 1 nm, 30 nm, or 60 nm. The doping type of the second doped semiconductor layer 5-2 is opposite to the doping type of the first doped semiconductor layer 2-2. For example, if the first doped semiconductor layer 2-2 is N-type doped, the second doped semiconductor layer 5-2 can be P-type doped.

[0120] The thickness of the tunnel oxide layer 6-1 is in the range of 0.5 nm to 2.5 nm, such as 0.5 nm, 1.5 nm, or 2.5 nm. The thickness of the doped polysilicon layer 6-2 is in the range of 10 nm to 300 nm, such as 10 nm, 50 nm, 150 nm, or 300 nm.

[0121] In some embodiments, the first doped semiconductor layer 2-2 may also be a doped polysilicon layer. Considering the need for light absorption, the thickness of the doped polysilicon layer 6-2 is less than the thickness of the first doped semiconductor layer 2-2.

[0122] Simultaneously with the formation of the third functional layer 6, the dopant elements in the doped polysilicon layer 6-2 enter the light-receiving surface of the semiconductor substrate 1 through the tunneling oxide layer 6-1 to form a second substrate doped layer 7. The doping type of the second substrate doped layer 7 is the same as that of the doped polysilicon layer 6-2. The thickness of the second substrate doped layer 7 ranges from 5 nm to 200 nm, for example, 5 nm, 50 nm, 100 nm, or 200 nm.

[0123] In some embodiments, the second functional layer 5 at least partially extends to the first polarity region A, and a first orthographic projection of the first functional layer 2 on the semiconductor substrate 1 partially overlaps with a second orthographic projection of the second functional layer 5 on the semiconductor substrate 1 .

[0124] In the first direction D1, the second passivation layer 5-1 and the second doped semiconductor layer 5-2 extend toward the first polarity regions A on both sides, and respectively overlap with the first passivation layer 2-1 and the first doped semiconductor layer 2-2 located in the first polarity regions A on both sides. The orthographic projection of the overlapping portion on the semiconductor substrate 1 is located within the first polarity region A. Therefore, in the first direction D1, both sides of the first polarity region A have overlapping portions.

[0125] As shown in Figure 13, an insulating layer 4 is provided between the first functional layer 2 and the second functional layer 5. In the overlapping portion of the first functional layer 2 and the second functional layer 5, the insulating layer 4 is provided between the second passivation layer 5-1 and the first doped semiconductor layer 2-2. This reduces leakage current. The insulating layer 4 is made of at least one of phosphosilicate glass or borosilicate glass, silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon, microcrystalline silicon, and polycrystalline silicon.

[0126] Alternatively, as shown in Figure 14, the first functional layer 2 and the second functional layer 5 can be in direct contact. Since the insulating layer 4 is not easily etched, etching the first functional layer 2 will cause the edge of the insulating layer 4 to protrude. When the insulating layer 4 is removed, the film quality of the second functional layer 5 is easier to control.

[0127] In some embodiments, the electrode structure includes a conductive layer 9 and an electrode. The conductive layer 9 is located on a side of the doped semiconductor layer away from the passivation layer, and the electrode is located on a side of the conductive layer away from the doped semiconductor layer.

[0128] The first electrode structure may have a P polarity and the second electrode structure may have an N polarity. Alternatively, the first electrode structure may have an N polarity and the second electrode structure may have a P polarity. The polarity of the electrode structure depends on the doping type of the functional layer it contacts.

[0129] The first electrode structure includes a first conductive layer 9-1 and a first electrode 10. A second opening G2 is formed on a side of the first doped semiconductor layer 2-2 away from the first passivation layer 2-1. The first conductive layer 9-1 covers the second opening G2 and extends along the first direction D1 to both sides of the second opening G2. The first electrode 10 is located on a side of the first conductive layer 9-1 away from the first doped semiconductor layer 2-2.

[0130] A portion of the second functional layer 5 may be between the portion of the first conductive layer 9-1 extending out of the second opening G2 and the first functional layer 2. That is, the insulating layer 4, the second passivation layer 5-1, and the second doped semiconductor layer 5-2 may be between the first conductive layer 9-1 and the first doped semiconductor layer 2-2, or the second passivation layer 5-1 and the second doped semiconductor layer 5-2 may be between them.

[0131] The second electrode structure includes a second conductive layer 9-2 and a second electrode 11. The second conductive layer 9-2 is formed on a side of the second doped semiconductor layer 5-2 away from the second passivation layer 5-1 and covers the second polarity region B. The second electrode 11 is located on a side of the second conductive layer 9-2 away from the second doped semiconductor layer 5-2.

[0132] In the first direction D1, both sides of the second conductive layer 9-2 can partially extend to the first polarity region A, and the orthographic projection of the second conductive layer 9-2 on the semiconductor substrate 1 at least partially overlaps with the second orthographic projection of the second functional layer 5 on the semiconductor substrate 1. The second conductive layer 9-2 and the first doped semiconductor layer 2-2 are separated by the insulating layer 4, the second passivation layer 5-1, and the second doped semiconductor layer 5-2, or by the second passivation layer 5-1 and the second doped semiconductor layer 5-2.

[0133] In some embodiments, the first conductive layer 9-1 and the second conductive layer 9-2 include a transparent conductive oxide. For example, the material of the first conductive layer 9-1 and the second conductive layer 9-2 includes at least one of zinc oxide, indium oxide, and tin oxide. The material of the first electrode 10 and the second electrode 11 can be a metal material, such as silver or copper.

[0134] In some embodiments, the first conductive layer 9 - 1 and the second conductive layer 9 - 2 may be doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten, and aluminum.

[0135] In some embodiments, the first conductive layer 9 - 1 and the second conductive layer 9 - 2 have the same thickness, ranging from 10 nm to 150 nm. For example, the thickness of the conductive layer 9 can be 10 nm, 50 nm, or 150 nm.

[0136] A third opening G3 is provided between adjacent first and second electrode structures. The third orthographic projection of the third opening G3 on the semiconductor substrate 1 is located within the overlapping region of the first and second orthographic projections. The first and second electrode structures are isolated by the third opening G3 to avoid short circuits.

[0137] The third opening G3 is located between each of the first opening G1 and the second opening G2. The third opening G3 at least separates the first conductive layer 9-1 and the second conductive layer 9-2 and exposes at most the first functional layer 2. As shown in FIG13 or FIG14 , the third opening G3 separates the first conductive layer 9-1 and the second conductive layer 9-2, and cuts off the second passivation layer 5-1 and the second doped semiconductor layer 5-2, exposing the insulating layer 4 or the first doped semiconductor layer 2-2.

[0138] One embodiment of the present disclosure further provides a battery assembly, comprising a back-contact solar cell prepared according to the aforementioned preparation method, or comprising a back-contact solar cell prepared according to the aforementioned preparation method. The specific structure and principle of the back-contact solar cell, as well as the preparation method, can be referred to in the aforementioned embodiments and will not be further described in this embodiment.

[0139] The battery assembly according to the present disclosure has better performance by adopting a back-contact solar cell with good passivation contact performance, low UV attenuation, high open circuit voltage and good photoelectric conversion efficiency.

[0140] As used herein, the terms "comprises," "includes," or any other variants thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present disclosure is not limited to performing functions in the order shown or discussed, but may also include performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved. For example, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0141] Although the embodiments of the present disclosure have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations may be made to the embodiments without departing from the principles and spirit of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for preparing a back-contact solar cell, wherein: include: forming a first functional layer and an insulating layer in sequence on a backlight surface of a semiconductor substrate, wherein the backlight surface of the semiconductor substrate is a polished surface, the first functional layer completely covers the backlight surface, and the insulating layer completely covers the first functional layer; Performing texturing on the light-receiving surface of the semiconductor substrate opposite to the backlight surface; forming a tunneling oxide layer, a doped polysilicon layer and an anti-reflection layer in sequence on the light-receiving surface of the semiconductor substrate after texturing; patterning the first functional layer and the insulating layer; forming a second functional layer on a side of the patterned first functional layer away from the semiconductor substrate; An electrode structure is formed on a side of the first functional layer and the second functional layer away from the semiconductor substrate.

2. The preparation method according to claim 1, wherein The remaining thickness of the anti-reflection layer after the step of forming an electrode structure on the side of the first functional layer and the second functional layer away from the semiconductor substrate is in a range of 20 nm to 150 nm.

3. The preparation method according to claim 2, wherein The anti-reflection layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and transparent conductive oxide.

4. The preparation method according to any one of claims 1 to 3, wherein Before sequentially forming the first functional layer and the insulating layer on the backlight surface of the semiconductor substrate, the method further includes: providing a semiconductor substrate; The light-receiving surface and the backlight surface of the semiconductor substrate are surface-polished.

5. The preparation method according to any one of claims 1 to 4, wherein The texturing of the light-receiving surface of the semiconductor substrate opposite to the backlight surface comprises: removing the insulating layer or oxide layer coated around the light-receiving surface of the semiconductor substrate opposite to the backlight surface; The semiconductor substrate is immersed in a texturing solution to form a texturing morphology on the light-receiving surface of the semiconductor substrate.

6. The preparation method according to any one of claims 1 to 5, wherein The patterned first functional layer forms a first opening, the first opening exposes the backlight surface of the semiconductor substrate, and the second functional layer is formed on a side of the patterned first functional layer away from the semiconductor substrate, comprising: forming an intrinsic amorphous silicon layer on a side of the patterned first functional layer away from the semiconductor substrate, wherein the intrinsic amorphous silicon layer contacts the semiconductor substrate through the first opening; forming a doped semiconductor layer on a side of the intrinsic amorphous silicon layer away from the semiconductor substrate; The doping type of the doped semiconductor layer in the second functional layer is opposite to the doping type of the doped semiconductor layer in the first functional layer.

7. The preparation method according to claim 6, wherein The forming of an electrode structure on a side of the first functional layer and the second functional layer away from the semiconductor substrate comprises: forming a second opening in the second functional layer, wherein an orthographic projection of the second opening on the semiconductor substrate is located within an orthographic projection of the patterned first functional layer on the semiconductor substrate, and the second opening exposes the patterned first functional layer; forming a conductive layer on a side of the second functional layer away from the semiconductor substrate; forming a third opening in the conductive layer to cut off the conductive layer, wherein the third opening is located between the first opening and the second opening; A first electrode and a second electrode are formed on a side of the conductive layer away from the semiconductor substrate, wherein the orthographic projection of the first electrode on the semiconductor substrate is located within the orthographic projection of the second opening on the semiconductor substrate, and the orthographic projection of the second electrode on the semiconductor substrate is located within the orthographic projection of the first opening on the semiconductor substrate.

8. The preparation method according to any one of claims 1 to 7, wherein The material of the insulating layer includes at least one of phosphosilicate glass or borosilicate glass, silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon, microcrystalline silicon, and polycrystalline silicon.

9. A back contact solar cell, wherein: include: A semiconductor substrate having a light-receiving surface and a backlight surface opposite to each other, wherein the backlight surface of the semiconductor substrate is a polished surface, the light-receiving surface of the semiconductor substrate is a velvet surface, and the backlight surface includes a first polarity region and a second polarity region alternately arranged along a first direction; a first polarity structure disposed in the first polarity region, the first polarity structure comprising a first passivation layer, a first doped semiconductor layer, and a first electrode structure stacked in a direction away from the semiconductor substrate, wherein a surface of the first passivation layer facing the semiconductor substrate is a polished surface; a second polarity structure disposed in the second polarity region, the second polarity structure comprising a second passivation layer, a second doped semiconductor layer, and a second electrode structure stacked in a direction away from the semiconductor substrate, wherein a surface of the second passivation layer facing the semiconductor substrate is a polished surface, and a doping type of the first doped semiconductor layer and a doping type of the second doped semiconductor layer are opposite; a tunneling oxide layer, disposed on the light-receiving surface of the semiconductor substrate; a doped polysilicon layer, disposed on a side of the tunnel oxide layer away from the semiconductor substrate; The anti-reflection layer is arranged on a side of the doped polysilicon layer away from the tunnel oxide layer.

10. The back contact solar cell according to claim 9, wherein: The thickness of the doped polysilicon layer is smaller than the thickness of the first doped semiconductor layer.

11. The back contact solar cell according to claim 10, wherein: The thickness of the tunnel oxide layer ranges from 0.5 nm to 2.5 nm, and the thickness of the doped polysilicon layer ranges from 3 nm to 100 nm.

12. The back contact solar cell according to claim 11, wherein: The first passivation layer includes tunneling oxide, and the thickness of the first passivation layer ranges from 0.5nm to 2.5nm. The first doped semiconductor layer includes doped polycrystalline silicon, and the thickness of the first doped semiconductor layer ranges from 10nm to 250nm. The second passivation layer includes intrinsic amorphous silicon, and the thickness of the second passivation layer ranges from 1nm to 15nm. The second doped semiconductor layer includes doped amorphous silicon and / or microcrystalline silicon, and the thickness of the second doped semiconductor layer ranges from 1nm to 60nm.

13. The back-contact solar cell according to any one of claims 9 to 12, wherein: The second passivation layer at least partially extends to the first polarity region, and a first orthographic projection of the first doped semiconductor layer on the semiconductor substrate at least partially overlaps with a second orthographic projection of the second passivation layer on the semiconductor substrate; There is direct contact between the first doped semiconductor layer and the second passivation layer; or, An insulating layer is provided between the first doped semiconductor layer and the second passivation layer.

14. The back-contact solar cell according to any one of claims 9 to 13, wherein: The electrode structure includes a conductive layer and an electrode, wherein the conductive layer is located on a side of the doped semiconductor layer away from the passivation layer, and the electrode is located on a side of the conductive layer away from the doped semiconductor layer; The material of the conductive layer includes at least one of zinc oxide, indium oxide and tin oxide, and the conductive layer is doped with at least one of gallium, tin, titanium, zirconium, molybdenum, cerium, fluorine, tungsten and aluminum. The thickness of the conductive layer ranges from 10nm to 150nm.

15. A battery assembly, wherein: A back-contact solar cell comprising a preparation method according to any one of claims 1-8, or a back-contact solar cell comprising a back-contact solar cell according to any one of claims 9-14.

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