Coding method, decoding method, apparatus, program product, and storage medium

Abstract

Embodiments of the present invention provide a coding method, a decoding method, an apparatus, a program product, and a storage medium. The method comprises: obtaining a first bit sequence of a transport block; dividing the first bit sequence to obtain C second bit sequences, wherein C is an integer greater than or equal to 1; separately performing polar coding on the C second bit sequences to obtain C third bit sequences; concatenating the C third bit sequences to obtain a fourth bit sequence; and sending the fourth bit sequence.

Description

Coding method, decoding method, device, program product and storage medium

[0001] This disclosure claims priority to Chinese patent application No. 202410383645.1, filed on March 29, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of communication technologies, and in particular to an encoding method, a decoding method, an apparatus, a program product, and a storage medium. Background Art

[0003] Due to their good reliability on short codes, polar codes have been adopted as the coding scheme for 5G new radio (NR) control messages in the fifth-generation mobile communication (5G) standard developed by the 3rd Generation Partnership Project (3GPP). These control messages include downlink control information (DCI) and uplink control information (UCI) in the control channel, and broadcast information carried by the physical broadcast channel (PBCH).

[0004] Summary of the Invention

[0005] Embodiments of the present disclosure provide an encoding method, a decoding method, an apparatus, a program product, and a storage medium.

[0006] In a first aspect, a coding method is provided, the method comprising:

[0007] Obtaining a first bit sequence of a transport block;

[0008] Dividing the first bit sequence to obtain C second bit sequences, where C is an integer greater than or equal to 1;

[0009] Polarization encoding is performed on the C second bit sequences respectively to obtain C third bit sequences;

[0010] Cascading the C third bit sequences to obtain a fourth bit sequence;

[0011] The fourth bit sequence is sent.

[0012] In a second aspect, a decoding method is provided, the method comprising:

[0013] receiving a signal comprising a fourth bit sequence;

[0014] Dividing the signal including the fourth bit sequence to obtain C sub-signals, where C is an integer greater than or equal to 1;

[0015] Demodulating and decoding the C sub-signals respectively to obtain C estimated values ​​of the second bit sequence;

[0016] The estimated values ​​of the C second bit sequences are concatenated to obtain the first bit sequence of the transport block.

[0017] According to a third aspect, a communication device is provided, the device comprising:

[0018] an acquiring unit, configured to acquire a first bit sequence of a transport block;

[0019] a processing unit, configured to: divide the first bit sequence to obtain C second bit sequences, where C is an integer greater than or equal to 1; perform polarization coding on the C second bit sequences respectively to obtain C third bit sequences; and concatenate the C third bit sequences to obtain a fourth bit sequence;

[0020] The sending unit is configured to send a fourth bit sequence.

[0021] According to a fourth aspect, a communication device is provided, the device comprising:

[0022] a receiving unit, configured to receive a signal including a fourth bit sequence;

[0023] A processing unit is configured to: divide a signal including a fourth bit sequence to obtain C sub-signals, where C is an integer greater than or equal to 1; demodulate and decode the C sub-signals respectively to obtain C estimated values ​​of the second bit sequence; and concatenate the C estimated values ​​of the second bit sequence to obtain a first bit sequence of the transport block.

[0024] In a fifth aspect, a communication device is provided, comprising: a processor and a memory; the memory and the processor are coupled; the memory is used to store instructions executable by the processor, and the memory stores instructions executable by the processor; when the processor is configured to execute the instructions, the communication device implements the method provided in any one of the first or second aspects above.

[0025] In a sixth aspect, a computer-readable storage medium is provided, which stores computer instructions. When the computer instructions are executed on a computer, the computer executes the method provided in either the first aspect or the second aspect.

[0026] In a seventh aspect, a computer program product comprising a computer program is provided, which, when executed on a computer, enables the computer to execute the method provided in either the first aspect or the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0028] FIG1 is a schematic structural diagram of a communication system provided by an embodiment of the present disclosure.

[0029] FIG2 is a flow chart of an encoding method provided in an embodiment of the present disclosure.

[0030] FIG3 is a schematic diagram of a polarization conversion factor diagram provided by an embodiment of the present disclosure.

[0031] FIG4 is a schematic diagram of code block segmentation provided by an embodiment of the present disclosure.

[0032] FIG5 is a gain schematic diagram provided by an embodiment of the present disclosure.

[0033] FIG6 is another schematic diagram of code block segmentation provided by an embodiment of the present disclosure.

[0034] FIG7 is another gain schematic diagram provided by an embodiment of the present disclosure.

[0035] FIG8 is a schematic diagram of another code block segmentation provided by an embodiment of the present disclosure.

[0036] FIG9 is another gain schematic diagram provided by an embodiment of the present disclosure.

[0037] FIG10 is another schematic diagram of code block segmentation provided by an embodiment of the present disclosure.

[0038] FIG11 is another gain schematic diagram provided by an embodiment of the present disclosure.

[0039] FIG12 is a flow chart of a decoding method provided in an embodiment of the present disclosure.

[0040] FIG13 is a schematic diagram showing the composition of a communication device provided in an embodiment of the present disclosure.

[0041] FIG14 is a schematic diagram showing the composition of another communication device provided in an embodiment of the present disclosure.

[0042] FIG15 is a schematic structural diagram of a communication device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of such features. Throughout this disclosure, unless otherwise specified, "plurality" means two or more.

[0046] In the embodiments of the present disclosure, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present disclosure should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in an illustrative manner.

[0047] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0048] The code length of the original polar code (also known as the mother code) is an integer power of 2. To control the encoding and decoding complexity of the polar code, 5G NR stipulates that the maximum mother code length of the original polar code is 1024 bits. Therefore, to support the flexible code length requirements of 5G NR control messages, rate matching operations are required after polar code encoding. Currently, there are three main rate matching schemes for polar codes: puncturing, shortening, and repetition. In the first two schemes, when the mother code length is greater than or equal to the target code length E, the puncturing or shortening position is determined according to preset rules, and the coded bits at the corresponding position are deleted during transmission to achieve rate matching.

[0049] Polar codes have better performance than low-density parity-check (LDPC) codes at short code lengths and are suitable for use in scenarios involving the transmission of small data packets, such as the passive Internet of Things (IoT). Since passive IoT devices have low receiving and transmitting power consumption (e.g., milliwatts or even microwatts), the device's receiving threshold needs to be set low. Therefore, ultra-low code rate (e.g., 1 / 16 or even lower) error correction coding is required to achieve reliable communication. To achieve ultra-low code rates, currently 5G polar codes can only be implemented through repetition coding due to limitations in the size of the original polar code (also known as the mother code). However, repetition coding does not have coding gain. Therefore, how to improve the coding performance of polar codes when the mother code size is limited is an urgent problem to be solved.

[0050] Based on this, embodiments of the present disclosure provide an encoding method, a decoding method, an apparatus, a program product, and a storage medium. After dividing a first bit sequence into C second bit sequences, polar coding is performed on each of the C second bit sequences. That is, each second bit sequence is independently encoded, thereby improving the coding performance of polar codes when the mother code size is limited.

[0051] The following describes the solutions of the embodiments of the present disclosure in conjunction with the accompanying drawings.

[0052] The technical solutions provided by the embodiments of the present disclosure can be applied to various mobile communication networks, for example, NR mobile communication networks using 5G, future mobile communication networks (such as 6G wireless communication systems) or multiple communication convergence systems, etc., and the embodiments of the present disclosure are not limited to this.

[0053] Figure 1 is a schematic diagram of the structure of a communication system provided by an embodiment of the present disclosure. As shown in Figure 1, the communication system includes, but is not limited to, a first node 110 and a second node 120. Specifically, the first node 110 and the second node 120 can transmit and receive wireless signals, and perform related interactions.

[0054] In a wireless communication scenario, a first node 110 and a second node 120 communicate via a wireless channel. For example, the first node 110 is a terminal and the second node 120 is a base station, and the terminal and the base station communicate via a wireless channel. In another example, the first node 110 is a terminal and the second node 120 is a wireless router, and the wireless router and the terminal communicate via a wireless channel. In another example, the first node 110 is a first base station and the second node 120 is a second base station, and the first base station and the second base station communicate via a wireless channel. In another example, the first node 110 is a first terminal and the second node 120 is a second terminal, and the first terminal and the second terminal communicate via a wireless channel. In another example, the first node 110 is a repeater and the second node 120 is a base station, and the base station and the repeater communicate via a wireless channel. In another example, the first node 110 is a terminal and the second node 120 is a repeater, and the repeater and the terminal communicate via a wireless channel. For another example, the first node 110 is a first relay, the second node 120 is a second relay, and the first relay and the second relay communicate via a wireless channel. For another example, the first node 110 is a base station, the second node 120 is a satellite, and the satellite and the base station communicate via a wireless channel. For another example, the first node 110 is a satellite, the second node 120 is a base station, and the base station and the satellite communicate via a wireless channel. For another example, the first node 110 is a terminal, the second node 120 is a satellite, and the satellite and the terminal communicate via a wireless channel. For another example, the first node 110 is a satellite, the second node 120 is a terminal, and the terminal and the satellite communicate via a wireless channel. For another example, the first node 110 is a ground device, the second node 120 is an aircraft, and the aircraft and the ground device communicate via a wireless channel. For another example, the first node 110 is a first aircraft, the second node 120 is a second aircraft, and the first aircraft and the second aircraft communicate via a wireless channel.

[0055] In the embodiment of the present disclosure, the first node and the second node may also have other names. For example, the first node may also be called a first communication node, and the second node may also be called a second communication node, etc. The embodiment of the present disclosure does not limit this.

[0056] In some embodiments, the base station may be any of an evolution nodeB (eNB), a next generation nodeB (gNB), a transmission receive point (TRP), a transmission point (TP), and some other access node. Depending on the size of the service coverage area provided, base stations can be further divided into macro base stations for providing macro cells, micro base stations for providing pico cells, and femto base stations for providing femto cells. With the continuous evolution of wireless communication technology, future base stations may also adopt other names.

[0057] The terminal may be a device with wireless transceiver capabilities, such as a mobile phone, tablet computer, wearable device, vehicle-mounted device, augmented reality (AR) / virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), etc. The embodiments of the present disclosure do not limit the specific type of terminal.

[0058] It should be understood that FIG1 is an exemplary structural diagram, and the number of devices included in the communication system shown in FIG1 is not limited. For example, the number of first nodes and second nodes is not limited. Furthermore, in addition to the devices shown in FIG1 , the communication system shown in FIG1 may also include other devices, which is not limited.

[0059] Next, as shown in FIG2 , an embodiment of the present disclosure provides an encoding method, which is applied to an encoding end. The encoding end may be the first node or the second node shown in FIG1 , that is, the encoding end may be a base station or a terminal, which is not limited in the embodiment of the present disclosure. The method includes the following steps:

[0060] S101. Obtain a first bit sequence of a transport block.

[0061] The first bit sequence may be referred to by other names, such as an original bit sequence, which is not limited.

[0062] S102: Divide the first bit sequence to obtain C second bit sequences.

[0063] C is an integer greater than or equal to 1.

[0064] In some embodiments, dividing the first bit sequence to obtain C second bit sequences may be performed by performing code block segmentation on the first bit sequence to obtain the C second bit sequences.

[0065] In some embodiments, when the first bit sequence satisfies a preset condition, the first bit sequence is divided to obtain C second bit sequences. The preset condition includes at least one of the following:

[0066] Condition 1: The number of bits in the first bit sequence is greater than or equal to a first number threshold, and the transmission length of the fourth bit sequence is greater than or equal to a transmission length threshold.

[0067] The number of bits in the first bit sequence can be understood as the size of the transport block. The transmission length of the fourth bit sequence represents the number of bits or the length of time required to transmit a complete data block during communication. The transmission length of the fourth bit sequence can be obtained when the first bit sequence of the transport block is obtained. The fourth bit sequence is the bit sequence to be transmitted after processing the first bit sequence. That is, after obtaining the first bit sequence of the transport block, the encoder can obtain the transmission length of the fourth bit sequence. For an example description of the fourth bit sequence, refer to the corresponding description in step S104 below and are not repeated here.

[0068] Condition 2: The number of bits in the first bit sequence is greater than or equal to a second number threshold.

[0069] The first number threshold is less than the second number threshold; the first number threshold, the second number threshold, and the transmission length threshold may be preconfigured. For example, the first number threshold is 360, the second number threshold is 1013, and the transmission length threshold is 1088. That is, assuming that the number of bits of the first bit sequence is A and the transmission length of the fourth bit sequence is G, when A ≥ 360 and G ≥ 1088, or when A ≥ 1013, the first bit sequence is divided to obtain C second bit sequences.

[0070] Condition 3: A first indication signaling is received, and the value of the first indication signaling is a specific value.

[0071] The first indication signaling may be uplink control information, downlink control information, or broadcast information. For example, when the first indication signaling includes a code block division number value of 2, the first bit sequence is divided to obtain C = 2 second bit sequences; when the first indication signaling includes a code block division number value of 3, the first bit sequence is divided to obtain C = 3 second bit sequences. In this way, when the first indication signaling is received and the first indication signaling value is a specific value, the first bit sequence is divided. The number of code blocks can be pre-designed for different usage scenarios, which can improve performance and reduce the calculation of the transmitting device.

[0072] Condition 4: The information type of the information included in the first bit sequence is a specific information type.

[0073] The specific information type can be data information such as synaesthesia information, temperature information, and pressure information, or control information such as uplink control information, downlink control information, or broadcast information. When the specific information type is numerical information, the first bit sequence is divided to obtain C = 2 second bit sequences; when the specific information type is control information, the first bit sequence is divided to obtain C = 1 second bit sequence. In this way, the number of code blocks can be pre-designed for different usage scenarios, which can improve performance and reduce the computation of the transmitter.

[0074] Condition 5: The channel corresponding to the first bit sequence is a specific channel.

[0075] A specific channel can be an uplink control channel, a downlink control channel, or a broadcast channel. For example, when the specific channel is a broadcast channel, the first bit sequence is divided to obtain C = 1 second bit sequence; when the specific channel is an uplink control channel, the first bit sequence is divided to obtain C = 3 second bit sequences; when the specific channel is a downlink control channel, the first bit sequence is divided to obtain C = 2 second bit sequences. The advantage of this design is that the optimal number of code blocks can be pre-designed for different usage scenarios, improving performance and reducing the computational effort of the transmitter.

[0076] Condition 6: The number of bits in the first bit sequence belongs to the first set.

[0077] The first set may be preconfigured. For example, when the number of bits in the first bit sequence belongs to the set {24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 208, 224, 240, 256, 272, 288, 304, 320, 336, 352}, the first bit sequence is divided to obtain C=1 second bit sequence. For another example, when the number of bits in the first bit sequence belongs to the set {368, 384, 408, 432, 456, 480, 504, 528, 552, 576, 608, For example, when the number of bits in the first bit sequence belongs to the set {640,672,704}, the first bit sequence is divided to obtain C=2 second bit sequences; for another example, when the number of bits in the first bit sequence belongs to the set {736,768,808,848,888,928,984,1032}, the first bit sequence is divided to obtain C=3 second bit sequences; for another example, when the number of bits in the first bit sequence belongs to the set {1064,1128,1160,1192,1224,1256,1288,1320,1352,1416,1480,1544,1608,1672,1706}, the first bit sequence is divided to obtain C=4 second bit sequences.

[0078] Condition 7: The number of bits in the encoded first bit sequence is greater than or equal to a third number threshold.

[0079] The third number threshold may be preconfigured. For example, the third number threshold is 4548. That is, assuming that the number of bits in the encoded first bit sequence is E, then when E ≥ 4548, the first bit sequence is divided to obtain C = 2 second bit sequences. For another example, the third number threshold is 8964. That is, assuming that the number of bits in the encoded first bit sequence is E, then when E ≥ 8964, the first bit sequence is divided to obtain C = 3 second bit sequences. For another example, the third number threshold is 12900. That is, assuming that the number of bits in the encoded first bit sequence is E, then when E ≥ 12900, the first bit sequence is divided to obtain C = 4 second bit sequences.

[0080] Condition 8: The number of bits in the encoded first bit sequence belongs to the second set.

[0081] The second set may be preconfigured. For example, if the number of bits in the encoded first bit sequence belongs to the set {4548, 4740, 5028, 5316, 5604, 5892, 6180, 6468, 6756, 7044, 7428, 7812, 8196, 8580}, the first bit sequence is divided to obtain C = 2 second bit sequences. For another example, if the number of bits in the encoded first bit sequence belongs to the set {8964, 9348, 9828, 10308, 10788, 11268, 11940, 12516}, the first bit sequence is divided to obtain C = 3 second bit sequences. For another example, when the number of bits of the encoded first bit sequence belongs to the set {12900, 13668, 14052, 14436, 14820, 15204, 15588, 15972, 16356, 17124, 17892, 18660, 19428, 20196, 20604}, the first bit sequence is divided to obtain C=4 second bit sequences.

[0082] The encoded first bit sequence may be the following third bit sequence. For the description of the third bit sequence, reference may be made to the corresponding description in the following step S103 and will not be repeated here.

[0083] In some embodiments, the number C of second bit sequences may be determined first, and then the first bit sequence may be divided based on the number C of second bit sequences to obtain C second bit sequences. The number C of second bit sequences may be determined based on at least one of the following:

[0084] Q first number thresholds, Q transmission length thresholds, X second number thresholds, the number of bits of the first bit sequence, and the transmission length of the fourth bit sequence, where Q and X are both positive integers.

[0085] As an example, a code rate can be determined based on the number of bits in the first bit sequence and the transmission length of the fourth bit sequence, and then the number C of second bit sequences can be determined based on the number of bits in the first bit sequence, the code rate, and a first preset corresponding relationship. The first preset corresponding relationship is the correspondence between the number of bits in the first bit sequence, the code rate, and the number C of second bit sequences. The code rate is the ratio of the number of bits in the first bit sequence to the transmission length of the fourth bit sequence. For example, if the code rate is R, the number of bits in the first bit sequence is A, and the transmission length of the fourth bit sequence is G, then R = A / G.

[0086] As a possible example, the first preset correspondence is a table with Q+2 rows and S+2 columns, wherein each row of the table corresponds to a division of the range of the number of bits of a first bit sequence, and each column of the table corresponds to a division of the range of the bit rate. The table is composed of the first number threshold 0 <A1<A2<...<A Q and bitrate threshold 0 <R1<R2<...<R S <1 OK; C in the table i,j That is the number of the second bit sequence, C i,j is a positive integer, S+1 is the number of bit rate intervals, and S is a positive integer. For example, the first preset correspondence relationship can be shown in the following Table 1:

[0087] Table 1

[0088] With S=14, R1=1 / 12, R2=1 / 10, R3=1 / 8, R4=1 / 6, R5=1 / 5, R6=1 / 4, R7=1 / 3, R8=2 / 5, R9=1 / 2, R 10 =2 / 3, R 11 =3 / 4, R 12 =4 / 5, R 13 =5 / 6, R 14 =8 / 9; S=21, A1=320, A2=336, A3=384, A4=480, A5=504, A6=528, A7=576, A8=608, A9=640, A 10 =704, A 11 =768, A 12 =808,A 13 =848, A 14 =888, A 15 =928, A 16 =984, A 17 =1160, A 18 =1128,A 19 =1352,A 20 =1416,A 21 =1608 as an example, the first preset correspondence relationship may be as shown in Table 2 below:

[0089] Table 2

[0090] After the code rate is determined, the number C of the second bit sequences may be determined based on the code rate, the number of bits of the first bit sequence, and Table 2 above.

[0091] As another example, a bit number set corresponding to the number of bits in the first bit sequence can be determined based on the second preset correspondence between the number of bits in the first bit sequence and the second preset correspondence, and then the number C of the second bit sequence can be determined based on the bit number set and the third correspondence. The second preset correspondence is the correspondence between the number of bits in the first bit sequence and the bit number set, and the third preset correspondence is the correspondence between the bit number set and the number C of the second bit sequence. That is, multiple bit number sets are predefined, each number of bits in the first bit sequence corresponds to a bit number set, and each bit number set corresponds to the number C of the second bit sequence. Based on the number of bits in the first bit sequence and the second preset correspondence, the corresponding bit number set is determined, and based on the third correspondence between the bit number set and the number C of the second bit sequence, the number C of the second bit sequence is determined.

[0092] After the number C of second bit sequences is determined, the first bit sequence may be divided based on the number C of second bit sequences to obtain C second bit sequences.

[0093] As an example, when the number of bits in the first bit sequence is an integer multiple of the number C of the second bit sequence, the first bit sequence is divided based on the number C of the second bit sequences to obtain C second bit sequences. For example, the first bit sequence is a=[a0, a1, ..., a A-1 ], then a is divided into blocks to obtain C second bit sequences c0, c1, ..., c C-1 , where the length of each second bit sequence is

[0094] As another example, when the number of bits in the first bit sequence is not an integer multiple of the number C of the second bit sequences, the first bit sequence is padded with zeros to obtain a first bit sequence after the zero-padded operation; and the first bit sequence after the zero-padded operation is divided based on the number C of second bit sequences to obtain C second bit sequences.

[0095] The first bit sequence is padded with zeros to obtain the first bit sequence after the zero-padded operation. The zero-padded operation may be performed at the beginning of the first bit sequence to obtain the first bit sequence after the zero-padded operation; or the zero-padded operation may be performed at the end of the first bit sequence to obtain the first bit sequence after the zero-padded operation.

[0096] For example, the first bit sequence is a=[a0,a1,...,a A-1], when the number of bits A in the first bit sequence is not an integer multiple of the number C in the second bit sequence, add A'-A bits "0" before the starting position of the first bit sequence a, and obtain a'=[a'0,a'1,...,a' A’-1 ],in, A′ is the number of bits in the first bit sequence after the zero-padding operation. For example, the pseudo code may be as follows:

[0097] For i=0to A'-A-1

[0098] a' i =0;

[0099] End

[0100] For i=A'-A to A'-1

[0101] a' i =a i-(A’-A) ;

[0102] End.

[0103] For example, in the first bit sequence a=[a0,a1,...,a A-1 ] Add A'-A bits of "0" to the end of the position, and get the first bit sequence after the zero-padding operation a'=[a'0,a'1,...,a' A’-1 ]=[a0,a1,...,a A-1 ,0,0,...,0]. Then a' is divided into blocks to obtain C second bit sequences c0,c1,...,c C-1 , where the length of each second bit sequence is

[0104] S103. Perform polarization coding on the C second bit sequences respectively to obtain C third bit sequences.

[0105] Polar coding includes at least one of the following: adding frozen bits, polarization transform, and rate matching.

[0106] In polar coding, frozen bits are bits known to both the sender and receiver. Frozen bits do not transmit information during the coding process.

[0107] The main purpose of polarization conversion is to transform the original channel in such a way that the capacity of the resulting virtual subchannels exhibits polarized differentiation. For example, one segmented channel will approach a perfect channel (a noise-free state with a capacity approaching 1), while another segmented channel may exhibit poor performance. Polarization coding, through polarization conversion, can transform the original channel into subchannels with varying degrees of reliability, thereby more efficiently utilizing channel resources and improving communication reliability and efficiency.

[0108] Rate matching is used to adjust the bit rate of the polar code to match the specific physical channel capacity or transmission requirements.

[0109] In some embodiments, rate matching includes sub-block interleaving and bit selection.

[0110] Sub-block interleaving is used to combat sudden errors in the channel. Sub-block interleaving divides the original data bit stream into multiple smaller sub-blocks and then rearranges these sub-blocks according to a predetermined pattern. This allows errors to be dispersed across different sub-blocks rather than concentrated in a single, continuous area. This helps subsequent decoders detect and correct errors more accurately.

[0111] Bit selection determines which bits should be used in a particular modulation symbol. In digital modulation, the original data bit stream is mapped onto a specific modulation symbol, such as binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), or higher-order modulation schemes. The bit selection process involves selecting the appropriate number of bits from the original data bit stream to form a modulation symbol, based on the selected modulation scheme.

[0112] In some embodiments, the added frozen bits are determined based on at least the value of C. For example, when C = 1, all added frozen bits are bits "0." For another example, when C = 2, the frozen bits of polarization subchannels with odd indexes are bits "1," and the frozen bits of polarization subchannels with even indexes are bits "0."

[0113] In some embodiments, polar coding includes adding frozen bits and polarization transformation.

[0114] In some embodiments, polar coding includes adding frozen bits, polarization conversion, and rate matching.

[0115] In some embodiments, the lengths of the C third bit sequences are all the same.

[0116] Taking polar coding including adding frozen bits and polarization conversion as an example, assuming that the C bit sequences are r=0,1,...,C-1, for c r Polar coding including the two steps of "adding frozen bits and polarization conversion" is performed to obtain C third bit sequences e r , e r The length is E r And E0=E1=...=E C-1 Among them, e r is the polarization conversion codeword d r =u r ·G N , that is, e r =u r ·G N ,u r By c r As input, add frozen bits to get G N Represents polarization transformation.

[0117] Taking polar coding including adding frozen bits, polarization conversion and rate matching as an example, assuming that the C bit sequences are r=0,1,...,C-1, for c r Polar coding including the three steps of “adding frozen bits, polarization conversion and rate matching” is performed to obtain C third bit sequences e r , e r The length is E r And E0=E1=...=E C-1 .

[0118] In some embodiments, the length of at least one third bit sequence among the C third bit sequences is different from the lengths of the other third bit sequences.

[0119] Taking polar coding including adding frozen bits and polarization conversion as an example, assuming that the C second bit sequences are r=0,1,...,C-1, for c r Polar coding including the two steps of "adding frozen bits and polarization conversion" is performed to obtain C third bit sequences e r , where e r is the polarization conversion codeword d r =u r ·G N , that is, e r =u r ·G N ,u r By c r As input, add frozen bits to get G N Represents polarization transformation. e r The length is E rAnd there exist i, j such that E i ≠E j For example, when E=3002 and C=3, E0=E1=1001 and E2=1000; for another example, when E=3002 and C=3, E0=1000 and E1=E2=1001.

[0120] Taking polar coding including adding frozen bits, polarization conversion and rate matching as an example, assuming that C second bit sequences are r=0,1,...,C-1, for c r Polar coding including the three steps of “adding frozen bits, polarization conversion and rate matching” is performed to obtain C third bit sequences e r , e r The length is E r And there exist i, j such that E i ≠E j For example, when E=3002 and C=3, E0=E1=1001 and E2=1000; for another example, when E=3002 and C=3, E0=1000 and E1=E2=1001.

[0121] In some embodiments, the third bit sequence may also have other names, for example, the encoded first bit sequence, which is not limited.

[0122] The above example directly performs polarization coding on each of the C second bit sequences to obtain C third bit sequences. As a possible example, to implement data error detection and correction functions and improve data transmission reliability, after obtaining the C second bit sequences, L cyclic redundancy check (CRC) bits can be added to each of the C second bit sequences to obtain C sixth bit sequences. Polarization coding is then performed on each of the C sixth bit sequences to obtain C third bit sequences, where L is a positive integer.

[0123] In some embodiments, the frozen bits of each sixth bit sequence are generated independently, or the frozen bits of C sixth bit sequences are generated jointly. In other words, the frozen bits of each sixth bit sequence can be generated independently or jointly with other sixth bit sequences.

[0124] S104: Concatenate C third bit sequences to obtain a fourth bit sequence.

[0125] The fourth bit sequence may also be called by other names, for example, a cascade sequence, which is not limited.

[0126] As an example, after obtaining C third bit sequences, the C third bit sequences can be concatenated to obtain a fourth bit sequence. For example, the C third bit sequences are e=e0, e1, ..., e C-1 For example, for e=e0,e1,...,e C-1 The length obtained by cascading is E=E0+E1+...+E C-1 The fourth bit sequence g=[e0,e1,...,e C-1 ].

[0127] The above example is one method of concatenating C third bit sequences to obtain a fourth bit sequence. As another example, after obtaining the C third bit sequences, channel interleaving can be performed on each of the C third bit sequences to obtain C fifth bit sequences, which are then concatenated to obtain a fourth bit sequence. The fifth bit sequence may also be referred to by other names, such as an interleaved bit sequence, without limitation.

[0128] Let C third bit sequences be e=e0,e1,...,e C-1 For example, for e r Channel interleaving is performed to obtain the fifth bit sequence f r , r is an integer less than or equal to C-1. As a possible example, determine f r The pseudo code can be shown as follows:

[0129] Let T be such that T(T+1) / 2≥E r The smallest positive integer, where T is the channel interleaver parameter, E r is a third bit sequence e r The number of bits.

[0130] e r,k is the kth bit of the rth third bit sequence.

[0131] As another possible example, f r It can be determined based on:

[0132]

[0133] f r,i is the i-th bit of the r-th fifth bit sequence in the C fifth bit sequences, that is, the i-th bit of the r-th fifth bit sequence is composed of the third bit sequence e r P i bits are determined, where P = [P0, P1, ..., P Er-1] is the channel interleaving pattern of channel interleaving. Channel interleaving pattern P=[P0,P1,...,P Er-1 ] can be the sequence [0,1,2,...,E r ] can be rearranged as desired. For example, the i-th element P of the channel interleaving pattern i and i satisfy the following formula: P i =mod(f1·i+f2·i 2 ,Er);

[0134] Where mod(a,b) represents the remainder when a is divided by b, and f1 and f2 are interleaving parameters. The interleaving parameters f1 and f2 for different Er can be shown in Table 3 below.

[0135] Table 3

[0136] As a possible example, when E r When =8, the channel interleaving pattern P=[P0,P1,P2,P3,P4,P5,P6,P7]=[5,4,7,1,6,0,2,3].

[0137] S105. Send a fourth bit sequence.

[0138] Based on the embodiment shown in FIG. 2 , after the first bit sequence is divided into multiple second bit sequences, polar coding is performed on each of the C second bit sequences. That is, each second bit sequence is independently encoded. This improves the coding performance of the polar code when the mother code size is limited.

[0139] The following describes an encoding method provided by an embodiment of the present disclosure with reference to an example.

[0140] Assuming that the number of bits of the first bit sequence of the transport block is A and the transmission length of the fourth bit sequence is G, the preset conditions may be as follows:

[0141] When A≥360 and G≥1088, or when A≥1013, code block segmentation is performed, for example, segmentation into 2 code blocks, that is, the number of second bit sequences C=2.

[0142] Otherwise, code block segmentation is not performed, that is, the number of second bit sequences C=1.

[0143] Let the first bit sequence of the transport block be a = [a0, a1, ..., a A-1 ], the code block segmentation operation is as follows:

[0144] Zero padding operation: When A is not an integer multiple of C, add A'-A 0 bits before the start position or after the end position of the first bit sequence a, and get a'=[a'0,a'1,...,a' A’-1 ],in,

[0145] Block operation: Each consecutive A′ / C bits in a′ is a code block, that is, a second bit sequence.

[0146] After obtaining C second bit sequences, L CRC bits can be added to each second bit sequence to obtain C sixth bit sequences. Let the rth sixth bit sequence be c r =[c r,0 ,c r,1 ,...,c r,K-1 ], where K = A' / C + L, and L CRC bits can be obtained based on the following pseudo code:

[0147] Use the CRC polynomial g CRC(D) Calculate sequence c r,0 ,c r,1 ,...,cr,(A' / C-1) of L CRC bits p r,0 ,p r,1 ,...,p r,(L-1) .

[0148] For k=A' / C to A' / C+L-1

[0149] c r,k =p r , k- A' / C;

[0150] End.

[0151] When 12≤A≤19, g CRC(D) =g CRC6(D) =D 6 +D 5 +1; when A>19, g CRC(D) =g CRC11(D) =D 11 +D 10 +D 9 +D 5 +1; the value of A is not greater than 1706.

[0152] After obtaining C sixth bit sequences, polar coding can be performed on the C sixth bit sequences. Taking polar coding including adding frozen bits, polarization conversion and rate matching as an example, for example, let b = [b0, b1, ..., b K-1] is the sixth information sequence of length K=A' / C+L, where L is the number of CRC bits, N=2 n is the size of the polarization matrix, Q is the information bit index set (a subset of the set of integers {0, 1, 2, ..., N-2, N-1} of size K), where n is an integer greater than 0, b = [b0, b1, ..., b K-1 ]=c r =[c r,0 ,c r,1 ,...,c r,K-1 ] is the sixth bit sequence after division and addition of CRC bits. The sixth bit sequence b is encoded into a third bit sequence of length E, e=[e0,e1,...,e E-1 ] of length N codeword d=[d0,d1,...,d N-1 The encoding process of ] is as follows:

[0153] (1) Add frozen bits: Select appropriate subchannels for carrying data and placing frozen bits, and add the frozen bits to the sixth bit sequence b = [b0, b1, ..., b K-1 ]Add NK frozen bits to get the sequence u=[u0,u1,...,u N-1 ], the pseudo code can be as follows:

[0154] (2) Polarization transformation: transform the sequence u into the polarization matrix G with N rows and N columns. N Multiplying on GF(2) yields the codeword d = u·G N ,in, G N Representing polarization transformation, illustratively, taking N=16 as an example, FIG3 is a schematic diagram of a polarization transformation factor diagram provided by an embodiment of the present disclosure.

[0155] (3) Rate matching: Rate matching includes two steps: sub-block interleaving and bit selection. Sub-block interleaving includes: interleaving the codeword d with a length of N to output the bit sequence y = [y0, y1, ..., y N-2 ,y N-1 ], can be determined by the sub-block interleaver pattern π of length 32, the codeword d, and the polarization code matrix size N in the following manner:

[0156] π=[π0,π1,π2,π3,π4,π5,π6,π7,π8,π9,π 10 ,π 11 ,π 12 ,π 13 ,π 14 ,π15 , π 16 , π 17 , π 18 , π 19 , π 20 , π 21 , π 22 , π 23 , π 24 , π 25 , π 26 , π 27 , π 28 , π 29 , π 30 , π 31 = [0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31], J = [J0, J1, ..., J N-2 , J N-1 is an interleaver pattern of length N. The interleaver pattern J is a rearrangement of the integer sequence [0, 1, 2, ..., N - 2, N - 1].

[0157] Bit selection includes:

[0158] There are three types of bit selection in 5G polar coding, namely repetition, puncturing, and shortening. Given the fifth bit sequence y, the length K of the sixth bit sequence, the number of bits E = Er of a third bit sequence, and the size N of the polar code matrix, a third bit sequence e is obtained in the following way.

[0159] Repetition: When E ≥ N, e k = y mod(k,N) , k = 0, 1, 2, ..., E - 2, E - 1;

[0160] Puncturing: When E < N and K / E ≤ 7 / 16, e k = y N-E+k , k = 0, 1, 2, ..., E - 2, E - 1;

[0161] Shortening: When E < N and K / E > 7 / 16, e k = y k , k = 0, 1, 2, ..., E - 2, E - 1.

[0162] After obtaining C third bit sequences, the C third bit sequences can be concatenated to obtain a fourth bit sequence, and then the fourth bit sequence is transmitted.

[0163] The following example illustrates how to determine the number C of second bit sequences based on Q first number thresholds, Q transmission length thresholds, X second number thresholds, the number A of bits of the first bit sequence, and the transmission length G of the fourth bit sequence.

[0164] Exemplarily, the Q first number thresholds include A1, A2, ..., A Q , Q sending length thresholds include G1, G2, ..., G Q , X second number thresholds include A'1, A'2, ..., A' X , where 0 <A1<A2<...<A Q-1 Q , 0 <G1<G2<...<G Q-1 <G Q , 0 <A’1<A’2<...<A’ X .

[0165] Taking Q=X+1 as an example, the pseudo code for determining the number C of second bit sequences may be as follows:

[0166] Taking Q=3, X=2 as an example, the following situations may be included:

[0167] When A≥A3 and G≥G3, determine C=4;

[0168] Otherwise, when A≥A2 and G≥G2, or A≥A'2, determine C=3;

[0169] Otherwise, when A≥A1 and G≥G1, or A≥A'1, determine C=2;

[0170] Otherwise, determine C = 1,

[0171] Among them, A3>A2>A1>0 is the first number threshold, G3>G2>G1>0 is the sending length threshold, and A'2>A'1>0 is the second number threshold.

[0172] For example, A3=1064, A2=720, A1=360, A'2=1480, A'1=1013, G3=4288, G2=2944, G1=1088, the pseudo code for determining C can be as follows:

[0173] ​As shown in Figure 4, a schematic diagram of code block segmentation is provided for an embodiment of the present disclosure, and as shown in Figure 5, a schematic diagram of gain is provided for an embodiment of the present disclosure. Figure 4 shows a schematic diagram of the number of blocks when Q=3, X=2, and Figure 5 shows a schematic diagram of gain under different combinations of the number of bits A of the first bit sequence and the code rate R=(A+L) / G relative to 5G code block segmentation when Q=3, X=2. It can be seen from Figure 5 that the new block maintains the performance of the 5G block while bringing significant gain when the number of bits in the first bit sequence A≥736, with the highest gain close to 2dB. Here, the definition of the code rate R is only for this example and does not affect the specific block operation.

[0174] Taking Q=2, X=1 as an example, the following situations may be included:

[0175] When A≥A2 and G≥G2, determine C=3;

[0176] Otherwise, when A≥A1 and G≥G1, or A≥A'1, determine C=2;

[0177] Otherwise, determine C = 1,

[0178] Among them, A2>A1>0 is the first number threshold, G2>G1>0 is the sending length threshold. A'1>0 is the second number threshold. For example, A2=720, A1=360, A'1=1013, G2=2944, G1=1088, the pseudo code for determining C can be as follows:

[0179] Take Q=4, X=2 as an example, where [A1, A2, A3, A4]=[360, 720, 1064, 1256], [G1, G2, G3, G4]=[1088, 2944, 4288, 6336], [A'1, A'2]=[1013, 1480],

[0180] As shown in Figure 6, another schematic diagram of code block segmentation is provided in an embodiment of the present disclosure, and as shown in Figure 7, another schematic diagram of gain is provided in an embodiment of the present disclosure. Figure 6 shows a schematic diagram of the number of blocks when Q = 4, X = 2, and Figure 7 shows a schematic diagram of the gain of a code block segmentation under different combinations of the number of bits A of the first bit sequence and the code rate R = (A + L) / G when Q = 4, X = 2 relative to 5G. Referring to Figure 7, when the number of bits A in the first bit sequence is ≥ 736, a significant gain is achieved, with the highest gain exceeding 2dB. Based on this, the pseudo code for determining C can be as follows:

[0181] Taking Q=5 and X=2 as an example, where [A1, A2, A3, A4, A5]=[360, 720, 1064, 1224, 1256], [G1, G2, G3, G4, G5]=[1088, 2944, 4288, 4940, 6336], and [A'1, A'2]=[1013, 1480], as shown in FIG8 , which is another code block segmentation schematic diagram provided in an embodiment of the present disclosure, and FIG9 , which is another gain schematic diagram provided in an embodiment of the present disclosure. FIG8 is a schematic diagram showing the number of blocks when Q=5 and X=2. FIG9 is a schematic diagram showing the gain of 5G code block segmentation under different combinations of the number of bits A in the first bit sequence and the code rate R=(A+L) / G when Q=5 and X=2. Referring to FIG9 , when the number of code blocks in the first bit sequence A≥736, a significant gain is achieved, with the highest gain exceeding 2 dB. Based on this, the pseudo code for determining C can be shown as follows:

[0182] Still taking Q=5, X=2 as an example, as shown in Figure 10, another code block segmentation schematic diagram provided by an embodiment of the present disclosure is shown in Figure 11, another gain schematic diagram provided by an embodiment of the present disclosure is shown. Figure 10 shows a schematic diagram of the number of blocks when Q=5, X=2, and Figure 11 shows a schematic diagram of the gain of a 5G code block segmentation under different combinations of the number of bits A in the first bit sequence and the code rate R=(A+L) / G when Q=5, X=2. Referring to Figure 11, when the number of code blocks in the first bit sequence A≥736, a significant gain is achieved, with the highest gain exceeding 2dB. Based on this, the pseudo code for determining C can be as follows:

[0183] The above example is described using the example of Q being greater than X. The following example is described using the example of Q being equal to X. When Q is equal to X, the pseudo code for determining the number C of second bit sequences may be as follows:

[0184] For example, when Q=3, the following situations may be included:

[0185] When A≥A3 and G≥G3, or A≥A'3, determine C=4;

[0186] Otherwise, when A≥A2 and G≥G2, or A≥A'2, determine C=3;

[0187] Otherwise, when A≥A1 and G≥G1, or A≥A'1, determine C=2;

[0188] Otherwise, determine C = 1,

[0189] Among them, A3>A2>A1>0 is the first number threshold, G3>G2>G1>0 is the transmission length threshold. A'3>A'2>A'1>0 is the second number threshold. For example, A3=1064, A2=720, A1=360, A'3=1920, A'2=1480, A'1=1013, G3=4288, G2=2944, G1=1088. The pseudo code for determining the number C of the second bit sequence can be as follows:

[0190] For example, when Q=2, the following situations may be included:

[0191] When A≥A2 and G≥G2, or A≥A'2, determine C=3;

[0192] Otherwise, when A≥A1 and G≥G1, or A≥A'1, determine C=2;

[0193] Otherwise, determine C = 1,

[0194] Where A2>A1>0 is the first number threshold, G2>G1>0 is the sending length threshold. A'2>A'1>0 is the second number threshold. For example, A2=720, A1=360, A'2=1480, A'1=1013, G2=2944, G1=1088. The pseudo code for determining the number C of the second bit sequence can be as follows:

[0195] In some embodiments, as shown in FIG12 , an embodiment of the present disclosure further provides a decoding method, which is applied to a decoding end, and the decoding end may be a node other than the encoding end, in the first node or the second node shown in FIG1 . The method includes the following steps:

[0196] S201. Receive a signal including a fourth bit sequence.

[0197] For the description of the fourth bit sequence, reference may be made to the corresponding description in the example shown in FIG2 , and details thereof will not be repeated here.

[0198] S202: Divide the signal including the fourth bit sequence to obtain C sub-signals.

[0199] C is an integer greater than or equal to 1.

[0200] In some embodiments, a sub-signal includes a third bit sequence. For the description of the third bit sequence, reference may be made to the corresponding description in the example shown in FIG. 2 , and details are omitted here.

[0201] S203 : Demodulate and decode the C sub-signals respectively to obtain C estimated values ​​of the second bit sequences.

[0202] For the description of the second bit sequence, reference may be made to the corresponding description in the example shown in FIG2 , and details will not be repeated here.

[0203] S204: Concatenate the estimated values ​​of the C second bit sequences to obtain a first bit sequence of the transport block.

[0204] For the description of the first bit sequence, reference may be made to the corresponding description in the example shown in FIG2 , and details will not be repeated here.

[0205] Based on the embodiment shown in FIG. 12 , after dividing the signal including the fourth bit sequence into multiple sub-signals, each of the C sub-signals is demodulated and decoded. That is, each sub-signal is independently demodulated and decoded. This improves polar code decoding performance when the mother code size is limited.

[0206] The above mainly introduces the solution provided by the present disclosure from the perspective of the interaction between the encoding end and the decoding end. It can be understood that each node, such as the encoding end or the decoding end, includes a hardware structure and / or software module corresponding to the execution of each function in order to realize the above functions. Those skilled in the art should easily realize that, in combination with the algorithm steps of each example described in the embodiments disclosed herein, the present disclosure can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present disclosure.

[0207] FIG13 is a schematic diagram showing the composition of a communication device provided by an embodiment of the present disclosure. As shown in FIG13 , the communication device 30 includes an acquiring unit 301 , a processing unit 302 , and a sending unit 303 .

[0208] The communication device 30 may be the above-mentioned encoding end or a chip in the encoding end. When the communication device 30 is used to implement the functions of the encoding end in the above-mentioned embodiment, each unit may be used to implement the following functions.

[0209] An acquiring unit 301 is configured to acquire a first bit sequence of a transport block;

[0210] The processing unit 302 is configured to: divide the first bit sequence to obtain C second bit sequences, where C is an integer greater than 1 or equal to 1; perform polar coding on the C second bit sequences to obtain C third bit sequences; and concatenate the C third bit sequences to obtain a fourth bit sequence.

[0211] The sending unit 303 is configured to send a fourth bit sequence.

[0212] In some embodiments, the processing unit 302 may be configured to divide the first bit sequence to obtain C second bit sequences when the first bit sequence meets a preset condition.

[0213] In some embodiments, the processing unit 302 may be configured to: determine the number C of second bit sequences; and divide the first bit sequence based on the number C of second bit sequences to obtain C second bit sequences.

[0214] In some embodiments, the processing unit 302 can be used to: determine the code rate based on the number of bits of the first bit sequence and the transmission length of the fourth bit sequence; determine the number C of second bit sequences based on the number of bits of the first bit sequence, the code rate, and a first preset correspondence; wherein the first preset correspondence is the correspondence between the number of bits of the first bit sequence, the code rate, and the number C of second bit sequences.

[0215] In some embodiments, the processing unit 302 can be used to: determine a bit number set corresponding to the bit number of the first bit sequence based on the number of bits of the first bit sequence and a second preset correspondence; the second preset correspondence is the correspondence between the number of bits of the first bit sequence and the bit number set; determine the number C of the second bit sequence based on the bit target set and a third preset correspondence; the third preset correspondence is the correspondence between the bit target set and the number C of the second bit sequence.

[0216] In some embodiments, the processing unit 302 can be used to: when the number of bits in the first bit sequence is not an integer multiple of the number C of the second bit sequences, perform a zero-padding operation on the first bit sequence to obtain a first bit sequence after the zero-padding operation; and divide the first bit sequence after the zero-padding operation based on the number C of the second bit sequences to obtain C second bit sequences.

[0217] In some embodiments, the processing unit 302 can be used to: perform a zero-padding operation on the starting position of the first bit sequence to obtain the first bit sequence after the zero-padding operation; or perform a zero-padding operation on the end position of the first bit sequence to obtain the first bit sequence after the zero-padding operation.

[0218] In some embodiments, the processing unit 302 may be configured to: when the number of bits in the first bit sequence is an integer multiple of the number C of second bit sequences, divide the first bit sequence based on the number C of second bit sequences to obtain C second bit sequences.

[0219] In some embodiments, the processing unit 302 may be configured to: perform channel interleaving on the C third bit sequences respectively to obtain C fifth bit sequences; and perform concatenation on the C fifth bit sequences to obtain a fourth bit sequence.

[0220] In some embodiments, the processing unit 302 may be configured to: add L cyclic redundancy check (CRC) bits to each of the C second bit sequences to obtain C sixth bit sequences, where L is a positive integer; and perform polar coding on the C sixth bit sequences to obtain C third bit sequences.

[0221] FIG14 is a schematic diagram showing the composition of a communication device provided by an embodiment of the present disclosure. As shown in FIG14 , the communication device 40 includes a receiving unit 401 and a processing unit 402 .

[0222] The communication device 40 may be the above-mentioned decoding end or a chip in the decoding end. When the communication device 40 is used to implement the functions of the decoding end in the above-mentioned embodiment, each unit may be used to implement the following functions.

[0223] The receiving unit 401 is configured to receive a signal including a fourth bit sequence;

[0224] The processing unit 402 is configured to: divide the signal including the fourth bit sequence to obtain C sub-signals, where C is an integer greater than or equal to 1; demodulate and decode the C sub-signals respectively to obtain C estimated values ​​of the second bit sequence; and concatenate the C estimated values ​​of the second bit sequence to obtain a first bit sequence of the transport block.

[0225] It should be noted that the units in Figures 13 and 14 may also be referred to as modules. For example, the sending unit may be referred to as a sending module. In addition, in the embodiments shown in Figures 13 and 14, the names of the units may not be those shown in the figures. For example, the sending unit may be referred to as a communication unit, and the receiving unit may be referred to as a communication unit.

[0226] If the various units in Figures 13 and 14 are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the various embodiments of the present disclosure. The storage medium for storing computer software products includes various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0227] When the communication device 30 or 40 implements the functions of the integrated modules in hardware, the present disclosure provides a schematic structural diagram of the communication device. As shown in Figure 15, the communication device 50 includes: a processor 502, a communication interface 503, and a bus 504. In some embodiments, the communication device 50 may also include a memory 501.

[0228] The processor 502 can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the present disclosure. The processor 502 can be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof, and can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the present disclosure. The processor 502 can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0229] The communication interface 503 is used to connect to other devices via a communication network, such as Ethernet, wireless access network, wireless local area network (WLAN), etc.

[0230] The memory 501 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0231] As a possible implementation, the memory 501 can exist independently of the processor 502. The memory 501 can be connected to the processor 502 via a bus 504 to store instructions or program codes. When the processor 502 calls and executes the instructions or program codes stored in the memory 501, the encoding method or decoding method provided in the embodiments of the present disclosure can be implemented.

[0232] In another possible implementation, the memory 501 may also be integrated with the processor 502 .

[0233] Bus 504 can be an Extended Industry Standard Architecture (EISA) bus, etc. Bus 504 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, FIG15 shows only one thick line, but this does not mean that there is only one bus or only one type of bus.

[0234] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and conciseness of the description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the encoding end or the decoding end can be divided into different functional modules to complete all or part of the functions described above.

[0235] The embodiments of the present disclosure also provide a computer-readable storage medium (for example, including a non-transitory computer-readable storage medium). All or part of the processes in the above-mentioned method embodiments can be completed by computer instructions to instruct the relevant hardware, and the program can be stored in the above-mentioned computer-readable storage medium. When the program is executed, it may include the processes of the above-mentioned method embodiments. The above-mentioned computer-readable storage medium may also be an external storage device of the above-mentioned encoding end or decoding end, such as a plug-in hard disk, a smart memory card (smart media card, SMC), a secure digital (secure digital, SD) card, a flash card (flash card), etc. equipped on the above-mentioned encoding end or decoding end. Furthermore, the above-mentioned computer-readable storage medium may also include both the internal storage unit of the above-mentioned encoding end or decoding end and an external storage device. The above-mentioned computer-readable storage medium is used to store the above-mentioned computer program and other programs and data required by the above-mentioned encoding end or decoding end. The above-mentioned computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0236] The embodiments of the present disclosure further provide a computer program product, which includes computer instructions. When the computer instructions are executed on a computer, the computer is enabled to execute any one of the encoding methods or decoding methods provided in the above embodiments.

[0237] Although the present disclosure is described herein in conjunction with various embodiments, in the process of implementing the disclosure for which protection is sought, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple components. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0238] Although the present disclosure has been described in conjunction with example features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present disclosure. Accordingly, this specification and the drawings are merely illustrative of the present disclosure as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present disclosure. It will be apparent that those skilled in the art may make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is intended to encompass such modifications and variations as would fall within the scope of the claims of the present disclosure and their equivalents.

[0239] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or replacements within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A coding method comprising: Obtaining a first bit sequence of a transport block; Dividing the first bit sequence to obtain C second bit sequences; C is an integer greater than or equal to 1; Performing polarization coding on the C second bit sequences respectively to obtain C third bit sequences; cascading the C third bit sequences to obtain a fourth bit sequence; The fourth bit sequence is sent.

2. The method according to claim 1, wherein The dividing the first bit sequence to obtain C second bit sequences includes: When the first bit sequence meets a preset condition, the first bit sequence is divided to obtain the C second bit sequences.

3. The method according to claim 2, wherein: The preset conditions include any of the following: The number of bits of the first bit sequence is greater than or equal to a first number threshold, and the sending length of the fourth bit sequence is greater than or equal to a sending length threshold; The number of bits in the first bit sequence is greater than or equal to a second number threshold; wherein the first number threshold is less than the second number threshold; Receiving a first indication signaling, where the value of the first indication signaling is a specific value; The information type of the information included in the first bit sequence is a specific information type; The channel corresponding to the first bit sequence is a specific channel; The number of bits of the first bit sequence belongs to a first set; The number of bits in the encoded first bit sequence is greater than or equal to a third number threshold; The number of bits in the encoded first bit sequence belongs to the second set.

4. The method according to claim 1, wherein The dividing the first bit sequence to obtain C second bit sequences includes: determining the number C of the second bit sequences; The first bit sequence is divided based on the number C of the second bit sequences to obtain the C second bit sequences.

5. The method according to claim 4, wherein The number C of the second bit sequences is determined based on at least one of the following: Q first number thresholds; Q sending length thresholds; X second number thresholds; the number of bits in the first bit sequence; a transmission length of the fourth bit sequence; Wherein, Q and X are both positive integers.

6. The method according to claim 4, wherein: The determining the number C of the second bit sequences includes: determining a code rate based on the number of bits of the first bit sequence and a transmission length of the fourth bit sequence; The number C of the second bit sequences is determined based on the number of bits of the first bit sequence, the code rate, and a first preset corresponding relationship; wherein the first preset corresponding relationship is a corresponding relationship between the number of bits of the first bit sequence, the code rate, and the number C of the second bit sequences.

7. The method according to claim 4, wherein: The determining the number C of the second bit sequences includes: Determining, based on the number of bits in the first bit sequence and a second preset correspondence, a bit number set corresponding to the number of bits in the first bit sequence; the second preset correspondence being a correspondence between the number of bits in the first bit sequence and the bit number set; Based on the bit target set and a third preset correspondence, the number C of the second bit sequences is determined; the third preset correspondence is the correspondence between the bit target set and the number C of the second bit sequences.

8. The method according to claim 4, wherein: The dividing the first bit sequence based on the number C of second bit sequences to obtain the C second bit sequences includes: If the number of bits in the first bit sequence is not an integer multiple of the number C of the second bit sequence, performing a zero-padding operation on the first bit sequence to obtain a first bit sequence after the zero-padding operation; The first bit sequence after the zero-padding operation is divided based on the number C of the second bit sequences to obtain the C second bit sequences.

9. The method according to claim 8, wherein The performing a zero-padding operation on the first bit sequence to obtain a first bit sequence after the zero-padding operation includes: Performing a zero-padding operation on the starting position of the first bit sequence to obtain a first bit sequence after the zero-padding operation; or, A zero-padding operation is performed at the end position of the first bit sequence to obtain a first bit sequence after the zero-padding operation.

10. The method according to claim 4, wherein: The dividing the first bit sequence based on the number C of second bit sequences to obtain the C second bit sequences includes: When the number of bits in the first bit sequence is an integer multiple of the number C of the second bit sequences, the first bit sequence is divided based on the number C of the second bit sequences to obtain the C second bit sequences.

11. The method according to claim 1, wherein The step of concatenating the C third bit sequences to obtain a fourth bit sequence includes: performing channel interleaving on the C third bit sequences respectively to obtain C fifth bit sequences; The C fifth bit sequences are concatenated to obtain the fourth bit sequence.

12. The method according to claim 1, wherein The polar coding includes at least one of the following: adding frozen bits, polarization conversion, and rate matching.

13. The method according to claim 12, wherein: The frozen bit is determined based on at least the value of C.

14. The method according to claim 12, wherein: The performing polarization coding on the C second bit sequences respectively to obtain C third bit sequences includes: Adding L cyclic redundancy check (CRC) bits to each of the C second bit sequences to obtain C sixth bit sequences, where L is a positive integer; Polarization coding is performed on the C sixth bit sequences respectively to obtain the C third bit sequences.

15. The method according to claim 14, wherein The frozen bits of each of the C sixth bit sequences are generated independently, or the frozen bits of the C sixth bit sequences are generated jointly.

16. The method according to claim 1, wherein Among the C third bit sequences, at least one third bit sequence has a length different from that of the other third bit sequences.

17. A decoding method, comprising: receiving a signal comprising a fourth bit sequence; Dividing the signal including the fourth bit sequence to obtain C sub-signals, where C is an integer greater than or equal to 1; Demodulating and decoding the C sub-signals respectively to obtain C estimated values ​​of the second bit sequences; The estimated values ​​of the C second bit sequences are concatenated to obtain a first bit sequence of the transport block.

18. A communication device comprising: memory and processor; The memory is coupled to the processor; The memory is used to store instructions executable by the processor; When the processor executes the instructions, the method according to any one of claims 1 to 17 is performed.

19. A computer program product, wherein The computer program product comprises computer instructions, which, when executed on a computer, cause the computer to perform the method according to any one of claims 1 to 17 .

20. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer instructions, which, when executed on a computer, enable the computer to perform the method according to any one of claims 1 to 17.

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