Backside illuminated CMOS image sensor and forming method therefor

Abstract

A backside illuminated CMOS image sensor and a forming method therefor. The backside illuminated CMOS image sensor comprises: a substrate and a device layer located on the surface of the substrate, wherein a plurality of mutually separated photoelectric doping regions are provided in the substrate, the device layer comprises a plurality of device structures, each device structure is located on the surface of the substrate between the adjacent photoelectric doping regions, the substrate comprises a first surface and a second surface opposite to each other, and the device layer is located on the first surface; a metal reflecting layer located on the device layer, wherein the reflectivity range of the metal reflecting layer to near-infrared light is larger than a preset value, a plurality of reserved openings are formed in the metal reflecting layer, and the reserved openings penetrate through the metal reflecting layer in the direction perpendicular to the surface of the substrate; and a metal interconnection layer located on the substrate, wherein the metal interconnection layer comprises a first metal layer and a plurality of first conductive plugs, the first metal layer is electrically connected to the device structures by means of the plurality of first conductive plugs, the plurality of first conductive plugs penetrate through the metal reflecting layer from the reserved openings and are electrically isolated from the metal reflecting layer, thereby improving near-infrared light absorption and quantum conversion efficiency.

Description

Back-illuminated CMOS image sensor and method for forming the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 29, 2024, with application number 202410388616.4 and invention name “Back-illuminated CMOS image sensor and method for forming the same”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a back-illuminated CMOS image sensor and a method for forming the same. Background Art

[0003] Image sensors, devices that convert light signals into electrical signals, are widely used in digital television and visual communications. CMOS image sensors are manufactured using traditional CMOS circuit processes, integrating the image sensor and its required peripheral circuits, giving them a broad range of applications.

[0004] Based on the location where light is received, CMOS image sensors can be categorized as front-side illuminated (FSI) or back-side illuminated (BSI). Compared to front-illuminated image sensors, back-illuminated image sensors offer an improvement by altering the internal structure of the sensor. This redirects the incident light path through the photosensitive layer, allowing light to enter directly from the back. This avoids the influence of the structure and thickness between the microlens and photodiode in front-illuminated image sensors, improving the efficiency of fiber optic reception. With the advancement of image sensing technology, back-illuminated CMOS image sensors are becoming the mainstream technology for mid- to high-end CMOS image sensors.

[0005] However, the performance of existing back-illuminated CMOS image sensors needs to be further improved.

[0006] Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a back-illuminated CMOS image sensor and a method for forming the same, so as to improve the performance of the formed back-illuminated CMOS image sensor.

[0008] To solve the above technical problems, the technical solution of the present invention provides a back-illuminated CMOS image sensor, comprising: a substrate structure, the substrate structure comprising a substrate and a device layer located on a surface of the substrate, the substrate having a plurality of discrete photoelectrically doped regions therein, the device layer comprising a plurality of device structures, each of the device structures being located on the substrate surface between adjacent photoelectrically doped regions, the substrate comprising a first surface and a second surface opposite each other, the device layer being located on the first surface; a metal reflective layer located on the device layer, the metal reflective layer having a reflectivity range for near-infrared light greater than a preset value, the metal reflective layer having a plurality of reserved openings therein, each of the reserved openings penetrating the metal reflective layer in a direction perpendicular to the substrate surface; and a metal interconnection layer located on the substrate, the metal interconnection layer comprising a first metal layer and a plurality of first conductive plugs, the first metal layer being electrically connected to the device structures via the plurality of first conductive plugs, the plurality of first conductive plugs penetrating the metal reflective layer from the reserved openings and being electrically isolated from the metal reflective layer.

[0009] Optionally, it also includes: a first dielectric layer located on the surface of the device layer, the middle relative edge of the surface of the first dielectric layer on each of the photoelectric doping regions protrudes in a direction away from the first surface; the metal reflective layer on each of the photoelectric doping regions has a metal convex surface protruding in a direction away from the first surface, and the metal convex surface is adjacent to the surface of the first dielectric layer.

[0010] Optionally, the first dielectric layer has a maximum first thickness and a minimum second thickness in a direction perpendicular to the substrate surface, and a difference between the first thickness and the second thickness ranges from 100 nm to 800 nm.

[0011] Optionally, the preset value includes 70%.

[0012] Optionally, the wavelength range of the near-infrared light is 0.7 μm to 2.5 μm.

[0013] Optionally, the material of the metal reflective layer includes Ag, Cu, Al or TiN.

[0014] Optionally, the thickness of the metal reflective layer ranges from 20 nm to 100 nm.

[0015] Optionally, the back-illuminated CMOS image sensor further includes: an isolation structure within the substrate structure, the isolation structure extending from the second surface to the first surface and located between adjacent photoelectric doping regions and on the second surface; a metal grid and a plurality of filter layers located on the isolation structure, the metal grid located between adjacent filter layers, and a projection of the metal grid on the first surface located between adjacent photoelectric doping regions; and a plurality of lenses located on the plurality of filter layers.

[0016] Optionally, the substrate further comprises a plurality of floating diffusion regions, each of the floating diffusion regions being located between adjacent photoelectric doping regions; the metal interconnection layer further comprises a plurality of second conductive plugs and a second metal layer located on the plurality of second conductive plugs, the second metal layer being electrically connected to the plurality of floating diffusion regions through the plurality of second conductive plugs, and the plurality of second conductive plugs passing through the metal reflective layer from the reserved openings and being electrically isolated from the metal reflective layer.

[0017] Accordingly, the technical solution of the present invention also provides a method for forming a back-illuminated CMOS image sensor, comprising: forming a substrate structure, the substrate structure comprising a substrate and a device layer located on a surface of the substrate, the substrate having a plurality of discrete photoelectric doped regions therein, the device layer comprising a plurality of device structures, each of the device structures being located on the substrate surface between adjacent photoelectric doped regions, the substrate comprising a first surface and a second surface opposite each other, the device layer being located on the first surface; forming a metal reflective layer on the surface of the device layer, the metal reflective layer having a reflectivity range for near-infrared light greater than a preset value, the metal reflective layer having a plurality of reserved openings therein, each of the reserved openings penetrating the metal reflective layer in a direction perpendicular to the substrate surface; and after forming the metal reflective layer, forming a metal interconnection layer, the metal interconnection layer comprising a first metal layer and a plurality of first conductive plugs, the first metal layer being electrically connected to the device structures via the plurality of first conductive plugs, the plurality of first conductive plugs penetrating the metal reflective layer from the reserved openings and being electrically isolated from the metal reflective layer.

[0018] Optionally, before forming the metal reflective layer, a first dielectric layer is further formed on the surface of the device layer, and the middle relative edge of the surface of the first dielectric layer on each of the photoelectric doped regions protrudes in a direction away from the first surface; the metal reflective layer on each of the photoelectric doped regions has a metal convex surface protruding in a direction away from the first surface, and the metal convex surface is adjacent to the surface of the first dielectric layer.

[0019] Optionally, the method for forming the first dielectric layer includes: forming a first dielectric material layer on the surface of the device layer; patterning the first dielectric material layer to form several initial first dielectric layers, one of the initial first dielectric layers being located on one of the photoelectric doping regions; forming a second dielectric material layer on the surface of the device layer and on the surfaces of the several initial first dielectric layers, and forming the first dielectric layer with the initial first dielectric layer and the second dielectric material layer.

[0020] Optionally, the method for forming the metal reflective layer includes: forming a metal reflective material layer on the surface of the first dielectric layer; and patterning the metal reflective material layer to form the metal reflective layer.

[0021] Optionally, after forming the metal interconnection layer, the method further includes: etching the substrate from the second surface to form deep trenches in the substrate, wherein the deep trenches are located between adjacent photoelectric doping regions; forming an isolation structure on the second surface and in the deep trenches; forming a metal grid and several filter layers on the isolation structure, wherein the metal grid is located between adjacent filter layers, and the projection of the metal grid on the first surface is located between adjacent photoelectric doping regions; and forming several lenses on several of the filter layers.

[0022] Optionally, after forming the metal interconnection layer and before forming the deep trench, the method further includes: bonding a second substrate on the metal interconnection layer using a silicon wafer bonding process; and after the bonding process, thinning the substrate from the second surface.

[0023] Optionally, the metal interconnection layer further includes a second dielectric layer and a third dielectric layer located on the surface of the second dielectric layer, the plurality of first conductive plugs are located in the second dielectric layer, and the first metal layer is located on the surface of the third dielectric layer; the method for forming the metal interconnection layer includes: forming the second dielectric layer on the metal reflective layer and in the plurality of reserved openings; etching the second dielectric layer and the first dielectric layer until the device structure is exposed, forming a plurality of first through holes in the second dielectric layer and the first dielectric layer; forming a plurality of first conductive plugs in the plurality of first through holes; forming the third dielectric layer on the surface of the second dielectric layer and on the surface of the plurality of first conductive plugs; and forming the first metal layer in the third dielectric layer.

[0024] Optionally, the process of forming the plurality of first through holes includes a dry etching process.

[0025] Optionally, the device layer further includes a fourth dielectric layer, and several of the device structures are located in the fourth dielectric layer; several of the first through holes are also located in the fourth dielectric layer; and the method for forming the metal interconnection layer further includes: etching the fourth dielectric layer.

[0026] Optionally, the substrate further comprises a plurality of floating diffusion regions, each of the floating diffusion regions being located between adjacent photoelectric doping regions; the metal interconnection layer further comprises a plurality of second conductive plugs and a second metal layer located on the plurality of second conductive plugs, the second metal layer being electrically connected to the plurality of floating diffusion regions via the plurality of second conductive plugs, the plurality of second conductive plugs penetrating the metal reflective layer from the reserved openings and being electrically isolated from the metal reflective layer; the method for forming the metal interconnection layer further comprises: etching the second dielectric layer, the first dielectric layer and the fourth dielectric layer until the plurality of floating diffusion regions are exposed, forming a plurality of second through holes in the second dielectric layer, the first dielectric layer and the fourth dielectric layer; forming a plurality of second conductive plugs in the plurality of second through holes; and forming the second metal layer in the third dielectric layer.

[0027] Optionally, the process of forming the plurality of second through holes includes a dry etching process.

[0028] Optionally, the device structure includes a gate layer.

[0029] Compared with the existing technology, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0030] In the back-illuminated CMOS image sensor provided by the technical solution of the present invention, a metal reflective layer is provided between the device layer and the metal interconnect layer. The reflectivity range of the metal reflective layer for near-infrared light is greater than a preset value, thereby increasing the probability of near-infrared light being reflected to each of the photoelectric doping regions, thereby improving the absorption of near-infrared light and the quantum conversion efficiency. In addition, the metal reflective layer has a number of reserved openings, which do not affect the arrangement of conductive plugs in the subsequent metal interconnect layer.

[0031] Furthermore, the metal reflective layer on each of the photoelectric doping regions has a metal convex surface protruding in a direction away from the first surface, which is beneficial for concentrating more reflected near-infrared light on the photoelectric doping region, thereby further improving quantum efficiency.

[0032] In the method for forming a back-illuminated CMOS image sensor provided by the technical solution of the present invention, a metal reflective layer is provided between the device layer and the metal interconnect layer. The metal reflective layer has a reflectivity range for near-infrared light greater than a preset value, thereby increasing the probability of near-infrared light being reflected by each of the photoelectric doping regions, thereby improving near-infrared light absorption and quantum conversion efficiency. In addition, the metal reflective layer has several reserved openings, which do not affect the subsequent arrangement of conductive plugs in the metal interconnect layer.

[0033] Furthermore, the metal reflective layer on each of the photoelectric doping regions has a metal convex surface protruding in a direction away from the first surface, which is beneficial for concentrating more reflected near-infrared light on the photoelectric doping region, thereby further improving quantum efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] 1 to 8 are schematic structural diagrams of various steps of a method for forming a back-illuminated CMOS image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0036] As described in the background, the performance of existing back-illuminated CMOS image sensors needs to be further improved. Specifically, conventional back-illuminated CMOS image sensors cannot effectively absorb and convert long-wavelength near-infrared light into photoelectricity, limiting the sensor's quantum efficiency and near-infrared sensitivity.

[0037] To address the aforementioned issues, the present invention provides a back-illuminated CMOS image sensor and a method for forming the same. A metal reflective layer is disposed between the device layer and the metal interconnect layer. The metal reflective layer has a reflectivity range for near-infrared light greater than a preset value, thereby increasing the probability of near-infrared light being reflected by each of the photoelectrically doped regions, thereby improving near-infrared light absorption and quantum conversion efficiency. Furthermore, the metal reflective layer includes a number of reserved openings, which do not affect the placement of conductive plugs in the subsequent metal interconnect layer.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] 1 to 8 are schematic structural diagrams of various steps of a method for forming a back-illuminated CMOS image sensor according to an embodiment of the present invention.

[0040] Please refer to Figure 1 to form a substrate structure, which includes a substrate 100 and a device layer 101 located on the surface of the substrate 100. The substrate 100 has a plurality of separate photoelectric doping regions 102. The device layer 101 includes a plurality of device structures, each of which is located on the surface of the substrate 100 between adjacent photoelectric doping regions 102. The substrate 100 includes a first surface 100a and a second surface 100b relative to each other, and the device layer 101 is located on the first surface 100a.

[0041] In this embodiment, the photoelectric doping region 102 includes an N-type doping region and a P-type doping region, which are used to form a photodiode. It should be noted that only the N-type doping region is shown in the figure.

[0042] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate is made of silicon carbide, silicon germanium, a multinary semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multinary semiconductor material composed of Group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0043] In this embodiment, a second substrate (not shown in the figure) is also provided. The second substrate is used as a support during the process.

[0044] In this embodiment, a single pixel unit has a 4T-APS (advanced photo system) structure, i.e., a single pixel unit includes four transistors: a transfer transistor, a reset switch transistor (not shown), a source follower (not shown), and a select switch transistor (not shown). It should be noted that in other embodiments, the specific structure of the pixel unit is not limited.

[0045] In this embodiment, the device structure includes a gate layer 103. Here, the gate layer 103 belongs to a transfer transistor. The device structure may also include gate layers of other transistors.

[0046] The substrate 100 also includes source and drain doping regions (not shown) corresponding to the transistors. In this embodiment, the substrate 100 also includes a plurality of floating diffusion regions 104 , each of which is located between adjacent photoelectric doping regions 102 .

[0047] In this embodiment, the device layer 101 further includes a fourth dielectric layer 105 , and the plurality of device structures are located in the fourth dielectric layer 105 .

[0048] Subsequently, a metal reflective layer is formed on the surface of the device layer 101. The reflectivity range of the metal reflective layer to near-infrared light is greater than a preset value. The metal reflective layer has a plurality of reserved openings, and each of the reserved openings penetrates the metal reflective layer in a direction perpendicular to the surface of the substrate 100.

[0049] In this embodiment, before forming the metal reflective layer, a first dielectric layer is further formed on the surface of the device layer 101 , and the center of the surface of the first dielectric layer on each of the photoelectric doping regions 102 protrudes away from the first surface 100 a relative to the edge.

[0050] In this embodiment, the method for forming the first dielectric layer is shown in FIG. 2 to FIG. 3 .

[0051] 2 , a first dielectric material layer (not shown) is formed on the surface of the device layer 101 ; the first dielectric material layer is patterned to form a plurality of initial first dielectric layers 106 , one of the initial first dielectric layers 106 being located on one of the photoelectric doping regions 102 .

[0052] The reflective performance of the subsequently formed metal reflective layer can be controlled by adjusting the width of the initial first dielectric layer 106 in a direction parallel to the surface of the substrate 100 .

[0053] The projection of each of the initial first dielectric layers 106 on the surface of the substrate 100 may be a circle or a rounded rectangle.

[0054] 3 , a second dielectric material layer (not shown) is formed on the surface of the device layer 101 and on surfaces of several of the initial first dielectric layers 106 , and the first dielectric layer 107 is formed by the initial first dielectric layer 106 and the second dielectric material layer.

[0055] The first dielectric layer 107 is used to assist in forming the metal reflective layer into a convex shape. In other embodiments, the first dielectric layer 107 may not be formed.

[0056] In this embodiment, the first dielectric layer 107 has a maximum first thickness and a minimum second thickness in a direction perpendicular to the surface of the substrate 100. The difference between the first thickness and the second thickness ranges from 100 nm to 800 nm. The difference can be adjusted to control the reflective properties of the subsequently formed metal reflective layer.

[0057] Please refer to Figure 4. A metal reflective layer 108 is formed on the surface of the device layer 101. The reflectivity range of the metal reflective layer 108 to near-infrared light is greater than a preset value. The metal reflective layer 108 has a plurality of reserved openings 109. Each of the reserved openings 109 penetrates the metal reflective layer 108 in a direction perpendicular to the surface of the substrate 100.

[0058] Here, by setting a metal reflective layer 108 between the device layer 101 and the metal interconnection layer, the reflectivity range of the metal reflective layer 108 to near-infrared light is greater than a preset value, thereby increasing the probability of near-infrared light being reflected to each of the photoelectric doping regions 102, which is beneficial to improving the absorption of near-infrared light and the quantum conversion efficiency. In addition, the metal reflective layer 108 has a number of reserved openings 109, which does not affect the arrangement of conductive plugs in the subsequent metal interconnection layer.

[0059] In this embodiment, the method for forming the metal reflective layer 108 includes: forming a metal reflective material layer (not shown) on the surface of the first dielectric layer 107 ; and patterning the metal reflective material layer to form the metal reflective layer 108 .

[0060] In this embodiment, the material of the metal reflective layer 108 includes Ag, Cu, Al or TiN. The metal reflective layer 108 has a high near-infrared light reflection characteristic.

[0061] In this embodiment, the thickness of the metal reflective layer ranges from 20 nm to 100 nm.

[0062] In this embodiment, the preset value includes 70%. The purpose of limiting the preset value is that the larger the preset value is, the more obvious the reflective performance of the metal reflective layer for near-infrared light is.

[0063] In this embodiment, the wavelength range of the near-infrared light is 0.7 μm to 2.5 μm.

[0064] In this embodiment, a plurality of reserved openings 109 expose the surface of the first dielectric layer 107 .

[0065] In this embodiment, the metal reflective layer 108 on each of the photoelectrically doped regions 102 has a metal convex surface that protrudes away from the first surface 100a, and the metal convex surface is adjacent to the surface of the first dielectric layer 107. The metal convex surface helps to concentrate more reflected near-infrared light on the photoelectrically doped region 102, further improving quantum efficiency.

[0066] Subsequently, after forming the metal reflective layer 108, a metal interconnection layer and a plurality of first conductive plugs are formed. The metal interconnection layer includes a first metal layer. The first metal layer is electrically connected to the device structure through a plurality of first conductive plugs. The plurality of first conductive plugs pass through the metal reflective layer from the reserved opening and are electrically isolated from the metal reflective layer.

[0067] In this embodiment, the metal interconnection layer further includes a second dielectric layer and a third dielectric layer located on the surface of the second dielectric layer. The first conductive plugs are located in the second dielectric layer, and the first metal layer is located on the surface of the third dielectric layer.

[0068] In this embodiment, the method for forming the metal interconnection layer is shown in FIG5 .

[0069] Referring to Figure 5, the second dielectric layer 110 is formed on the metal reflective layer 108 and in the plurality of reserved openings 109; the second dielectric layer 110 and the first dielectric layer 107 are etched until the device structure is exposed, and a plurality of first through holes (not shown in the figure) are formed in the second dielectric layer 110 and the first dielectric layer 107; a plurality of first conductive plugs (not shown in the figure) are formed in the plurality of first through holes; the third dielectric layer 111 is formed on the surface of the second dielectric layer 110 and the surface of the plurality of first conductive plugs; and the first metal layer (not shown in the figure) is formed in the third dielectric layer 111.

[0070] The first metal layer is used to electrically lead out the device structure, specifically, to electrically lead out the gate layer 103 .

[0071] In this embodiment, the process of forming the plurality of first through holes includes a dry etching process.

[0072] In this embodiment, a plurality of the first through holes are further located in the fourth dielectric layer 105 ; and the method for forming the metal interconnection layer further includes: etching the fourth dielectric layer 105 .

[0073] In this embodiment, the metal interconnection layer also includes a plurality of second conductive plugs 112 and a second metal layer 113 located on the plurality of second conductive plugs 112. The second metal layer 113 is electrically connected to the plurality of floating diffusion areas 104 through the plurality of second conductive plugs 112. The plurality of second conductive plugs 112 pass through the metal reflective layer 108 from the reserved opening 109 and are electrically isolated from the metal reflective layer 108.

[0074] Specifically, a plurality of second conductive plugs 112 are located on the surfaces of the plurality of floating diffusion regions 104 and within the second dielectric layer 110, the first dielectric layer 107, and the fourth dielectric layer 105. The second metal layer 113 is located within the third dielectric layer 111 and on the surfaces of the plurality of second conductive plugs 112 and a portion of the surface of the second dielectric layer 110. The second metal layer 113 is used to lead electrical signals out of the floating diffusion region 104.

[0075] In this embodiment, the method for forming the metal interconnection layer further includes: etching the second dielectric layer 110, the first dielectric layer 107 and the fourth dielectric layer 105 until the plurality of floating diffusion regions 104 are exposed, forming a plurality of second through holes (not shown in the figure) in the second dielectric layer 110, the first dielectric layer 107 and the fourth dielectric layer 105; forming a plurality of second conductive plugs 112 in the plurality of second through holes; and forming the second metal layer 113 in the third dielectric layer 111.

[0076] In this embodiment, the process of forming the plurality of second through holes includes a dry etching process.

[0077] In this embodiment, the metal interconnect layer further includes several layers of metal wires (not shown) located on the first metal layer and the second metal layer 113. The metal interconnect layer is used to transmit electrical signals, including controlling the switching of each transistor and transmitting electrical signals generated by photoelectric conversion.

[0078] In this embodiment, after the metal interconnection layer is formed, please refer to FIG. 6 to FIG. 8 .

[0079] 6 , the substrate 100 is etched from the second surface 100 b to form deep trenches (not shown) in the substrate 100 . The deep trenches are located between adjacent photoelectric doping regions 102 . An isolation structure 114 is formed on the second surface 100 b and in the deep trenches.

[0080] In this embodiment, after forming the metal interconnection layer and before forming the deep trench, it also includes: bonding a second substrate (not shown in the figure) on the metal interconnection layer using a silicon wafer bonding process; after the bonding process, thinning the substrate 100 from the second surface 100b.

[0081] 7 , a metal grid 115 and a plurality of filter layers 116 are formed on the isolation structure 114 . The metal grid 115 is located between adjacent filter layers 116 , and a projection of the metal grid 115 on the first surface 100 a is located between adjacent photoelectric doping regions 102 .

[0082] Referring to FIG. 8 , a plurality of lenses 117 are formed on the plurality of filter layers 116 .

[0083] Accordingly, an embodiment of the present invention further provides a CMOS image sensor formed by the above method, which, with reference to FIG8 , comprises: a substrate structure, wherein the substrate structure comprises a substrate 100 and a device layer 101 located on the surface of the substrate 100, wherein the substrate 100 has a plurality of mutually separated photoelectric doping regions 102, wherein the device layer 101 comprises a plurality of device structures, each of which is located on the surface of the substrate 100 between adjacent photoelectric doping regions 102, wherein the substrate 100 comprises a first surface 100a and a second surface 100b opposite to each other, wherein the device layer 101 is located on the first surface 100a; and a metal reflector located on the device layer 101. Layer 108, the reflectivity range of the metal reflective layer 108 to near-infrared light is greater than a preset value, the metal reflective layer 108 has a plurality of reserved openings 109 (as shown in FIG4 ), and each of the reserved openings 109 penetrates the metal reflective layer 108 in a direction perpendicular to the surface of the substrate 100; a metal interconnection layer located on the substrate 100, the metal interconnection layer comprising a first metal layer and a plurality of first conductive plugs, the first metal layer (not shown in the figure) being electrically connected to the device structure through the plurality of first conductive plugs, and the plurality of first conductive plugs penetrate the metal reflective layer 108 from the reserved openings 109 and are electrically isolated from the metal reflective layer 108.

[0084] Here, by setting a metal reflective layer 108 between the device layer 101 and the metal interconnection layer, the reflectivity range of the metal reflective layer 108 to near-infrared light is greater than a preset value, thereby increasing the probability of near-infrared light being reflected to each of the photoelectric doping regions 102, which is beneficial to improving the absorption of near-infrared light and the quantum conversion efficiency. In addition, the metal reflective layer 108 has a number of reserved openings 109, which does not affect the arrangement of conductive plugs in the subsequent metal interconnection layer.

[0085] In this embodiment, the back-illuminated CMOS image sensor further includes: a first dielectric layer 107 located on the surface of the device layer 101; the center portion of the surface of the first dielectric layer 107 on each of the photoelectrically doped regions 102 protrudes relative to the edge in a direction away from the first surface 100a; and the metal reflective layer 108 on each of the photoelectrically doped regions 102 includes a metal convex surface protruding away from the first surface 100a, with the metal convex surface adjacent to the surface of the first dielectric layer 107. The metal convex surface facilitates the concentration of reflected near-infrared light on the photoelectrically doped region 102, further improving quantum efficiency.

[0086] In this embodiment, the first dielectric layer 107 has a maximum first thickness and a minimum second thickness in a direction perpendicular to the surface of the substrate 100 , and the difference between the first thickness and the second thickness ranges from 100 nm to 800 nm.

[0087] In this embodiment, the preset value includes 70%.

[0088] In this embodiment, the wavelength range of the near-infrared light is 0.7 μm to 2.5 μm.

[0089] In this embodiment, the material of the metal reflective layer 108 includes Ag, Cu, Al or TiN.

[0090] In this embodiment, the thickness of the metal reflective layer 108 ranges from 20 nm to 100 nm.

[0091] In this embodiment, the back-illuminated CMOS image sensor further includes: an isolation structure 114 located within the substrate structure, the isolation structure 114 extending from the second surface 100 b toward the first surface 100 a and located between adjacent photoelectric doping regions 102 and on the second surface 100 b; a metal grid 115 and a plurality of filter layers 116 located on the isolation structure 114, the metal grid 115 located between adjacent filter layers 116, and a projection of the metal grid 115 on the first surface 100 a located between adjacent photoelectric doping regions 102; and a plurality of lenses 117 located on the plurality of filter layers 116.

[0092] In this embodiment, the substrate 100 further has a plurality of floating diffusion regions 104, and each of the floating diffusion regions 104 is located between adjacent photoelectric doping regions 102; the metal interconnection layer also includes a plurality of second conductive plugs 112 and a second metal layer 113 located on the plurality of second conductive plugs 112, and the second metal layer 113 is electrically connected to the plurality of floating diffusion regions 104 through the plurality of second conductive plugs 112, and the plurality of second conductive plugs 112 pass through the metal reflective layer 108 from the reserved opening 109 and are electrically isolated from the metal reflective layer 108.

[0093] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A back-illuminated CMOS image sensor, characterized in that: include: A substrate structure comprising a substrate and a device layer located on a surface of the substrate, wherein the substrate has a plurality of mutually discrete photoelectric doped regions, the device layer comprises a plurality of device structures, each of the device structures being located on the surface of the substrate between adjacent photoelectric doped regions, the substrate comprising a first surface and a second surface opposite to each other, the device layer being located on the first surface; a metal reflective layer located on the device layer, wherein the reflectivity range of the metal reflective layer to near-infrared light is greater than a preset value, and the metal reflective layer has a plurality of reserved openings therein, each of the reserved openings penetrating the metal reflective layer in a direction perpendicular to the substrate surface; A metal interconnection layer located on the substrate, the metal interconnection layer includes a first metal layer and a plurality of first conductive plugs, the first metal layer is electrically connected to the device structure through the plurality of first conductive plugs, and the plurality of first conductive plugs pass through the metal reflective layer from the reserved opening and are electrically isolated from the metal reflective layer.

2. The back-illuminated CMOS image sensor according to claim 1, wherein: Also includes: A first dielectric layer is located on the surface of the device layer, and the middle portion of the surface of the first dielectric layer on each of the photoelectric doped regions protrudes in a direction away from the first surface relative to the edge; the metal reflective layer on each of the photoelectric doped regions has a metal convex surface protruding in a direction away from the first surface, and the metal convex surface is adjacent to the surface of the first dielectric layer.

3. The back-illuminated CMOS image sensor according to claim 2, wherein: The first dielectric layer has a maximum first thickness and a minimum second thickness in a direction perpendicular to the substrate surface, and a difference between the first thickness and the second thickness ranges from 100 nm to 800 nm.

4. The back-illuminated CMOS image sensor according to claim 1, wherein: The preset value includes 70%.

5. The back-illuminated CMOS image sensor according to claim 1, wherein: The wavelength range of the near-infrared light is 0.7 μm to 2.5 μm.

6. The method for forming a back-illuminated CMOS image sensor according to claim 1, wherein: The material of the metal reflective layer includes Ag, Cu, Al or TiN.

7. The method for forming a back-illuminated CMOS image sensor according to claim 1, wherein: The thickness of the metal reflective layer ranges from 20 nm to 100 nm.

8. The back-illuminated CMOS image sensor according to claim 1, wherein: The back-illuminated CMOS image sensor further includes: an isolation structure within the substrate structure, the isolation structure extending from the second surface toward the first surface and located between adjacent photoelectric doping regions and on the second surface; a metal grid and a plurality of filter layers located on the isolation structure, the metal grid located between adjacent filter layers, and a projection of the metal grid on the first surface located between adjacent photoelectric doping regions; and a plurality of lenses located on the plurality of filter layers.

9. The back-illuminated CMOS image sensor according to claim 1, wherein: The substrate also has a plurality of floating diffusion regions, each of which is located between adjacent photoelectric doping regions; the metal interconnection layer also includes a plurality of second conductive plugs and a second metal layer located on the plurality of second conductive plugs, the second metal layer is electrically connected to the plurality of floating diffusion regions through the plurality of second conductive plugs, and the plurality of second conductive plugs pass through the metal reflective layer from the reserved openings and are electrically isolated from the metal reflective layer.

10. A method for forming a back-illuminated CMOS image sensor, characterized in that: include: forming a substrate structure, the substrate structure comprising a substrate and a device layer located on a surface of the substrate, the substrate having a plurality of mutually discrete photoelectric doped regions, the device layer comprising a plurality of device structures, each of the device structures being located on the substrate surface between adjacent photoelectric doped regions, the substrate comprising a first surface and a second surface opposite to each other, the device layer being located on the first surface; A metal reflective layer is formed on the surface of the device layer, and the metal reflective layer is resistant to near infrared light. The reflectivity range is greater than a preset value, and the metal reflective layer has a plurality of reserved openings, each of the reserved openings penetrates the metal reflective layer in a direction perpendicular to the substrate surface; After forming the metal reflective layer, a metal interconnection layer is formed, wherein the metal interconnection layer includes a first metal layer and a plurality of first conductive plugs. The first metal layer is electrically connected to the device structure through the plurality of first conductive plugs. The plurality of first conductive plugs pass through the metal reflective layer from the reserved opening and are electrically isolated from the metal reflective layer.

11. The method for forming a back-illuminated CMOS image sensor according to claim 10, wherein: Before forming the metal reflective layer, a first dielectric layer is further formed on the surface of the device layer, and the center portion of the surface of the first dielectric layer on each of the photoelectric doped regions protrudes in a direction away from the first surface relative to the edge; the metal reflective layer on each of the photoelectric doped regions has a metal convex surface protruding in a direction away from the first surface, and the metal convex surface is adjacent to the surface of the first dielectric layer.

12. The method for forming a back-illuminated CMOS image sensor according to claim 11, wherein: The method for forming the first dielectric layer includes: forming a first dielectric material layer on the surface of the device layer; patterning the first dielectric material layer to form a plurality of initial first dielectric layers, wherein one of the initial first dielectric layers is located on one of the photoelectric doping regions; forming a second dielectric material layer on the surface of the device layer and on the surfaces of the plurality of initial first dielectric layers, and forming the first dielectric layer with the initial first dielectric layer and the second dielectric material layer.

13. The method for forming a back-illuminated CMOS image sensor according to claim 11, wherein: The method for forming the metal reflective layer includes: forming a metal reflective material layer on the surface of the first dielectric layer; and patterning the metal reflective material layer to form the metal reflective layer.

14. The method for forming a back-illuminated CMOS image sensor according to claim 11, wherein: After forming the metal interconnection layer, the method further includes: etching the substrate from the second surface to form deep trenches in the substrate, wherein the deep trenches are located between adjacent photoelectric doping regions; forming an isolation structure on the second surface and in the deep trenches; forming a metal grid and a plurality of filter layers on the isolation structure, wherein the metal grid is located between adjacent filter layers, and a projection of the metal grid on the first surface is located between adjacent photoelectric doping regions; and forming a plurality of lenses on the plurality of filter layers.

15. The method for forming a back-illuminated CMOS image sensor according to claim 14, wherein: After forming the metal interconnection layer and before forming the deep trench, the method further includes: bonding a second substrate on the metal interconnection layer using a silicon wafer bonding process; and thinning the substrate from the second surface after the bonding process.

16. The method for forming a back-illuminated CMOS image sensor according to claim 15, wherein: The metal interconnection layer further includes a second dielectric layer and a third dielectric layer located on a surface of the second dielectric layer, the plurality of first conductive plugs are located in the second dielectric layer, and the first metal layer is located on a surface of the third dielectric layer; The method for forming the metal interconnection layer includes: forming the second dielectric layer on the metal reflective layer and in the plurality of reserved openings; etching the second dielectric layer and the first dielectric layer until the device structure is exposed, and forming a plurality of first through holes in the second dielectric layer and the first dielectric layer; forming a plurality of first conductive plugs in the plurality of first through holes; forming the third dielectric layer on the surface of the second dielectric layer and the surface of the plurality of first conductive plugs; and forming the first metal layer in the third dielectric layer. 17 . The method for forming a back-illuminated CMOS image sensor according to claim 16 , wherein a process for forming the plurality of first through holes comprises a dry etching process.

18. The method for forming a back-illuminated CMOS image sensor according to claim 16, wherein: The device layer further includes a fourth dielectric layer, and several of the device structures are located in the fourth dielectric layer; several of the first through holes are also located in the fourth dielectric layer; and the method for forming the metal interconnection layer further includes: etching the fourth dielectric layer.

19. The method for forming a back-illuminated CMOS image sensor according to claim 18, wherein: The substrate also has a plurality of floating diffusion regions, each of which is located between adjacent photoelectric doping regions; the metal interconnection layer also includes a plurality of second conductive plugs and a second metal layer located on the plurality of second conductive plugs, the second metal layer is electrically connected to the plurality of floating diffusion regions through the plurality of second conductive plugs, and the plurality of second conductive plugs pass through the metal reflective layer from the reserved opening and are electrically isolated from the metal reflective layer; the method for forming the metal interconnection layer also includes: etching the second dielectric layer, the first dielectric layer, and the fourth dielectric layer until the plurality of floating diffusion regions are exposed, forming a plurality of second through holes in the second dielectric layer, the first dielectric layer, and the fourth dielectric layer; forming a plurality of second conductive plugs in the plurality of second through holes; and forming the second metal layer in the third dielectric layer. 20 . The method for forming a back-illuminated CMOS image sensor according to claim 19 , wherein a process for forming the plurality of second through holes comprises a dry etching process. 21 . The method for forming a back-illuminated CMOS image sensor according to claim 19 , wherein the device structure comprises a gate layer.

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