Communication link control method, electronic device and nonvolatile readable storage medium

Abstract

The present application relates to the technical field of computers. Disclosed are a communication link control method and apparatus, an electronic device and a nonvolatile readable storage medium. The method is applied to a switch compliant with the peripheral component interconnect express, a processor being connected to a terminal device by means of the switch compliant with the peripheral component interconnect express. The method comprises: controlling a credit timeout mechanism for a target communication link to be enabled, the target communication link being a communication link between the switch compliant with the peripheral component interconnect express and the terminal device; and, in the case of the credit timeout mechanism being enabled, when no credit queue sent by the terminal device has been received upon timeout of a target duration, sending to the processor a notification indicating disconnection of the target communication link, the target duration being less than a completion timeout time of the peripheral component interconnect express. The present application prevents communication congestion during hot plugging of switches compliant with the peripheral component interconnect express, thereby improving the efficiency of handling linkdown events.

Description

Communication link control method, electronic device, and non-volatile readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on March 29, 2024, with application number 202410382149.4, and application name “A communication link control method, device, electronic device and storage medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular, to a communication link control method, device, electronic device, and non-volatile readable storage medium. Background Art

[0004] In scenarios where the processor is connected to terminal devices through a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) switch, in order to meet performance requirements, the bandwidth between the processor and the terminal device is generally greater than x16, that is, multiple PCIe cables are used to connect the processor and the terminal device. Due to the use of multiple cables, each cable may be plugged in or out or fail. The plugged in or failed cables are connected to multiple terminal devices, and the read requests of these terminal devices will accumulate in the PCIe switch, causing communication congestion and affecting the communication of normal devices. In addition, the PCIe protocol stipulates that when hot plugging occurs, it is necessary to wait for a timeout period of 48ms before a communication link disconnection event is generated, and the link disconnection event processing time is relatively long.

[0005] Related technologies modify the CTO (completion timeout) of the corresponding device, increasing the completion timeout between the processor and the terminal device to exceed the PCIe standard. However, this solution cannot completely resolve the impact on normal devices, nor can it solve the timeout period for reading and writing to unplugged devices, nor can it solve the problem of upper-layer service timeouts.

[0006] Therefore, how to avoid communication congestion during hot plugging of a PCIe switch and improve the efficiency of handling link disconnection events are technical problems that need to be solved by those skilled in the art. Summary of the Invention

[0007] The purpose of the present application is to provide a communication link control method, device, electronic device and non-volatile readable storage medium, which avoid communication congestion during hot plugging of a PCIe switch and improve the efficiency of link disconnection event processing.

[0008] To achieve the above objectives, a first aspect of an embodiment of the present application provides a communication link control method, which is applied to a switch that complies with the high-speed serial computer expansion bus standard. A processor is connected to a terminal device through the switch that complies with the high-speed serial computer expansion bus standard. The method includes:

[0009] Controlling the activation of a credit timeout mechanism of a target communication link, wherein the target communication link is a communication link between a switch and a terminal device that complies with a high-speed serial computer expansion bus standard;

[0010] When the credit timeout mechanism is enabled, when the credit queue sent by the terminal device is not received within the target time, a notification of target communication link disconnection is sent to the processor; wherein the target time is less than the completion timeout of the high-speed serial computer expansion bus standard.

[0011] Among them, the credit timeout mechanism of the control target communication link is enabled, including:

[0012] Determining a credit timeout mechanism register of a target communication link; wherein the credit timeout mechanism register is set to control whether the credit timeout mechanism is enabled;

[0013] Set the enable flag in the credit timeout mechanism register to control the start of the credit timeout mechanism.

[0014] Determining the credit timeout mechanism register of the target communication link includes:

[0015] The registers corresponding to the target communication link are traversed to determine the credit timeout mechanism register.

[0016] The registers corresponding to the target communication link are traversed to determine the credit timeout mechanism register, including:

[0017] Use the software toolkit to traverse the registers corresponding to the target communication link to determine the credit timeout mechanism register.

[0018] Among them, setting the permission flag bit in the credit timeout mechanism register includes:

[0019] Set the enable flag in the credit timeout mechanism register through the command line command.

[0020] Among them, setting the permission flag bit in the credit timeout mechanism register includes:

[0021] Set the enable flag in the credit timeout mechanism register through the configuration management tool.

[0022] Among them, setting the permission flag bit in the credit timeout mechanism register includes:

[0023] A first configuration file is generated based on the configuration information of the credit timeout mechanism register with the enable flag set, and the switch compliant with the high-speed serial computer expansion bus standard is configured using the first configuration file to set the enable flag in the credit timeout mechanism register.

[0024] Among them, also include:

[0025] Control the target communication link's read rate control mechanism to start, and set the corresponding read threshold for the terminal device;

[0026] When the read rate control mechanism is enabled, the number of read requests sent by the terminal device to the processor through the switch that complies with the high-speed serial computer expansion bus standard is less than the read threshold corresponding to the terminal device.

[0027] Among them, the read rate control mechanism of the control target communication link is turned on and the read threshold corresponding to the terminal device is set, including:

[0028] determining a read rate control register and a read threshold configuration register of a target communication link;

[0029] Set the enable flag in the read rate control register to enable the read rate control mechanism, and configure the read threshold corresponding to the terminal device in the read threshold configuration register.

[0030] Determining the read rate control register and the read threshold configuration register of the target communication link includes:

[0031] A flow control register of a target communication link is determined, and a read rate control register and a read threshold configuration register are determined in the flow control register.

[0032] Determining the flow control register of the target communication link includes:

[0033] Traverse the registers corresponding to the target communication link to determine the flow control register.

[0034] The read rate control register and the read threshold configuration register are determined in the flow control register, including:

[0035] Determine the read rate control register in the flow control register;

[0036] In the flow control register, a corresponding read threshold configuration register is determined according to the bandwidth between the switch and the terminal device that complies with the high-speed serial computer expansion bus standard.

[0037] Among them, the enable flag is set in the read rate control register to control the start of the read rate control mechanism, and the read threshold corresponding to the terminal device is configured in the read threshold configuration register, including:

[0038] Set the enable flag in the read rate control register through the command line command to control the read rate control mechanism to start;

[0039] Configure the read threshold corresponding to the terminal device in the read threshold configuration register through the command line command.

[0040] Among them, the enable flag is set in the read rate control register to control the start of the read rate control mechanism, and the read threshold corresponding to the terminal device is configured in the read threshold configuration register, including:

[0041] Use the configuration management tool to set the enable flag in the read rate control register to enable the read rate control mechanism.

[0042] Use the configuration management tool to configure the read threshold corresponding to the terminal device in the read threshold configuration register.

[0043] Among them, the enable flag is set in the read rate control register to control the start of the read rate control mechanism, and the read threshold corresponding to the terminal device is configured in the read threshold configuration register, including:

[0044] Generate a second configuration file based on the configuration information of the read rate control register in which the enable flag is set and the read threshold corresponding to the terminal device;

[0045] The second configuration file is used to set the permission flag in the read rate control register and configure the read threshold corresponding to the terminal device in the read threshold configuration register.

[0046] Before configuring the read threshold corresponding to the terminal device in the read threshold configuration register, the following steps are also included:

[0047] A read threshold corresponding to the terminal device is determined according to the bandwidth between the switch and the terminal device that complies with the high-speed serial computer expansion bus standard; wherein the read threshold is positively correlated with the bandwidth.

[0048] Before determining the read threshold corresponding to the terminal device based on the bandwidth between the switch that complies with the high-speed serial computer expansion bus standard and the terminal device, the method further includes:

[0049] The reading threshold corresponding to different bandwidths is determined within a preset range using the dichotomy method.

[0050] To achieve the above-mentioned objectives, a second aspect of an embodiment of the present application provides a communication link control device, which is applied to a switch that complies with the high-speed serial computer expansion bus standard. A processor is connected to a terminal device via the switch that complies with the high-speed serial computer expansion bus standard. The switch that complies with the high-speed serial computer expansion bus standard is connected to the terminal device via a mini serial small computer system interface cable. The device includes:

[0051] A first control module is configured to control the activation of a credit timeout mechanism of a target communication link, wherein the target communication link is a communication link between a switch and a terminal device that complies with a high-speed serial computer expansion bus standard;

[0052] The sending module is configured to send a notification of target communication link disconnection to the processor when the credit queue sent by the terminal device is not received within a target time period when the credit time period is enabled; wherein the target time period is less than the completion timeout period of the high-speed serial computer expansion bus standard.

[0053] Among them, the first control module is configured to: determine the credit timeout mechanism register of the target communication link; wherein the credit timeout mechanism register is configured to control whether the credit timeout mechanism is enabled; and set an enable flag in the credit timeout mechanism register to control the activation of the credit timeout mechanism.

[0054] The first control module is configured to: traverse registers corresponding to the target communication link to determine a credit timeout mechanism register.

[0055] The first control module is configured to: utilize a software toolkit to traverse registers corresponding to the target communication link to determine a credit timeout mechanism register.

[0056] The first control module is configured to set an enable flag in a credit timeout mechanism register through a command line.

[0057] The first control module is configured to: set an enable flag in a credit timeout mechanism register through a configuration management tool.

[0058] Among them, the first control module is configured to: generate a first configuration file based on the configuration information of the credit timeout mechanism register with the enable flag set, and use the first configuration file to configure the switch that complies with the high-speed serial computer expansion bus standard to set the enable flag in the credit timeout mechanism register.

[0059] Among them, also include:

[0060] The second control module is configured to control the read rate control mechanism of the target communication link to be turned on and set a read threshold corresponding to the terminal device; when the read rate control mechanism is turned on, the number of read requests sent by the terminal device to the processor through a switch that complies with the high-speed serial computer expansion bus standard is less than the read threshold corresponding to the terminal device.

[0061] Among them, the second control module is configured to: determine the read rate control register and read threshold configuration register of the target communication link; set the enable flag in the read rate control register to control the start of the read rate control mechanism, and configure the read threshold corresponding to the terminal device in the read threshold configuration register.

[0062] The second control module is configured to: determine a flow control register of the target communication link, and determine a read rate control register and a read threshold configuration register in the flow control register.

[0063] The second control module is configured to: traverse registers corresponding to the target communication link to determine the flow control register.

[0064] The second control module is configured to: determine a read rate control register in the flow control register; determine a corresponding read threshold configuration register in the flow control register according to the bandwidth between the switch and the terminal device that complies with the high-speed serial computer expansion bus standard.

[0065] Among them, the second control module is configured to: set the enable flag in the read rate control register through a command line command to control the start of the read rate control mechanism; configure the read threshold corresponding to the terminal device in the read threshold configuration register through a command line command.

[0066] Among them, the second control module is configured to: set the enable flag in the read rate control register through the configuration management tool to control the start of the read rate control mechanism; configure the read threshold corresponding to the terminal device in the read threshold configuration register through the configuration management tool.

[0067] Among them, the second control module is configured to: generate a second configuration file based on the configuration information of the read rate control register with the enable flag set and the read threshold corresponding to the terminal device; use the second configuration file to set the enable flag in the read rate control register and configure the read threshold corresponding to the terminal device in the read threshold configuration register.

[0068] Among them, also include:

[0069] The first determination module is configured to determine a read threshold corresponding to the terminal device according to a bandwidth between a switch conforming to a high-speed serial computer expansion bus standard and the terminal device; wherein the read threshold is positively correlated with the bandwidth.

[0070] Among them, also include:

[0071] The second determining module is configured to determine the reading thresholds corresponding to different bandwidths within a preset range by using a dichotomy method.

[0072] To achieve the above-mentioned purpose, a third aspect of the embodiments of the present application provides an electronic device, including:

[0073] a memory arranged to store a computer program;

[0074] The processor is configured to implement the steps of the communication link control method described above when executing the computer program.

[0075] To achieve the above-mentioned purpose, the fourth aspect of an embodiment of the present application provides a computer non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned communication link control method are implemented.

[0076] It can be seen from the above scheme that a communication link control method provided by the present application is applied to a switch that complies with the high-speed serial computer expansion bus standard. The processor is connected to the terminal device through the switch that complies with the high-speed serial computer expansion bus standard. The method includes: controlling the credit timeout mechanism of the target communication link to be turned on; wherein, the target communication link is the communication link between the switch that complies with the high-speed serial computer expansion bus standard and the terminal device; when the credit timeout mechanism is turned on, when the credit queue sent by the terminal device is not received within the target time length, a notification of the disconnection of the target communication link is sent to the processor; wherein, the target time length is less than the completion timeout time of the high-speed serial computer expansion bus standard.

[0077] The communication link control method provided in this application uses a credit timeout mechanism to notify the processor of a communication link disconnection within a target duration when a PCIe cable is hot-plugged, i.e., when a PCIe switch port fails. This method avoids communication congestion in the PCIe switch and improves the efficiency of handling link disconnection events. This application also discloses a communication link control device, an electronic device, and a non-volatile computer-readable storage medium, all of which can achieve the aforementioned technical effects.

[0078] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The drawings are used to provide an understanding of the present disclosure and constitute part of the specification. Together with the following optional implementation methods, they are used to explain the present disclosure, but do not constitute a limitation of the present disclosure. In the drawings:

[0080] FIG1 is a schematic diagram showing a hardware application scenario according to an exemplary embodiment;

[0081] FIG2 is a flow chart showing a communication link control method according to an exemplary embodiment;

[0082] FIG3 is a flow chart showing another communication link control method according to an exemplary embodiment;

[0083] FIG4 is a structural diagram of a communication link control device according to an exemplary embodiment;

[0084] Fig. 5 is a structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0085] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. In addition, in the embodiments of the present application, "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0086] In the storage field, with the popularity of SSDs (Solid State Drives), disk enclosures based on direct PCIe connections have also developed. Storage controllers use PCIe cables, typically MiniSaS (Mini Serial Attached SCSI) cables, to connect to expansion enclosures and disk enclosures. To meet performance requirements, the PCIe bandwidth between the controller and expansion enclosure is generally at least x16, while the common MiniSaS cable is x4. Therefore, multiple cables are often used to connect the processor and expansion enclosure. Because multiple cables are used, each cable may become unplugged or fail. When a PCIe cable is disconnected, the corresponding PCIe link fails, and the PCIe LTSSM (Link Training and Status State Machine) jumps to the Recovery state, reducing the supported bandwidth. In addition, when the PCIe cable is disconnected, the PCIe communication link is actually disconnected. However, the protocol stipulates that the LTSSM state machine must first jump to the Recovery state and wait for a timeout of up to 48ms (milliseconds) before generating a LinkDown event.

[0087] Because the unplugged PCIe switch is connected to dozens of NVMe (Non-Volatile Memory Express) disks, PCIe read and write are asynchronous. Each NVMe disk initiates several KB of read requests, which cumulatively exceed the cache size of the receiving port of a typical PCIe switch, which is generally 8 KB. When the PCIe switch is unplugged, the reply responses will accumulate in the cache of the PCIe switch, causing congestion and affecting the communication of other normal devices in place, such as network cards and fiber optic cards.

[0088] In addition, because of the 48ms timeout period, all requests to the NVMe disk mounted under the unplugged PCIe Switch during this period will wait for the 48ms timeout period, which will cause the upper-layer business to time out.

[0089] In related technologies, the CTO of the corresponding device is modified, that is, the completion timeout between the processor and the terminal device is increased to exceed the basic PCIe specification, generally 50ms or 210ms. However, this solution cannot completely eliminate the impact on normal devices, nor can it solve the timeout period for reading and writing to unplugged devices, and cannot solve the problem of upper-layer service timeouts.

[0090] Therefore, in this application, a credit timeout mechanism is used to notify the processor of communication link disconnection within the target time when the PCIe cable is hot-plugged, that is, when the port of the PCIE switch fails, thereby avoiding communication congestion of the PCIe switch and improving the efficiency of link disconnection event processing.

[0091] The embodiment of the present application discloses a communication link control method, which avoids communication congestion during hot plugging of a PCIe switch and improves the efficiency of handling link disconnection events.

[0092] The hardware application scenario of this embodiment is shown in Figure 1. The processor is connected to multiple terminal devices through a switch that complies with the high-speed serial computer expansion bus standard. The processor and the PCIe switch, and the PCIe switch and the terminal devices are connected through PCIe cables.

[0093] Referring to FIG. 2 , a flow chart of a communication link control method according to an exemplary embodiment is shown. As shown in FIG. 2 , the method includes:

[0094] S101: Controlling the activation of a credit timeout mechanism of a target communication link; wherein the target communication link is a communication link between a switch and a terminal device that complies with a high-speed serial computer expansion bus standard;

[0095] The execution subject of this embodiment is a PCIe switch, and the communication link between the PCIe switch and the terminal device is the target communication link. In actual implementation, when initializing the PCIe switch, the credit timeout mechanism of the target communication link is enabled by configuring the PCIe switch.

[0096] It should be noted that this embodiment does not limit the method for enabling the credit timeout mechanism. As a feasible implementation, controlling the activation of the credit timeout mechanism of the target communication link includes: determining a credit timeout mechanism register of the target communication link; wherein the credit timeout mechanism register is configured to control whether the credit timeout mechanism is enabled; and setting an enable flag in the credit timeout mechanism register to control the activation of the credit timeout mechanism.

[0097] It is understood that the target communication link is configured with multiple registers for data communication, and the credit timeout mechanism register configured to control whether the credit timeout mechanism is enabled is determined. In actual implementation, registers corresponding to the target communication link are traversed to determine the credit timeout mechanism register. Due to the inherent characteristics of the credit timeout mechanism register, the credit timeout mechanism is enabled when the credit timeout mechanism register is enabled, and disabled when the credit timeout mechanism register is disabled.

[0098] As a feasible implementation method, traversing registers corresponding to the target communication link to determine the credit timeout mechanism register includes: using a software toolkit to traverse registers corresponding to the target communication link to determine the credit timeout mechanism register.

[0099] In actual implementation, the registers corresponding to the target communication link can be traversed based on the PLX_SDK (PLX Software Development Kit). The PLX_SDK software toolkit provides some well-tested tools for compiling, debugging, and driving user programs to determine the credit timeout mechanism registers.

[0100] Optionally, after determining the credit timeout mechanism register, an enable flag is set in it to control the activation of the credit timeout mechanism. For example, the flag of the credit timeout mechanism register can be set to 0, where 0 indicates enable and 1 indicates disable.

[0101] As a feasible implementation, setting an enable flag in the credit timeout mechanism register includes setting the enable flag in the credit timeout mechanism register using a command line command. In actual implementation, the enable flag in the credit timeout mechanism register can be set using a command line command such as setpci (Set PCI Command).

[0102] As another feasible implementation, setting an enable flag in the credit timeout mechanism register includes setting the enable flag in the credit timeout mechanism register using a configuration management tool. In actual implementation, the enable flag in the credit timeout mechanism register can be set using a configuration management tool, such as Chiplink (a Microchip configuration management tool) or a small tool in the PLX_SDK toolkit.

[0103] As another feasible implementation, setting an enable flag in a credit timeout mechanism register includes: generating a first configuration file based on configuration information of the credit timeout mechanism register with the enable flag set, and using the first configuration file to configure a switch compliant with the high-speed serial computer expansion bus standard to set the enable flag in the credit timeout mechanism register. In actual implementation, the first configuration file is generated based on the configuration information of the credit timeout mechanism register with the enable flag set, and the first configuration file can implement batch configuration of communication links. Configuring a PCIe switch using the first configuration file can include using the configuration information in the first configuration file to configure registers corresponding to target communication links in the PCIe switch, and setting the enable flag in the credit timeout mechanism register of the target communication link.

[0104] S102: When the credit timeout mechanism is enabled, when the credit queue sent by the terminal device is not received within the target time, a notification of target communication link disconnection is sent to the processor; wherein the target time is less than the completion timeout of the high-speed serial computer expansion bus standard.

[0105] In practice, if the credit timeout mechanism is enabled and no credit queue is received within a target duration, a communication link disconnect event is declared for the faulty port, sending a notification of the target communication link disconnection to the processor. The credit timeout mechanism works as follows: The protocol stipulates that when a link is in the L0 or L0s (second) state, a credit queue update must be transmitted at least every 30µs (microseconds). After the target duration timer expires, the LTSSM is used to restore the state, instructing the physical layer to retrain the link.

[0106] This embodiment does not limit the value of the target duration. It only needs to be less than the completion timeout of the PCIe basic specification to quickly notify the processor that the communication link is disconnected. For example, the target duration can be 1.024ms.

[0107] The communication link control method provided in the embodiment of the present application uses a credit timeout mechanism to notify the processor of communication link disconnection within a target duration when a PCIe cable is hot-plugged, that is, when a port failure of a PCIE switch occurs, thereby avoiding communication congestion of the PCIe switch and improving the efficiency of link disconnection event processing.

[0108] Based on the above embodiment, as an optional implementation manner, as shown in FIG3 , the communication link control method further includes:

[0109] S201: Controlling the read rate control mechanism of the target communication link to start, and setting the corresponding read threshold of the terminal device;

[0110] In actual implementation, when initializing the PCIe switch, the read rate control mechanism of the target communication link is enabled by configuring the PCIe switch, and the read threshold corresponding to each terminal device is set.

[0111] It should be noted that this embodiment does not limit the method for enabling the read rate control mechanism and setting the read threshold. As a feasible implementation method, controlling the read rate control mechanism of the target communication link to be enabled and setting the read threshold corresponding to the terminal device includes: determining a read rate control register and a read threshold configuration register of the target communication link; setting an enable flag in the read rate control register to control the read rate control mechanism to be enabled, and configuring the read threshold corresponding to the terminal device in the read threshold configuration register.

[0112] It is understood that a plurality of registers are provided in the target communication link to implement data communication, among which a control read rate control mechanism register configured to control whether the read rate control mechanism is enabled and a read threshold configuration register configured to configure a read threshold are determined. Based on the inherent characteristics of the control read rate control mechanism register, when the control read rate control mechanism register is enabled, the read rate control mechanism is enabled, and when the control read rate control mechanism register is disabled, the read rate control mechanism is disabled.

[0113] As a feasible implementation method, determining the read rate control register and the read threshold configuration register of the target communication link includes: determining the flow control register of the target communication link, and determining the read rate control register and the read threshold configuration register in the flow control register. In actual implementation, the flow control register of the target communication link can be first determined, and the registers corresponding to the target communication link can be traversed to determine the flow control register. For example, for a certain type of PCIe switch, its flow control register is the F30 register. Then, the read rate control register and the read threshold configuration register are determined in the flow control register. It can be understood that the read rate control register and the read threshold configuration register are sub-registers in the flow control register. For example, for a certain type of PCIe switch, the 1D0 register in the F30 register is the read rate control register, and bits 0 to 3 of the 1D0 register are set to 0 to enable the read rate control mechanism. The 1D4 register is the read threshold configuration register, and the read threshold is set by configuring bits 0 to 12 of the 1D4 register.

[0114] As a feasible implementation, determining a read rate control register and a read threshold configuration register in a flow control register includes: determining a read rate control register in the flow control register; and determining a corresponding read threshold configuration register in the flow control register based on the bandwidth between a switch and a terminal device that complies with the high-speed serial computer expansion bus standard. In actual implementation, different bandwidths may correspond to different read threshold configuration registers. For example, for a certain type of PCIe switch, register 1D4 is set to the read threshold corresponding to terminal devices with x16 or x8 bandwidths, and register 1D8 is set to the read threshold corresponding to terminal devices with x4 or x2 bandwidths.

[0115] Optionally, after determining the read rate control register and read threshold configuration register of the target communication link, an enable flag is set in the read rate control register to control the start of the read rate control mechanism, and the read threshold corresponding to the terminal device is configured in the read threshold configuration register.

[0116] As a feasible implementation method, an enable flag is set in the read rate control register to control the activation of the read rate control mechanism, and the read threshold corresponding to the terminal device is configured in the read threshold configuration register, including: setting the enable flag in the read rate control register through a command line command to control the activation of the read rate control mechanism; and configuring the read threshold corresponding to the terminal device in the read threshold configuration register through a command line command. In actual implementation, the enable flag can be set in the read rate control register and the read threshold corresponding to the terminal device can be configured in the read threshold configuration register through a command line command such as setpci. Optional configuration methods are:

[0117] setpci –s BDF 0xF30.b=xx; / / Change the value of F30 register to xx;

[0118] setpci –s BDF 0x1D4.b=xx; / / Change the value of 1D4 register to xx;

[0119] setpci –s BDF 0x1D0.b=xx; / / Change the value of 1D0 register to xx.

[0120] As another feasible implementation, an enable flag is set in a read rate control register to control the activation of the read rate control mechanism, and a read threshold corresponding to the terminal device is configured in a read threshold configuration register, including: setting an enable flag in the read rate control register to control the activation of the read rate control mechanism through a configuration management tool; and configuring the read threshold corresponding to the terminal device in the read threshold configuration register through the configuration management tool. In actual implementation, the enable flag in the read rate control register and the read threshold corresponding to the terminal device in the read threshold configuration register can be set through a configuration management tool, such as a small tool in Chiplink or the PLX_SDK toolkit.

[0121] As another feasible implementation, an enable flag is set in the read rate control register to control the start of the read rate control mechanism, and the read threshold corresponding to the terminal device is configured in the read threshold configuration register, including: generating a second configuration file based on the configuration information of the read rate control register with the enable flag set and the read threshold corresponding to the terminal device; using the second configuration file to set the enable flag in the read rate control register and configure the read threshold corresponding to the terminal device in the read threshold configuration register. In actual implementation, the second configuration file is generated based on the configuration information of the read rate control register with the enable flag set and the read threshold corresponding to the terminal device. The second configuration file can realize batch configuration of communication links, and the second configuration file is used to configure the PCIe switch. The process can be to use the configuration information and read threshold in the second configuration file to configure the register corresponding to the target communication link in the PCIe switch accordingly, set the enable flag in the read rate control register, and configure the read threshold in the read threshold configuration register.

[0122] S202: When the read rate control mechanism is enabled, the number of read requests sent by the terminal device to the processor via the switch compliant with the high-speed serial computer expansion bus standard is less than a read threshold corresponding to the terminal device.

[0123] It should be noted that when a terminal device issues several long read requests in succession, if the port link is narrow, the speed of receiving these read data packets becomes very slow, and the waiting time for other read requests will become longer, thereby affecting performance. Therefore, this embodiment reduces the number of queued read requests by adjusting the number of read requests issued by downstream devices, providing sufficient service for all downstream devices. When a new read request arrives at the downstream port, the new request can be reasonably processed based on the number of read requests already waiting. The maximum number of unfinished data requests that can be issued by the port requesting to read is the read threshold (Read Threshold) to be set.

[0124] When the read rate control mechanism is enabled, the number of read requests sent by the terminal device to the processor through the PCIe switch is less than its corresponding read threshold.

[0125] As an optional embodiment, before configuring the read threshold corresponding to the terminal device in the read threshold configuration register, the method further includes: determining the read threshold corresponding to the terminal device based on the bandwidth between the switch and the terminal device that complies with the high-speed serial computer expansion bus standard; wherein the read threshold is positively correlated with the bandwidth. In actual implementation, different bandwidths may correspond to different read threshold configuration registers. For example, the read threshold corresponding to a terminal device with an x16 bandwidth is 8 kilobytes (KB), the read threshold corresponding to a terminal device with an x8 bandwidth is 6 KB, the read threshold corresponding to a terminal device with an x4 bandwidth is 4 KB, and the read threshold corresponding to a terminal device with an x2 bandwidth is 2 KB.

[0126] As a feasible implementation, before determining the read threshold corresponding to the terminal device based on the bandwidth between the switch and the terminal device that complies with the high-speed serial computer expansion bus standard, the method further includes: using a binary search method to determine the read threshold corresponding to different bandwidths within a preset range. In actual implementation, the binary search method can be used to continuously find the most appropriate read threshold, without affecting performance, while ensuring that link traffic is controlled, avoiding link congestion, and improving performance.

[0127] Thus, this embodiment enables the read rate control mechanism and coordinates resource allocation for the read threshold corresponding to the terminal device, thereby adjusting the amount of read requests issued by the downstream and preventing the slowdown in receiving these read data packets that affects performance.

[0128] A communication link control device provided in an embodiment of the present application is introduced below. The communication link control device described below and the communication link control method described above can be referenced to each other.

[0129] Referring to FIG4 , a structural diagram of a communication link control device according to an exemplary embodiment is shown. As shown in FIG4 , the device includes:

[0130] A first control module 401 is configured to control the activation of a credit timeout mechanism of a target communication link, wherein the target communication link is a communication link between a switch and a terminal device that complies with a high-speed serial computer expansion bus standard;

[0131] The execution subject of this embodiment is a PCIe switch, and the communication link between the PCIe switch and the terminal device is the target communication link. In actual implementation, when initializing the PCIe switch, the credit timeout mechanism of the target communication link is enabled by configuring the PCIe switch.

[0132] It should be noted that this embodiment does not limit the method for enabling the credit timeout mechanism. As a feasible implementation, the first control module 401 is configured to: determine a credit timeout mechanism register for the target communication link; wherein the credit timeout mechanism register is configured to control whether the credit timeout mechanism is enabled; and set an enable flag in the credit timeout mechanism register to control the activation of the credit timeout mechanism.

[0133] It can be understood that, in the target communication link, a plurality of registers are provided to implement data communication, among which the credit timeout mechanism register that is set to control whether the credit timeout mechanism is enabled is determined.

[0134] As a feasible implementation manner, the first control module 401 is configured to: traverse the registers corresponding to the target communication link to determine the credit timeout mechanism register.

[0135] As a feasible implementation, the first control module 401 is configured to: utilize a software toolkit to traverse registers corresponding to the target communication link to determine the credit timeout mechanism register.

[0136] In actual implementation, the registers corresponding to the target communication link can be traversed based on the PLX_SDK software toolkit. The PLX_SDK software toolkit provides some well-tested tools for compiling, debugging, and driving user programs to determine the credit timeout mechanism registers.

[0137] Optionally, after determining the credit timeout mechanism register, an enable flag is set in it to control the activation of the credit timeout mechanism. For example, the flag of the credit timeout mechanism register can be set to 0, where 0 indicates enable and 1 indicates disable.

[0138] As a feasible implementation, the first control module 401 is configured to set an enable flag in the credit timeout mechanism register via a command line command. In actual implementation, the enable flag can be set in the credit timeout mechanism register via a command line command such as setpci.

[0139] As a feasible implementation, the first control module 401 is configured to set an enable flag in the credit timeout mechanism register via a configuration management tool. In actual implementation, the enable flag in the credit timeout mechanism register can be set via a configuration management tool, such as Chiplink (Microchip configuration management tool) or a small tool in the PLX_SDK toolkit.

[0140] As a feasible implementation, the first control module 401 is configured to generate a first configuration file based on the configuration information of the credit timeout mechanism register with the enable flag set, and use the first configuration file to configure a switch that complies with the high-speed serial computer expansion bus standard to set the enable flag in the credit timeout mechanism register. In actual implementation, the first configuration file is generated based on the configuration information of the credit timeout mechanism register with the enable flag set. The first configuration file can implement batch configuration of communication links. Using the first configuration file to configure a PCIe switch can involve using the configuration information in the first configuration file to configure registers corresponding to target communication links in the PCIe switch, thereby setting the enable flag in the credit timeout mechanism register of the target communication link.

[0141] The sending module 402 is configured to send a notification of target communication link disconnection to the processor when the credit queue sent by the terminal device is not received within a target time period when the credit timeout mechanism is enabled; wherein the target time period is less than the completion timeout period of the high-speed serial computer expansion bus standard.

[0142] In practice, if the credit timeout mechanism is enabled and no credit queue is received within a target duration, a faulty port communication link disconnection event is declared, sending a notification of the target communication link disconnection to the processor. The credit timeout mechanism works as follows: The protocol stipulates that when a link is in the L0 or L0s state, a credit queue update must be transmitted at least every 30us (0% / +50%). After the target duration timer expires, the LTSSM is used to restore the state, instructing the physical layer to retrain the link.

[0143] This embodiment does not limit the value of the target duration. It only needs to be less than the completion timeout of the PCIe basic specification to quickly notify the processor that the communication link is disconnected. For example, the target duration can be 1.024ms.

[0144] The communication link control device provided in the embodiment of the present application uses a credit timeout mechanism to notify the processor of communication link disconnection within a target duration when a PCIe cable is hot-plugged, that is, when a port failure of a PCIE switch occurs, thereby avoiding communication congestion of the PCIe switch and improving the efficiency of link disconnection event processing.

[0145] Based on the above embodiment, as an optional implementation manner, the following is further included:

[0146] The second control module is configured to control the read rate control mechanism of the target communication link to be turned on and set a read threshold corresponding to the terminal device; when the read rate control mechanism is turned on, the number of read requests sent by the terminal device to the processor through a switch that complies with the high-speed serial computer expansion bus standard is less than the read threshold corresponding to the terminal device.

[0147] In actual implementation, when initializing the PCIe switch, the read rate control mechanism of the target communication link is enabled by configuring the PCIe switch, and the read threshold corresponding to each terminal device is set.

[0148] It should be noted that this embodiment does not limit the method for enabling the read rate control mechanism and setting the read threshold. As a feasible implementation, the second control module is configured to: determine the read rate control register and read threshold configuration register of the target communication link; set an enable flag in the read rate control register to control the activation of the read rate control mechanism; and configure the read threshold corresponding to the terminal device in the read threshold configuration register.

[0149] It is understood that a plurality of registers are provided in the target communication link to implement data communication, among which a control read rate control mechanism register configured to control whether the read rate control mechanism is enabled and a read threshold configuration register configured to configure a read threshold are determined. Based on the inherent characteristics of the control read rate control mechanism register, when the control read rate control mechanism register is enabled, the read rate control mechanism is enabled, and when the control read rate control mechanism register is disabled, the read rate control mechanism is disabled.

[0150] As a feasible implementation method, the second control module is configured to: determine the flow control register of the target communication link, and determine the read rate control register and the read threshold configuration register in the flow control register. In actual implementation, the flow control register of the target communication link can be determined first, and the registers corresponding to the target communication link can be traversed to determine the flow control register. For example, for a certain type of PCIe switch, its flow control register is the F30 register. Then, the read rate control register and the read threshold configuration register are determined in the flow control register, which can be understood as the read rate control register and the read threshold configuration register being sub-registers in the flow control register. For example, for a certain type of PCIe switch, the 1D0 register in the F30 register is the read rate control register, and bits 0 to 3 of the 1D0 register are set to 0 to enable the read rate control mechanism. The 1D4 register is the read threshold configuration register, and the read threshold is set by configuring bits 0 to 12 of the 1D4 register.

[0151] Based on the above embodiment, as an optional implementation manner, the second control module is configured to: traverse the registers corresponding to the target communication link to determine the flow control register.

[0152] Based on the above embodiment, as an optional implementation, the second control module is configured to: determine a read rate control register in the flow control register; determine a corresponding read threshold configuration register in the flow control register based on the bandwidth between the switch and the terminal device that complies with the high-speed serial computer expansion bus standard.

[0153] In an optional implementation, different bandwidths may correspond to different read threshold configuration registers. For example, for a certain type of PCIe switch, register 1D4 may be configured to correspond to the read threshold for terminal devices with x16 and x8 bandwidths, while register 1D8 may be configured to correspond to the read threshold for terminal devices with x4 and x2 bandwidths.

[0154] Optionally, after determining the read rate control register and read threshold configuration register of the target communication link, an enable flag is set in the read rate control register to control the start of the read rate control mechanism, and the read threshold corresponding to the terminal device is configured in the read threshold configuration register.

[0155] As a feasible implementation, the second control module is configured to: set an enable flag in a read rate control register via a command line command to enable the read rate control mechanism; and configure a read threshold corresponding to the terminal device in a read threshold configuration register via a command line command. In actual implementation, the enable flag in the read rate control register and the read threshold corresponding to the terminal device in the read threshold configuration register can be set via a command line command such as setpci.

[0156] As a feasible implementation, the second control module is configured to: set an enable flag in the read rate control register via a configuration management tool to enable the read rate control mechanism; and configure the read threshold corresponding to the terminal device in the read threshold configuration register via the configuration management tool. In actual implementation, the enable flag in the read rate control register and the read threshold corresponding to the terminal device in the read threshold configuration register can be set via a configuration management tool, such as a tool in Chiplink or the PLX_SDK toolkit.

[0157] As a feasible implementation, the second control module is configured to: generate a second configuration file based on the configuration information of the read rate control register with the enable flag set and the read threshold corresponding to the terminal device; and use the second configuration file to set the enable flag in the read rate control register and configure the read threshold corresponding to the terminal device in the read threshold configuration register. In actual implementation, the second configuration file is generated based on the configuration information of the read rate control register with the enable flag set and the read threshold corresponding to the terminal device. The second configuration file can implement batch configuration of communication links, and the second configuration file is used to configure the PCIe switch. The process can be to use the configuration information and read threshold in the second configuration file to configure the register corresponding to the target communication link in the PCIe switch accordingly, set the enable flag in the read rate control register, and configure the read threshold in the read threshold configuration register.

[0158] Based on the above embodiment, as an optional implementation manner, the following is further included:

[0159] The first determination module is configured to determine a read threshold corresponding to the terminal device according to a bandwidth between a switch conforming to a high-speed serial computer expansion bus standard and the terminal device; wherein the read threshold is positively correlated with the bandwidth.

[0160] In actual implementation, different bandwidths may correspond to different read threshold configuration registers. For example, a terminal device with x16 bandwidth corresponds to a read threshold of 8KB, a terminal device with x8 bandwidth corresponds to a read threshold of 6KB, a terminal device with x4 bandwidth corresponds to a read threshold of 4KB, and a terminal device with x2 bandwidth corresponds to a read threshold of 2KB.

[0161] Based on the above embodiment, as an optional implementation manner, the following is further included:

[0162] The second determining module is configured to determine the reading thresholds corresponding to different bandwidths within a preset range by using a dichotomy method.

[0163] In actual implementation, the most appropriate reading threshold can be continuously found through the binary search method, which will not affect performance while ensuring the effect of controlling the flow of the link, avoiding communication congestion on the link, and improving performance.

[0164] Thus, this embodiment enables the read rate control mechanism and coordinates resource allocation for the read threshold corresponding to the terminal device, thereby adjusting the amount of read requests issued by the downstream and preventing the slowdown in receiving these read data packets that affects performance.

[0165] Regarding the apparatus in the above embodiment, the manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated on here.

[0166] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiment of the present application, the embodiment of the present application further provides an electronic device. FIG5 is a structural diagram of an electronic device according to an exemplary embodiment. As shown in FIG5 , the electronic device includes:

[0167] Communication interface 1, capable of exchanging information with other devices such as network devices;

[0168] The processor 2 is connected to the communication interface 1 to implement information exchange with other devices and is configured to execute the communication link control method provided by one or more of the above technical solutions when running a computer program. The computer program is stored in the memory 3.

[0169] Of course, in actual applications, the various components in the electronic device are coupled together via bus system 4. It will be appreciated that bus system 4 is configured to enable communication between these components. In addition to a data bus, bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in FIG5 , all of these buses are labeled as bus system 4.

[0170] The memory 3 in the embodiment of the present application is configured to store various types of data to support the operation of the electronic device. Examples of such data include any computer program used to operate on the electronic device.

[0171] It is understood that the memory 3 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a magnetic disk memory or a magnetic tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM).The memory 3 described in the embodiments of the present application is intended to include but is not limited to these and any other suitable types of memories.

[0172] The method disclosed in the above-mentioned embodiment of the present application can be applied to processor 2 or implemented by processor 2. Processor 2 may be an integrated circuit device with signal processing capabilities. During implementation, each step of the above-mentioned method can be completed by the integrated logic circuit of the hardware in processor 2 or instructions in the form of software. The above-mentioned processor 2 can be a general-purpose processor, DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. Processor 2 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a non-volatile readable storage medium, which is located in memory 3. Processor 2 reads the program in memory 3 and completes the steps of the above-mentioned method in combination with its hardware.

[0173] When the processor 2 executes the program, the corresponding processes in each method of the embodiment of the present application are implemented. For the sake of brevity, they are not repeated here.

[0174] In an exemplary embodiment, the present application also provides a non-volatile readable storage medium, for example, a computer-readable non-volatile storage medium, including, for example, a memory 3 storing a computer program, which can be executed by a processor 2 to perform the aforementioned method steps. The computer-readable non-volatile storage medium can be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface storage, optical disk, CD-ROM, or the like.

[0175] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer non-volatile readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned non-volatile readable storage medium includes: various non-volatile readable storage media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

[0176] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer non-volatile readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a non-volatile readable storage medium, including a number of instructions for enabling an electronic device (which can be a personal computer, server, network device, etc.) to execute all or part of the methods of each embodiment of the present application. The aforementioned non-volatile readable storage medium includes: various non-volatile readable storage media that can store program code, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

[0177] The above are only optional implementation methods of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A communication link control method, characterized in that: Applied to a switch conforming to a high-speed serial computer expansion bus standard, a processor is connected to a terminal device via the switch conforming to the high-speed serial computer expansion bus standard, and the method includes: Controlling the activation of a credit timeout mechanism of a target communication link; wherein the target communication link is a communication link between the switch conforming to the high-speed serial computer expansion bus standard and the terminal device; When the credit timeout mechanism is enabled, when the credit queue sent by the terminal device is not received within a target time period, a notification of disconnection of the target communication link is sent to the processor; wherein the target time period is less than the completion timeout period of the high-speed serial computer expansion bus standard.

2. The communication link control method according to claim 1, characterized in that: Controls the credit timeout mechanism of the target communication link, including: Determining a credit timeout mechanism register of a target communication link; wherein the credit timeout mechanism register is configured to control whether a credit timeout mechanism is enabled; An enable flag is set in the credit timeout mechanism register to control the activation of the credit timeout mechanism.

3. The communication link control method according to claim 2, characterized in that: Determines the credit timeout mechanism register for the target communication link, including: The registers corresponding to the target communication link are traversed to determine the credit timeout mechanism register.

4. The communication link control method according to claim 2, wherein: Traverse the registers corresponding to the target communication link to determine the credit timeout mechanism register, including: Use the software toolkit to traverse the registers corresponding to the target communication link to determine the credit timeout mechanism register.

5. The communication link control method according to claim 2, wherein: Setting an enable flag bit in the credit timeout mechanism register includes: An enable flag is set in the credit timeout mechanism register via a command line command.

6. The communication link control method according to claim 2, characterized in that: Setting an enable flag bit in the credit timeout mechanism register includes: An enable flag is set in the credit timeout mechanism register through a configuration management tool.

7. The communication link control method according to claim 2, characterized in that: Setting an enable flag bit in the credit timeout mechanism register includes: A first configuration file is generated based on the configuration information of the credit timeout mechanism register with the enable flag set, and the switch compliant with the high-speed serial computer expansion bus standard is configured using the first configuration file to set the enable flag in the credit timeout mechanism register.

8. The communication link control method according to claim 1, wherein: Also includes: Controlling the read rate control mechanism of the target communication link to start, and setting the read threshold corresponding to the terminal device; When the read rate control mechanism is enabled, the number of read requests sent by the terminal device to the processor via the switch compliant with the high-speed serial computer expansion bus standard is less than a read threshold corresponding to the terminal device.

9. The communication link control method according to claim 8, characterized in that: Controlling the read rate control mechanism of the target communication link to start, and setting the read threshold corresponding to the terminal device, including: Determining a read rate control register and a read threshold configuration register of the target communication link; An enable flag is set in the read rate control register to control the start of the read rate control mechanism, and a read threshold corresponding to the terminal device is configured in the read threshold configuration register.

10. The communication link control method according to claim 9, characterized in that: Determining a read rate control register and a read threshold configuration register of the target communication link, comprising: A flow control register of the target communication link is determined, and a read rate control register and a read threshold configuration register are determined in the flow control register.

11. The communication link control method according to claim 10, characterized in that: Determining a flow control register of the target communication link includes: Traverse the registers corresponding to the target communication link to determine the flow control register.

12. The communication link control method according to claim 10, characterized in that: Determining a read rate control register and a read threshold configuration register in the flow control register includes: determining a read rate control register in the flow control register; In the flow control register, a corresponding read threshold configuration register is determined according to the bandwidth between the switch conforming to the high-speed serial computer expansion bus standard and the terminal device.

13. The communication link control method according to claim 9, characterized in that: Setting an enable flag in the read rate control register to control the start of the read rate control mechanism, and configuring the read threshold corresponding to the terminal device in the read threshold configuration register, including: Setting an enable flag in the read rate control register via a command line command to control the read rate control mechanism to be enabled; The read threshold corresponding to the terminal device is configured in the read threshold configuration register through a command line command.

14. The communication link control method according to claim 9, characterized in that: Setting an enable flag in the read rate control register to control the start of the read rate control mechanism, and configuring the read threshold corresponding to the terminal device in the read threshold configuration register, including: Setting an enable flag in the read rate control register through a configuration management tool to control the read rate control mechanism to be enabled; The read threshold corresponding to the terminal device is configured in the read threshold configuration register through a configuration management tool.

15. The communication link control method according to claim 9, characterized in that: Setting an enable flag in the read rate control register to control the start of the read rate control mechanism, and configuring the read threshold corresponding to the terminal device in the read threshold configuration register, including: Generate a second configuration file based on the configuration information of the read rate control register in which the enable flag is set and the read threshold corresponding to the terminal device; The second configuration file is used to set an enable flag in the read rate control register and to configure a read threshold corresponding to the terminal device in the read threshold configuration register.

16. The communication link control method according to claim 9, characterized in that: Before configuring the read threshold corresponding to the terminal device in the read threshold configuration register, the method further includes: The reading threshold corresponding to the terminal device is determined according to the bandwidth between the switch conforming to the high-speed serial computer expansion bus standard and the terminal device; wherein the reading threshold is positively correlated with the bandwidth.

17. The communication link control method according to claim 16, characterized in that: Before determining the read threshold corresponding to the terminal device according to the bandwidth between the switch conforming to the high-speed serial computer expansion bus standard and the terminal device, the method further includes: The reading threshold corresponding to different bandwidths is determined within a preset range using the dichotomy method.

18. A communication link control device, characterized in that: The device is applied to a switch conforming to the high-speed serial computer expansion bus standard, wherein a processor is connected to a terminal device via the switch conforming to the high-speed serial computer expansion bus standard, and the switch conforming to the high-speed serial computer expansion bus standard is connected to the terminal device via a mini serial connection small computer system interface cable. The device comprises: A first control module is configured to control the activation of a credit timeout mechanism of a target communication link; wherein the target communication link is a communication link between the switch conforming to the high-speed serial computer expansion bus standard and the terminal device; The sending module is configured to send a notification of disconnection of the target communication link to the processor when the credit queue sent by the terminal device is not received within a target time period when the credit time period is enabled; wherein the target time period is less than the completion timeout period of the high-speed serial computer expansion bus standard.

19. An electronic device, characterized in that: include: a memory arranged to store a computer program; A processor is configured to implement the steps of the communication link control method according to any one of claims 1 to 17 when executing the computer program.

20. A computer-readable non-volatile storage medium, characterized in that: The computer non-volatile readable storage medium stores a computer program, and when the computer program is executed, the steps of the communication link control method according to any one of claims 1 to 17 are implemented.

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