Clock calibration method and time-interleaved analog digital converter

Abstract

The present disclosure provides a clock calibration method, comprising: acquiring an output value of each ADC in a TIADC, wherein the TIADC comprises at least two ADCs connected in parallel, and each ADC sequentially samples according to a sampling sequence; for each ADC, calculating a first correlation value and a second correlation value of the ADC on the basis of the output value of the ADC and the output values of two ADCs adjacent to the ADC in the sampling sequence; and calibrating a clock phase of the ADC on the basis of the first correlation value and the second correlation value. The present disclosure further provides a TIADC.

Description

Clock calibration method and time-interleaved analog-to-digital converter

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application CN 202410377599.4, entitled “Clock Calibration Method and Time-Interleaved Analog-to-Digital Converter,” filed on March 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of signal processing technology, and in particular to a clock calibration method and a time-interleaved analog-to-digital converter. Background Art

[0004] The rapidly developing fields of AI (Artificial Intelligence) and data-intensive applications are driving high-performance interconnect technologies. AI applications, with their massive data sets and complex algorithms, are driving unprecedented demands for data transmission speeds. To support newer, faster data interfaces, transceiver speeds need to be significantly increased. Consequently, receiver architectures based on TIADC (Time-Interleaved Analog Digital Converter) are becoming mainstream. The performance of each ADC (Analog Digital Converter) in the TIADC is a key factor influencing receiver performance.

[0005] Affected by various physical and electrical characteristics, ADC has the problem of sampling time mismatch, which is the key difficulty in calibrating TIADC. Summary of the Invention

[0006] In view of the above shortcomings, the present disclosure provides a clock calibration method and a TIADC.

[0007] An embodiment of the present disclosure provides a clock calibration method, comprising: obtaining an output value of each ADC in a TIADC, wherein the TIADC includes at least two ADCs connected in parallel, and each ADC performs sampling in sequence; for each ADC, calculating a first correlation value and a second correlation value of the ADC based on the output value of the ADC and output values ​​of two ADCs adjacent to the ADC in the sampling sequence; and calibrating a clock phase of the ADC based on the first correlation value and the second correlation value.

[0008] An embodiment of the present disclosure provides a TIADC, comprising: at least two ADCs connected in parallel; a processing module, configured to obtain an output value of each ADC in the TIADC, wherein each ADC performs sampling in sequence; and, for each ADC, calculate a first correlation value and a second correlation value of the ADC based on the output value of the ADC and the output values ​​of two ADCs adjacent to the ADC in the sampling sequence; and a calibration module, configured to calibrate a clock phase of the ADC based on the first correlation value and the second correlation value. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG1 is a schematic diagram of the structure of a TIADC provided in an embodiment of the present disclosure;

[0010] FIG2 is a flow chart of a clock calibration method provided by an embodiment of the present disclosure;

[0011] FIG3 is a flowchart of a specific implementation of step S3 in the clock calibration method provided by an embodiment of the present disclosure;

[0012] FIG4 is a flowchart of a specific implementation of step S32 in the clock calibration method provided by an embodiment of the present disclosure;

[0013] FIG5 is a flowchart of a specific implementation of step S321 in the clock calibration method provided by an embodiment of the present disclosure;

[0014] FIG6 is a schematic diagram of the structure of a TIADC provided in an embodiment of the present disclosure;

[0015] FIG7 is a schematic diagram of the structure of a TIADC provided in an embodiment of the present disclosure;

[0016] FIG8 is a schematic diagram of the output spectrum of the TIADC before clock calibration according to an embodiment of the present disclosure;

[0017] FIG9 is a schematic diagram of an output spectrum of a TIADC after clock calibration according to an embodiment of the present disclosure;

[0018] FIG10 is a schematic diagram illustrating changes in the output spectrum of the TIADC during a clock calibration process according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the clock calibration method of the control and the TIADC provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0020] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.

[0021] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0022] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] The terms used herein are used only to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof is not excluded.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0025] In this disclosure, unless otherwise specified, the following technical terms should be understood according to the following explanations.

[0026] TIADC connects multiple ADCs in parallel, staggering the sampling clocks of each ADC so that they can sample the same signal in a temporally staggered manner. The sampling results from each ADC are then combined, thereby achieving high-speed sampling. TIADC offers advantages such as high sampling speed, low power consumption, and low cost. However, the ADCs connected in parallel in TIADC may experience sampling time mismatches. The embodiments of the present disclosure do not limit the type of ADC in TIADC. TIADC can be single-stage, dual-stage, or triple-stage, and the present disclosure is not limited thereto.

[0027] Sampling mismatch refers to a mismatch between the actual sampling moment of an ADC and the actual changes in the signal it is sampling. Although each ADC samples at a fixed frequency, if the signal changes faster than the sampling frequency, the sampling moment may not match the signal's changes, resulting in a mismatch. This in turn introduces errors, affecting signal reconstruction and analysis.

[0028] FIG1 is a schematic diagram of the structure of a TIADC provided by an embodiment of the present disclosure.

[0029] Referring to Figure 1, in some embodiments, the TIADC includes a first analog-to-digital converter (ADC1), a second analog-to-digital converter (ADC2), a third analog-to-digital converter (ADC3), and a fourth analog-to-digital converter (ADC4) arranged in parallel. The output values ​​sampled by ADC1, ADC2, ADC3, and ADC4 are synchronized and output in parallel, thereby obtaining the output result of the TIADC. If there is a mismatch in the sampling times of ADC1, ADC2, ADC3, and ADC4, calibration of ADC1, ADC2, ADC3, and ADC4 is required.

[0030] Some related technologies pre-input a single-tone sinusoidal or quasi-sinusoidal signal into the TIADC, then use an algorithm to estimate the sampling time mismatch of each ADC in the TIADC before calibration. However, this calibration method requires interrupting the normal operation of each ADC in the TIADC and cannot be performed while the ADCs are operating normally. In other words, this calibration method can only be used for foreground calibration. Therefore, it may lead to problems such as being unable to calibrate in time after a sampling time mismatch occurs, or frequent foreground calibration leading to reduced TIADC operating efficiency.

[0031] In other related technologies, an additional ADC sampling channel is designed to serve as a reference, and the sampling channels of other ADCs are aligned with this reference sampling channel. However, this calibration method increases the overall analog circuit design complexity and sampling power consumption, and the calibration accuracy is not high.

[0032] Therefore, there is an urgent need for a TIADC clock calibration method that can support foreground and background calibration, has low computational complexity and higher calibration accuracy.

[0033] FIG2 is a flow chart of a clock calibration method provided by an embodiment of the present disclosure.

[0034] 2 , an embodiment of the present disclosure provides a clock calibration method, including the following steps S1 to S3 .

[0035] In step S1 , the output value of each ADC in the TIADC is obtained, wherein the TIADC includes at least two ADCs connected in parallel, and each ADC performs sampling in sequence.

[0036] In step S2 , for each ADC, a first correlation value and a second correlation value of the ADC are calculated based on the output value of the ADC and the output values ​​of two ADCs adjacent to the ADC in sampling order.

[0037] In step S3, the clock phase of the ADC is calibrated according to the first correlation value and the second correlation value.

[0038] In an embodiment of the present disclosure, a correlation value (i.e., a first correlation value and a second correlation value) is calculated between the output value of each ADC and the output values ​​of two ADCs adjacent to it in the sampling order. The correlation value can reflect the sampling time relationship between the ADC and the ADCs adjacent to it in the sampling order. In some embodiments, in the absence of a sampling time mismatch, the correlation values ​​between the ADC and the two adjacent ADCs before and after it in the sampling order should be the same or similar, so that the sampling time mismatch size of the ADC can be estimated by the correlation value, and the clock phase of the ADC can be calibrated. The computational complexity of this calibration process is low, it will not affect the sampling process of the TIADC, it can support foreground and background calibration, and can effectively improve the overall performance of the ADC.

[0039] In some embodiments, a TIADC includes at least two parallel ADCs. The sampling sequence refers to multiple rounds of cyclic sampling performed by a limited number of parallel ADCs. Each round of cyclic sampling means that each ADC performs a sample once in a fixed order. As an example, a TIADC with three sampling channels includes three sampling switches and three parallel ADCs, ADC1, ADC2, and ADC3. These three ADCs perform multiple rounds of cyclic sampling, and in each round of cyclic sampling, ADC1, ADC2, and ADC3 each perform a sample once in a fixed order.

[0040] The two ADCs adjacent to an ADC in a sampling order refer to an ADC that performs sampling before the ADC and an ADC that performs sampling after the ADC.

[0041] In some embodiments, step S2 includes: multiplying the output value of the ADC with the output values ​​of two adjacent ADCs respectively to obtain a first correlation value and a second correlation value of the ADC, wherein the two adjacent ADCs are adjacent to the ADC in sampling order.

[0042] As an example, a TIADC with N channels includes N sampling switches and N parallel ADCs. In the fixed order of each round of sampling, the N ADCs are named ADC1 to ADC N , where for ADC2, its adjacent ADCs are ADC1 and ADC3 respectively, the first correlation value between ADC2 and ADC1 is Y1=output value of ADC1*output value of ADC2, and the second correlation value between ADC2 and ADC3 is Y2=output value of ADC2*output value of ADC3.

[0043] FIG3 is a flowchart of a specific implementation of step S3 in the clock calibration method provided by an embodiment of the present disclosure.

[0044] 3 , in some embodiments, step S3 includes the following steps S31 to S32 .

[0045] In step S31 , a clock position deviation value between the ADC and two adjacent ADCs is calculated based on the first correlation value and the second correlation value.

[0046] In step S32, the clock phase of the ADC is calibrated according to the clock position deviation value.

[0047] In an embodiment of the present disclosure, since the TIADC includes at least two parallel ADCs, the correlation values ​​between adjacent ADCs in the sampling order should be the same or similar, that is, the first correlation value is the same or similar to the second correlation value, so the clock position deviation value between the ADC and the two adjacent ADCs can be obtained by calculating the difference between the first correlation value and the second correlation value. The clock position deviation value can reflect the direction and magnitude of the clock position deviation of the ADC. In some embodiments, the absolute value of the difference between the first correlation value and the second correlation value can reflect the magnitude of the clock position deviation, that is, the magnitude of the error value of the sampling time mismatch; the positive or negative value of the difference between the first correlation value and the second correlation value can reflect the direction of the clock position deviation, so that the clock phase of the ADC can be calibrated according to the clock position deviation value.

[0048] In some embodiments, when the clock position deviation value is within a preset deviation range (ie, the first correlation value is close to the second correlation value), the clock phase of the ADC does not need to be calibrated.

[0049] It should be noted that the difference between the first correlation value and the second correlation value can be the first correlation value minus the second correlation value, or the second correlation value minus the first correlation value. The calculation method can be unified in each ADC of the same TIADC, and the present disclosure is not limited to this.

[0050] As an example, for ADC2, its adjacent ADCs are ADC1 and ADC3, the first correlation value between ADC2 and ADC1 is Y1=output value of ADC1*output value of ADC2, the second correlation value between ADC2 and ADC3 is Y2=output value of ADC2*output value of ADC3, and the clock position deviation value of ADC2 is D=Y1-Y2.

[0051] In some embodiments, step S2 may further include: subtracting the output value of the ADC from the output values ​​of two adjacent ADCs respectively to obtain a first difference and a second difference, wherein the two adjacent ADCs are adjacent to the ADC in sampling order; determining the absolute value of the first difference as the first correlation value of the ADC, and determining the absolute value of the second difference as the second correlation value of the ADC.

[0052] As an example, a TIADC with N channels includes N sampling switches and N parallel ADCs. In the fixed order of each round of sampling, the N ADCs are named ADC1 to ADC N , where for ADC2, its adjacent ADCs are ADC1 and ADC3 respectively, the first correlation value between ADC2 and ADC1 is Y1 = |output value of ADC1 - output value of ADC2|, and the second correlation value between ADC2 and ADC3 is Y2 = |output value of ADC2 - output value of ADC3|.

[0053] In some embodiments, when the correlation value is the absolute value of the difference obtained by subtracting the output values ​​of two ADCs adjacent in the sampling order, step S3 includes: calculating the clock position deviation value between the ADC and the two adjacent ADCs based on the first correlation value and the second correlation value; and calibrating the clock phase of the ADC based on the clock position deviation value.

[0054] In an embodiment of the present disclosure, since the TIADC includes at least two parallel ADCs, the correlation values ​​between adjacent ADCs in the sampling order should be the same or similar, that is, the first correlation value is the same or similar to the second correlation value, so the clock position deviation value between the ADC and the two adjacent ADCs can be obtained by calculating the difference between the first correlation value and the second correlation value. The clock position deviation value can reflect the direction and magnitude of the clock position deviation of the ADC. In some embodiments, the absolute value of the difference between the first correlation value and the second correlation value can reflect the magnitude of the clock position deviation, that is, the magnitude of the error value of the sampling time mismatch; the positive or negative value of the difference between the first correlation value and the second correlation value can reflect the direction of the clock position deviation, so that the clock phase of the ADC can be calibrated according to the clock position deviation value.

[0055] In some embodiments, when the clock position deviation value is within a preset deviation range (ie, the first correlation value is close to the second correlation value), the clock phase of the ADC does not need to be calibrated.

[0056] It should be noted that the difference between the first correlation value and the second correlation value can be the first correlation value minus the second correlation value, or the second correlation value minus the first correlation value. The calculation method can be unified in each ADC of the same TIADC, and the present disclosure is not limited to this.

[0057] As an example, for ADC2, its adjacent ADCs are ADC1 and ADC3, the first correlation value between ADC2 and ADC1 is Y1 = |output value of ADC1 - output value of ADC2|, the second correlation value between ADC2 and ADC3 is Y2 = |output value of ADC2 - output value of ADC3|, and the clock position deviation value of ADC2 is D = Y1-Y2.

[0058] FIG4 is a flowchart of a specific implementation of step S32 in the clock calibration method provided by an embodiment of the present disclosure.

[0059] 4 , in some embodiments, step S32 includes the following steps S321 to S322 .

[0060] In step S321, the control word of the ADC is determined according to the clock position deviation value.

[0061] In step S322, the clock phase of the ADC is calibrated according to the control word of the ADC.

[0062] In this embodiment, the delay line can be adjusted by the control word to change the sampling clock phase of the ADC. The embodiment of the present disclosure does not impose any special restrictions on the method of determining the control word, which can be LMS (Least Mean Squares) or other methods.

[0063] FIG5 is a flowchart of a specific implementation of step S321 in the clock calibration method provided by an embodiment of the present disclosure.

[0064] 5 , in some embodiments, step S321 includes the following steps S3211 to S3212 .

[0065] In step S3211, the first control word of the ADC preceding the ADC in the sampling order is obtained.

[0066] In step S3212, the first control word is subtracted from the product of the clock position deviation value of the ADC and the preset control coefficient to obtain the control word of the ADC.

[0067] In the embodiment of the present disclosure, the clock position deviation values ​​corresponding to different sampling moments of the ADC obtained in the sampling order are iteratively calculated by LMS to obtain the control word of the ADC. As an example, LMS uses formula D skew(ck1),n+1 =D skew(ck1),n -μ*d1 calculates the control word of ADC, where D skew(ck1),n is the control word of the previous ADC (ie, the first control word), D skew(ck1),n+1is the current ADC control word, d1 is the current ADC clock position deviation value, and μ is the convergence coefficient. The disclosed embodiments do not impose any specific restrictions on the value of the convergence coefficient μ, which can be determined based on actual needs. The value of the convergence coefficient μ affects the convergence speed: a larger μ results in faster convergence and poorer calibration results, while a smaller μ results in slower convergence and better calibration results.

[0068] In the embodiments of the present disclosure, there is no special limitation on the method of calibrating the clock phase of the ADC according to the control word. It can be parallel calibration before the start of each round of sampling in accordance with the sampling order, or it can be calibrated once each time the control word of an ADC is calculated, or it can be calibrated based on one ADC in the TIADC.

[0069] In some embodiments, step S322 includes: calibrating clock phases of all ADCs in parallel according to control words of all ADCs in the TIADC within a preset period, wherein all ADCs in the TIADC perform sampling once within the preset period.

[0070] In this embodiment, the preset period refers to each sampling round in a plurality of sampling rounds performed in a sampling order, and before the start of each sampling round, all ADCs are calibrated in parallel according to their control words. The embodiments of the present disclosure do not impose any particular limitation on the length of the preset period.

[0071] In some further embodiments, step S322 includes: calibrating the clock phase of each ADC in sequence according to the sampling order based on the control word of each ADC in the TIADC.

[0072] In this embodiment, based on the control word of each ADC in the TIADC, the clock phase of each ADC may be calibrated in a different order for each sampling round, rather than in the sampling order. As an example, the TIADC includes parallel ADC1, ADC2, ADC3, and ADC4, where the clock of ADC1 is ck1, the clock of ADC2 is ck2, the clock of ADC3 is ck3, and the clock of ADC4 is ck4. The clock phases of ck1, ck2, ck3, and ck4 may be calibrated in sequence in the sampling order, or ck3 may be calibrated first, followed by ck1, ck2, and ck4.

[0073] In some embodiments, step S322 includes: obtaining a control word of a preset ADC, where the preset ADC is one of at least two ADCs of the TIADC; and calibrating other ADCs except the preset ADC according to the control word of the preset ADC.

[0074] The embodiments of the present disclosure do not impose any particular restrictions on the manner in which the ADC in the TIADC is designated as the preset ADC. The designated preset ADC does not perform clock phase calibration, but calibrates other ADCs other than the preset ADC based on the clock of the preset ADC.

[0075] The embodiments of the present disclosure can calibrate the sampling time mismatch error of the ADC in the TIADC. In the embodiments of the present disclosure, the correlation value between the output value of each ADC and the output values ​​of the two ADCs adjacent to it in the sampling order is calculated. The correlation value can reflect the sampling time relationship between the ADC and the ADCs adjacent to it in the sampling order, so that the sampling time mismatch size of the ADC can be estimated by the correlation value, and the clock phase of the ADC can be calibrated to improve the linearity of the TIADC system. The sampling time error (i.e., the clock position deviation value) is extracted in the digital domain. The algorithm is simple and clear, does not require other additional reference channels, is easy to implement, and the computational complexity of the calibration process is low. It is not affected by PVT (Pressure-Temperature-Voltage) factors, has good compatibility, supports TIADCs with any number of channels, and supports foreground and background calibration.

[0076] FIG6 is a schematic diagram of the structure of a TIADC provided by an embodiment of the present disclosure.

[0077] 6 , an embodiment of the present disclosure provides a TIADC 600, comprising: at least two ADCs 601 connected in parallel; a processing module 602 for obtaining an output value of each ADC in the TIADC, wherein each ADC is sampled sequentially in a sampling order; for each ADC, calculating a first correlation value and a second correlation value of the ADC based on the output value of the ADC and the output values ​​of two ADCs adjacent to the ADC in the sampling order; and a calibration module 603 for calibrating a clock phase of the ADC based on the first correlation value and the second correlation value.

[0078] For a specific embodiment of how the processing module 602 calculates the first correlation value and the second correlation value of the ADC, and a specific embodiment of how the calibration module 603 calibrates the clock phase of the ADC, please refer to the corresponding parts in the clock calibration method embodiment according to the present disclosure. To avoid repetition, they are not repeated here.

[0079] The TIADC provided in the embodiments of the present disclosure is capable of implementing the various processes of the various embodiments of the above-mentioned clock calibration method. The technical features correspond one to one and can achieve the same technical effects. To avoid repetition, they are not described here.

[0080] In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present disclosure, the technical solutions provided by the embodiments of the present disclosure are described in detail below through specific examples.

[0081] Example 1

[0082] FIG7 is a schematic diagram of the structure of a TIADC provided in an embodiment of the present disclosure.

[0083] Referring to FIG7 , in one embodiment, the TIADC includes four ADC channels (ADC1, ADC2, ADC3, and ADC4). The output values ​​of the ADCs of two adjacent channels in sampling order are input to a multiplier, so that the output values ​​of the two ADCs are multiplied to obtain a correlation value. The output values ​​of the two adjacent multipliers are input to an adder-subtractor, which adds or subtracts the correlation value obtained by multiplication. The control word obtained by LMS calculation controls the clock phase of each ADC through a delay line.

[0084] Next, the clock calibration method of the TIADC is described.

[0085] In ADC4_0, ADC1_1, ADC2_1, ADC3_1, ADC4_1, and ADC1_2, the number after the underscore "_" indicates sampling round information, that is, the number of cycles in the preset period. ADC4's sampling in round 0 is sequentially adjacent to ADC1's sampling in round 1, ADC1's sampling in round 1 is sequentially adjacent to ADC2's sampling in round 1, ADC2's sampling in round 1 is sequentially adjacent to ADC3's sampling in round 1, ADC3's sampling in round 1 is sequentially adjacent to ADC4's sampling in round 1, and ADC4's sampling in round 1 is sequentially adjacent to ADC1's sampling in round 2.

[0086] Multiply the output value of ADC4 in the 0th round by the output value of ADC1 in the 1st round to obtain the first correlation value y1=ADC4_0*ADC1_1 of ADC1 in the 1st round; multiply the output value of ADC1 in the 1st round by the output value of ADC2 in the 1st round to obtain the second correlation value y2=ADC1_1*ADC2_1 of ADC1 in the 1st round (and also obtain the first correlation value of ADC2 in the 1st round); multiply the output value of ADC2 in the 1st round by the output value of ADC3 in the 1st round to obtain the second correlation value y2=ADC1_1*ADC2_1 of ADC1 in the 1st round. The second correlation value y3=ADC2_1*ADC3_1 (the first correlation value of ADC3 in the first round is also obtained); the output value of ADC3 in the first round is multiplied by the output value of ADC4 in the first round to obtain the second correlation value y4=ADC3_1*ADC4_1 of ADC3 in the first round (the first correlation value of ADC4 in the first round is also obtained); the output value of ADC4 in the first round is multiplied by the output value of ADC1 in the second round to obtain the second correlation value y5=ADC4_1*ADC1_2 of ADC4 in the first round.

[0087] Then, the first correlation value of each ADC is subtracted from the second correlation value to obtain the clock position deviation value. The clock position deviation value of ADC1 in the first round is d1 = y1 - y2, the clock position deviation value of ADC2 in the first round is d2 = y2 - y3, the clock position deviation value of ADC3 in the first round is d3 = y3 - y4, and the clock position deviation value of ADC4 in the first round is d4 = y4 - y5.

[0088] Substitute the clock position deviation values ​​d1, d2, d3, and d4 into the LMS calculation formula to obtain D skew(ck1),n+1 =D skew(ck1),n -μ*d1、D skew(ck2),n+1 =D skew(ck2),n -μ*d2、D skew(ck3),n+1 =D skew(ck3),n -μ*d3、D skew(ck4),n+1 =D skew(ck4),n -μ*d4.

[0089] D skew(ck1),n+1 is the control word of ADC1 in the delay line of the n+1th round, D skew(ck2),n+1 is the control word of ADC2's delay line in the n+1th round, D skew(ck3),n+1 It is the control word of ADC3 delay line in the n+1th round, D skew(ck4),n+1is the control word for ADC4's delay line in the n+1th round. In this example, n = 0, and μ is the convergence coefficient, which controls the rate of change of the calibration control word and can be set to 2e-6. The control word of each ADC sequentially affects the control word of the next ADC in the sampling order. The delay line controls the clock phase, shifting it forward or backward, completing a single clock calibration.

[0090] Each round of parallel calibration of the four-phase clocks can complete the calibration of the sampling time mismatch of the four-phase clocks after several cycles, thereby achieving the effect of calibrating the sampling time mismatch error of the TIADC.

[0091] Example 2

[0092] By detecting the output spectrum of the TIADC before and after clock calibration, the state of the sampling time mismatch error before and after clock calibration can be more intuitively observed.

[0093] FIG8 is a schematic diagram of the output spectrum of the TIADC before clock calibration according to an embodiment of the present disclosure, FIG9 is a schematic diagram of the output spectrum of the TIADC after clock calibration according to an embodiment of the present disclosure, and FIG10 is a schematic diagram of the change in the output spectrum of the TIADC during the clock calibration process according to an embodiment of the present disclosure.

[0094] 8 , it can be seen that before the TIADC performs clock calibration, there are obvious harmonics of the sampling time mismatch error, and the ENOB (effective number of bits) of the ADC is 4.7.

[0095] 9 , it can be seen that after the TIADC performs clock calibration, the ADC's ENOB is reduced to 6.8, and the harmonics of the previously obvious sampling time mismatch error are effectively reduced.

[0096] 10 , it can be seen that during the calibration process of each ADC (ie, ADC1 , ADC2 , ADC3 , ADC4 ) of the TIADC, the sampling time mismatch error gradually decreases.

[0097] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0098] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A clock calibration method, comprising: Obtaining an output value of each analog-to-digital converter ADC in a time-interleaved analog-to-digital converter TIADC, wherein the TIADC includes at least two ADCs connected in parallel, and each ADC performs sampling in sequence; For each ADC, calculating a first correlation value and a second correlation value of the ADC according to an output value of the ADC and output values ​​of two ADCs adjacent to the ADC in a sampling order; The clock phase of the ADC is calibrated according to the first correlation value and the second correlation value.

2. The clock calibration method according to claim 1, wherein: Calculating a first correlation value and a second correlation value of the ADC according to an output value of the ADC and output values ​​of two ADCs adjacent to the ADC in a sampling order includes: Multiplying the output value of the ADC with the output values ​​of two adjacent ADCs respectively to obtain a first correlation value and a second correlation value of the ADC, The two adjacent ADCs are adjacent to the ADC in sampling order.

3. The clock calibration method according to claim 1, wherein: Calculating a first correlation value and a second correlation value of the ADC according to an output value of the ADC and output values ​​of two ADCs adjacent to the ADC in a sampling order includes: subtracting the output value of the ADC from the output values ​​of two adjacent ADCs respectively to obtain a first difference and a second difference, wherein the two adjacent ADCs are adjacent to the ADC in a sampling order; An absolute value of the first difference is determined as a first correlation value of the ADC, and an absolute value of the second difference is determined as a second correlation value of the ADC.

4. The clock calibration method according to claim 2 or 3, wherein: Calibrating a clock phase of the ADC according to the first correlation value and the second correlation value includes: Calculating a clock position deviation value between the ADC and the two adjacent ADCs according to the first correlation value and the second correlation value; The clock phase of the ADC is calibrated according to the clock position deviation value.

5. The clock calibration method according to claim 4, wherein: Calibrating the clock phase of the ADC according to the clock position deviation value includes: Determining a control word of the ADC according to the clock position deviation value; The clock phase of the ADC is calibrated according to the control word of the ADC. The clock calibration method according to claim 5 , wherein: Determining a control word of the ADC according to the clock position deviation value includes: Obtain a first control word of an ADC preceding the ADC in sampling order; The first control word is subtracted from the product of the clock position deviation value of the ADC and a preset control coefficient to obtain the control word of the ADC.

7. The clock calibration method according to claim 5, wherein: Calibrating a clock phase of the ADC according to a control word of the ADC includes: According to the control words of all ADCs in the TIADC within a preset period, the clock phases of all ADCs are calibrated in parallel. Wherein, within the preset period, all ADCs in the TIADC perform sampling once each.

8. The clock calibration method according to claim 5, wherein: Calibrating a clock phase of the ADC according to a control word of the ADC includes: According to the control word of each ADC in the TIADC, the clock phase of each ADC is calibrated in sequence according to the sampling order.

9. The clock calibration method according to claim 5, wherein: Calibrating a clock phase of the ADC according to a control word of the ADC includes: Obtaining a control word of a preset ADC, wherein the preset ADC is one of the at least two ADCs of the TIADC; According to the control word of the preset ADC, other ADCs except the preset ADC are calibrated.

10. A time-interleaved analog-to-digital converter (TIADC), comprising: At least two ADCs in parallel; Processing module for: Obtaining an output value of each analog-to-digital converter ADC in the TIADC, wherein each ADC performs sampling in sequence according to a sampling order; For each ADC, calculating a first correlation value and a second correlation value of the ADC according to an output value of the ADC and output values ​​of two ADCs adjacent to the ADC in a sampling order; A calibration module is configured to calibrate a clock phase of the ADC according to the first correlation value and the second correlation value.

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