Methods, devices, and systems for executing a logical quantum circuit

Abstract

In a computer-implemented method for executing a logical quantum circuit on a target quantum hardware device, a gate operation weight is obtained for each pair of a plurality of pairs of logical qubits in the logical quantum circuit. The gate operation weight depends on an occurrence frequency of multi-qubit gate operations between the pair of logical qubits. For each pair of a plurality of pairs of quantum systems in the target quantum hardware device, a link quality weight is obtained. The link quality weight depends on quality of an optical connection between the pair of quantum systems. A mapping of the logical qubits to the quantum systems is generated such that a mapping cost function is minimized. The mapping cost function depends on the gate operation weights and the link quality weights. The logical quantum circuit is executed on the target quantum hardware device based on the mapping.

Description

METHODS, DEVICES, AND SYSTEMS FOR EXECUTING A LOGICAL QUANTUM CIRCUITCross-Reference to Related Application

[0001] This application claims priority from US application No. 63 / 570454 filed27 March 2024 and entitled METHODS, DEVICES, AND SYSTEMS FOR EXECUTING A LOGICAL QUANTUM CIRCUIT which is hereby incorporated herein by reference for all purposes. For purposes of the United States of America, this application claims the benefit under 35 U.S.C. §119 of US application No. 63 / 570454 filed 27 March 2024 and entitled METHODS, DEVICES, AND SYSTEMS FOR EXECUTING A LOGICAL QUANTUM CIRCUIT which is hereby incorporated herein by reference for all purposes. Field

[0002] This disclosure generally relates to methods, devices, and systems for executing logical quantum circuits. In particular, the disclosure relates to a method and a device for executing a logical quantum circuit on a target quantum hardware device, and to an information processing system.Background

[0003] Quantum computers are expected to have numerous applications in such diverse fields as quantum chemistry, the design of novel materials, and cryptography. Besides quantum computers, quantum networks have been proposed which can provide a greater connectivity which can be used for secure communication, modular quantum computing, or sensing.

[0004] Simmons, “Scalable Fault-Tolerant Quantum Technologies with Silicon Colour Centres”, arXiv:2311.04858, 2023, which is hereby incorporated by reference in its entirety, describes how both quantum computing and quantum networks basically depend on the distribution of high-quality entanglement. An architecture is proposed which is based on color center spins in silicon, so-called T centres, which are connected via telecom-band optical photons. The architecture can allow for a high connectivity which can significantly reduce overhead.

[0005] Physical quantum computers comprise physical qubits (such as the T centres described above) that are embedded in a quantum processor. Physical operations can be run on the processor. On the conceptual side, a quantum circuit is a model of aquantum algorithm, where quantum operators are described as quantum gates or operations. Quantum circuits that represent the execution of a fault- or non-fault-tolerant quantum algorithm and abstract away information regarding the physical details of a quantum processor are known as logical quantum circuits. The qubits and gates that make up a logical quantum circuit are referred to as logical qubits and logical gates, respectively.

[0006] A critical task in quantum information processing is determining how to execute a logical quantum circuit on a physical quantum computer. Several mapping solutions for monolithic quantum processors have been proposed. These mapping solutions are usually based on the assumption that multi-qubit gate operations are deterministic.

[0007] Mapping solutions for monolithic quantum processors can comprise the initial placement of physical qubits such that the need for physical relocation of qubits to execute specific gate operations, such as two-qubit gate operations, is minimized. Nonneighboring qubits that need to perform two-qubit operations are relocated by qubitrouting to adjacent physical qubits, e.g. using SWAP gate operations. Further, gate operations can be scheduled to maximize parallelism, while also respecting their dependencies and the constraints of the quantum hardware.

[0008] The assumption of deterministic multi-qubit operations is however not valid in general. Quantum architectures that support a high degree of non-local qubit interaction do so by establishing entanglement (via optical paths, for instance), which makes the delivery of their multi-qubit operations probabilistic. The optical paths can comprise integrated photonic waveguides, optical fibers, switches, detectors and the like. Even in best-case scenarios, entanglement delivery is probabilistic because a certain amount of photon loss cannot be avoided when transmitting photons through optical paths. The photon loss can depend on the length and quality of the optical paths.

[0009] There is therefore a need for mapping solutions for mapping logical quantum circuits to quantum systems of quantum hardware devices which are applicable in scenarios that rely on probabilistic entanglement delivery.Summary

[0010] The present disclosure has several aspects, including a method for executing a logical quantum circuit on a target quantum hardware device, a device for executing alogical quantum circuit on a target quantum hardware device, and an information processing system.

[0011] A first aspect of the disclosure provides a method for executing a logical quantum circuit on a target quantum hardware device. A gate operation weight is obtained for each pair of a plurality of pairs of logical qubits in the logical quantum circuit. The gate operation weight depends on an occurrence frequency of multi-qubit gate operations between the pair of logical qubits. A link quality weight is obtained for each pair of a plurality of pairs of quantum systems in the target quantum hardware device. The link quality weight depends on the quality of an optical connection between the pair of quantum systems. A mapping of the logical qubits to the quantum systems is generated such that a mapping cost function is minimized. The mapping cost function depends on the gate operation weights and the link quality weights. The logical quantum circuit is executed on the target quantum hardware device based on the mapping.

[0012] The invention provides a solution to the qubit mapping problem (or qubit assignment problem), i.e., the process of finding an optimal configuration of the quantum systems of the target quantum hardware device. In particular, the quantum systems may comprise physical qubits and the mapping assigns physical qubits to the logical qubits based at least on the quality of the optical connections between the physical qubits.

[0013] According to an embodiment of the invention, each pair of logical qubits is assigned a gate operation weight. The gate operation weight is reflective of an interaction frequency of the pair of logical qubits (e.g., number of multi-qubit logical quantum gates between the pair of logical qubits).

[0014] According to an embodiment of the invention, each pair of quantum systems is assigned a link quality weight. The link quality weight is reflective of loss associated with transmitting photons through an optical connection between the pair of quantum systems. As used here, being optically connected means that said quantum systems can interact with each other. The optical connection may be provided via one or more of an optical path, optical link, optical waveguide, or optical network extending between the quantum systems, and may include hardware resources / components such as optical switches, Bell State Analyzers (BSAs), photon detectors, etc., as applicable.

[0015] By minimizing the mapping cost function, an optimal physical implementation of the logical quantum circuit is obtained. The optimized implementation will have less cumulative photon loss compared to a scenario where logical qubits are randomly assigned to physical qubits. In particular, logical qubits that interact frequently with each other can be implemented on physical qubits which are connected via high quality optical connections. The execution of the quantum circuit on the target quantum hardware device can then be performed in an optimized manner.

[0016] The invention takes into account an outcome of one or more probabilistic events associated with the quantum hardware device. In one embodiment, the probabilistic event is entanglement generation facilitated by transmitting photons through an optical connection. As will be appreciated, the photon loss probability (quality) of the optical connection determines the probability of successfully generating entanglement between physical qubits connected by that optical connection. Specifically, the more lossy the optical connection, the lower the probability of success and the more the entanglement attempts needed to generate the required entanglement.

[0017] According to the invention, the quality of an optical connection depends on the loss associated with transmitting photons through the optical connection. In some embodiments, this loss can be computed by calculating the sum total of photon losses from hardware components constituting the optical connection.

[0018] As used here, minimizing the mapping cost function does not necessarily mean that the global minimum is found in each case. It might be the case that the mapping is such that a local minimum of the mapping cost function is found. In any case, this assignment can be significantly better than a random assignment.

[0019] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the logical quantum circuit is represented as a first weighted graph having a plurality of first nodes and a plurality of first edges. Each first edge of the plurality of first edges joins two first nodes of the plurality of first nodes. Each first node corresponds to a logical qubit of the logical quantum circuit. A weight of each first edge is given by the gate operation weight of the pair of logical qubits corresponding to the first nodes joined by said first edge.

[0020] The hardware components and the optical connectivity of the quantum hardware device are represented as a second weighted graph having a plurality of second nodes and a plurality of second edges. Each second edge of the plurality of second edges joins two second nodes of the plurality of second nodes. Each second node corresponds to a quantum system. The weight of each second edge is given by the link quality weight of the pair of quantum systems corresponding to the second nodes joined by said second edge. The mapping of the logical qubits to the quantum systems comprises mapping the first weighted graph to the second weighted graph using a graph overlaying algorithm. The graph overlaying algorithm is used in mapping the first weighted graph to the second weighted graph. Each first edge is mapped to a second edge and first edges are mapped to second edges in a consistent way, i.e., if a first edge is mapped to a second edge, then the endpoints of the first edge are mapped to the endpoints of the second edge.

[0021] By mapping the first weighted graph to the second weighted graph, frequently interacting logical qubits can be mapped to physical qubits which are connected by high quality optical connection. Accordingly, characteristics of the quantum circuits can be optimized, including the connectivity between physical qubits and the quality of the optical connection.

[0022] Minimizing the mapping cost function can be understood as finding the optimal way to overlay the first weighted graph (corresponding to a logical circuit graph) onto the second weighted graph (corresponding to a hardware connectivity graph). Herein, the term “optimal” may refer a logical-to-physical assignment with the minimum total photon loss.

[0023] According to the invention, the term “logical (quantum) circuit” relates to the circuit to be executed or implemented on a quantum processor. The logical circuit comprises of a plurality of logical qubits (or virtual qubits) and a plurality of gate operations executed on the logical qubits.

[0024] The first weighted graph represents a "logical circuit mapping graph”. Each vertex (or node) corresponds to a logical qubit and each edge can correspond to a two-qubit gate operation between corresponding logical qubits.According to the invention, the “occurrence frequency of multi-qubit gate operations” relates to the number of multi-qubit gates that act on the logical qubits involved in saidmulti-qubit gates. A multi-qubit gate corresponds to an operation (i.e. , a quantum gate) that is defined on a finite number of logical qubits. A subset of those logical qubits can control the operation and the remaining logical qubits are the targets of the operation.

[0025] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the contribution to the gate operation weight depends on the type of the multi-qubit gate. For example, some gates may be costlier than others. In this case, the occurrence frequency of multi-qubit gate operations for the different gates are also weighted differently in the computation of the gate operation weight. That is, the gate operation weight might depend on the costs of performing different types of multi-qubit gates.

[0026] The second weighted graph represents a “hardware graph”, i.e., a diagram representing the physical layout of the quantum processor. The hardware graph comprises nodes corresponding to physical qubits and optical connections connecting the physical qubits. In some embodiments, the hardware graph may further comprise nodes corresponding to additional hardware components apart from the physical qubits.

[0027] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the graph overlaying algorithm implements a logical-to-physical qubit map. This means that at least one physical qubit is assigned to each logical qubit.

[0028] The graph overlaying algorithm may generate as an output a structure that stores the map of the logical qubits to the physical qubits. The structure may be based on a sequence of logical qubit indices ( / = io, ii, ... , in), where n denotes the total number of logical qubits, and a sequence of physical qubit indices ( / = jo, ji, ... , jm), where the number n of logical qubits is smaller than or equal to the number m of physical qubits. An example of a map would be:{ io =jl, i2 =j5, ■■■ , in = jn }-

[0029] According to this example, the physical qubit with index ji is assigned to the logical qubit with index io, the physical qubit with index js is assigned to the logical qubit with index / 2, and so on.

[0030] According to an embodiment, the list can be a single sequence of integers, where the Ithentry indicates the index of the physical qubit that is associated with the Ithlogical qubit.

[0031] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the target quantum hardware device is implemented on a monolithic quantum processor. Monolithic quantum processors have all the key functionalities and capabilities of initialization, manipulation, and measurement of quantum states integrated on a single chip or module.

[0032] In certain architectures, operations in a monolithic quantum processor are probabilistic. For example, in quantum computing architectures based on spin-photon interfaces, all operations involving more than one qubit are mediated via entanglement. In these architectures, entanglement can be a fundamental resource for performing multi-qubit gate operations. Similarly, in architectures where physical qubits are linked optically, the quality of the optical connections that enable generation or distribution of entanglement between any two physical qubits may differ. This variance in optical connection quality makes it so that distributing entanglement (i.e. , performing multi-qubit operations) between certain subsets of physical qubits will be harder than for other subsets. This can be taken into account by considering the quality of the optical connections when mapping the first weighted graph (corresponding to the logical quantum circuit) to the second weighted graph (corresponding to the target quantum hardware device).

[0033] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the target quantum hardware device is implemented on a modular quantum processor. A modular quantum processor combines multiple chips or modules when executing a quantum process.

[0034] A modular quantum processor can perform intra-module and inter-module operations. The term “intra-module operation” relates to gate operations that take place on the same quantum processor. The term “inter-module operation” relates to gate operations between qubits from different quantum processors. Inter-module operations are generally delivered via entanglement and are inherently probabilistic. Accordingly,taking the quality of optical connection between qubits from different processors into account is particularly advantageous.

[0035] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, gate operation weights are assigned to each pair of logical qubits in the logical quantum circuit. In addition or alternatively, link quality weights can be assigned to each pair of quantum systems based on the quality of the optical connection connecting said pair of quantum systems. In other embodiments, gate operation weights are assigned to only some of the pairs of logical qubits. Likewise, link quality weights may be assigned to only some of the pairs of quantum systems.

[0036] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, generating the mapping of the logical qubits to the quantum systems comprises mapping the first weighted graph to the second weighted graph using a graph overlaying algorithm. The graph overlaying algorithm computes a map between two graphs and assigns one edge of the second graph for each edge of the first graph and associates the corresponding endpoints (nodes) of the edges.

[0037] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the graph overlaying algorithm is an overlaying weight minimizing algorithm having the goal of minimizing an overlaying weight of the graph overlaying. The overlaying weight can correspond to the mapping cost function. The overlaying then corresponds to a mapping between the first weighted graph and the second weighted graph such that the mapping cost function is minimized, e.g., the photon loss that occurs when executing the logical circuit on the target quantum hardware device is minimized. The overlaying weight minimizing algorithm seeks to minimize the overlaying weight but does not need to achieve a global minimum weight overlaying but may rather determine a local minimum.

[0038] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the overlaying weight minimizing algorithm maps the first edges in descending order of the weights of said first edges (i.e. , the gate operation weights) to the second edges in ascending order of the weights ofsaid second edges (i.e., link quality weights). In this way, highly connected logical qubits are associated with physical qubits connected via high quality optical connections.

[0039] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, mapping the first weighted graph to the second weighted graph comprises iterating the steps of: a) determining a first edge having the highest weight among the first edges that are not yet associated with a second edge, and b) associating the determined first edge with a second edge having the lowest weight among the second edges that are not yet associated with a first edge and comply with previous associations.

[0040] By iterating the steps a) and b), pairs of first nodes corresponding to logical qubits with higher gate operation weights are associated with pairs of second nodes corresponding to quantum systems with better quality optical connections.

[0041] If one of the endpoints of the first edge (i.e., a first node) is already associated with a second node because of a previous association, the determined first edge is only associated with a second edge having this first second node as an endpoint. In this way, compliance with previous associations is taken care of.

[0042] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the two first nodes connected by the determined first edge are associated with the two second nodes connected by the second edge associated with said determined first edge. In particular, the logical qubits corresponding to the first nodes are then mapped to the quantum systems corresponding to the second nodes.

[0043] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, where there is a plurality of second edges having lowest weights among the second edges that are not yet associated with a first edge, the iteration is performed for each possible choice of associating the determined first edge to one of said plurality of second edges. In this way, ambiguities can be taken into account. By performing the iteration for each possible choice, an optimal solution can be found in principle.

[0044] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the iteration is stopped after a predefined number of iteration steps. After stopping the iteration, the choice with a lowest cumulative weight of the association is selected. The determined first edge is associated to the second edge according to the selected choice. Stopping the iteration after the predefined number of iteration steps represents an interruption in order to avoid excessive calculations.

[0045] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the cumulative weight of the choice is computed by adding the weights of all second edges that are associated with a first edge after the predefined iteration steps. This cumulative weight is the total weight associated with the mapping up to this point. A good solution can be obtained by minimizing the cumulative weight.

[0046] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, mapping the first weighted graph to the second weighted graph comprises mapping each first node to a second node and mapping each first edge to a second edge. This implies mapping each logical qubit to a quantum system based on the quality of the optical connections of the quantum hardware device.

[0047] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the second weighted graph is an undirected fully connected weighted graph. This implies that the set of all necessary connections between physical qubits to execute the logical quantum circuit can be arranged, i.e. , any pair of physical qubits can be connected. The high connectivity of the target quantum hardware device is highly advantageous. For example, the temporal overhead for implementing quantum gates between arbitrary physical qubits can be greatly reduced. Further, no physical relocation of qubits is required because an arbitrary physical qubit on the quantum processor can be entangled with another qubit regardless of their physical locations.

[0048] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, each second node either corresponds toa physical qubit or to a hardware component, i.e. , a physical element or gadget used to connect physical qubits. The second weighted graph is reduced by eliminating all second nodes corresponding to the connecting components. The second nodes of the reduced second weighted graph comprises only physical qubits. The mapping then corresponds to a mapping of logical qubits to physical qubits. By eliminating the hardware components other than the physical qubits, the mapping can be simplified.

[0049] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the link quality weights of a pair of physical qubits in the reduced second weighted graph are computed based on link quality weights of links involving hardware components along an optical connection between said pair of physical qubits. For example, the link quality weights of all hardware components along the optical connection can be replaced by a single link quality weight which is computed based on the link quality weights of the hardware components.

[0050] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the mapping cost function corresponds to a weight difference associated with the mapping. The weight difference can correspond to the sum of single weight differences between each gate operation weight of a pair of logical qubits and the link quality weight of an associated pair of quantum systems according to the mapping.

[0051] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the link quality weights decrease with increasing quality of the optical connection. The goal can be set to associate logical qubits with high gate operation weights with physical qubits with low link quality weights. This goal can be achieved by maximizing the weight difference.

[0052] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the link quality weight corresponds to photon loss probability associated with the optical connection between the pair of quantum systems. By minimizing the mapping cost function, the total photon loss associated with execution of the logical quantum circuit on the target quantum hardware device can be minimized.

[0053] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, a machine learning algorithm is used for generating the mapping of the logical qubits to the quantum systems.

[0054] In an embodiment, the machine learning algorithm can implement a graph overlaying algorithm. An exemplary method for graph overlaying using machine learning techniques is described in Seo et al., “A Graph Embedding Technique for Weighted Graphs Based on LSTM Autoencoders”, Journal of Information Processing Systems, Vol. 16, No. 6 (2020), pp. 1407 - 1423, which is hereby incorporated by reference in its entirety. The graph overlaying can be performed based on machine learning techniques including but not restricted to matrix factorization methods, graph kernel methods, and deep learning-based methods.

[0055] For example, in matrix factorization methods, the first weighted graph is represented in the form of a matrix and the matrix is factorized to obtain its embedding vector.

[0056] In graph kernel methods, the first weighted graph and the second weighted graphs are represented as vectors and a measure of similarity between the two graphs is determined by calculating the inner product of their representing vectors.

[0057] With deep learning-based methods, the features of the first weighted graph and the second weighted graph can be determined using an artificial neural network. The deep-learning methods can comprise node embedding approaches and whole-graph embedding approaches. In node embedding approaches, a low-dimensional vector representation of each node in the first and second weighted graph is learned. In wholegraph embedding approaches, the whole graph is represented as a single vector.

[0058] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, at least some of the quantum systems correspond to T centre defects in a silicon substrate. In particular, the T centre defects can be used as the physical qubits of the quantum hardware device.

[0059] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the optical connection between a pair of T centre defects comprises a telecom photonic interface of the T centre in the silicon substrate. This allows a low-loss linking of the T centres.

[0060] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the optical connection between a pair of T centre defects comprises at least one photonic waveguide integrated in the silicon substrate and / or at least one optical fibre. An architecture can be based on T centres linked by photons in the telecom optical band with high connectivity, i.e. all or almost all T centres are linked with each other. All-to-all connectivity can be achieved via optical switches for routing photons and / or means for photons to traverse other physical elements (e.g., other physical qubits) to designated destinations on the chip or module.

[0061] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the target quantum hardware device supports entanglement of quantum systems, in particular entanglement of pairs of T centre defects. T centre defects can become entangled regardless of their proximity, in particular the T centre defects do not need to be nearest neighbors.

[0062] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the target quantum hardware device is configured such that the entanglement is distributed by photons which are transmitted over the optical connections connecting the T centre defects.

[0063] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the target quantum hardware device can prepare maximally entangled Bell pairs using the T centre defects. According to an embodiment of the method, the maximally entanglement Bell pairs are generated according to the Barrett-Kok protocol. In particular, the electron spins of two separated T centres can be prepared in a superposition of spin-up and spin-down states, and are triggered to emit a photon resonant with the spin-up transition. After interfering with a beam splitter, the photonic modes are detected. After inverting the spin states, emission and detection is repeated. A maximally-entangled Bell pair is obtained by using exactly one photon detection in each of the first and second optical cycles as a herald signal.

[0064] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, each pair of quantum systems in the target quantum hardware device is connectable by at least one optical connection. This guarantees maximal connectivity. The target quantum hardware therefore allows theconnectivity of the quantum systems, which may involve re-arrangement to provide the necessary physical connections.

[0065] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, at least one pair of quantum systems in the target quantum hardware device is connected by a plurality of optical connections. In particular, physical qubits may be connected via different links.

[0066] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the optical connections connecting two quantum systems in the target quantum hardware device comprise at least one of an optical link, a switch, and a detector. The switches can comprise optical switches.

[0067] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, quantum systems in the target quantum hardware device can become entangled by means of at least two detectors. For example, entanglement may be obtained based on the Barrett-Kok protocol described above.

[0068] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the weight that represents the quality of an optical connection between a pair of quantum systems depends on the number of the optical links and / or on the number of the switches and / or the number of the detectors in the optical connection between said pair of quantum systems. In general, the more components that are present, the lower the quality of the optical connection will be because each component is associated with some loss.

[0069] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the link quality weight of a pair of quantum systems depends on at least one of the photon loss values associated with the optical links, a photon loss value associated with the switches and a photon loss value associated with the detectors in the optical connection between said pair of quantum systems. The photon loss value can correspond to a probability of photon loss associated with the respective component.

[0070] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the link quality weight of a pair ofquantum systems depends on at least one of a sum of the photon loss values of all optical links, a sum of the photon loss values of all switches and a sum of the photon loss values of all detectors in the optical connection between said pair of quantum systems.

[0071] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, a representation of the mapping of the logical qubits to the quantum systems is stored in a database. For example, the representation of the mapping of the logical qubits to the quantum systems can be retrieved during circuit design.

[0072] According to an embodiment of the method for executing the logical quantum circuit on the target quantum hardware device, the target quantum hardware is operated to perform a quantum algorithm on the target quantum hardware. The quantum algorithm may relate to an application in quantum sensing, quantum computing, quantum communication, or the like.

[0073] A second aspect of the disclosure provides a computer program product comprising executable program code configured to, when executed by a computing device, perform the method according to the first aspect.

[0074] A third aspect of the disclosure provides a non-transitory, computer-readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method according to the first aspect.

[0075] A fourth aspect of the disclosure provides a device for executing a logical quantum circuit on a target quantum hardware device. The device comprises at least one processor, and at least one tangible computer-readable storage device communicatively coupled to at least one processor. The storage device stores processor-executable instructions. When executed by at least one processor, the instructions cause the at least one processor to obtain a gate operation weight for each pair of a plurality of pairs of logical qubits in the logical quantum circuit. The gate operation weight depends on the occurrence frequency of multi-qubit gate operations between the pair of logical qubits. For each pair of a plurality of pairs of quantum systems in the target quantum hardware device, the processor obtains a link quality weight. The link quality weight depends on quality of an optical connection between the pair of quantum systems. The processor further generates a mapping of the logical qubits to the quantum systems such that amapping cost function is minimized. The mapping cost function depends on the gate operation weights and the link quality weights. The processor generates a control signal for controlling the quantum hardware device to execute the logical quantum circuit on the target quantum hardware device based on the mapping.

[0076] A fifth aspect of the disclosure provides an information processing system comprising a quantum hardware device. At least one processor is communicatively coupled to the quantum hardware device. At least one tangible computer-readable storage device is communicatively coupled to at least one processor and stores processor-executable instructions. When executed by at least one processor, the instructions cause the at least one processor to generate a mapping of a plurality of logical qubits of a logical quantum circuit to a plurality of physical qubits of the quantum hardware device. A gate operation weight is assigned to each pair of a plurality of pairs of the logical qubits. The gate operation weight depends on the number of multi-qubit gate operations between the pair of logical qubits. A link quality weight is assigned to each pair of a plurality of pairs of the physical qubits. The link quality weight depends on the quality of an optical connection between the pair of physical qubits. A mapping cost function depending on the gate operation weights and the link quality weights is minimized. The quantum hardware device is controlled to execute the logical quantum circuit, based on the mapping.

[0077] According to an embodiment of the information processing system, the quantum hardware device comprises a semiconductor body with a plurality of luminescent defects disposed within the semiconductor body. According to an embodiment of the information processing system, the semiconductor body consists principally of silicon.

[0078] According to an embodiment of the information processing system, the luminescent defects comprise T centre defects.

[0079] According to an embodiment of the information processing system, the processor further represents the logical quantum circuit as a first weighted graph having a plurality of first nodes and a plurality of first edges. Each first edge of the plurality of first edges joins two first nodes of the plurality of first nodes. Each first node corresponds to a logical qubit of the logical quantum circuit. The weight of each first edge is given by the gate operation weight of the pair of logical qubits corresponding to the first nodes joined bysaid first edge. The processor represents a connectivity of the quantum hardware device as a second weighted graph having a plurality of second nodes and a plurality of second edges, wherein each second edge of the plurality of second edges joins two second nodes of the plurality of second nodes. Each second node corresponds to a physical qubit. The weight of each second edge is given by the link quality weight of the pair of physical qubits corresponding to the second nodes joined by said second edge.

[0080] According to an embodiment of the information processing system, the optical connection between a pair of T centre defects comprises a telecom photonic interface of the T centre in the silicon substrate.

[0081] According to an embodiment of the information processing system, the optical connection between a pair of T centre defects comprises at least one photonic waveguide integrated in the silicon substrate and / or at least one optical fibre.

[0082] According to an embodiment of the information processing system, the target quantum hardware device is configured such that a pair of T centre defects can become nonlocally entangled.

[0083] According to an embodiment of the information processing system, the target quantum hardware device is configured such that the entanglement is distributed by photons which are transmitted over the optical connection connecting the T centre defects.

[0084] According to an embodiment of the information processing system, the target quantum hardware device is configured to prepare maximally entangled Bell pairs using the T centre defects.

[0085] According to an embodiment of the information processing system, each pair of physical qubits in the target quantum hardware device is connectable by at least one optical connection.

[0086] According to an embodiment of the information processing system, at least one pair of physical qubits in the target quantum hardware device is connectable by a plurality of optical connections.

[0087] According to an embodiment of the information processing system, the optical connections connecting two quantum systems in the target quantum hardware device comprise at least one of an optical link, a switch, and a detector.

[0088] According to an embodiment of the information processing system, physical qubits in the target quantum hardware device can become entangled by means of at least one detector.

[0089] The disclosure relates to all combinations of the above features, even if these are recited in different aspects or different claims.Brief description of the drawings

[0090] In the following, further aspects and exemplary embodiments will be described with reference to the accompanying drawings. However, the present disclosure is not limited to the described exemplary embodiments and may be modified in various different ways. Consequently, the drawings and description are intended to be illustrative in nature and not limiting. Identical reference numbers denote identical elements in the specification.Fig. 1 schematically shows a block diagram illustrating an information processing system according to an embodiment of the disclosure;Fig. 2 shows a flow diagram illustrating a method for executing a logical quantum circuit on a target quantum hardware device according to an embodiment of the disclosure;Fig. 3 shows a flow diagram illustrating a method for mapping logical qubits to quantum systems according to an embodiment of the disclosure;Fig. 4 shows a flow diagram illustrating a method for mapping a first weighted graph to a second weighted graph according to an embodiment of the disclosure;Fig. 5 shows an exemplary illustration of a reduction of a second weighted graph;Fig. 6 shows an example of a first weighted graph obtained from a logical circuit; andFig. 7 shows an exemplary mapping of the first weighted graph from Figure 6 to a second weighted graph.Detailed description

[0091] Figure 1 schematically shows a block diagram illustrating an information processing system 100. The information processing system 100 comprises a quantumhardware device 400, i.e. , a physical device or machine which can be used to implement algorithms (e.g., a quantum computer).

[0092] The quantum hardware device 400 comprises quantum systems 401 and hardware components 402. An example of quantum system 401 is a physical qubit having first and second quantum states that can be used to represent quantum information and which can exist in a quantum superposition. The hardware components 402 may comprise optical paths, optical links, optical networks, grating couplers, optical switches, Bell State Analyzers (BSAs) and detectors for facilitating optical connection between the quantum systems 401. For example, optical links can be used in connecting the quantum systems 401 with the switches and detectors and can further connect switches and detectors to each other. Similarly, the switches can be controlled to select specific optical links for connecting a given quantum system 401 to at least one other quantum system. Preferably, by controlling one or more hardware components in a suitable manner, any pair of quantum systems 401 in the quantum hardware device 400 may be connected to each other.

[0093] The detectors can be used in generating entanglement between the quantum systems 401 based on a photon detection pattern of photon states associated with said quantum systems 401 . The entanglement may be generated according to an entanglement protocol, such as the Barrett-Kok protocol.

[0094] The quantum hardware device 400 may comprise a spin-photon interface. For example, the quantum hardware device 400 may comprise a semiconductor body with luminescent defects which form the quantum systems 401. The semiconductor body may comprise silicon or similar semiconductor materials. For example, the semiconductor material may include natural silicon, silicon carbide, silicon germanium, isotopically purified paramagnetic silicon, a so-called silicon vacuum or combinations thereof. The semiconductor body may be processed to remove a large fraction of non-paramagnetic isotopes (e.g., silicon-29). The semiconductor body may comprise enriched or purified silicon that has been processed to remove some to nearly all non-zero-nuclear spin isotopes, such as silicon-29. Purified silicon includes material enriched to various levels of silicon-28, such as, 99%, 99.9%, and 99.99%. Purified silicon includes material enriched with silicon-28. Purified silicon includes silicon where spectroscopic linewidthsare at least ten to hundred times sharper than in natural silicon. The semiconductor body may also comprise an epilayer of isotopically purified silicon, grown on top of a natural silicon wafer.

[0095] The luminescent defects may comprise T centre defects, as described in US 2022 / 0366290 A1 and / or US 2022 / 0327416 A1 , which are hereby incorporated by reference in their entirety.

[0096] Quantum systems 401 in the quantum hardware device 400 can be connected via plurality of optical connections. Each optical connection provides a path that connects pair of quantum systems 401 and enables performing operations between said quantum systems. Different optical connections may comprise different hardware components 402, i.e. , different routes including switches, detectors, and the like. In particular, the number of switches, detectors, and the like can vary for different optical connections.

[0097] In embodiments where the quantum systems 401 are T centre defects, pairs of T centre defects may be optically connected by means of a telecom photonic interface (i.e., operating in the telecom frequency band) of the T centre in the silicon substrate. In some embodiments, each T centre defects can be optically connected to any other T centre defects, i.e., all-to-all optical connection between the T centre defects is possible. The optical connection between a pair of T centre defects may comprise at least one photonic waveguide integrated in the silicon substrate (“on-chip”). In addition or alternatively, the optical connection can also comprise optical fibres or other components which can be external to the silicon substrate (“off-chip”). The optical connection may be configured to facilitate entanglement between T centre defects. The entanglement can be generated and / or distributed by photons which are transmitted over the optical connections connecting the T centre defects. The quantum hardware device 400 can be configured to prepare maximally entangled Bell pairs, using the T centre defects.

[0098] The quantum hardware device 400 may further include means for implementing physical gates on the quantum systems 401 . For example, the quantum hardware device may include means for generating and applying pulses for manipulating the state of quantum systems 401 . The quantum hardware device 400 may be used for any practical application in quantum sensing, quantum computing or quantum communication.

[0099] Quantum sensing comprises measurements which utilize quantum effects such as entanglement, interference or quantum state squeezing.

[0100] Quantum computing comprises any processing of information based on quantum effects, such as superpositions of states of quantum systems 401 , 402 and (de-) coherence or entanglement of quantum systems 401 , 402. The quantum hardware device 400 may have quantum systems 401 that can be entangled with each other or with quantum systems of other quantum hardware device 400.

[0101] Quantum communication comprises the transmission of classical information or of quantum states between different devices, e.g., between the quantum hardware device 400 and another quantum hardware device based on quantum effects as described above.

[0102] Quantum circuits of the quantum hardware device 400 are designed for carrying out the necessary steps of a given quantum algorithm. Logical quantum circuits can be implemented as physical quantum circuits (or physical circuits). Logical quantum circuits comprise a plurality of logical gates (or operators).

[0103] In some embodiments, the target quantum hardware device 400 is implemented on a modular quantum processor. A modular quantum processor combines multiple chips or modules when executing a quantum process and can perform “intra-module” and “inter-module” operations. The term “intra-module operation” relates to gate operations between quantum systems on the same quantum chip or module. The term “inter-module operation” relates to gate operations between quantum systems of different chips or modules. In certain applications, it can be advantageous to link multiple computer modules instead of building ever-larger monolithic quantum supercomputers (i.e., having only a single chip or module). Herein, modules are separate components with quantum systems and different modules can be spatially separated. Optical links or one or more optical networks can be used to connect the modules.

[0104] The quantum hardware device 400 can be a non-locally connected hardware device, as described in Simmons, “Scalable Fault-Tolerant Quantum Technologies with Silicon Colour Centres”, arXiv:2311.04858, 2023, which is hereby incorporated by reference in its entirety.

[0105] As will be appreciated, a quantum hardware device comprising a spin-photon interface, for example T centre defects, supports interactions between non-local quantum systems. These interactions are facilitated through the generation and / or distribution of entanglement. Entanglement can be generated by sending photons from different quantum systems to interfere on a beam splitter, followed by detection. The photons are transmitted through optical connections, which inherently have associated losses. This results in the interactions between non-local quantum systems being probabilistic in nature.

[0106] Returning now to Fig. 1 , the information processing system 100 comprises a logical circuit executing device 200, i.e. , a device for executing a logical quantum circuit on the quantum hardware device 400. The device 200 comprises at least one processor 203, and at least one first memory 204 (i.e., a tangible computer-readable storage device) communicatively coupled to the at least one processor 203.

[0107] The processor 203 can be a logic processing unit and can comprise a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller (pC), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a program logic unit (PLU), a network processor (NP) or a combination thereof.

[0108] The first memory 204 can comprise at least one of a magnetic hard disk, an optical disc (e.g., compact disc, digital video disc, Blu-ray disc), a solid state disc (SSD), a magneto-optical memory or a hard disc drive (HDD). For example, the memory 204 can comprise a volatile semiconductor or solid state memory, e.g., a random access memory (RAM), dynamic RAM (DRAM), or static RAM (SRAM). The first memory 204 can comprise a non-volatile semiconductor or solid state memory, e.g., a read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), or the like.

[0109] The first memory 204 stores processor-executable instructions and / or processor- readable data associated with the operation of the logical circuit executing device 200. The processor-executable instructions and / or processor-readable data can comprise an operating system, peripheral drivers, server instructions, application instructions, calibration instructions, or communication channel instructions.

[0110] The logical circuit executing device 200 further comprises a user interface 205, having at least one of a display, a keyboard, a touch screen, a mouse, buttons, a microphone, loudspeakers and the like. A user may provide or receive information regarding the operation of the information processing system 100 via the user interface 205.

[0111] An interface 202 is provided for connecting the processor 203 with a second memory 700 and a control device 300. The interface 202 can be any port or link or interface capable of communicating information to another system, e.g., a wired connection or a wireless connection (e.g. wireless LAN, Bluetooth®, ethernet, or the like).

[0112] All of the components of the representation determining device 200 described above can be controlled and / or can communicate over at least one bus 201 . The processor 203 may be configured to control the other above-described components 202, 204, 205 of the logical circuit executing device 200.

[0113] The first memory 204 stores processor-executable instructions. When executed by the processor 203, the instructions cause the processor 203 to obtain a gate operation weight for each pair of a plurality of pairs of logical qubits in the logical quantum circuit. The gate operation weight depends on an occurrence frequency of multi-qubit gate operations between the pair of logical qubits.

[0114] For each pair of a plurality of pairs of quantum systems in the target quantum hardware device, the processor obtains a link quality weight. The link quality weight depends on the quality of an optical connection between the pair of quantum systems. As will be appreciated, the quality of an optical connection describes the loss associated with transmitting photons through the optical connection and can be computed by calculating the sum total of losses from the hardware components that constitute the optical connection.

[0115] The system 100 comprises the second memory 700 which stores a database with descriptions of the logical quantum circuit and the quantum hardware device 400. In particular, the gate operation weights for the pairs of logical qubits and the link quality weights for the pairs of quantum systems 401 , 402 can be stored in the second memory 700.

[0116] Although the second memory 700 is illustrated as an additional memory external to the logical circuit executing device 200, in other embodiments, the second memory 700 can be part of the logical circuit executing device 200 or can be identical with the first memory 204.

[0117] Likewise, the user interface 205 is illustrated as part of the logical circuit executing device 200, but there can also be a separate user interface.

[0118] The database with descriptions of the logical quantum circuit and the quantum hardware device 400 can be provided by a user, e.g., via the user interface 205. The link quality weights can be selected by a user, e.g., based on measurements of the quality of the optical connections (or exemplary optical connections) obtained from calibration measurements performed on the quantum hardware device. The quality of an optical connection describes the photon loss probability associated with the optical connection.

[0119] Likewise, the logical circuit can be provided by the user, e.g., via the user interface 205.

[0120] The processor 203 further generates a mapping of the logical qubits to the quantum systems 401 , 402 such that a mapping cost function is minimized. The mapping cost function depends on the gate operation weights and the link quality weights. The mapping cost function corresponds to a weight difference associated with the mapping. The weight difference is given by the sum of single weight differences between each gate operation weight of a pair of logical qubits and the link quality weight of an associated pair of quantum systems according to the mapping. By minimizing the mapping cost function, an optimal physical implementation of the logical quantum circuit is obtained. The optimized implementation will have less cumulative photon loss compared to the scenario where logical qubits are randomly assigned to quantum systems.

[0121] In order to generate the mapping, the processor may first represent the logical quantum circuit as a first weighted graph having a plurality of first nodes and a plurality of first edges. The first weighted graph can be a bipartite graph G(V,E), where V denotes the first nodes (vertices) and E denotes the first edges with weights W(e) which can take integer or real-number values.

[0122] Each first edge of the plurality of first edges joins two first nodes of the plurality of first nodes. Each first node corresponds to a logical qubit of the logical quantum circuit. A weight of each first edge is given by the gate operation weight of the pair of logical qubits corresponding to the first nodes joined by said first edge. The processor represents the physical resources (e.g., quantum systems and hardware components) of the quantum hardware device as a second weighted graph having a plurality of second nodes and a plurality of second edges. Each second edge of the plurality of second edges joins two second nodes of the plurality of second nodes. Each second node corresponds to a quantum system. A weight of each second edge is given by the link quality weight of the pair of quantum systems corresponding to the second nodes joined by said second edge.

[0123] The processor 203 may store a representation of the mapping of the logical qubits to the quantum systems 401 in a database in at least one of the first memory 204, the second memory 700 and / or in an external database, e.g., on an external server. The representation of the mapping may comprise an assignment of logical qubits to physical qubits, e.g., in form of a list or matrix.

[0124] The information processing system 100 comprises the control device 300 which can control the quantum hardware device 400 to implement a specific quantum algorithm. For example, the algorithm can be obtained by a user, e.g., via the user interface 205 of the logical circuit executing device 200 or via a separate user interface of the control device 300.

[0125] The processor 203 generates a control signal for the control device 300 to control the quantum hardware device 400 to execute the logical quantum circuit based on the mapping.

[0126] The control device 300 may further control a cooling device 500 and an actuator device 600 which can influence the quantum hardware device 400.

[0127] The cooling device 500 may maintain the quantum hardware device 400 at a predefined cryogenic temperature, e.g., in a range from about 1 mK to 77 K, or more particularly in a range from about 1 .5 K to 4 K. The quantum hardware device 400 may also be kept at constant air pressure, e.g., a stable vacuum.

[0128] The actuator system 600 can comprise a plurality of actuators. For example, the actuator system 600 can comprise an electromagnet to apply a time-invariant electric field, a time-varying electric field or a pulsed electric field to the quantum hardware device 400.

[0129] Specific implementation details of determining the mapping between the logical qubits and the physical quantum systems are outlined in the following.

[0130] Figure 2 shows a flow diagram illustrating a method for executing a logical quantum circuit on a target quantum hardware device, in particular the quantum hardware device 400 of the information processing system 100 described above. In turn, the above-described information processing system 100 can be configured to perform the method for executing a logical quantum circuit on a target quantum hardware device 400 described in the following.

[0131] In step S100, a gate operation weight is obtained for each pair of a plurality of pairs of logical qubits in the logical quantum circuit. The gate operation weight depends on an occurrence frequency of multi-qubit gate operations between the pair of logical qubits. The logical quantum circuit can be provided by a user via a user interface. The gate operation weight may be automatically computed from the description of the logical quantum circuit. For example, for a given pair of logical qubits, the gate operation weight is increased by a predetermined number for each multi-qubit gate operation between the two logical qubits.

[0132] In some embodiments, the gate operation weight may depend on the nature / type of the multi-qubit gate operation. For example, some multi-qubit gate operations may be costlier than others depending on the quantum hardware device. A multi-qubit gate operation may be costly because more resources are required to implement said multiqubit gate operation compared to other multi-qubit gate operations. These resources can include computational time, the number of elementary (single) gate operations needed, and the complexity of the multi-qubit gate operation. In such cases, the cost of the multiqubit gate operation and the occurrence frequency of the gates are considered when computing the gate operation weight. For example, costlier multi-qubit gate operations may have a higher gate operation weight.

[0133] In step S200, a link quality weight is obtained for each pair of a plurality of pairs of quantum systems in the target quantum hardware device. The link quality weight depends on quality of an optical connection between the pair of quantum systems. The link quality weight can be retrieved from memory and can be based on calibration measurements performed on the quantum hardware device. The link quality weight may be determined such that the value decreases with increasing quality of the optical connection. For example, the link quality weight can be given by an integer value or by a non-negative or positive real value. In some embodiments, a value of infinity (represented by a predetermined high value) indicates that there is no optical connection between a pair of quantum systems.

[0134] The link quality weight may be provided by a user, e.g., based on previous experience or based on measurements performed on exemplary optical connections. For example, a photon loss probability associated with optical links or detectors corresponding to the optical connection can be measured and the link quality weight is set based on these measurements.

[0135] The link quality weight can therefore correspond to a photon loss probability associated with an optical connection between the pair of quantum systems. In particular, the link quality weight is reflective of loss associated with transmitting photons through the optical connection connecting the pair of quantum systems.

[0136] In step S300, a mapping of the logical qubits to the quantum systems is generated such that a mapping cost function is minimized. The mapping cost function depends on the gate operation weights and the link quality weights. The mapping is a logical-to- physical qubit map which assigns a physical qubit of the second weighted graph to each logical qubit of the first weighted graph. The mapping can be given in the form of a list which assigns to each logical qubit index a corresponding physical qubit index.

[0137] If all logical qubits are treated according to the numerical order of the indices, the list can be simplified to a list of the of the physical qubits, e.g.{j3, ... } such that the Ithentry in the list indicates the index of the physical qubit assigned to the Ithlogical qubit. According to the above example, the physical qubit with index j3 is associated with the first logical qubit.

[0138] In some embodiments, a machine learning algorithm is used for generating the mapping of the logical qubits to the quantum systems. The machine learning algorithm may be based on an artificial neural network which receives the first weighted graph and the second weighted graph as inputs. The artificial neural network is trained to provide a mapping of the first weighted graph to the second weighted graph as an output. The output can be in the form of a list or sequence, as explained above. For example, the mapping can be performed as described in Seo et al., “A Graph Embedding Technique for Weighted Graphs Based on LSTM Autoencoders”, which is hereby incorporated by reference in its entirety.

[0139] The result of the mapping of the logical qubits to the quantum systems can be stored in a database for later use.

[0140] In step S400, the logical quantum circuit is executed on the target quantum hardware device based on the mapping. The logical quantum circuit can be executed on a monolithic quantum processor or a modular quantum processor. The target quantum hardware is operated to perform a quantum algorithm on the target quantum hardware. The quantum algorithm can have any practical application, e.g., in quantum sensing, quantum computing or quantum communication.

[0141] Figure 3 shows a flow diagram illustrating a method for mapping logical qubits to quantum systems. The method can be implemented as a sub-method of the method illustrated in Figure 2 and described above. In particular, the method described in the following can be used as a specific implementation of step S300 of the above-described method.

[0142] In step S310, the logical quantum circuit is represented as a first weighted graph which corresponds to a logical circuit mapping graph. The first weighted graph has a plurality of first nodes and a plurality of first edges. Each first edge of the plurality of first edges joins two first nodes of the plurality of first nodes. Each first node corresponds to a logical qubit of the logical quantum circuit. A weight of each first edge is given by the gate operation weight of the pair of logical qubits corresponding to the first nodes joined by said first edge.

[0143] In step S320, the connectivity of the quantum hardware device (i.e. , how quantum systems and hardware components of the quantum hardware device are physicallyconnected to each other) is represented as a second weighted graph which corresponds to a hardware connectivity graph. The second weighted graph comprises second nodes and a plurality of second edges. Each second edge of the plurality of second edges joins two second nodes of the plurality of second nodes. Each second node corresponds to a quantum system 401 .

[0144] In some embodiments, the quantum system 401 correspond to luminescent defects in silicon, in particular ? centre defects in a silicon substrate. The optical connection between a pair of T centre defects can comprise telecom photonic interfaces of the T centre in the silicon substrate. Pairs of T centre defects can be coupled by photonic waveguide integrated in the silicon substrate (i.e., on-chip photonic waveguides). In addition or alternatively, off-chip optical fibres can be used in providing the optical connection between T centres. In some embodiments, all or almost all T centres are can be optically connected with each other. Pairs of non-local (e.g., non- nearest neighbor) T centre defects can be entangled. Entanglement can be generated according to a suitable entanglement protocol.

[0145] The entanglement can be determined by observing a predefined photon detection pattern from the detectors. The entanglement is distributed by photons which are transmitted over the optical connections connecting the T centre defects. The T centre defects can be prepared as maximally entangled Bell pairs.

[0146] Returning now to Fig. 3, the weight of a given second edge of the second weighted graph is given by the link quality weight of the pair of quantum systems corresponding to the second nodes joined by the second edge.

[0147] The link quality weight depends on quality of an optical connection between a pair of quantum systems. In some embodiments, the quality of an optical connection is determined by the number of the optical links, the number of the optical switches and the number of the detectors associated with the optical connection. In general, each of these hardware components is associated with a photon loss probability, which characterizes the inherent photon loss of the component. Accordingly, an optical connection that comprises a higher number of hardware components 402 may have a higher probability of photon loss (i.e. a lower quality) than an optical connection with less hardware components.

[0148] The quality of an optical connection between a pair of quantum systems may be obtained based on sums of the photon loss values of the hardware components 402 associated with that optical connection. For instance, the quality of an optical connection comprising optical links, switches and detectors may be given by the sum of the photon loss values of the optical links, a sum of the photon loss values of all switches and a sum of the photon loss values of all detectors.

[0149] Returning now to Fig. 3, besides second nodes that correspond to quantum systems 401 (e.g., physical qubits), some embodiments may include other second nodes that correspond to hardware components. In an optional step S330, the second weighted graph is reduced by eliminating all second nodes corresponding to the hardware components 402. The reduced second weighted graph comprises only second nodes corresponding to quantum systems 401. To determine the reduced second weighted graph, for each pair of quantum systems 401 , all optical connections connecting these quantum systems 401 are examined. For each optical connection, a quality of the optical connection is determined as described previously. The optical connection with the highest quality is selected. The second weighted graph is reduced by directly connecting the physical qubits by a new second edge whose weight corresponds to the quality of the selected optical connection.

[0150] In some embodiments, the reduced second weighted graph is an undirected fully connected weighted graph. This means that all physical qubits are fully connected, i.e. for each pair of physical qubits there is an edge connecting the pair of physical qubits.

[0151] In step S340, the first weighted graph is mapped to the reduced second weighted graph using a graph overlaying algorithm which minimizes a mapping cost function. The mapping cost function can be given by a weight difference associated with the mapping. That is, in order to minimize the mapping cost function, logical qubits with a high gate operation weight are mapped to physical qubits which are connected by high quality optical connection (i.e., low probability of photon loss) and logical qubits with a low gate operation weight are mapped to physical qubits connected via low quality optical connection (i.e., high probability of photon loss).

[0152] The graph overlaying algorithm can seek to minimize the overlaying. The graph overlaying algorithm may determine a global minimum the overlaying. In some cases, the graph overlaying algorithm only determines a local minimum of the overlaying.

[0153] The graph overlaying algorithm maps each first node to a second node and can also map each first edge to a second edge.

[0154] Figure 4 shows a flow diagram illustrating a method for mapping the first weighted graph to the second weighted graph. The method can be implemented as a sub-method of the method illustrated in Figure 3 and described above. In particular, the method described in the following can be used as a specific implementation of step S340 of the above-described method.

[0155] The graph overlaying algorithm may be an overlaying weight minimizing algorithm that maps the first edges in descending order of the weights of the first edges to the second edges in ascending order of the weights of said second edges.

[0156] In step S341 , the first edge with the highest weight is determined.

[0157] In step S342, the first edge is associated with a second edge having the lowest weight among all second edges. The endpoints joined by the first edge (i.e. , two of the first nodes) are associated with the endpoints joined by the second edge (i.e., two of the second nodes).

[0158] In step S343, it is determined whether there are any further first edges which are not yet associated with a second edge. If this is the case, step S341 is repeated, now selecting the first edge with the highest weight amongst all first edges not yet associated with the second edge. Similarly, in step S342 only second edges not yet associated with a first edge are taken into account. Moreover, in step S342, previous associations are taken into account. That is, if one of the endpoints (i.e., first nodes) of the selected first edge is already associated with a second node, only second edges are taken into account which have said second node as an endpoint. In this way, the mapping complies with previous associations.

[0159] If there are no further first edges which are not yet associated with a second edge, the obtained mapping is provided as an output, S344.

[0160] In some cases, there can be a plurality of second edges having lowest weights among the second edges that are not yet associated with a first edge. In someembodiments, one of the second edges is randomly selected. In other embodiments, steps S341 to S343 are iterated for each possible choice of associating the determined first edge to one of plurality of second edges. After a predetermined number of iteration steps, iteration is stopped. For each possible choice of second edge, a cumulative weight of the association is computed. For example, the cumulative weight of the choice may be obtained by adding the weights of all second edges that are associated with a first edge after the predefined iteration steps. The second edge is selected which is associated with the lowest cumulative weight.

[0161] Figure 5 shows an exemplary illustration of a reduction of a second weighted graph. The graph includes nodes represented as circles, diamonds, and squares, which represent physical qubits, optical switches, and detectors, respectively. The original second weighted graph is illustrated on the left-hand side and comprises a first physical qubit Q1 and a second physical qubit Q2. Each of the physical qubits Q1 , Q2 can be a T centre in silicon but the invention is not restricted to any particular implementation of the physical qubit.

[0162] The second weighted graph further comprises a first switch S1 , a second switch S2, a third switch S3, and a detector D1. The physical qubits Q1 , Q2 can be connected via the detector D1. Detection patterns from detector D1 are used to herald entanglement between the physical qubits Q1 and Q2 according to a predetermined entanglement protocol.

[0163] In the second weighted graph, the physical qubits Q1 , Q2 can be connected according to a first optical connection,Q1 S1 D1 S1 S2 S3 Q2, going from the first physical qubit Q1 to the first switch S1 , to the detector D1 , back to the first switch S1 , to the second switch S2, to the third switch S3 and finally to the second physical qubit Q2. A second optical connection,Q1 -^ S1 — > D1 -^ S3 ^ Q2, goes from the first physical qubit Q1 to the first switch S1 , to the detector D1 , to the third switch S3, and finally to the second physical qubit Q2.

[0164] In order to reduce the second weighted graph, the quality of the first and second optical connections are computed. The quality of the optical connections can becomputed by calculating the sum total of photon loss probabilities associated with the corresponding hardware components, e.g., optical links, optical paths, optical switches and detectors. In the illustrated example, the first optical connection is more lossy than the second optical connection because the sum total of photon loss probabilities associated with the first optical connection includes additional contributions from the first switch S1 and the second switch S2. Accordingly, the second optical connection is selected (indicated by solid links in the figure) as the optical connection that defines the weight of the second edge. A reduced second weighted graph based on the second optical connection may be generated by eliminating the hardware components S1 , D1 , and S3, such that the reduced graph comprises only two nodes corresponding to the first physical qubit Q1 and the second physical qubit Q2. These nodes are connected by a reduced second edge as illustrated on the right-hand side of figure 5. A weight of reduced second edge is given by the quality of the second optical connection.

[0165] As will be appreciated, to generate the reduced second weighted graph, the intermediate switches S1 , S3 and the detector D1 have been eliminated from the second weighted graph and only an optical link between the physical qubits Q1 , Q2 remains.

[0166] In the above illustration, the photon loss inherent to each of the switches S1 , S2, and S3 was assumed to be equal for simplicity purposes. As will be appreciated, the photon loss inherent to the hardware component may differ.

[0167] Figure 6 shows an example of a first weighted graph obtained from a logical circuit. In the upper part, the logical quantum circuit is illustrated, having five logical qubits with indices q_0, q_1 , q_2, q_3, and q_4.

[0168] In total, there are six CNOT gates:- three CNOT gates connect the first logical qubit within index q_0 and the second logical qubit with index q_1 ,- one CNOT gate connects the second logical qubit within index q_1 and the third logical qubit with index q_2,- one CNOT gate connects the second logical qubit within index q_1 and the fourth logical qubit with index q_3, and- one CNOT gate connects the first logical qubit within index q_0 and the fifth logical qubit with index q_4.

[0169] Further, there are two Fredkin gates:- a first Fredkin gate connects the first logical qubit within index q_0, the second logical qubit with index q_1 , and the third logical qubit with index q_2, and- a second Fredkin gate connects the second logical qubit with index q_1 , the third logical qubit with index q_2, and the fourth logical qubit within index q_3.

[0170] In total, there are:- four logical gates connecting the first logical qubit within index q_0 and the second logical qubit with index q_1 ,- three logical gates connecting the second logical qubit within index q_1 and the third logical qubit with index q_2,- two logical gates connecting the second logical qubit within index q_1 and the fourth logical qubit with index q_3, and- one logical gate connecting the first logical qubit within index q_0 and the fifth logical qubit with index q_4.

[0171] Accordingly, the logical quantum circuit is represented by the first weighted graph illustrated in the lower part of the figure. The first weighted graph comprises five first nodes with indices q_0 to q_4 corresponding to the five logical qubits with indices q_0 to q_4. Moreover, there are four first edges with weights corresponding to the connections described above (i.e., having values 1 , 2, 3, and 4, respectively).

[0172] Figure 7 shows an exemplary mapping of the first weighted graph from figure 6 to a second weighted graph. The second weighted graph represents a target quantum hardware device and is illustrated in the lower part of the figure. The second weighted graph comprises five second nodes with indices Q_0 to Q_4 corresponding to five physical qubits. The second weighted graph is fully connected, i.e., for each pair of second nodes (i.e., pair of physical qubits) there is a second edge (i.e., optical connection) connecting the second nodes.

[0173] A link quality weight is associated with each second edge, corresponding to the quality of the optical connection corresponding to the second edge.

[0174] For this specific case, the mapping of the first weighted graph to the second weighted graph may be obtained as follows:

[0175] First, a first edge with the highest weight among the first edges is identified. In this case, this is the first edge connecting the first node with index q_0 and the first node with index q_1 (with weight 4). This first edge is associated with the second edge having the lowest weight, i.e. the second edge between the second node with index Q_1 and the second node with index Q_4 (having a weight of 1). The corresponding endpoints (nodes) are mapped, i.e.:- the first node with index q_0 is associated with the second node with index Q_1 , and- the first node with index q_1 is associated with the second node with index Q_4.

[0176] In the next iteration, the first edge with the highest weight among the first edges that are not yet associated with a second edge is identified. This is the first edge between the first node with index q_1 and the first node with index q_2 (with weight 3). This first edge is associated with the second edge having the lowest weight among the second edges that are not yet associated with a first edge and comply with (i.e., respect) previous associations.

[0177] Because the first node with index q_1 is already associated with the second node with index Q_4, this means that only second edges connected to the second node with index Q_4 are taken into account. Amongst these second edges, the second edge with the lowest weight is the second edge between the second node with index Q_4 and the second node with index Q_0 (having a weight of 2). The corresponding endpoints (nodes) are mapped, which gives the additional identification:- the first node with index q_2 is associated with the second node with index Q_0.

[0178] In the next step, the first edge between the first node with index q_1 and the first node with index q_3 (with weight 2) is associated with the second edge between the second node with index Q_4 and the second node with index Q_3 (with weight 5). The corresponding endpoints (nodes) are mapped, which gives the additional identification:- the first node with index q_3 is associated with the second node with index Q_3.

[0179] In the final step, the first edge between the first node with index q_0 and the first node with index q_4 (with weight 1) is associated with the second edge between the second node with index Q_1 and the second node with index Q_2 (with weight 6). The corresponding endpoints (nodes) are mapped, which gives the additional identification:- the first node with index q_4 is associated with the second node with index Q_2.

[0180] In total, the first nodes of the first weighted graph are mapped to the second nodes of the second weighted graph as follows:- the first node with index q_0 is associated with the second node with index Q_1 ,- the first node with index q_1 is associated with the second node with index Q_4,- the first node with index q_2 is associated with the second node with index Q_0,- the first node with index q_3 is associated with the second node with index Q_3, and- the first node with index q_4 is associated with the second node with index Q_2.

[0181] The illustrated mapping is only exemplary and the implementation is not restricted to any particular number of logical qubits or physical qubits.

[0182] In summary, the specification relates to a mapping of logical qubits to quantum systems which allows implementing the logical quantum circuit on target quantum hardware devices such that the quality of optical connections between the quantum systems are accounted for in generating the mapping.

[0183] The devices, apparatuses and systems described in the present disclosure may comprise electronic components and circuits known to those skilled in the art. Therefore, details of the circuitry and its components have not be explained in any greater extent than that considered necessary for the understanding and appreciation of the underlying concepts of the present disclosure.

[0184] Where reference is made to a component, such as a device, component, software module or the like, the reference to that component is intended to include as equivalents any component being functionally equivalent, i.e., performing the same function, even though the component is not necessarily structurally equivalent to the component that performs in the exemplary embodiments.

[0185] In the above description, embodiments have been described with reference to specific details, e.g., parts of a method, components, materials, and the like. A person skilled in the art will understand that embodiments may be implemented without one or more of these specific details.

[0186] All of the US patents, US patent application publications, US patent applications, foreign patents, foreign patent applications, and non-patent publications referred to inthis specification, or referred to on any application data sheet, are incorporated by reference in their entireties for all purposes herein.

[0187] A person skilled in the art may understand that certain method steps may be described or depicted in a particular order of occurrence while such specificity with respect to sequence is not actually required.

[0188] Phrases like “an embodiment” and “another embodiment” are used in the sense that particular features described in connection with the embodiment are included in at least one embodiment. Those phrases do not necessarily all refer to the same embodiment. Terms such as "first", "second", “third”, and so on, are used to distinguish between the elements described by these terms. These terms do not necessarily imply any temporal or other prioritization of such elements.

[0189] As used herein, the singular forms "a," "one," and "the " are also intended to encompass the plural forms unless the context indicates otherwise. In addition, it is understood that the expressions "includes" and / or "including" when used in this specification relates to the presence of features, numbers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more features, numbers, steps, operations, elements and / or combinations thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed elements.

[0190] Terms such as “horizontal”, “vertical”, “upper”, “lower”, “above”, “below”, “forward” and “backward” refer to particular orientations of components and / or events in time and / or space. The skilled person understands that may therefore depend on the specific orientation and may change if the components and / or events are oriented differently.

[0191] In this specification, the present disclosure has been described with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the present disclosure is not limited to the described exemplary embodiments described and may be modified in various different ways. Consequently, the drawings and description are intended to be illustrative in nature and not limiting. Identical reference numbers denote identical elements in the specification.

[0192] As used herein, the terms "about," "approximately," or "substantially" refer to a value, amount, or property that is close to the specified value, amount, or property. Thevalue, amount, or property is such that a desired function or result is still achieved. According to an example, an amount may be less than 10%, 5%, 1%, or 0.1 % of the specified amount, respectively.

[0193] Even if the disclosure has been described and illustrated with reference to illustrative embodiments, various modifications may be made without departing from the scope of the present disclosure as defined in the claims. Such modifications may comprise replacement of features, components and / or method steps with equivalent features, components and / or method steps; mixing of features, components and / or method steps from different embodiments; and / or omitting or combining features, components and / or method steps from described embodiments. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.

Claims

WHAT IS CLAIMED IS:

1. A method for executing a logical quantum circuit on a target quantum hardware device, the method comprising: obtaining, for each pair of a plurality of pairs of logical qubits in the logical quantum circuit, a gate operation weight, wherein the gate operation weight depends on an occurrence frequency of multi-qubit gate operations between the pair of logical qubits; obtaining, for each pair of a plurality of pairs of quantum systems in the target quantum hardware device, a link quality weight, wherein the link quality weight depends on quality of an optical connection between the pair of quantum systems; generating a mapping of the logical qubits to the quantum systems such that a mapping cost function is minimized, wherein the mapping cost function depends on the gate operation weights and the link quality weights; and executing the logical quantum circuit on the target quantum hardware device based on the mapping.

2. The method of claim 1 , further comprising the steps of: representing the logical quantum circuit as a first weighted graph having a plurality of first nodes and a plurality of first edges, wherein each first edge of the plurality of first edges joins two first nodes of the plurality of first nodes, wherein each first node corresponds to a logical qubit of the logical quantum circuit, and wherein a weight of each first edge is given by the gate operation weight of the pair of logical qubits corresponding to the first nodes joined by said first edge; representing a connectivity of the quantum hardware device as a second weighted graph having a plurality of second nodes and a plurality of second edges, whereineach second edge of the plurality of second edges joins two second nodes of the plurality of second nodes, wherein each second node corresponds to a quantum system, and wherein a weight of each second edge is given by the link quality weight of the pair of quantum systems corresponding to the second nodes joined by said second edge; wherein generating the mapping of the logical qubits to the quantum systems comprises mapping the first weighted graph to the second weighted graph using a graph overlaying algorithm.

3. The method of claim 2, wherein the graph overlaying algorithm is an overlaying weight minimizing algorithm.

4. The method of claim 3, wherein the overlaying weight minimizing algorithm maps the first edges in descending order of the weights of said first edges to the second edges in ascending order of the weights of said second edges.

5. The method of claim 2, wherein mapping the first weighted graph to the second weighted graph comprises iterating the following steps: determining a first edge having the highest weight among the first edges that are not yet associated with a second edge; and associating said determined first edge with a second edge having the lowest weight among the second edges that are not yet associated with a first edge and comply with previous associations.

6. The method of claim 5, wherein the two first nodes connected by said determined first edge are associated with the two second nodes connected by said second edge associated with said determined first edge.

7. The method of claim 5, wherein, where there are a plurality of second edges having lowest weights among the second edges that are not yet associated with a first edge, the iteration is performed for each possible choice of associating the determined first edge to one of said plurality of second edges.

8. The method of claim 7, wherein the iteration is stopped after a predefined number of iteration steps, wherein the choice with a lowest cumulative weight of the association is selected, and wherein the determined first edge is associated to one of said plurality of second edges according to the selected choice.

9. The method of claim 8, wherein the cumulative weight of the choice is computed by adding the weights of all second edges that are associated with one of the first edges after the predefined iteration steps.

10. The method of claim 2, wherein mapping the first weighted graph to the second weighted graph comprises mapping each first node to a second node and mapping each first edge to a second edge.11 . The method of claim 2, wherein the second weighted graph is an undirected fully connected weighted graph.

12. The method of claim 1 , wherein the mapping cost function corresponds to a weight difference associated with the mapping.

13. The method of claim 1 , wherein the link quality weights decrease with increasing quality of the optical connection.

14. The method of claim 1 , wherein the link quality weight corresponds to photon loss probability associated with the optical connection between the pair of quantum systems.

15. The method of claim 1 , further comprising using a machine learning algorithm for generating the mapping of the logical qubits to the quantum systems.

16. The method of claim 1 , wherein at least some of the quantum systems correspond to T centre defects in a silicon substrate.

17. The method of claim 16, wherein the optical connection between a pair of T centre defects comprises a telecom photonic interface of the T centre in the silicon substrate.

18. The method of claim 17, wherein the optical connection between a pair of T centre defects comprises at least one photonic waveguide integrated in the silicon substrate and / or at least one optical fibre.

19. The method of claim 16, wherein the target quantum hardware device is configured for supporting entanglement of T centre defects.

20. The method of claim 19, wherein the target quantum hardware device is configured such that the entanglement is distributed by photons which are transmitted over the optical connections between T centre defects.21 . The method of claim 19, wherein the target quantum hardware device is configured to prepare maximally entangled Bell pairs using the T centre defects.

22. The method of claim 1 , wherein each pair of quantum systems in the target quantum hardware device is connectable by at least one optical connection.

23. The method of claim 1 , wherein at least one pair of quantum systems in the target quantum hardware device is connected by a plurality of optical connections.

24. The method of claim 1 , wherein the optical connection connecting two quantum systems in the target quantum hardware device comprise at least one of an optical link, a switch, and a detector.

25. The method of claim 24, wherein quantum systems in the target quantum hardware device can become entangled by means of at least two detectors.

26. The method of claim 24, wherein the quality of the optical connection between a pair of quantum systems depends on at least one of a number of the optical links, a number of the switches and a number of the detectors in the optical connection between said pair of quantum systems.

27. The method of claim 24, wherein the quality of the optical connection between a pair of quantum systems depends on at least one of a photon loss value associated with the optical links, a photon loss value associated with the switches and a photon loss value associated with the detectors in the optical connection between said pair of quantum systems.

28. The method of claim 27, wherein the quality of the optical connection between a pair of quantum systems depends on at least one of a sum of the photon loss values of all optical links, a sum of the photon loss values of all switches and a sum of the photon loss values of all detectors in the optical connection between said pair of quantum systems.

29. The method according to claim 1 , wherein a representation of the mapping of the logical qubits to the quantum systems is stored in a database.

30. The method according to claim 1 , comprising the further step of operating the target quantum hardware device to perform a quantum algorithm on the target quantum hardware device.31 . A computer program product comprising executable program code configured to, when executed by a computing device, perform the method according to claim 1.

32. A non-transitory, computer-readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method according to claim 1 .

33. A device for executing a logical quantum circuit on a target quantum hardware device, comprising: at least one processor; and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to: obtain, for each pair of a plurality of pairs of logical qubits in the logical quantum circuit, a gate operation weight, wherein the gate operation weight depends on an occurrence frequency of multi-qubit gate operations between the pair of logical qubits; obtain, for each pair of a plurality of pairs of quantum systems in the target quantum hardware device, a link quality weight, wherein the link quality weight depends on quality of an optical connection between the pair of quantum systems; generate a mapping of the logical qubits to the quantum systems such that a mapping cost function is minimized, wherein the mapping cost function depends on the gate operation weights and the link quality weights; and generate a control signal for controlling the quantum hardware device to executethe logical quantum circuit on the target quantum hardware device based on the mapping.

34. An information processing system comprising: a quantum hardware device; at least one processor communicatively coupled to the quantum hardware device; at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to: generate a mapping of a plurality of logical qubits of a logical quantum circuit to a plurality of physical qubits of the quantum hardware device, wherein a gate operation weight is assigned to each pair of a plurality of pairs of the logical qubits, wherein the gate operation weight depends on a number of multi-qubit gate operations between the pair of logical qubits, wherein a link quality weight is assigned to each pair of a plurality of pairs of the physical qubits, wherein the link quality weight depends on quality of an optical connection between the pair of physical qubits, wherein a mapping cost function is minimized, and wherein the mapping cost function depends on the gate operation weights and the link quality weights; and control the quantum hardware device to execute the logical quantum circuit, based on the mapping.

35. The information processing system of claim 34, wherein the processor-executable instructions, when executed by the at least one processor, further cause the at least one processor to:represent the logical quantum circuit as a first weighted graph having a plurality of first nodes and a plurality of first edges, wherein each first edge of the plurality of first edges joins two first nodes of the plurality of first nodes, wherein each first node corresponds to a logical qubit of the logical quantum circuit, and wherein a weight of each first edge is given by the gate operation weight of the pair of logical qubits corresponding to the first nodes joined by said first edge; and represent a connectivity of the quantum hardware device as a second weighted graph having a plurality of second nodes and a plurality of second edges, wherein each second edge of the plurality of second edges joins two second nodes of the plurality of second nodes, wherein each second node corresponds to a physical qubit, and wherein a weight of each second edge is given by the link quality weight of the pair of physical qubits corresponding to the second nodes joined by said second edge; wherein the at least one processor is configured to generate the mapping of the logical qubits to the quantum systems by mapping the first weighted graph to the second weighted graph using a graph overlaying algorithm.

36. The information processing system of claim 34, wherein the quantum hardware device comprises a semiconductor body with a plurality of luminescent defects disposed within the semiconductor body.

37. The information processing system of claim 36, wherein the luminescent defects comprise T centre defects.

38. The information processing system of claim 36, wherein the optical connection between a pair of T centre defects comprises a telecom photonic interface of the T centre in the silicon substrate.

39. The information processing system of claim 36, wherein the optical connection between a pair of T centre defects comprises at least one photonic waveguide integrated in the silicon substrate and / or at least one optical fibre.

40. The information processing system of claim 36, wherein the target quantum hardware device is configured for supporting entanglement of T centre defects.41 . The information processing system of claim 40, wherein the target quantum hardware device is configured such that the entanglement is distributed by photons which are transmitted over the optical connections connecting the T centre defects.

42. The information processing system of claim 40, wherein the target quantum hardware device is configured to prepare maximally entangled Bell pairs using the T centre defects.

43. The information processing system of claim 34, wherein each pair of physical qubits in the target quantum hardware device is connectable by at least one optical connection.

44. The information processing system of claim 34, wherein at least one pair of physical qubits in the target quantum hardware device is connectable by a plurality of optical connections.

45. The information processing system of claim 34, wherein the optical connections connecting two quantum systems in the target quantum hardware device comprise at least one of an optical link, a switch, and a detector.

46. The information processing system of claim 34, wherein physical qubits in the target quantum hardware device can become entangled by means of at least two detectors.

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