Pseudo-interdigitated-corbino thin film transistor with multi-finger source and drain electrical contacts

Abstract

Disclosed is a semiconductor thin film transistor (TFT) with an easily implementable and improved Corbino-type TFT architecture to accommodate a large channel width in a limited layout space. According to the invention, the semiconductor TFT comprises an optimized architecture in which the source and drain electrodes are arranged in a novel Pseudo-interdigitated-corbino configuration. The TFT architecture comprises a more readily manufacturable pseudo-corbino type multi-finger configuration that offers infinite output resistance to provide constant drain current in the saturation region with reduced fabrication process steps compared to a conventional corbino TFT architecture.

Description

PSEUDO-INTERDIGITATED-CORBINO THIN FILM TRANSISTOR WITH MULTI-FINGER SOURCE AND DRAIN ELECTRICAL CONTACTSFIELD OF THE INVENTION:

[0001] The present invention pertains to thin film transistors (TFTs), more particularly, to a TFT with a multi -finger or Corbino source / drain architecture. One embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.BACKGROUND OF THE INVENTION:

[0002] Thin film transistors (TFTs) are the essential building block in various thin film electronic applications, such as LED (Light emitting diodes) displays, image sensors, RF-ID (Radio Frequency Identification) tags, and other low-cost electronics. In recent years, different TFT technologies, such as low- temperature poly-silicon (LTPS) TFT, amorphous oxide semiconductor (AOS) TFT, and Organic TFT (OTFT), achieved desired performance in terms of figures of merit, like mobility, sub-threshold slope, and contact resistance, along with reliability [J. Li etal., “A stable solution-processed polymer semiconductor with record high-mobility for printed transistors,” Scientific Reports, vol. 2, p. 754, 10, 2012], [J. W. Borchert et al., “Small contact resistance and high- frequency operation of flexible low-voltage inverted coplanar organic transistors,” Nature Communications, vol. 10, no. 1, pp. 1-11, 2019],

[0003] However, achieving high transconductance, infinite output resistance, and reduced parasitic leakage in a limited layout space is desirable when adapting suitable TFT technology for logic-TFT or driver-TFT applications [H. E. A. Huitema et al., “Active -matrix displays driven by solution-processed polymeric transistors,” Advanced Materials, vol. 14, no. 17, pp. 1201-1204, 2002], [H. Jia et al., “Gate induced leakage and drain current offset in organic thin film transistors,” Organic Electronics: physics, materials, applications, vol.7, no. 1, pp. 16-21, 2006], The use of high-mobility semiconductors or forcible downscaling of channel length(L) and gate overlap (Lov) using photolithography to achieve high transconductance pose challenges in adopting various TFT technologies, such as limiting the choice of semiconductor, incompatibility with photolithography and high manufacturing cost.

[0004] Along with it, the aggressive downscaling of the TFT dimensions gives rise to short-channel effects, one of which is the finite output resistance in the saturation region of TFT operation due to the effective channel length modulation [M. Mativenga etal. , “Infinite output resistance of corbino thin-film transistors with an amorphous-InGaZnO active layer for large-area AMOLED displays,” IEEE Transactions on Electron Devices, vol. 61, no. 9, pp. 3199- 3205, 2014], This short channel effect may cause variation in the output current of the TFT at constant gate voltage, affecting the quality of the display.

[0005] In addition, TFT technologies that employ low-mobility semiconductors, such as organic semiconductors or polymers, have poor performance due to low transconductance. These materials also show incompatibility with photolithography due to their soft nature. Moreover, achieving low parasitic leakage also requires patterning the semiconductor layer by different processes, resulting in complex and expensive fabrication [S. De Vusser et al. , “Integrated shadow mask method for patterning small molecule organic semiconductors,” Applied Physics Letters, vol. 88, no. 10, pp. 2004- 2007, 2006],

[0006] Meanwhile, adapting TFTs with the large W / L (width-to -length) ratio in the circuit design is another approach to achieve increased transconductance, even for low -mobility semiconductors. To this end, interdigitated electrodes are favorable in overcoming the challenge of accommodating high W / L ratio TFTs in limited layout space [H. Lee et al. , “Asymmetric electrical properties of half corbino hydrogenated amorphous silicon thin-film transistor and its applications to flat panel displays,” Japanese Journal of Applied Physics, vol. 50, no. 7 PART1, pp. 1-8, 2011], [E. E. Hollis, “Design ofVLSI Gate Array ICs,” Upper SaddleRiver, NJ: Prentice-Hall, 1987],

[0007] Further, the circular Corbino structure is recommended to achieve a low OFF -current, which not only offers infinite output resistance but also results in reduced parasitic leakage current due to its impressive electrical isolation characteristics without semiconductor pattering [H. Klank et al., “Pentacene organic thin-film transistors for circuit and display applications,” IEEE Transactions on Electron Devices, vol. 46, no. 6, pp. 1258-1263, 1999],

[0008] However, implementing a conventional Corbino structure is difficult for TFTs consisting of low-mobility semiconductors with large W / L ratio TFTs due to sufficiently large dimensions of concentric electrodes [L. Chen et al., “Thin film transistor and fabricating method thereof, and array substrate,” US Patent 10535781B2, (2020, Jan 14)]. The conventional circular Corbino TFT is challenging to accommodate in the limited layout space, leading to a smaller pixel aperture ratio in a limited footprint.

[0009] In the prior arts, United States Patent No. 7425734 B2 to William S. Wong etal., entitled “Thin-film transistor array with ring geometry,” deals with different types of TFT electrode geometries, including a ring geometry for a layered display structure including a transistor layer to drive pixels in a media. Whereas, United States Patent No. 10535781 B2 to Lin Chen et al., entitled “Thin film transistor and fabricating method thereof, and array substrate,” discloses a thin film transistor comprised of double active layers arranged as one top of another with dual gate dielectrics and circular Corbino source and drain electrodes at the side of respective active layers. Also, M. Mativenga et al., in the article “Infinite output resistance of corbino thin-film transistors with an amorphous-InGaZnO active layer for large-area AMOLED displays” discusses the application of conventional circular Corbino TFT architecture in oxide semiconductor TFTs.

[0010] Though the few existing prior art discloses the conventional circular or ring Corbino geometry to leverage low-cost semiconductors, particularly with polymer semiconductors, and to achieve infinite output resistance, none of the existing literature delves into novel methods or approaches to overcome the limitations of conventional multi-finger and Corbino TFT architectures to attain excellent electrical isolation, increased transconductance and infinite output resistance, simultaneously, while accommodating high W / L ratio TFT in a limited footprint using a more simplified fabrication approach.

[0011] Thus, a novel TFT structure or method that can accommodate a sizable large channel width with a coupled Corbino geometry facilitating reduced off- current characteristics and high transconductance with a more simplified fabrication approach is needed.SUMMARY OF THE INVENTION:

[0012] An object of the present invention is to provide a manufacturable TFT architecture to produce thin-film transistors wherein the source and drain electrodes are arranged to accommodate a large channel width using an enclosed interdigitated pattern.

[0013] An object of the present invention is to provide a manufacturable TFT architecture to produce thin-film transistors wherein the source and drain electrodes are arranged to provide improved electrical isolation similar to conventional Corbino TFT architecture.

[0014] Another object of the present invention is to provide a more readily manufacturable Corbino-type TFT architecture to produce thin-film transistors with reduced fabrication process steps compared to a conventional Corbino TFT architecture.

[0015] Yet another object of the present invention is to provide high- performance thin-film transistor, comprising the gate dielectric layer and at least the gate and the source and drain electrodes, with a thin film semiconductor layer formed over or below the said source and drain electrodes arranged in any of the possible configurations: top-gate top-contact (TG-TC), top-gate bottomcontact (TG-BC), bottom-gate bottom-contact (BG-BC) or bottom-gate topcontact (BG-TC).

[0016] Yet another object of the present invention is to provide a high- performance thin film transistor with infinite output resistance to provide a constant drain current in the saturation region.BRIEF DESCRIPTION OF THE DRAWINGS:

[0017] The objectives of the present invention are described in more detail concerning the following accompanying drawings.

[0018] Fig. 1. represents the top view and the cross-section view of the conventional circular Corbino TFT in traditional miniaturized bottom-gate topcontact (BG-TC) configuration (as per the prior arts);

[0019] Fig. 2. shows the schematic of the Pseudo-interdigitated-corbino architecture having the arrangement of source and drain contacts as a combination of multiple overlapping linear channel regions with channel width Wov and half of the Corbino disks, with outer electrode 01 arranged symmetrically around the inner electrode 02 with the right and left mirror sides to minimize any aspect ratio variation (aberration).

[0020] Fig. 3. (a) represents atop schematic of circular Corbino TFT (as per the prior arts) (b) having the circular semiconductor channel region 02 with inner and outer radius rl and r2, modified into a partially shielded Corbino structure (c) and further enveloped into an arrangement of overlapping linear channelregions with channel width Wov and half of the corbino disks with average channel width Ws.

[0021] Fig. 4. Illustrates the Pseudo-interdigitated-corbino TFT architecture according to the present disclosure with channel length L and the inner and outer radius Ri and R2 of half of the corbino disks with average channel width Ws.

[0022] Fig. 5. illustrates the schematic of a miniaturized TFT in BG-BC configuration with source element 14 and drain element 15 arranged in the novel Pseudo-interdigitated-corbino architecture according to the present disclosure.

[0023] Fig. 6. Illustrates the output characteristics of the fabricated poly( / V- alkyldikctopyrrolo-pyrrolc-dithicnylthicno|3.2- / ?|thiophcnc) (DPP-DTT) semiconductor-based TFT in BG-BC configuration with 8 pm channel length and a W / L (width-to-length) ratio of 500, having source element 14 and drain element 15 arranged in the novel Pseudo-interdigitated-corbino architecture according to the present disclosure.

[0024] Fig. 7. shows the transfer characteristics of the fabricated DPP-DTT semiconductor-based TFT in BG-BC configuration with 8 pm channel length and a W / L ratio of 500, having source element 14 and drain element 15 arranged in the novel Pseudo-interdigitated-corbino architecture according to the present disclosure.

[0025] Fig. 8. shows the single output characteristics at VGS = -20V of the fabricated P3HT semiconductor-based TFT in BG-BC configuration with 8 pm channel length and a W / L ratio of 500, having source element 14 and drain element 15 arranged in the novel Pseudo-interdigitated-corbino architecture according to the present disclosure.

[0026] Fig. 9. shows the differential output conductance characteristics corresponding to the output characteristics at VGS = -20V of the fabricated P3HTsemiconductor-based TFT in BG-BC configuration with 8 pm channel length and a W / L ratio of 500, having source element 14 and drain element 15 arranged in the novel Pseudo-interdigitated-corbino architecture according to the present disclosure.DETAILED DESCRIPTION OF THE INVENTION:

[0027] The embodiments herein and the various features and advantageous details thereof are explained with reference to the non-limiting embodiments and drawings in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.

[0028] The term “interdigitated” TFT refers to a specific configuration of a thin- film transistor where the source and drain electrodes have interdigitated fingers, wherein the fingers of the source electrode alternate with the fingers of the drain electrode. The term “corbino geometry” refers to incorporating the circular or ring-shaped concentric / nested source and drain electrode structure into the TFT.

[0029] According to an embodiment of the present invention, an improved semiconductor thin film transistor (TFT) with an optimized and easily implementable novel Corbino-type TFT architecture to accommodate a large channel width (W) within a limited layout space is disclosed. The semiconductor TFT comprises a TFT architecture in which the source and drain electrodes are arranged in a novel Pseudo-interdigitated-corbino configuration.

[0030] The novel Psuedo-interdigitated-corbino TFT architecture comprises an arrangement of the source and drain electrodes to accommodate the large channel width (W) of the TFT in an enclosed interdigitated pattern. It isachieved by realizing an equivalent pseudo-corbino structure design as a combination of half-corbino structure and overlapping linear channels.

[0031] In a typical TFT, the interdigitated electrode configuration is favorable in overcoming the challenge of accommodating high channel width (W) to channel length (L) ratio in a limited layout space, which is also an approach to obtaining increased transconductance [see E. E. Hollis et al. , “Design of VLSI Gate Array ICs,” Upper Saddle River, NJ: Prentice -Hall, 1987] other than the approach of aggressive downscaling of the TFT dimensions (i.e., channel length L and gate overlap length Lov). This architecture is employed to achieve high ON-current characteristics in TFTs; for example, see R. Schmechel et al., Proc. SPIE, 5217 (2003), 101.

[0032] Another available TFT architecture is with the conventional circular Corbino source and drain electrodes, illustrated in Fig. 1 (as per the prior art). The concentric source electrode 01 and drain electrode 03 enclose the semiconductor layer 02 in between, as shown in the top view. A clearer picture of the arrangement of the concentric source electrode 01, the drain electrode 03, and the semiconductor layer 02 is shown in the cross-section schematic of the circular Corbino TFT. It has a nested ring arrangement of source and drain elements instead of lateral source and drain elements, preventing leakage through the unpattemed semiconductor layer [see H. Klauk et al., “Pentacene organic thin film transistors for circuit and display applications,” Electron Devices, IEEE Transactions, 46(6), 1258-1263, 1999],

[0033] Moreover, It results in reduced parasitic leakage current due to its impressive electrical isolation characteristics and offers infinite output resistance in the saturation region with stable drain output characteristics for TFTs [M. Mativenga et al., “Infinite output resistance of corbino thin-film transistors with an amorphous-InGaZnO active layer for large-area AMOLED displays,” IEEE Transactions on Electron Devices, vol. 61, no. 9, pp. 3199- 3205, 2014], [H. Klauk et al. , “Pentacene organic thin-film transistors for circuitand display applications,” IEEE Transactions on Electron Devices, vol. 46, no.6, pp. 1258-1263, 1999],

[0034] Meanwhile, the drawback of the increased number of added mask steps is also involved in the implementation of the circular Corbino TFT architecture due to the requirement of the additional insulator layer 04 and metal layer 05 to create the topography to access the central electrode element on top of the semiconductor layer 02, resulting in no net mask count savings as illustrated in the cross-section view of circular Corbino TFT in Fig. 1 [I. Kymissis et al., “Organic Field Effect Transistors: Theory, Fabrication and Characterization,” USA, NY, New York: Springer-Verlag, 2009], However, a guarded structure with a compromised corbino geometry can be implemented to overcome this drawback of the additional mask step. This compromised corbino geometry, called pseudo-corbino geometry, has an outer electrode element partially shielding the central electrode element that requires no additional patterning to access the central electrode element.

[0035] According to another embodiment of the present invention, the novel Pseudo-interdigitated-corbino TFT architecture is disclosed. The Pseudo- interdigitated-corbino architecture comprises a combination of lateral and pseudo-corbino geometry of TFT channel in an arrangement of the channel region as a combination of multiple overlapping linear channel regions (03) with channel width Wov and half of the Corbino disk (04) formation, as illustrated in Fig. 2, with an outer electrode 01 partially shielding the inner electrode 02 in a manner equivalent to a Corbino geometry. The outer electrode 01 is arranged symmetrically around the inner electrode 02, forming multiple half-corbino disks that connect overlapping linear channel regions with the right and left mirror sides to minimize any aspect ratio variation (aberration).

[0036] A circular Corbino structure, as shown in Fig. 3(a), having the channel region 02 fully enclosed with concentric source electrode 01 and drain electrode 03 with the inner electrode radius rl and outer electrode radius r2, can be turned into a partially shielded corbino geometry, as shown in Fig. 3(b). It can be afurther arranged, for example, to achieve an equivalent Pseudo-interdigitated- corbino architecture with a channel width (W) equal to the perimeter of the partially shielded Corbino structure. Channel region 02 can be enveloped into an arrangement as a combination of overlapping linear channel regions of channel width Wov and half of the corbino disks of average channel width Ws, as shown in Fig. 3(c). The arrangement in Fig. 3(c) is equivalent to a pseudo- corbino pattern with multiple interdigitated electrodes, a partially shielded corbino architecture, referred to as Pseudo-interdigitated-corbino architecture, as shown in Fig. 4.

[0037] In accordance with the present disclosure, the guidelines for a pseudo- interdigitated-corbino structure are delineated as follows:1. The width of the overlapping linear channel region, denoted as Wov, is emphasized to be sufficiently larger than the width Ws of the half-corbino disks, as depicted in Fig. 4.2. More specifically, Wov should be equal to or greater than two times the Ws, with the understanding that this specification is not confined to strict limitations.3. For a pseudo-interdigitated-corbino architecture with “n” number of interdigitated overlapping linear channels, the total channel width Wt is given by {n.Wov + (n-2).Ws}, where “n” is the number of interdigitated overlapping linear channels.4. The average width of half of the corbino disk (W s) is calculated using the middle circumference approximation {TI(RI+R2) / 2} as a function of geometrical parameters Ri and R2 (Fig. 4), i.e., the inner and the outer radius of half of the corbino disk with average channel width Ws, respectively, as shown in Fig. 4.

[0038] According to an embodiment of the present invention, the novel Pseudo- interdigitated-corbino architecture results in an easily manufacturable TFT architecture with reduced fabrication process steps compared to conventionalCorbino TFT architecture as the design formulates a guarded structure with the partially shielded corbino geometry in which the inner electrode can be accessed without any additional mask step, resulting in a net reduction in the mask steps due to no semiconductor patterning.

[0039] According to an embodiment of the present invention, a thin fdm transistor using the novel Pseudo-interdigitated-corbino architecture results in the TFT with infinite output resistance, providing constant drain output current in the saturation region, independent of drain bias VD.

[0040] According to an embodiment, Fig. 5 illustrates a miniaturized TFT configuration 10, according to the present disclosure, specifically but not limited to the BG-BC configuration, that comprises a lithographically patterned gate electrode 12 over a chosen substrate 11, a gate insulator 13 composed of a dielectric medium facilitating photolithography atop of it, a semiconductor film 16, and two laterally spaced photolithographically patterned source and drain conductive strips 14 and 15 arranged in Pseudo-interdigitated-corbino architecture as per the present invention, made of stable metal, a metal alloy, or a transparent conductor such as indium-tin-oxide, as a source and a drain electrode.

[0041] The miniaturized TFTs (e.g., TFT 10) generally include a gate dielectric 13 such as SiOx, SiNx, A1OX, or polymer dielectric media such as cross-linked PVP, cytop, or parylene-c, enabling the patterning of the source and drain electrodes using photolithography on top of these gate insulator 13.

[0042] A better understanding of the embodiments of the invention may be obtained in light of the following example, which is set forth to illustrate but is not to be construed to limit the above-described embodiments.Example 1:

[0043] Thin-film transistors with short channel lengths and a constant channel width-to-length ratio (W / L) of 500 in the BG-BC configuration are fabricated according to the invention as per the configuration illustrated in Fig. 5. The three-terminal TFTs are fabricated using 200 nm thermally grown (dry-wet-dry oxide) SiCh layer over the n-type silicon (Si) substrate. The bulk of the heavily doped Si substrate is used as a gate electrode in the common-gate configuration. The source and drain contacts are realized using photolithography in the Pseudo-interdigitated-corbino configuration as per the present discloser, with thermally evaporated Cr / Au (2 nm / 38 nm) metal stack, followed by the lift-off process. The average width of half of the corbino disk (Ws) is calculated using the middle circumference approximation {TI(RI+R2) / 2} as a function of geometrical parameters Ri and R2 as shown in Fig. 4, i.e., the inner and the outer radius, respectively. For the fabricated Pseudo-interdigitated-corbino TFT with channel length L = 8 pm with Ri = 9.5pm, R2 = 1.5pm and measured Wov = 94.7pm, the total channel width Wt is estimated to be approximately 4000pm.

[0044] The short channel length TFTs were achieved by finally coating the poly(A-alkyldikctopyrrolo-pyrrolc-dithicnylthicno|3.2- / ? |thiophcnc) (DPP- DTT) semiconductor over the patterned source / drain contacts arranged in Pseudo-interdigitated-corbino architecture according to the present disclosure. DPP-DTT thin films were prepared by spin-coating from dichlorobenzene (DCB) solution (5 mg / ml) on top of the already patterned source and drain metal electrodes.

[0045] The characterization of the fabricated TFT based on the DPP-DTT semiconductor shows the apparent p-type enhancement-mode behavior. The output and transfer characteristics of the 8 pm channel length device with a W / L ratio of 500 are shown in Fig. 6 and Fig. 7, respectively. As observed in Fig. 6, beyond pinch-off, the device shows flat output characteristics displaying the infinite output resistance characteristic in the saturation region for (VDS > VGS - Vth). The saturation mobility of 0.23 cm2 / V-s and the on / off ratio of 105has been calculated from the saturation transfer characteristics of the device shown in Fig. 7. The device showed a threshold voltage of -10 V. The device showedexcellent performance in terms of device parameters compared with the earlier reported results.

[0046] Fig. 8 shows the individual output characteristics of Poly(3- hexylthiophene) (P3HT) polymer semiconductor-based TFT with the same device design parameters as DPP-DTT-based TFT for gate bias VGS = -20V. P3HT thin fdms were prepared by spin-coating from dichlorobenzene (DCB) solution (5 mg / ml) on top of the already patterned source and drain metal electrodes. The individual output characteristics clearly show flat output characteristics displaying the infinite output resistance character in the saturation region for (VDS > Vcs_Vth). The corresponding differential output conductance for the output characteristic at VGS = -20V is shown in Fig. 9, further signifying the infinite output resistance achieved in the saturation region.

[0047] While the preceding written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should, therefore, not be limited by the above-described embodiment, method, and examples but by all embodiments and methods within the scope and spirit of the invention as claimed.

Claims

We Claim:

1. A thin film transistor, comprising: a. a gate dielectric layer and at least a photolithographically patterned gate electrode adjacent to the gate dielectric layer and positioned over a substrate; b. two laterally spaced, photolithographically patterned source and drain electrodes arranged in a Pseudo-interdigitated-corbino architecture; and c. a semiconductor film positioned adjecent to the gate dielectric layer and formed over or below the said source and drain electrodes arranged in any of the possible configurations.

2. The Pseudo-interdigitated-corbino architecture for thin film transistor, as claimed in claim 1, wherein the thin film transistor channel region comprises an arrangement of a combination of overlapping linear channel regions of channel width (Wov) and half of the corbino disks of average channel width (Ws).

3. The Pseudo-interdigitated-corbino architecture for thin film transistor, as claimed in claim 1, wherein the thin film transistor channel region comprises an arrangement forming an enclosed interdigitated pattern having multiple interdigitated electrodes into a partially shielded corbino geometry.

4. The Pseudo-interdigitated-corbinoarchitecture for thin film transistor, as claimed in claim 1, wherein the overlapping linear channel region width Wov is at least twice as large but not limited to a width Ws of the half corbino disks.

5. The Pseudo-interdigitated-corbino architecture for thin film transistor, as claimed in claim 1, wherein for the pseudo-interdigitated-corbino architecture with "n" interdigitated overlapping linear channels, a total channel width (W t) is based on {n. Wov+ (n-2).Ws}.

6. The Pseudo-interdigitated-corbino architecture for thin film transistor, as claimed in claim 1, wherein an average width of half of the corbino disk (Ws) is based on the middle circumference approximation { JT(R1+R2) / 2 } as a function of geometrical parameters R1 and R2.

7. The thin film transistor, as claimed in claim 1, exhibits infinite output resistance, providing constant drain output current in the saturation region, independent of drain bias voltage.

8. The thin film transistor, as claimed in claim 1, wherein the source and drain electrodes are made of a stable metal, a metal alloy, or a transparent conductor.

9. The thin film transistor, as claimed in claim 1, wherein the substrate is selected from glass, Si / SiC>2, flexible metal sheet, preferably stainless steel, aluminum, or flexible plastic substrate, specifically a PET or a PEN substrate.

10. The thin film transistor, as claimed in claim 1, wherein the gate dielectric layer is selected from SiOx, SiNx, A10Xjor organic polymeric dielectric media such as cross-linked PVP, Cytop, or Parylene-c, enabling the patterning of the source and drain electrodes using photolithography.

11. The thin film transistor, as claimed in claim 1, wherein the semiconductor layer is made of an inorganic semiconductor material such as amorphous-silicon, an organic semiconductor material, or an oxide semiconductor material such as IGZO (Indium gallium zinc oxide).

12. The thin film transistor, as claimed in claim 1, wherein the semiconductor layer is formed over or below the said source and drain electrodes in the top-gate topcontact, top-gate bottom-contact, bottom-gate bottom-contact, or bottom-gate top-contact configuration.

Images