Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention comprises: a semiconductor substrate (12); a channel layer (14) formed on the semiconductor substrate (12); a barrier layer (16) formed on the channel layer (14); and an electrode (18) formed on the barrier layer (16) and having a region diffused into the barrier layer (16) to a depth equal to or greater than half the thickness of the barrier layer (16).

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Among semiconductor devices using nitride semiconductors, such as gallium nitride (GaN), there is a high electron mobility transistor (HEMT) formed on a semiconductor layer, which has a source electrode, a drain electrode, and a gate electrode. In such semiconductor devices, in order to increase the amount of current flowing between the source electrode and the drain electrode, it is important to increase the electron density of the semiconductor layer and also to reduce the contact resistance between the source electrode and the drain electrode and the semiconductor layer.

[0003] In the semiconductor device described in Patent Document 1, in order to reduce the contact resistance, a heat treatment is performed after the source electrode and the drain electrode are formed.

[0004] Japanese Patent Application Laid-Open No. 2019-36586

[0005] However, heat treatment alone does not sufficiently diffuse the metal atoms that make up the electrodes, resulting in only a small reduction in contact resistance. Therefore, in the semiconductor device described in Patent Document 1, it is necessary to thin the film thickness by etching away a portion of the electron supply layer before forming the source and drain electrodes. Furthermore, because the electron supply layer is thin, controlling the etching time becomes complicated. Thus, Patent Document 1 requires an etching step to reduce the contact resistance, complicating the manufacturing process.

[0006] The present disclosure has been made to solve the above problems, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can reduce contact resistance while suppressing the complexity of the manufacturing process.

[0007] The semiconductor device according to the present disclosure comprises a semiconductor substrate, a channel layer formed on the semiconductor substrate, a barrier layer formed on the channel layer, and an electrode formed on the barrier layer and having a region diffused into the barrier layer to a depth of at least half the thickness of the barrier layer.

[0008] The method for manufacturing a semiconductor device according to the present disclosure includes the steps of forming a channel layer on a semiconductor substrate, forming a barrier layer on the channel layer, forming an electrode on the barrier layer, and thermal annealing the electrode so that the electrode has a region diffused to a depth of at least half the thickness of the barrier layer.

[0009] According to the present disclosure, a semiconductor device can be obtained that can reduce contact resistance while suppressing the complexity of the manufacturing process.

[0010] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 2 is a view for explaining a manufacturing method of a semiconductor device according to a first embodiment. FIG. 3 is a view for explaining a manufacturing method of a semiconductor device according to a first embodiment. FIG. 4 is a view for explaining a manufacturing method of a semiconductor device according to a first embodiment. FIG. 5 is an electron microscope photograph of a cross-section of a conventional semiconductor device. FIG. 6 is an electron microscope photograph of a cross-section of a semiconductor device according to a first embodiment. FIG. 7 is a diagram showing the annealing temperature dependence of contact resistivity of a semiconductor device according to a first embodiment. FIG. 8 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 9 is a view for explaining a manufacturing method of a semiconductor device according to a second embodiment. FIG. 10 is a view for explaining a manufacturing method of a semiconductor device according to a second embodiment. FIG. 11 is a view for explaining a manufacturing method of a semiconductor device according to a second embodiment.

[0011] First Embodiment A semiconductor device 10 according to a first embodiment is shown in Fig. 1. The semiconductor device 10 is a semiconductor device including a HEMT formed using a nitride semiconductor. Fig. 1 shows a cross section including a source electrode or a drain electrode that constitutes the HEMT.

[0012] The semiconductor device 10 includes a semiconductor substrate 12. The semiconductor substrate 12 is made of, for example, Si.

[0013] A channel layer 14 is formed on a semiconductor substrate 12. The channel layer 14 is made of, for example, GaN.

[0014] A barrier layer 16 is formed on the channel layer 14. The barrier layer 16 is made of, for example, AlGaN. A highly concentrated two-dimensional electron gas is formed at the boundary between the channel layer 14 and the barrier layer 16.

[0015] An electrode 18 is formed on the barrier layer 16. The electrode 18 is a source electrode or a drain electrode. The lower portion of the electrode 18 is diffused into the barrier layer 16 to a depth of at least half the thickness of the barrier layer 16. When viewed in a direction perpendicular to the semiconductor substrate 12, the entire region of the electrode 18 does not need to be diffused into the barrier layer 16 to a depth of at least half the thickness of the barrier layer 16; it is sufficient if a portion of the region is diffused into the barrier layer 16 to a depth of at least half the thickness of the barrier layer 16.

[0016] The electrode 18 has a first alloy layer 20 and a second alloy layer 22 stacked from the side closest to the semiconductor substrate 12. The first alloy layer 20 has a region diffused into the barrier layer 16 to a depth of more than half the thickness of the barrier layer 16. The first alloy layer 20 contains, for example, Ga, N, Ta, Al, Au, or Nb, and further contains any one of Ti, Ni, Mo, or Pt. The second alloy layer contains, for example, Al, Au, or Nb, and further contains any one of Ti, Ni, Mo, or Pt. Note that the electrode 18 may have more than the above two alloy layers stacked thereon, as long as it has a multilayer structure in which at least the first alloy layer 20 and the second alloy layer 22 are stacked from the side closest to the semiconductor substrate 12.

[0017] A method for manufacturing the semiconductor device 10 according to the first embodiment will be described. First, as shown in FIG. 2, a channel layer 14 is formed on a semiconductor substrate 12. The channel layer 14 is formed, for example, by a metal organic chemical vapor deposition (MOCVD) method. Next, as shown in FIG. 3, a barrier layer 16 is formed on the channel layer 14. The barrier layer 16 is also formed, for example, by a MOCVD method.

[0018] Next, as shown in FIG. 4, an electrode 18 is formed on the barrier layer 16. The electrode 18 thus formed is, for example, a laminate of Ta / Al / Ni / Au / Nb from the bottom up. To form the electrode 18, a resist is formed on the barrier layer 16. Next, the materials for the electrode 18 are sequentially deposited by, for example, electron beam evaporation. The resist is then removed by lift-off.

[0019] Next, thermal annealing is performed to form the first alloy layer 20 and the second alloy layer 22, thereby forming the semiconductor device 10 shown in FIG. Rapid thermal annealing, for example, can be used as the thermal annealing method. The thermal annealing is performed in a nitrogen atmosphere at a temperature range of 830 to 900°C. Note that the electrode 18 may be exposed during the thermal annealing, but thermal annealing may also be performed after forming an insulating film such as SiN by chemical vapor deposition, for example.

[0020] Cross-sectional photographs of a conventional semiconductor device and the semiconductor device 10 according to the first embodiment are compared. FIG. 5 is a photograph of the cross section of the conventional semiconductor device taken using an electron microscope. As can be seen from FIG. 5, the electrode does not diffuse deep into the barrier layer made of AlGaN. In the conventional semiconductor device, Ta / Al / Ni / Au is stacked as an electrode, and then thermal annealing is performed. In the conventional semiconductor device, alloying occurs due to thermal annealing, but only phases such as TaAlAuNi, AlNi, and AlAu are formed, and the degree of alloy diffusion is small.

[0021] FIG. 6 shows an electron microscope photograph of a cross section of the semiconductor device 10 according to the first embodiment. The semiconductor device 10 according to the first embodiment is fabricated by stacking Ta / Al / Ni / Au / Nb layers as electrodes and then thermally annealing the electrodes at temperatures ranging from 830 to 900°C. As shown in FIG. 6, the semiconductor device 10 exhibits a greater degree of diffusion in the electrodes 18 than the conventional semiconductor device. Specifically, regions of the electrodes that have diffused to more than half the depth of the barrier layer, which are not observed in conventional semiconductor devices, are observed. When the semiconductor device 10 according to the first embodiment is thermally annealed, AlAuNb is formed on the upper layer side of the electrode at around 800°C during the temperature rise, and TaAlAuNi is formed on the lower layer side. When the annealing temperature reaches at least 830°C, the Nb on the upper layer diffuses to the lower layer side, and in the process, the TaAlAuNbNi layer diffuses deep into the barrier layer. This action results in regions of the electrodes that have diffused to more than half the depth of the barrier layer.

[0022] 7 is a graph showing the results of measuring the contact resistivity of the electrode 18 in the semiconductor device 10 according to the first embodiment. The horizontal axis represents the annealing temperature (° C.), and the vertical axis represents the contact resistivity of the electrode 18 (Ωcm ２ ) From this figure, it can be seen that the contact resistivity is lower when the annealing temperature is 830 to 900° C. than when it is 600 to 800° C. In this way, if the electrode contains Nb and thermal annealing is performed at an annealing temperature of 830 to 900° C., the electrode 18 diffuses into the barrier layer 16, and the contact resistivity can be reduced.

[0023] As described above, in the semiconductor device 10 according to the first embodiment, the first alloy layer 20 has a region in which it diffuses into the barrier layer 16 to a depth of at least half the thickness of the barrier layer 16, thereby providing low contact resistance for the electrode 18. Furthermore, a simple thermal annealing process is all that is required to obtain the electrode 18 with low contact resistance, which can prevent the manufacturing process from becoming complicated.

[0024] Embodiment 2. Embodiment 2 is similar to embodiment 1, but differs in that the center of the electrode does not diffuse into the barrier layer to a depth of more than half the thickness of the barrier layer when viewed from a direction perpendicular to the semiconductor substrate.

[0025] 8 shows a cross-sectional view of a semiconductor device 20 according to the second embodiment. In an electrode 38 of the semiconductor device 20, a peripheral portion 48, which is located on the periphery when viewed perpendicularly to the semiconductor substrate 12, has a laminated structure of a first alloy layer 40 and a second alloy layer 42, similar to that of the first embodiment, and at least a portion of the peripheral portion 48 is diffused into the barrier layer 16 to a depth equal to or greater than half the thickness of the barrier layer 16.

[0026] On the other hand, in a central portion 46 located at the center when viewed perpendicularly to the semiconductor substrate 12, the impurities do not diffuse into the barrier layer 36 to a depth of more than half the thickness of the barrier layer 36. In the central portion 46, a stacked structure consisting of the first alloy layer 40 and the second alloy layer 42 may or may not be formed.

[0027] A method for manufacturing a semiconductor device 20 according to a second embodiment will now be described. The method for manufacturing the semiconductor device 20 is the same as that of the first embodiment up to the step of forming an electrode as shown in FIG. 4 . The layer structure of the electrode 38 is the same as that of the first embodiment, e.g., Ta / Al / Ni / Au / Nb stacked. After forming the electrode 38 shown in FIG. 4 , a resist 44 is formed to cover a peripheral portion 48 of the electrode 38 as shown in FIG. 9 . Then, as shown in FIG. 10 , Nb in a central portion 46 of the electrode 38 is etched by reactive dry etching using a fluorine-based gas such as SF6 or CF4. At this time, the Nb may be completely removed or only a portion may remain. Next, as shown in FIG. 11 , the resist 44 is removed. Removal methods include dry ashing and methods using a resist removal chemical.

[0028] Next, thermal annealing is performed in the same manner as in the first embodiment to obtain the semiconductor device 20 shown in Fig. 8. By the thermal annealing, a layer structure consisting of the first alloy layer 40 and the second alloy layer 42 is obtained in the peripheral portion 48 containing a sufficient amount of Nb, and the first alloy layer 40 diffuses into the barrier layer 36, thereby reducing the contact resistance of the electrode 38.

[0029] Etching the Nb in the central portion 46 in this manner can prevent Al from melting and protruding from the electrode 38. Because the melting point of Al is approximately 660°C, there is a concern that, depending on the layer structure of the electrode 38, thermal annealing at 830 to 900°C may cause Al in the electrode 38 to melt and protrude from the side surfaces of the electrode 38. On the other hand, by etching the Nb in the electrode 38 as in this embodiment, Al is more likely to move to the central portion 46, where there is less Nb, and thus the protrusion of Al is prevented.

[0030] Furthermore, since the electrode 38 is sufficiently thicker than the barrier layer 36, there is no need to precisely control the etching time during etching, which makes it possible to prevent the manufacturing process from becoming complicated.

[0031] 10, 20: semiconductor device; 12: semiconductor substrate; 14: channel layer; 16: barrier layer; 18: electrode; 20, 40: first alloy layer; 22, 42: second alloy layer; 46: central portion.

Claims

1. A semiconductor device comprising: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a barrier layer formed on the channel layer; and an electrode formed on the barrier layer, the electrode having a region diffused into the barrier layer to a depth of at least half the thickness of the barrier layer.

2. The semiconductor device according to claim 1, wherein the electrode contains Nb.

3. The semiconductor device according to claim 1 or 2, wherein the electrode has a multilayer structure in which at least a first alloy layer and a second alloy layer are stacked from the side closest to the semiconductor substrate, and the first alloy layer has a region that diffuses into the barrier layer to a depth of at least half the thickness of the barrier layer.

4. The semiconductor device according to claim 3, wherein the channel layer is made of GaN, the first alloy layer contains Ga, N, Ta, Al, Au, Nb, and further contains at least one of Ti, Ni, Mo, and Pt, and the second alloy layer contains Al, Au, Nb, and further contains at least one of Ti, Ni, Mo, and Pt.

5. A semiconductor device according to any one of claims 1 to 4, wherein the electrode has, in the center thereof, a region that has not diffused into the barrier layer to a depth of at least half the thickness of the barrier layer when viewed in a direction perpendicular to the semiconductor substrate.

6. A method for manufacturing a semiconductor device, comprising: a step of forming a channel layer on a semiconductor substrate; a step of forming a barrier layer on the channel layer; a step of forming an electrode on the barrier layer; and a step of thermally annealing the electrode so that the electrode has a region diffused to a depth of at least half the thickness of the barrier layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the electrode contains Nb.

8. The method for manufacturing a semiconductor device according to claim 6 or 7, wherein the thermal annealing step is carried out at a temperature in the range of 830 to 900°C.

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