Semiconductor device

Abstract

Over a semiconductor substrate (101) are formed a buffer layer (102), a channel layer (103), a spacer layer (104), and a barrier layer (105). The spacer layer (104) is made of a compound semiconductor having a higher band gap energy than the channel layer (103). The barrier layer (105) is made of a compound semiconductor having a higher band gap energy than the spacer layer (104). A source electrode (107) and a drain electrode (108) are formed directly on the spacer layer (104) with the barrier layer (105) interposed therebetween along the gate length direction.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] In recent years, applications using terahertz waves have been rapidly expanding, offering the potential for new applications such as high-speed wireless communications exceeding 100 Gb / s, non-destructive internal inspection using three-dimensional imaging, and component analysis using electromagnetic wave absorption. To realize applications using terahertz waves, the electronic devices that make up these devices must also have better high-frequency characteristics. Generally, electronic devices with good high-frequency characteristics are HEMTs (High Electron Mobility Transistors), a type of field-effect transistor made from compound semiconductors with particularly high electron mobility.

[0003] The basic structure of the above-mentioned HEMT will be described with reference to Fig. 8. The HEMT includes a semiconductor substrate 301, a buffer layer 302, a channel layer 303, a spacer layer 304, a barrier layer 305, a modulation doped layer 306, an etching stopper layer 307, a cap layer 308, and a modulation doped layer 309 in the cap layer.

[0004] A source electrode 310 and a drain electrode 311, which form ohmic junctions, are formed on the cap layer 308. An etching stopper layer 307 is exposed below a cap recess region 308a where a portion of the cap layer 308 has been removed, and a gate electrode 312, which forms a Schottky junction, is formed on the etching stopper layer 307. A protective layer 313 for preventing device degradation is formed on the etching stopper layer 307 exposed in the cap recess region 308a on the cap layer 308.

[0005] In this type of field-effect transistor, when a potential is applied to the gate electrode 312, the concentration of the two-dimensional electron gas (2DEG) formed by carriers being supplied from the modulation doping layer 306, which serves as a carrier supply layer, to the channel layer 303 is modulated according to the strength of the applied potential, and electrons move through the conduction channel formed between the source electrode 310 and the drain electrode 311.

[0006] The channel layer 303, in which the conduction channel through which the electrons (carriers) move (travel), is formed, and the modulation doped layer 306 are spatially separated, which suppresses scattering due to impurities in the modulation doped layer 306. Therefore, in the above-described field-effect transistor, it is possible to improve electron mobility and realize high-frequency operation.

[0007] An ohmic junction band diagram for the above-described conventional transistor is shown in Figure 9. At 0 nm on the horizontal axis (depth from the source / drain electrodes), the source electrode 310 (drain electrode 311) and the cap layer 308 are in junction, and electrons are injected into the channel layer 303 in the depth direction via the etching stopper layer 307, the barrier layer 305, and the spacer layer 304.

[0008] By inserting the modulation doped layer 309 in the cap layer into the cap layer 308 and the modulation doped layer 306 into the barrier layer 305 or the spacer layer 304 at an appropriate position, electrons can conduct by tunneling through the potential barrier, resulting in a relatively low ohmic resistance in a non-alloy ohmic junction.

[0009] 10 shows a Schottky junction band diagram for the above-described conventional transistor. At 0 nm on the horizontal axis (depth from the gate electrode), a Schottky junction is formed between the gate electrode 312 and the etching stopper layer 307. Unlike the ohmic junction shown in FIG. 9, the high Schottky barrier prevents electrons from leaking from the gate electrode 312 to the channel layer 303, and the 2DEG induced in the channel 303 by the electric field applied to the gate electrode 312 can be modulated.

[0010] For example, Patent Document 1 discloses a MOS field effect transistor having a buffer layer, a channel layer, a barrier layer, a modulation doping layer (carrier supply layer), and a cap layer similar to those described above, in which the barrier layer is oxidized to form a gate oxide film and an electrode is fitted into the protruding portion of the barrier layer. Based on the same concept as described above, a relatively low resistance of the ohmic junction can be achieved with non-alloy source and drain electrodes.

[0011] In addition, in Non-Patent Document 1, the above-mentioned ohmic junction structure is applied, and f max An example is shown in which high-frequency characteristics have been improved up to 900 GHz. Based on a resist pattern that shortens the distance between the source and drain electrodes, the source and drain electrodes are formed on the epitaxial structure, and then the gate electrode pattern is formed by electron beam lithography and photolithography, and the gate electrode metal is deposited. Again, a non-alloyed structure is used to achieve a relatively low ohmic junction resistance.

[0012] Patent No. 7392842

[0013] HB Jo et al., "Sub-30-nm In0.8Ga0.2As Composite-Channel High-Electron-Mobility Transistors With Record High-Frequency Characteristics", IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 2010-2016, 2021.

[0014] However, the above-mentioned conventional techniques have two problems: there is a limit to the reduction of the access resistance, and complex epitaxial growth is required.

[0015] First, all of the prior art techniques have a limitation in that they are based on the ohmic band diagram shown in Figure 9. The triangular potential formed by the modulation doping layer allows electrons to tunnel efficiently, thereby reducing the ohmic resistance despite the non-alloy electrode, but in order to reach at least the channel from the source electrode, it is necessary to pass through three triangular potentials as shown in Figure 9.

[0016] For this reason, in conventional technology, the reduction of the resistance component in the thickness direction from the source / drain electrodes to the channel layer is the rate-limiting factor, and particularly when scaling in the planar direction progresses, the parasitic resistance component in the thickness direction becomes significant, limiting the overall high-frequency characteristics.

[0017] Furthermore, the epitaxially grown crystal structure that constitutes a HEMT is extremely complex. It includes two modulation doping layers, a cap layer and a barrier layer, and the carrier density of the 2DEG strongly depends on the quality of the modulation doping layer, making the manufacturing process technically challenging. Therefore, conventional technologies face challenges in terms of the number of steps and the required density in order to ensure mass productivity of the epitaxial growth technology that forms the basic structure of a HEMT.

[0018] The present invention has been made to solve the above problems, and has as its object to obtain a lower ohmic resistance in the source / drain electrodes without increasing the difficulty of the manufacturing technique.

[0019] The semiconductor device according to the present invention includes a buffer layer made of a compound semiconductor formed on a semiconductor substrate, a channel layer made of a compound semiconductor formed on the buffer layer, a spacer layer made of a compound semiconductor formed on the channel layer and having a band gap energy larger than that of the channel layer, a barrier layer made of a compound semiconductor formed on the spacer layer and having a band gap energy larger than that of the spacer layer, a modulation doping layer formed in the vicinity of the interface between the spacer layer and the barrier layer, a source electrode and a drain electrode formed on the spacer layer with the barrier layer sandwiched therebetween in the gate length direction, and a gate electrode formed on the barrier layer in a Schottky junction.

[0020] As described above, according to the present invention, a spacer layer having a larger bandgap energy than the channel layer is formed on the channel layer, a barrier layer having a bandgap energy lower than that of the spacer layer is formed on the spacer layer, and the source electrode and the drain electrode are formed on the spacer layer. Therefore, it is possible to obtain a lower ohmic resistance in the source and drain electrodes without increasing the difficulty of the manufacturing technique.

[0021] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is an ohmic junction band diagram of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a Schottky junction band diagram of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of the present invention. FIG. 5 is an ohmic junction band diagram of the semiconductor device according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 7 is a cross-sectional view showing the configuration of another semiconductor device according to the third embodiment of the present invention. FIG. 8 is a cross-sectional view showing the configuration of a conventional semiconductor device. FIG. 9 is an ohmic junction band diagram of the conventional semiconductor device. FIG. 10 is a Schottky junction band diagram of the conventional semiconductor device.

[0022] A semiconductor device according to an embodiment of the present invention will be described below.

[0023] First Embodiment First, a semiconductor device according to a first embodiment of the present invention will be described with reference to Fig. 1. This semiconductor device is a HEMT (High Electron Mobility Transistor).

[0024] This HEMT includes a buffer layer 102, a channel layer 103, a spacer layer 104, and a barrier layer 105 formed on a semiconductor substrate 101. These layers can be formed by sequentially stacking them using well-known epitaxial growth techniques. The semiconductor substrate 101 can be made of, for example, InP doped with Fe to make it highly resistive.

[0025] The buffer layer 102 is made of a compound semiconductor such as undoped InAlAs. The buffer layer 102 serves as a buffer region when the layers above it are grown as crystals, and can have a thickness of, for example, 10 to 1000 nm. The channel layer 103 is formed on the buffer layer 102. The channel layer 103 is made of InAs, In x Ga 1-xThe channel layer 103 may be made of a non-doped compound semiconductor such as As, InSb, or InP. The channel layer 103 may have a composite channel structure with different compositions. The channel layer 103 may have a thickness of 3 to 20 nm.

[0026] The spacer layer 104 is formed on and in contact with the channel layer 103, and is made of a compound semiconductor having a band gap energy larger than that of the channel layer 103. The spacer layer 104 may be made of undoped InAlAs, InP, AlAs, or the like. The thickness of the spacer layer 104 may be 2 to 10 nm.

[0027] Furthermore, the spacer layer 104 can be made of a compound semiconductor that is more difficult to etch than the barrier layer 105 under the etching conditions in the etching process for forming the barrier layer 105, which will be described later. With this configuration, the spacer layer 104 can function as an etching stop layer to form the barrier layer 105. By providing the spacer layer 104 as an etching stop layer below the barrier layer 105, the upper surface of the spacer layer 104 at the locations where the source electrode 107 and the drain electrode 108, which will be described later, will be formed can be exposed without thinning the spacer layer 104 that has been formed (grown) to a desired thickness.

[0028] The barrier layer 105 is formed on (in contact with) the spacer layer 104. The barrier layer 105 is made of a compound semiconductor having a band gap energy larger than that of the spacer layer 104. The barrier layer 105 forms a Schottky junction with the gate electrode 110, which will be described later. The barrier layer 105 can be made of, for example, InP, InAlAs, InGaAs, or the like. The barrier layer 105 can be made of a material that can form a sufficiently high Schottky barrier with respect to the gate electrode 110.

[0029] The thickness of the barrier layer 105 is designed so that when the length of the gate electrode 110 to be formed later is 100 nm, the combined thickness with the spacer layer 104 is 20 nm or less, which is approximately ¼ to ⅕ of the length of the gate electrode 110. For example, when the thickness of the spacer layer 104 is 5 nm, the thickness of the barrier layer 105 can be 15 nm or less, typically 5 to 10 nm. The barrier layer 105 can have a composite barrier structure in which multiple semiconductor layers having different compositions are deposited to obtain a desired Schottky barrier.

[0030] A modulation doped layer 106 is formed near the interface between the spacer layer 104 and the barrier layer 105. The spacer layer 104 is formed to electrically separate the electron supply from the modulation doped layer 106 from the channel layer 103. The modulation doped layer 106 is formed in a sheet shape to supply carriers to the non-doped channel layer 103. In the case of an n-type channel, the dopant is mainly Si. The modulation doped layer 106 is formed in either the spacer layer 104 or the barrier layer 105. The position where the modulation doped layer 106 is formed is determined by energy band design so that the carrier density and drift velocity in the channel layer 103 are maximized under desired bias conditions.

[0031] The HEMT also includes a source electrode 107 and a drain electrode 108 formed on the spacer layer 104 with a barrier layer 105 sandwiched therebetween in the gate length direction. A gate electrode 110 is formed on the barrier layer 105 between the source electrode 107 and the drain electrode 108, in a Schottky junction. The gate electrode 110 may include, for example, a lower gate electrode and an upper gate electrode that is wider in the gate length direction than the lower gate electrode, and may have a substantially T-shaped cross section in the thickness direction parallel to the gate length direction. A protective layer 111 is formed on the upper surface (surface) of the barrier layer 105 and on parts of the source electrode 107 and the drain electrode 108 to prevent deterioration.

[0032] The source electrode 107 and the drain electrode 108, which are ohmic electrodes, are formed on the spacer layer 104 where the barrier layer 105 is not formed, and carriers such as electrons are injected into the channel via the ohmic junction. The source electrode 107 and the drain electrode 108 generally have a metal laminate structure. In the first embodiment, an ohmic junction is formed with the spacer layer 104 without providing a cap layer or a modulation doping layer in the cap layer.

[0033] 2 shows an ohmic junction band diagram for the semiconductor device according to the first embodiment. Fig. 2 shows the change in band gap energy when the spacer layer 104 is made of InP and the channel layer 103 is made of InGaAs with different In compositions, forming an InP-based HEMT.

[0034] By forming the source electrode 107 in contact with the spacer layer 104 without providing a cap layer, the distance from the source electrode 107 to the channel layer 103 can be significantly shortened, and a configuration can be achieved in which electrons can tunnel through a very thin potential region. By using such a simple layer configuration, it is possible to realize a HEMT with good characteristics, such as low resistance in the ohmic junction, while reducing the number of steps for epitaxial growth in the manufacturing process.

[0035] 3 shows a Schottky junction band diagram for the semiconductor device according to the first embodiment. This diagram shows the change in band gap energy when the barrier layer 105 is made of InAlAs, the spacer layer 104 is made of InP, and the channel layer 103 is made of InGaAs. It can be seen that a Schottky junction with a high potential barrier is formed with respect to the gate electrode 110.

[0036] Second Embodiment Next, a semiconductor device according to a twenty-first embodiment of the present invention will be described with reference to Fig. 4. This semiconductor device is a HEMT.

[0037] This HEMT includes a buffer layer 102, a channel layer 103, a spacer layer 104, a barrier layer 105, and a modulation doping layer 106 formed on a semiconductor substrate 101. The HEMT also includes a source electrode 107, a drain electrode 108, and a gate electrode 110. A protective layer 111 is formed on the upper surface (front surface) of the barrier layer 105 and on parts of the source electrode 107 and the drain electrode 108. These configurations are the same as those in the first embodiment described above.

[0038] In the second embodiment, a source electrode diffusion region 107a is provided in which the metal constituting the source electrode 107 is diffused into the spacer layer 104. Also, a drain electrode diffusion region 108a is provided in which the metal constituting the drain electrode 108 is diffused into the spacer layer 104. By using, for example, Pt, Au, or Al as the metal under the source electrode 107 and the drain electrode 108, the source electrode diffusion region 107a and the drain electrode diffusion region 108a can be formed by diffusing the metal into the spacer layer 104 by, for example, 1 to 2 nm in the thickness direction.

[0039] When the source electrode diffusion region 107a and the drain electrode diffusion region 108a are formed as described above, the diffusion coefficient of the metal in the spacer layer 104 at the portion where the source electrode 107 contacts the spacer layer 104 is set to be larger than the diffusion coefficient of the metal in the barrier layer 105 at the portion where the gate electrode 110 contacts the barrier layer 105. Similarly, the diffusion coefficient of the metal in the spacer layer 104 at the portion where the drain electrode 108 contacts the spacer layer 104 is set to be larger than the diffusion coefficient of the metal in the barrier layer 105 at the portion where the gate electrode 110 contacts the barrier layer 105.

[0040] For example, if the metal at the portion of gate electrode 110 in contact with barrier layer 105 is a high-melting-point metal such as W, Mo, or Ta, the metal at the portion of source electrode 107 and drain electrode 108 in contact with spacer layer 104 can be a highly diffusible metal such as Pt, Al, or Au. With this configuration, even after gate electrode 110, source electrode 107, and drain electrode 108 are simultaneously formed, source electrode diffusion region 107a and drain electrode diffusion region 108a can be selectively formed by annealing or the like.

[0041] 5 shows an ohmic junction band diagram for the case where the metal below the source electrode 107 and the drain electrode 108 is made of Pt and diffused 1 nm into the spacer layer 104 in the thickness direction to form the source electrode diffusion region 107a and the drain electrode diffusion region 108a. Compared to the case where the source electrode diffusion region 107a and the drain electrode diffusion region 108a are not formed (Embodiment 1), the height of the ohmic barrier is significantly reduced, and the resistance at the time of the ohmic junction can be significantly reduced. If the diffusion distance of the metal below the source electrode 107 and the drain electrode 108 can be controlled, it can be diffused into the channel layer 103.

[0042] Twenty-first embodiment A semiconductor device according to a twenty-first embodiment of the present invention will now be described with reference to Fig. 6. This semiconductor device is a HEMT.

[0043] This HEMT includes a buffer layer 102, a channel layer 103, a spacer layer 104, a barrier layer 105, and a modulation doping layer 106 formed on a semiconductor substrate 101. The HEMT also includes a source electrode 107, a drain electrode 108, and a gate electrode 110. A protective layer 111 is formed on the upper surface (surface) of the barrier layer 105 and on a portion of the source electrode 107 and the drain electrode 108. These configurations are the same as those in the first embodiment. Also, in the third embodiment, as in the second embodiment, a source electrode diffusion region 107a and a drain electrode diffusion region 108a can be provided.

[0044] In the third embodiment, the gate electrode 110 is composed of a lower gate electrode 110a in contact with the barrier layer 105 and an upper gate electrode 110b that is wider in the gate length direction than the lower gate electrode 110a. In the third embodiment, the cross section of the gate electrode 110 in the thickness direction parallel to the gate length direction is approximately T-shaped.

[0045] Furthermore, in the third embodiment, the distance between the source electrode 107 and the drain electrode 108 in the gate length direction is equal to or less than the length of the upper gate electrode 110b in the gate length direction. For example, the above-described structure can be achieved by forming the gate electrode 110 and then forming the source electrode 107 and the drain electrode 108 using the gate electrode 110 as a mask. By manufacturing in this manner, the distance between the source electrode 107 and the drain electrode 108 is automatically (self-alignedly) determined by the width of the gate electrode 110 in the gate length direction.

[0046] For example, if a source / drain electrode material is deposited by, for example, sink evaporation using the gate electrode 110 as a mask, the deposited electrode material will extend inside the upper gate electrode 110b in a plan view seen from above the semiconductor substrate 101. In this case, the distance in the gate length direction between the source electrode 107 and the drain electrode 108 will be smaller than the length in the gate length direction of the upper gate electrode 110b.

[0047] Typically, if the length of the upper gate electrode 110b in the gate length direction is formed to be in the range of 100 to 500 nm, the distance between the source electrode 107 (drain electrode 108) and the gate electrode 110 (lower gate electrode 110a) that is actually formed will be narrowed by about 10 to 100 nm. As a result, the distance between the source electrode 107 and the drain electrode 108 in the gate length direction will be about 80 to 300 nm.

[0048] Of course, the distance between the source electrode 107 and the drain electrode 108 in the gate length direction strongly depends on the conditions for forming the source electrode 107 and the drain electrode 108. For example, if the source / drain electrode material is deposited using the gate electrode 110 as a mask by a deposition method with high vertical anisotropy, such as sputtering, the deposited electrode material will hardly extend inside the upper gate electrode 110b in a plan view seen from above the semiconductor substrate 101. In this case, the distance between the source electrode 107 and the drain electrode 108 in the gate length direction will be approximately the same as the length of the upper gate electrode 110b in the gate length direction.

[0049] By adopting the above-described configuration, the distance between the source electrode 107 and the drain electrode 108 can be made as close as possible, and an improvement in high frequency characteristics can be expected due to a reduction in on-resistance.

[0050] In the above description, the eaves of the upper gate electrode 110b extending in the gate length direction from the lower gate electrode 110a are equal on the source electrode 107 side and the drain electrode 108 side, but this is not limitative. For example, as shown in Fig. 7, the eaves of the upper gate electrode 110b extending in the gate length direction from the lower gate electrode 110a can be made longer on the drain electrode 108 side than on the source electrode 107 side.

[0051] By forming the source electrode 107 and the drain electrode 108 using as a mask a gate electrode 110' in which the overhanging portion of the upper gate electrode 110b is longer on the drain electrode 108 side than on the source electrode 107 side, the distance between the source electrode 107 and the gate electrode 110 can be made shorter than the distance between the drain electrode 108 and the gate electrode 110. For example, the distance between the source electrode 107 and the gate electrode 110 (lower gate electrode 110a) can be set to 50 to 200 nm, and the distance between the gate electrode 110 (lower gate electrode 110a) and the drain electrode can be set to a range of about 75 to 400 nm, which is 50 to 100% longer than that.

[0052] By shortening the distance between the source electrode 107 and the gate electrode 110 in this way, the source resistance can be reduced while the distance between the gate electrode 110 and the drain electrode 108 can be extended to reduce the drain conductance and improve the high frequency characteristics.

[0053] Incidentally, when the source electrode 107 and the drain electrode 108 are formed using the gate electrode 110 as a mask as described above, the upper surface of the gate electrode 110 can be made of the same metal as the source electrode 107 and the drain electrode 108 .

[0054] As described above, according to the present invention, a spacer layer having a larger bandgap energy than the channel layer is formed on the channel layer, a barrier layer having a bandgap energy lower than that of the spacer layer is formed on the spacer layer, and the source electrode and the drain electrode are formed on the spacer layer. Therefore, it is possible to obtain a lower ohmic resistance in the source and drain electrodes without increasing the difficulty of the manufacturing technique.

[0055] Some or all of the above-described embodiments may also be described as, but are not limited to, the following supplementary notes.

[0056] [Supplementary Note 1] A semiconductor device comprising: a buffer layer made of a compound semiconductor formed on a semiconductor substrate; a channel layer made of a compound semiconductor formed on the buffer layer; a spacer layer made of a compound semiconductor formed on (in contact with) the channel layer and having a larger band gap energy than the channel layer; a barrier layer made of a compound semiconductor formed on (in contact with) the spacer layer and having a larger band gap energy than the spacer layer; a modulation dope layer formed in the vicinity of an interface between the spacer layer and the barrier layer; a source electrode and a drain electrode formed on (in contact with) the spacer layer with the barrier layer sandwiched therebetween in a gate length direction; and a gate electrode formed on the barrier layer in a Schottky junction.

[0057] [Supplementary Note 2] In the semiconductor device according to Supplementary Note 1, the spacer layer is made of a compound semiconductor that is more difficult to etch than the barrier layer under etching conditions in an etching process for forming the barrier layer.

[0058] [Supplementary Note 3] The semiconductor device according to Supplementary Note 1 or 2, further comprising: a source electrode diffusion region in which a metal constituting the source electrode is diffused into the spacer layer; and a drain electrode diffusion region in which a metal constituting the drain electrode is diffused into the spacer layer.

[0059] [Appendix 4] In the semiconductor device according to any one of Appendices 1 to 3, the gate electrode comprises a lower gate electrode in contact with the barrier layer and an upper gate electrode that is wider in the gate length direction than the lower gate electrode, and the distance between the source electrode and the drain electrode in the gate length direction is equal to the length of the upper electrode in the gate length direction.

[0060] [Appendix 5] In the semiconductor device according to any one of Appendices 1 to 4, a diffusion coefficient of a metal in the spacer layer at a portion where the source electrode contacts the spacer layer and a diffusion coefficient of a metal in the spacer layer at a portion where the drain electrode contacts the spacer layer are larger than a diffusion coefficient of a metal in the barrier layer at a portion where the gate electrode contacts the barrier layer.

[0061] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0062] 101...semiconductor substrate, 102...buffer layer, 103...channel layer, 104...spacer layer, 105...barrier layer, 106...modulation doped layer, 107...source electrode, 108...drain electrode, 110...gate electrode, 111...protective layer.

Claims

1. A semiconductor device comprising: a buffer layer made of a compound semiconductor formed on a semiconductor substrate; a channel layer made of a compound semiconductor formed on the buffer layer; a spacer layer made of a compound semiconductor formed on the channel layer and having a band gap energy larger than that of the channel layer; a barrier layer made of a compound semiconductor formed on the spacer layer and having a band gap energy larger than that of the spacer layer; a modulation doped layer formed in the vicinity of the interface between the spacer layer and the barrier layer; a source electrode and a drain electrode formed on the spacer layer with the barrier layer sandwiched therebetween in the gate length direction; and a gate electrode formed on the barrier layer in Schottky junction.

2. A semiconductor device according to claim 1, comprising: a source electrode diffusion region in which the metal constituting the source electrode is diffused into the spacer layer; and a drain electrode diffusion region in which the metal constituting the drain electrode is diffused into the spacer layer.

3. A semiconductor device according to claim 1, wherein the gate electrode comprises a lower gate electrode in contact with the barrier layer and an upper gate electrode that is wider in the gate length direction than the lower gate electrode, and the distance between the source electrode and the drain electrode in the gate length direction is equal to or less than the length of the upper gate electrode in the gate length direction.

4. A semiconductor device according to claim 1, wherein the diffusion coefficient of the metal in the spacer layer at the location where the source electrode contacts the spacer layer and the diffusion coefficient of the metal in the spacer layer at the location where the drain electrode contacts the spacer layer are greater than the diffusion coefficient of the metal in the barrier layer at the location where the gate electrode contacts the barrier layer.

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