Mounting device

Abstract

Provided is a mounting device that, when a stamp that retains a plurality of chip components is used to mount chip components on a substrate, can evaluate the degree of parallelism of the substrate and the stamp with relative ease and high frequency. Specifically, provided is a mounting device comprising: a substrate stage that retains a substrate; a stamp that retains a plurality of chip components; a stamp base that retains the stamp and raises and lowers the stamp with a surface retaining the chip components facing the substrate; and an optical thickness meter that performs thickness measurement using the reflection of projected light. The mounting device has a function of: projecting light past the stamp base by using the optical thickness meter; and measuring a gap between the surface of the stamp retaining the chip components and a surface of the substrate by using light reflected by the surface of the substrate and light reflected by the surface of the stamp retaining the chip components.

Description

Mounting Equipment

[0001] The present invention relates to a mounting apparatus that uses a stamp that holds a plurality of chip components.

[0002] There are applications where a large number of chip components are mounted on a substrate, such as a micro LED display in which a large number of micro LEDs are mounted on a TFT substrate. In such applications, it is necessary to align and mount the chip components on each of the many mounting positions PC on the substrate B shown in FIG.

[0003] For example, in a micro LED display, at least several hundred thousand LED chips need to be mounted on a single TFT substrate, and mounting the LED chips one by one would take an enormous amount of time. Therefore, efforts are being made to improve productivity by using a so-called stamp method (see, for example, Patent Document 1), which allows multiple chip components C to be mounted at once in accordance with the pitch of the mounting locations PC on the substrate B.

[0004] 6A and 6B illustrate a stamp used to mount multiple chip components C on a substrate B at one time, with FIG. 6A being a side view and FIG. 6B being a view from the surface holding the chip components C. In FIG. 6A, the stamp 6 has protrusions 61 arranged on a stamp body 60. The protrusions 61 function to hold the chip components C and are arranged to match the pitch of the mounting positions PC. The stamp 6 is held by a stamp base 5 from the side opposite the surface with the protrusions 61. The first stamp recognition mark 6A1 and the second stamp recognition mark 6A2 are provided at fixed positions relative to the arrangement of the protrusions 61. Positional information about the stamp 6 can be obtained from the positions of the first stamp recognition mark 6A1 and the second stamp recognition mark 6A2, and the arrangement of the protrusions 61 arranged on the stamp 6 can also be known.

[0005] FIG. 7 shows the state in which chip components C are mounted on a portion of the substrate B using the stamp 6 shown in FIG. 6, and multiple chip components C held by the stamp 6 are mounted on the substrate B at one time.

[0006] JP 2023-145354 A JP 2020-072109 A

[0007] In order to mount a plurality of chip components C on the mounting locations PC of the substrate B using the stamp 6, each of the plurality of chip components C held by the stamp 6 must be aligned with the mounting location PC of the substrate B before being mounted.

[0008] For this reason, alignment is performed using stamp recognition marks 6A (first stamp recognition mark 6A1 and second stamp recognition mark 6A2), which serve as a guide for determining the position information of the stamp and the arrangement of the chip components C held on the stamp, and board recognition marks BA, which serve as a guide for the arrangement of the mounting locations PC within the board B. Fig. 8(a) shows a state in which the stamp recognition marks 6A and the board recognition marks BA are observed using a dual-viewpoint camera 70 with an upper and lower field of view. The amount of positional misalignment is calculated from the relative positions of the stamp 6 and the board 2 obtained here, and the position of at least one of the board B and the stamp 6 is adjusted to correct the amount of positional misalignment. Fig. 8(b) shows a state in which the stamp 6 is lowered to bring the chip components C into close contact with the board B.

[0009] The chip component C is then heated to bond its electrodes to the electrodes of the substrate B, thereby bonding the chip component C to the substrate B. Recently, a method using a laser to heat the chip component C has been gaining attention, and an example of this is shown in FIG. 9 . FIG. 9 shows a method for heating individual chip components C with laser light L. Because the energy density of the laser light is high, the chip components C can be heated instantaneously. Therefore, even when heating individual chip components C sequentially, as shown in FIGS. 9( a ) to 9 ( c ), the time required to heat all of the chip components C held by the stamp 6 is short. To heat the chip components C with laser light L using the method shown in FIG. 9 , the stamp base 5 and stamp 6 must be able to transmit light linearly. That is, the stamp base 5 and stamp 6 are transparent.

[0010] Incidentally, in order to align the stamp 6 as shown in Figure 8(a) and then lower the stamp 6 to adhere multiple chip components C to the substrate B, the parallelism of the stamp 6 with respect to the substrate B is important. If the stamp 6 is tilted with respect to the substrate B, as shown in Figure 10, even if some chip components C are adhered to the substrate B, there will still be chip components C that are separated from the substrate B. For this reason, chip components C that are not in contact with the substrate B cannot be mounted even if they are heated.

[0011] In reality, the size of the stamp 6 ranges from several tens of mm square to approximately 100 mm square, and since mounting is difficult if the stamp 6 is floating by several tens of μm, the parallelism of the stamp 6 to the substrate B is extremely important.

[0012] Therefore, in order to adjust the parallelism between the substrate B and the stamp 6, the gap G between the substrate B and the stamp 6 is evaluated by measuring it at multiple points (see, for example, Patent Document 2), as shown in FIG. 11, and the inclination of the stamp base, etc. is adjusted so that the difference in values ​​at multiple points is within an acceptable range.

[0013] However, conventional parallelism evaluation methods could not be performed frequently because each evaluation required a long time. On the other hand, there may be a difference in height of several tens of micrometers within the entire surface of the substrate stage 2 that holds the substrate B, and changes in flatness may occur due to temperature rise caused by repeated mounting. For this reason, even if parallelism evaluation (and adjustment) was performed periodically, mounting defects that were thought to be caused by poor parallelism between the substrate B and the stamp 6 still occurred.

[0014] The present invention has been made in consideration of the above-mentioned problems, and provides a mounting device that can relatively easily and frequently evaluate the parallelism between a substrate and a stamp when mounting chip components on a substrate using a stamp that holds multiple chip components.

[0015] In order to solve the above problem, the invention described in claim 1 is a mounting device that mounts a plurality of chip components at predetermined positions on a substrate at one time, comprising: a substrate stage that holds the substrate; a stamp that holds the plurality of chip components; a stamp base that holds the stamp and moves it up and down while keeping the surface that holds the chip components facing the substrate; and an optical thickness meter that measures thickness using the reflection of irradiated light, and the mounting device has the function of using the optical thickness meter to irradiate light through the stamp base and measure the gap between the surface of the stamp that holds the chip components and the surface of the substrate using the light reflected by the surface of the substrate and the light reflected by the surface of the stamp that holds the chip components.

[0016] A second aspect of the present invention is the mounting apparatus according to the first aspect, which has a function of measuring the gap at a plurality of locations and evaluating the parallelism of the stamp with respect to the substrate.

[0017] A third aspect of the present invention is the mounting apparatus according to the second aspect, wherein the parallelism is adjusted by adjusting the inclination of the stamp base.

[0018] The invention of claim 4 is a mounting device according to any one of claims 1 to 3, further comprising an imaging means used to acquire relative position information of the stamp with respect to the in-plane direction of the substrate, and is a mounting device in which the optical thickness gauge and the imaging means are integrated.

[0019] A fifth aspect of the present invention is the mounting apparatus according to the fourth aspect, wherein the mounting apparatus is capable of measuring the gap and the relative position information simultaneously.

[0020] The invention described in claim 6 is a mounting device described in any one of claims 1 to 3, wherein the stamp base and the stamp are transparent, and the mounting device is equipped with a laser irradiation means that irradiates laser light onto the chip component through the stamp base while the chip component held by the stamp is in close contact with the substrate.

[0021] According to the present invention, the parallelism evaluation between a substrate and a stamp, which is performed when mounting chip components on a substrate using a stamp that holds multiple chip components, can be performed even during the process of bringing the stamp holding the chip components C closer to the substrate B. As a result, it is possible to perform the evaluation for each mounting process in which the stamp mounts chip components on the substrate, and it is possible to prevent mounting defects of the chip portion C caused by poor parallelism of the stamp to the substrate.

[0022] FIG. 1 is a schematic diagram of a mounting apparatus according to an embodiment of the present invention. This diagram explains gap measurement between a substrate and a stamp in the mounting apparatus according to an embodiment of the present invention, and (a) shows a configuration for performing gap measurement, and (b) shows irradiated light and reflected light used in gap measurement. This diagram explains an alignment method utilizing the transparency of the stamp and stamp base. This diagram shows the configuration of a mounting apparatus according to a modified embodiment of the present invention. This diagram explains an example of a substrate on which a large number of chip components are mounted. This diagram explains a stamp on which multiple chip components can be mounted at once and a stamp base that holds the stamp, and (a) shows a side view and (b) a view from the surface that holds the chip components. This diagram shows an example in which multiple chip components are mounted on a substrate at once using a stamp. This diagram explains the process of mounting multiple chip components on a substrate using a stamp, and (a) shows a state in which alignment is being performed and (b) shows a state in which the chip components have been closely attached to the substrate. This diagram explains the process of mounting multiple chip components on a substrate using a stamp, and (a) shows a state in which the chip components are being heated and mounted with a laser, and (b) shows a state in which different chip components are being heated and mounted in sequence with a laser, and (c) shows a stage in which mounting of the chip components held by the stamp is completed. 10A and 10B are diagrams illustrating a state in which a stamp is tilted relative to a substrate and multiple chip components are being mounted;FIGS. 10A and 10B are diagrams illustrating a state in which the parallelism of the stamp relative to the substrate is evaluated;FIGS.

[0023] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the accompanying drawings. Fig. 1 shows a mounting apparatus 1 according to an embodiment of the present invention.

[0024] The mounting device 1 in Figure 1 mounts multiple chip components C on a substrate B at once using a stamp 6, and is equipped with a substrate stage 2, a lifting means 3, a head unit 4, a stamp base 5, the stamp 6, and an optical thickness meter 9.

[0025] Here, the substrate stage 2 holds the substrate B on a flat surface by suction or the like, and may have a function to move the substrate B in the in-plane direction (XY direction).

[0026] The lifting means 3 is fixed to a frame (not shown), has a drive shaft connected to the head unit 4, and has the function of moving the head unit 4 up and down and the function of applying a predetermined pressure to the head unit 4. The lifting means 3 may also have the function of adjusting the rotation angle of the head unit 4 with the movement direction of the drive shaft (Z direction) as the rotation axis.

[0027] The head unit 4 has a stamp base 5 fixed to its underside, and is moved up and down (and its rotation angle around the vertical axis) by an elevation means 3, and has a cavity through which the imaging means 7 can enter and exit. It is also desirable for the stamp base 5 to have a function for adjusting the orientation of the stamp base 5 (the direction of the perpendicular to the surface holding the stamp 6), and this function is used to adjust the parallelism of the stamp 6 with respect to the substrate B.

[0028] The stamp base 5 is a transparent plate-like object that forms the underside of the head part 4, and has the function of holding the stamp 6 on its underside. Here, it is preferable that the stamp 6 is replaceable, as the stamp 6 is held by suction or the like, but care must be taken when attempting to heat the chip component C with a laser, because the laser light will be scattered if there is a reduced pressure flow path in the optical path of the laser light leading to the part that holds the chip component C (the protrusion 61 in FIG. 6(a)).

[0029] As shown in Figure 6, the stamp 6 has protrusions 61 provided at locations on a stamp body 60, which is a transparent plate, where the chip component C is to be held, and the side opposite to the side with the protrusions 61 is held by a stamp base 5. The protrusions 61 are provided at a pitch that matches the chip mounting locations PC of the substrate on which the chip component C is to be mounted. The surface of the protrusions 61 that comes into close contact with the chip component C may be adhesive, and the protrusions 61 themselves may be made of an adhesive material. Alternatively, there may be no protrusions 61, and the flat surface of the stamp body 60 may directly hold the chip component C.

[0030] The optical thickness meter 9 generally measures the film thickness by irradiating the target film with light and detecting the light reflected from the surface of the film and the light transmitted through the surface and reflected by the back surface. Since the gap between the stamp 6, which is the measurement target of the present invention, and the substrate B is several millimeters, this embodiment is premised on an optical thickness meter using laser interferometry, which is capable of measuring film thicknesses of about several millimeters with high accuracy. However, the present invention is not limited to laser interferometry, and any thickness meter capable of measuring film thicknesses of about several millimeters with high accuracy can be applied to the present invention.

[0031] The mounting apparatus 1 in FIG. 1 primarily illustrates the components related to parallelism evaluation, but also includes a heating means for heating the chip components C. In this embodiment of the present invention, it is assumed that the chip components C are heated with laser light, and the apparatus is equipped with a laser irradiation means 99 (not shown), which is composed of a laser light source and a scanning mechanism. Laser irradiation by the laser irradiation means 99 may be performed by scanning the laser light L to sequentially heat the chip components C, as shown in FIG. 9 . However, the takt time can be shortened by branching the laser light emitted from a high-output laser light source to simultaneously heat multiple chip components C. It is also desirable to include an imaging means 7 for aligning the stamp 6 with the substrate B.

[0032] When the laser irradiation means 99 irradiates the chip component C with laser light L as shown in FIG. 9, the optical thickness meter 9 must not be in the optical path of the laser light L, so the optical thickness meter 9 is configured to be able to move in and out of the cavity of the head portion 4 by a driving means (not shown).

[0033] The mounting device 1 also includes a control unit 10 (not shown), which is connected to the substrate stage 2, the lifting means 3, the head unit 4, the optical thickness meter 9, and the laser irradiation means 99 (not shown).

[0034] The control unit 10 is connected to the substrate stage 2 and has the function of controlling whether or not the substrate B is attracted and the position of the substrate within the XY plane.

[0035] The control unit 10 is connected to the lifting means 3 and has the function of controlling the lifting and pressure of the head unit 4, as well as the rotation angle around the lifting direction (Z direction) as the rotation axis.

[0036] The control unit 10 is connected to the head unit 4 and has a function of adjusting the orientation of the stamp base 5 .

[0037] The control unit 10 is connected to the imaging means 7 (and a driving means for moving the imaging means 7) and has the function of controlling the position of the imaging means 7 and capturing and processing images acquired by the imaging means 7.

[0038] The control unit 10 is connected to the optical thickness meter 9 and has the functions of controlling the light irradiation toward the object and calculating the distance between specified reflected lights from the light reflected by each interface in response to the light irradiation.

[0039] The control unit 10 is connected to a laser irradiation means 99 (not shown) and has a function of controlling the output and irradiation position of the laser light.

[0040] A method for evaluating the parallelism between the substrate B and the stamp 6 using the mounting device 1 of FIG. 1 will be described below.

[0041] First, FIG. 2A shows a state in which a gap G between the surface of the stamp 6 that holds the chip components C and the substrate B is measured in a parallelism evaluation according to the embodiment. In FIG. 2A, the stamp 6 and the stamp base 5 are transparent. Therefore, as shown in FIG. 2B, a portion of the measurement illumination light LI emitted from the optical thickness meter 9 reaches (is reflected from) the surface of the substrate B, and the substrate surface reflected light RB is detected by the light receiving unit of the optical thickness meter 9. Furthermore, a portion of the measurement illumination light LI is reflected by the surface that holds the chip components C, which is the interface between the stamp 6 and the air, and the stamp surface reflected light RS is detected by the light receiving unit of the optical thickness meter 9. Therefore, by calculating the distance between the substrate surface reflected light RB and the stamp surface reflected light RS as the "thickness," it is possible to measure the gap G between the surface of the stamp 6 that holds the chip components C and the substrate B.

[0042] By measuring the gap G between the surface of the stamp 6 that holds the chip components C and the substrate B at a plurality of locations (at least three locations), the parallelism of the stamp 6 with respect to the substrate B can be evaluated.

[0043] Since the stamp base 5 and stamp 6 are transparent, it is possible to measure the gap G between the surface of the stamp 6 that holds the chip components C and the substrate B from one direction. Also, by bringing the stamp 6 as close as possible to the substrate B and setting the gap G to a few mm or less, an optical thickness meter 9 using laser interferometry can be used. On the other hand, since the parallelism can be evaluated and adjusted with the stamp 6 brought as close as possible to the substrate B, the chip components C can be brought into close contact with the substrate B while maintaining the parallelism after adjustment.

[0044] Incidentally, if the stamp base 5 and stamp 6 are transparent, it is possible to obtain positional information of the stamp 6 and the substrate B through the stamp base 5 as shown in Fig. 3, without using the two-view imaging means 70 as shown in Fig. 8(a). This alignment can be performed by bringing the stamp 6 as close as possible to the substrate B, within a range where the chip components C do not come into contact with the substrate B. In other words, when measuring the gap G between the stamp 6 and the substrate B in Fig. 2, it is also possible to perform alignment in parallel.

[0045] Therefore, a modified embodiment of the present invention in which the image capturing means for alignment is integrated with the optical thickness gauge for gap measurement is shown in Fig. 4. In Fig. 4, the optical thickness gauge 91 and the image capturing means 71 are configured to face the measurement target in the same direction via a prism 97. Here, if the image captured by the image capturing means 71 is in the visible light range, it is possible to operate the optical thickness gauge 91 and the image capturing means 71 simultaneously by changing the wavelength of the measurement irradiation light LI emitted from the optical thickness gauge 91 to an infrared range.

[0046] As described above, the present invention allows the parallelism evaluation of the stamp 6 holding a plurality of chip components C and the substrate B to be performed even during the process of bringing the stamp 6 holding the chip components C closer to the substrate B. In other words, this can be performed relatively easily during each mounting process in which the stamp B mounts the chip components C on the substrate B. Furthermore, by driving the head unit 4 to adjust the orientation of the stamp base 5 according to the results of the parallelism evaluation, the parallelism between the substrate B and the stamp 6 falls within an allowable range during each mounting process, making it possible to significantly reduce mounting defects of chip components C caused by poor parallelism of the stamp 6 relative to the substrate B.

[0047] REFERENCE SIGNS LIST 1 Mounting device 2 Substrate stage 3 Elevating means 4 Head section 5 Stamp base 6 Stamp 7 Imaging means (camera) 8 Chip surface imaging means 9 Optical thickness gauge 10 Control section 60 Stamp body 61 Protrusion 70 Two-field imaging means (two-field camera) 99 Laser irradiation means 6A (6A1, 6A2) Stamp recognition mark B Substrate BA (BA1, BA2) Substrate recognition mark C Chip component L Laser light LI Measurement irradiation light PC Chip component mounting location RB Substrate surface reflected light RS Stamp surface reflected light

Claims

1. A mounting device that mounts multiple chip components at predetermined positions on a substrate at one time, comprising: a substrate stage that holds the substrate; a stamp that holds the multiple chip components; a stamp base that holds the stamp and moves up and down with the surface that holds the chip components facing the substrate; and an optical thickness meter that measures thickness using the reflection of irradiated light, wherein the mounting device has the function of irradiating light through the stamp base and measuring the gap between the surface of the stamp that holds the chip components and the surface of the substrate using the light reflected by the surface of the substrate and the light reflected by the surface of the stamp that holds the chip components.

2. A mounting device according to claim 1, having a function of measuring the gap at a plurality of locations and evaluating the parallelism of the stamp relative to the substrate.

3. A mounting apparatus according to claim 2, wherein the parallelism is achieved by adjusting the inclination of the stamp base.

4. A mounting device according to any one of claims 1 to 3, further comprising imaging means used to obtain relative position information of the stamp with respect to the in-plane direction of the substrate, wherein the optical thickness gauge and the imaging means are integrated.

5. A mounting apparatus according to claim 4, wherein the gap measurement and the relative position information can be measured simultaneously.

6. A mounting device according to any one of claims 1 to 3, wherein the stamp base and the stamp are transparent, and the mounting device is equipped with laser irradiation means for irradiating laser light onto the chip component through the stamp base while the chip component held by the stamp is in close contact with the substrate.

Images