Solid-state imaging element and electronic device

Abstract

The present disclosure relates to a solid-state imaging element and an electronic device that make it possible to achieve a further improvement in image quality. This solid-state imaging element comprises a pixel having: a first capacitor that holds a voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds a voltage of a pixel signal of a pixel signal level output from the pixel circuit; a first gate that connects the first capacitor and a node connected to an amplification gate that outputs the pixel signal; and a second gate that connects the second capacitor and the node. The difference between a first parasitic capacitance due to capacitive coupling generated between the first gate and the node and a second parasitic capacitance due to capacitive coupling generated between the second gate and the node is less than a prescribed value. The present invention can be applied to, for example, a global-shutter-type solid-state imaging element using a voltage-domain method.

Description

Solid-state imaging device and electronic device

[0001] The present disclosure relates to a solid-state imaging device and an electronic device, and more particularly to a solid-state imaging device and an electronic device that are capable of further improving image quality.

[0002] In recent years, there has been a demand for miniaturization of pixel size in global shutter CMOS (Complementary Metal Oxide Semiconductor) image sensors, which do not cause focal plane distortion during image capture, as the number of pixels increases.

[0003] For example, in global shutter CMOS image sensors, the most common methods used are the charge-domain method, which temporarily holds the signal generated by the photodiode as an electric charge, and the voltage-domain method, which temporarily holds the signal generated by the photodiode as a voltage.

[0004] In the charge-domain method, a memory unit provided on the same semiconductor substrate as the photodiode is used as the signal holding unit, while in the voltage-domain method, a capacitor provided outside the semiconductor substrate is used as the signal holding unit. Therefore, while the charge-domain method is configured so that the signal holding unit occupies the photodiode area, the voltage-domain method is configured so that the signal holding unit does not occupy the photodiode area, which is advantageous for miniaturization in terms of saturation signal amount.

[0005] For example, Patent Document 1 discloses a global shutter type image sensor that reduces coupling noise and generates clear images by enclosing a first capacitor and a second capacitor, which temporarily hold a signal generated by a photodiode as a voltage, in a shield structure.

[0006] US Patent Application Publication No. 2020 / 0058688

[0007] However, while the voltage-domain global shutter CMOS image sensor described above is advantageous for miniaturization in terms of saturation signal amount, there is a concern that image quality may be impaired due to capacitive coupling between wiring in the sample-and-hold circuit having a signal holding section.

[0008] For example, in the voltage-domain method, a signal is written as a voltage to a capacitor, so the signal storage node is in a floating state from the end of signal writing to the start of readout. This is likely to result in degradation of image quality, as the signal fluctuates after readout due to capacitive coupling between the signal storage node and the control line that performs the readout operation.

[0009] The present disclosure has been made in view of such circumstances, and aims to make it possible to further improve image quality.

[0010] a first capacitor having one end connected to the first node and holding a voltage of a pixel signal at a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding a voltage of a pixel signal at a pixel signal level output from the pixel circuit; an amplifier gate that generates a pixel signal according to a charge accumulated at a second node connected to a gate electrode; and a sample and hold circuit having at least a third node that is a connection point with the other end of the first capacitor, a first gate that connects the second node, a fourth node that is a connection point with the other end of the second capacitor, and a second gate that connects the second node, wherein a difference between parasitic capacitances due to capacitive coupling generated between the two nodes and the two gates of the sample and hold circuit is less than a specified value.

[0011] An electronic device according to one aspect of the present disclosure includes a pixel having: a pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding the voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding the voltage of a pixel signal of a pixel signal level output from the pixel circuit; an amplification gate that generates a pixel signal according to charge accumulated at a second node connected to a gate electrode; and a sample and hold circuit having at least a third node that is a connection point with the other end of the first capacitor, a first gate that connects the second node, a fourth node that is a connection point with the other end of the second capacitor, and a second gate that connects the second node, and includes a solid-state imaging element in which a difference between parasitic capacitances due to capacitive coupling generated between the two nodes and two gates of the sample and hold circuit is less than a specified value.

[0012] In one aspect of the present disclosure, in a pixel having: a pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding the voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding the voltage of a pixel signal of a pixel signal level output from the pixel circuit; an amplification gate that generates a pixel signal according to charge accumulated at the second node connected to the gate electrode; and a sample and hold circuit having at least a third node that is a connection point with the other end of the first capacitor, a first gate that connects the second node, a fourth node that is a connection point with the other end of the second capacitor, and a second gate that connects the second node, a difference between parasitic capacitances due to capacitive coupling that occurs between the two nodes and two gates of the sample and hold circuit is set to be less than a specified value.

[0013] 7 is a block diagram showing an example configuration of an embodiment of an imaging device to which the present technology is applied. FIG. 1 is a circuit diagram showing a first example configuration of a pixel. FIG. 2 is a circuit diagram showing an example configuration of a four-pixel sharing structure of the pixel of FIG. 2. FIG. 3 is a diagram showing an example of a planar layout for explaining capacitive coupling between an SR gate and a V2 node. FIG. 4 is a diagram showing an example of a planar layout for explaining capacitive coupling between an SR gate and a VCR node. FIG. 5 is a diagram showing an example of a wiring layout of a wiring layer in which RB wiring and SEL wiring are provided. FIG. 6 is a circuit diagram showing a second example configuration of a pixel. FIG. 7 is a diagram showing an example of a wiring layout of a wiring layer in which SR wiring, SD wiring, and VREG wiring are provided. FIG. 8 is a circuit diagram showing an example configuration of a four-pixel sharing structure of the pixel of FIG. 7. FIG. 8 is a diagram showing an example of a wiring layout of a wiring layer in which SR wiring, SD wiring, and VREG wiring are provided. FIG. 9 is a diagram showing an example of a gate layout. FIG. 10 is a diagram showing an example layout of a capacitor and a V1 node. FIG. 11 is a circuit diagram showing a third example configuration of a pixel. FIG. 12 is a circuit diagram showing a fourth example configuration of a pixel. FIG. 13 is a circuit diagram showing a fifth example configuration of a pixel. FIG. 14 is a circuit diagram showing a sixth example configuration of a pixel. FIG. 15 is a circuit diagram showing a seventh example configuration of a pixel. FIG. 16 is a circuit diagram showing an eighth example configuration of a pixel. FIG. 17 is a circuit diagram showing a ninth example configuration of a pixel. Fig. 13 is a circuit diagram showing a tenth configuration example of a pixel. Fig. 14 is a diagram showing a first cross-sectional configuration example of a solid-state imaging element. Fig. 15 is a diagram showing a second cross-sectional configuration example of a solid-state imaging element. Fig. 16 is a diagram showing a third cross-sectional configuration example of a solid-state imaging element. Fig. 17 is a diagram showing a fourth cross-sectional configuration example of a solid-state imaging element. Fig. 18 is a diagram showing an example of use in which an image sensor is used.

[0014] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.

[0015] <Configuration Example of Imaging Apparatus> FIG. 1 is a block diagram showing a configuration example of an embodiment of an imaging apparatus to which the present technology is applied.

[0016] 1, the imaging device 11 is configured to include an optical system 12, a solid-state imaging element 13, an imaging control circuit 14, a signal processing circuit 15, a monitor 16, and a memory 17. For example, the imaging device 11 can be applied to various electronic devices such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions, and is capable of capturing still images and moving images.

[0017] The optical system 12 is composed of one or more lenses, and collects incident light from the subject that enters the imaging device 11, directs it to the solid-state imaging element 13, and forms an image of the subject on the light-receiving surface (sensor section) of the solid-state imaging element 13.

[0018] The solid-state image sensor 13 captures an image of the subject formed on the light receiving surface via the optical system 12 under the control of the image capture control circuit 14 , and supplies an image signal obtained by the image capture to the signal processing circuit 15 .

[0019] The imaging control circuit 14 controls imaging by the solid-state imaging element 13. For example, the imaging control circuit 14 supplies the solid-state imaging element 13 with an imaging control signal including a vertical synchronization signal VSYNC, which is a periodic signal with a constant frequency (e.g., 60 Hz) indicating the timing of imaging.

[0020] The signal processing circuit 15 performs various signal processing on the image signal output from the solid-state image sensor 13 , and supplies the image data obtained as a result of the processing to a monitor 16 or a memory 17 .

[0021] The monitor 16 displays an image in accordance with the image data supplied from the signal processing circuit 15, and the memory 17 stores (records) the image data supplied from the signal processing circuit 15. If the solid-state imaging device 13 has a communication interface, the image data may be transmitted to an external device.

[0022] The solid-state imaging device 13 includes a pixel array section 21, a timing control circuit 22, a vertical scanning circuit 23, a digital-to-analog converter (DAC) 24, a load complementary metal oxide (MOS) circuit block 25, and a column signal processing circuit 26.

[0023] A plurality of pixels 31 are arranged in an array in the pixel array unit 21. Hereinafter, a group of pixels 31 arranged in the horizontal direction will be referred to as a "row," and a group of pixels 31 arranged in a direction perpendicular to the rows will be referred to as a "column." In the pixel array unit 21, each pixel 31 photoelectrically converts incident light to generate an analog pixel signal, and the pixel signals are output in parallel in the column direction in order for each row selected by the vertical scanning circuit 23.

[0024] The timing control circuit 22 controls the operation timing of each of the vertical scanning circuit 23 , the DAC 24 , and the column signal processing circuit 26 in synchronization with the vertical synchronization signal VSYNC supplied from the imaging control circuit 14 .

[0025] The vertical scanning circuit 23 sequentially selects rows so as to scan in the vertical direction, and supplies various control signals to the pixels 31 provided in each selected row, causing the pixels 31 to output analog pixel signals.

[0026] The DAC 24 generates a sawtooth ramp signal by DA conversion and supplies it to the column signal processing circuit 26 .

[0027] In the load MOS circuit block 25, a MOS transistor (for example, the constant current source 44 in FIG. 2) that supplies a constant current is provided for each column.

[0028] The column signal processing circuit 26 refers to the ramp signal supplied from the DAC 24, performs AD (Analog to Digital) conversion on the analog pixel signals output from the pixels 31 via the load MOS circuit block 25, and removes noise by performing CDS (Correlated Double Sampling) processing on the digital pixel signals.

[0029] Then, image data obtained as a result of the column signal processing circuit 26 performing signal processing on the pixel signals is output from the solid-state imaging device 13 .

[0030] <First Configuration Example of Pixel> A first configuration example of the pixel 31 will be described with reference to FIGS.

[0031] FIG. 2 shows an example of a circuit diagram of a pixel 31 according to the first configuration example.

[0032] As shown in FIG. 2 , the pixel 31 is composed of a pixel circuit 41 that generates a pixel signal corresponding to the amount of incident light, and a sample-and-hold circuit 42 that samples the pixel signal generated in the pixel circuit 41 and holds it at a constant level of voltage, and is connected to a constant current source 44 via a vertical signal line 43.

[0033] The pixel circuit 41 includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, an amplifier gate 56, and a switch gate 57. The sample-and-hold circuit 42 includes a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an RB gate 65, an amplifier gate 66, a selection gate 67, and a constant current source 68. When the pixel 31 is configured using a two-layer semiconductor substrate, the pixel circuit 41 is provided on the first semiconductor substrate layer, and the sample-and-hold circuit 42 is provided on the second semiconductor substrate layer. In FIG. 2 , a rectangle shown between the pixel circuit 41 and the sample-and-hold circuit 42 represents a connection point where the two semiconductor substrate layers are connected (e.g., a Cu-Cu connection).

[0034] The anode of the photoelectric conversion unit 51 is grounded, and the cathode of the photoelectric conversion unit 51 is connected to the source of the transfer gate 52. The drain of the transfer gate 52 is connected to the source of the FD gate 53 and the gate electrode of the amplifier gate 56, and this connection point is called an FD (Floating Diffusion) node. The drain of the FD gate 53 is connected to the source of the reset gate 54 and one end of the capacitor 55. The drain of the reset gate 54 is connected to a power supply VDD, and the other end of the capacitor 55 is grounded. The drain of the amplifier gate 56 is connected to a power supply AMD, and the source of the amplifier gate 56 is connected to the drain of the switch gate 57. The source of the switch gate 57 is connected to a constant current source 68 of the sample-and-hold circuit 42.

[0035] The connection point between one end of the capacitor 61 and one end of the capacitor 62 is called the V1 node, and the source of the switch gate 57 and the constant current source 68 are connected to this V1 node. The other end of the capacitor 61 is connected to the source of the SR gate 63, and the other end of the capacitor 62 is connected to the source of the SD gate 64. The drains of the SR gate 63 and the SD gate 64 are connected, and this connection point is called the V2 node. The gate electrode of the amplifier gate 66 and the source of the RB gate 65 are connected to this V2 node. The drain of the RB gate 65 is connected to the power supply VREG, and the drain of the amplifier gate 66 is connected to the power supply VDD. The source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43.

[0036] The photoelectric conversion unit 51 is configured by a photodiode that photoelectrically converts incident light that is incident on the pixel 31, and accumulates the electric charge generated by the photoelectric conversion.

[0037] The transfer gate 52 is driven in accordance with a control signal TRG supplied from the vertical scanning circuit 23, and transfers the charge accumulated in the photoelectric conversion unit 51 to the FD node at the timing when the transfer gate 52 is turned on.

[0038] The FD gate 53 is driven in accordance with a control signal FDG supplied from the vertical scanning circuit 23, and connects a capacitor 55 to the FD node while the transfer gate 52 is on. For example, by connecting the capacitor 55 to the FD node via the FD gate 53, it is possible to increase the storage capacitance that holds the charge transferred from the photoelectric conversion unit 51, and it is possible to perform HDR (High Dynamic Range) imaging.

[0039] The reset gate 54 is driven in accordance with a control signal RST supplied from the vertical scanning circuit 23, and when the reset gate 54 is turned on, the charge stored in the capacitor 55 and the charge stored in the FD node via the FD gate 53 are discharged to the power supply VDD and reset.

[0040] The capacitor 55 holds the charge transferred from the photoelectric conversion unit 51 together with the FD node while it is connected to the FD node via the FD gate 53 .

[0041] The amplification gate 56 generates a pixel signal according to the charge stored in the FD node or the charge stored in the FD node and the capacitor 55. The amplification gate 56 forms a source follower circuit together with a constant current source 68 connected via a switch gate 57, and outputs the generated pixel signal to the V1 node.

[0042] The switch gate 57 is driven in accordance with a control signal SW supplied from the vertical scanning circuit 23, and connects the amplifier gate 56 to the V1 node while the switch gate 57 is on. Then, the pixel signal generated in the amplifier gate 56 is output to the V1 node via the switch gate 57.

[0043] The capacitor 61 holds the voltage of the pixel signal (hereinafter also referred to as a P-phase signal) at the reset level at which the FD node is reset, in a signal holding capacitance C. A signal holding node that holds a charge corresponding to the P-phase signal between the capacitor 61 and the SR gate 63 is called a VCR node.

[0044] The capacitor 62 holds, in a signal holding capacitance C, the voltage of a pixel signal (hereinafter also referred to as a D-phase signal) at a pixel signal level corresponding to the charge generated in the photoelectric conversion unit 51 and held in the FD node (or the FD node and capacitor 55). A signal holding node that holds the charge corresponding to the D-phase signal between the capacitor 62 and the SD gate 64 is referred to as a VCD node.

[0045] The SR gate 63 is driven in accordance with a control signal SR supplied from the vertical scanning circuit 23, and when the SR gate 63 is turned on, it connects the VCR node to the V2 node, causing the charge corresponding to the P-phase signal held in the VCR node to be held by the VCR node and the V2 node.

[0046] The SD gate 64 is driven in accordance with a control signal SD supplied from the vertical scanning circuit 23, and when the SD gate 64 is turned on, it connects the VCD node to the V2 node, causing the charge corresponding to the D-phase signal that was held in the VCD node to be held by the VCD node and the V2 node.

[0047] The RB gate 65 is driven in accordance with a control signal RB supplied from the vertical scanning circuit 23, and when the RB gate 65 is turned on, the charges held by the VCR node and the V2 node, as well as the charges held by the VCD node and the V2 node, are discharged to the power supply VREG and reset.

[0048] The amplifier gate 66 generates a P-phase signal, which is a pixel signal corresponding to the charges held by the VCR node and the V2 node, and a D-phase signal, which is a pixel signal corresponding to the charges held by the VCD node and the V2 node. The amplifier gate 66 forms a source follower circuit together with the constant current source 44 connected via a selection gate 67, and outputs the P-phase signal and the D-phase signal to the vertical signal line 43.

[0049] The selection gate 67 is driven in accordance with a control signal SEL supplied from the vertical scanning circuit 23, and while the row is selected as the row from which pixel signals are to be read out and the selection gate 67 is turned on, the amplification gate 66 is connected to the vertical signal line 43. Then, the pixel signals (P-phase signal and D-phase signal) generated in the amplification gate 66 are read out to the vertical signal line 43 via the selection gate 67.

[0050] The constant current source 68 constitutes a load for the amplifier gate 56 and supplies a constant current sink to the V1 node.

[0051] In the solid-state imaging device 13, the operation of reading out pixel signals (P-phase signals and D-phase signals) from the pixels 31 in the selected row is as follows.

[0052] First, the RB gate 65 is turned on to reset the V2 node, and then the SR gate 63 is turned on, whereby a charge corresponding to the voltage of the P-phase signal charged in the capacitor 61 is held at the VCR node and the V2 node, and reading of the P-phase signal is completed via the amplification gate 66. Next, the RB gate 65 is turned on to reset the V2 node, and then the SD gate 64 is turned on, whereby a charge corresponding to the voltage of the D-phase signal charged in the capacitor 62 is held at the VCD node and the V2 node, and reading of the D-phase signal is completed via the amplification gate 66.

[0053] In this way, when a P-phase signal is read out from pixel 31, charge sharing occurs at the VCR node and the V2 node, and when a D-phase signal is read out from pixel 31, charge sharing occurs at the VCD node and the V2 node.

[0054] Therefore, in order to obtain a good image quality in the solid-state imaging device 13, the parasitic capacitance C SR-V2 and a parasitic capacitance C due to capacitive coupling occurring between the SD gate 64 and the V2 node. SD-V2 Therefore, in practice, the pixel 31 has a parasitic capacitance C SR-V2 and parasitic capacitance C SD-V2 The first capacitance ratio C1 is obtained by dividing the difference between ratio is less than 1 / 1000, that is, the pixel 31 is preferably configured to satisfy the following formula (1):

[0055]

[0056] Similarly, in order to obtain a good image quality in the solid-state image pickup device 13, the parasitic capacitance C due to the capacitive coupling occurring between the SR gate 63 and the VCR node is SR-VCR and a parasitic capacitance C due to capacitive coupling occurring between the SD gate 64 and the VCD node. SD-VCD Therefore, in practice, the pixel 31 has a parasitic capacitance C SR-VCR and parasitic capacitance C SD-VCDA second capacitance ratio C2 is obtained by dividing the difference between ratio is less than 1 / 1000, that is, the pixel 31 is preferably configured to satisfy the following formula (2):

[0057]

[0058] In order to obtain a good image quality in the solid-state image pickup device 13, the parasitic capacitance C RB-VCR and a parasitic capacitance C due to capacitive coupling occurring between the RB gate 65 and the VCD node. RB-VCD Therefore, in practice, the pixel 31 has a parasitic capacitance C RB-VCR and parasitic capacitance C RB-VCD and the difference between them is divided by the signal holding capacitance C to obtain a third capacitance ratio C3 ratio is less than 1 / 1000, that is, the pixel 31 is preferably configured to satisfy the following formula (3):

[0059]

[0060] In order to obtain a good image quality in the solid-state imaging device 13, the parasitic capacitance C due to the capacitive coupling generated between the selection gate 67 and the VCR node is SEL-VCR and a parasitic capacitance C due to capacitive coupling occurring between the select gate 67 and the VCD node. SEL-VCD Therefore, in practice, the pixel 31 has a parasitic capacitance C SEL-VCR and parasitic capacitance C SEL-VCD A fourth capacitance ratio C4 is obtained by dividing the difference between ratio is less than 1 / 1000, that is, the pixel 31 is preferably configured to satisfy the following formula (4):

[0061]

[0062] As described above, the solid-state imaging device 13 configures the pixels 31 to satisfy the above-described formulas (1) to (4), and suppresses fluctuations in pixel signals caused by capacitive coupling, thereby suppressing deterioration in image quality and further improving image quality. Note that the solid-state imaging device 13 does not need to satisfy all of the above-described formulas (1) to (4), and image quality can be improved by satisfying any one of them.

[0063] 3, the solid-state imaging device 13 can employ a four-pixel sharing structure in which four pixels 31[0] to 31[3] in a 2x2 array are shared at the V2 node. Note that in the drawings of the four-pixel sharing structure described below, the pixel circuit 41 is not shown. Furthermore, i is used to identify a specific pixel 31 among the multiple pixels 31, and in the four-pixel sharing structure, the individual pixels 31 are distinguished by i=1, 2, 3, 4.

[0064] 4 and 5 show an example of a planar layout of pixels 31[0] to 31[3] in a four-pixel sharing structure.

[0065] As shown in FIG. 4, in the pixel 31[i], a parasitic capacitance C SR[i]-V2 occurs, and a parasitic capacitance C SD[i]-V2 As shown in FIG. 5, in the pixel 31[i], a parasitic capacitance C SR[i]-VCR[i] occurs, and a parasitic capacitance C SD[i]-VCD[i] 4 and 5 show a planar layout of a configuration in which a DIFF gate 75 shown in FIG. 14 (described later) is provided, and the dashed rectangles represent contacts that connect the semiconductor substrate or gate electrode to the wiring layer.

[0066] In such a four-pixel sharing structure, as described above, the parasitic capacitance C SR[i]-V2 and parasitic capacitance C SD[i]-V2 The first capacitance ratio C1 is obtained by dividing the difference between ratioIt is preferable that the first capacitance ratio C1 be less than 1 / 1000. ratio [0] to first capacitance ratio C1 ratio [3] The maximum value maxC1 ratio [i] and minimum value minC1 ratio It is preferable that the difference with [i] is less than 1 / 1000. That is, it is preferable that the pixels 31[0] to 31[3] are configured to satisfy the following formula (5).

[0067]

[0068] Similarly, in the four-pixel sharing structure, as described above, the parasitic capacitance C SR[i]-VCR[i] and parasitic capacitance C SD[i]-VCD[i] A second capacitance ratio C2 is obtained by dividing the difference between ratio It is preferable that the second capacitance ratio C2 be less than 1 / 1000. ratio [0] to second capacitance ratio C2 ratio [3] The maximum value maxC2 ratio [i] and minimum value minC2 ratio It is preferable that the difference with [i] is less than 1 / 1000. That is, it is preferable that the pixels 31[0] to 31[3] are configured to satisfy the following formula (6).

[0069]

[0070] In addition, in the four-pixel sharing structure, as described above, the parasitic capacitance C RB-VCR[i] and parasitic capacitance C RB-VCD[i] and the difference between them is divided by the signal holding capacitance C to obtain a third capacitance ratio C3 ratio It is preferable that the third capacitance ratio C3 be set to be less than 1 / 1000. ratio [0] to third capacitance ratio C3 ratio [3] The maximum value maxC3 ratio [i] and minimum value minC3 ratio It is preferable that the difference with [i] is less than 1 / 1000. That is, it is preferable that the pixels 31[0] to 31[3] are configured to satisfy the following formula (7).

[0071]

[0072] In addition, in the four-pixel sharing structure, as described above, the parasitic capacitance C SEL-VCR[i] and parasitic capacitance C SEL-VCD[i] A fourth capacitance ratio C4 is obtained by dividing the difference between ratio It is preferable that the fourth capacitance ratio C4 be less than 1 / 1000. ratio [0] to fourth capacitance ratio C4 ratio [3] The maximum value maxC4 ratio [i] and minimum value minC4 ratio It is preferable that the difference with [i] is less than 1 / 1000. That is, it is preferable that the pixels 31[0] to 31[3] are configured to satisfy the following formula (8).

[0073]

[0074] As described above, the solid-state imaging device 13 employing the four-pixel sharing structure configures the pixel 31[i] to satisfy the above-described formulas (5) to (8), thereby suppressing fluctuations in pixel signals due to capacitive coupling, thereby suppressing deterioration in image quality and further improving image quality. Note that the solid-state imaging device 13 does not need to satisfy all of the above-described formulas (5) to (8), and image quality can be improved by satisfying any one of them.

[0075] In order to satisfy such capacitive coupling constraints, it is preferable to adopt a wiring layout in the planar layout as shown in FIGS. 3 and 4 such that the wirings generating the parasitic capacitances whose difference is desired to be reduced have a relative positional relationship (symmetry) with each other, as described above, and the shortest distances between these wirings are equal.

[0076] 6 shows an example of a wiring layout in a four-pixel sharing structure, in which a wiring layer is provided with RB wiring that supplies a control signal to an RB gate 65 that resets the V2 node and SEL wiring that supplies a control signal to a selection gate 67 that performs row selection, as viewed in plan. In addition to the RB wiring and SEL wiring, this wiring layer is also provided with other wiring, such as a VSSHPS wiring that supplies a power supply VSS, as shown in FIG.

[0077] As described above, the solid-state imaging device 13 has a parasitic capacitance C due to capacitive coupling between the RB gate 65 and the VCR node. RB-VCR and a parasitic capacitance C due to capacitive coupling occurring between the RB gate 65 and the VCD node. RB-VCD It is necessary to satisfy the coupling constraint (the above-mentioned formula (3)) that the difference between the RB wiring and the VCR wiring [2], the VCR wiring [3], the VCD wiring [2], and the VCD wiring [3]. For this reason, it is preferable that the solid-state imaging device 13 adopts a wiring layout in which wiring other than the RB wiring and the VCR wiring [2], the VCR wiring [3], the VCD wiring [2], and the VCD wiring [3] (in the example shown in FIG. 6 ) is arranged between these wirings.

[0078] Similarly, as described above, the solid-state imaging device 13 has a parasitic capacitance C due to capacitive coupling between the select gate 67 and the VCR node. SEL-VCR and a parasitic capacitance C due to capacitive coupling occurring between the select gate 67 and the VCD node. SEL-VCD It is necessary to satisfy the coupling constraint (the above-mentioned formula (4)) that the difference between the SEL wiring and the VCR wiring [0], the VCR wiring [1], the VCD wiring [0], and the VCD wiring [1]. For this reason, it is preferable that the solid-state imaging device 13 adopts a wiring layout in which wiring other than the SEL wiring and the VCR wiring [0], the VCR wiring [1], the VCD wiring [0], and the VCD wiring [1] (in the example shown in FIG. 6 ) is arranged between these wirings.

[0079] By realizing such coupling constraints, the solid-state imaging element 13 can suppress the occurrence of an offset between the P-phase signal and the D-phase signal when reading out a pixel signal from pixel 31[i], and the occurrence of a difference between the pixel signals of each pixel 31[i] that share the V2 node.

[0080] 6 shows an example of a wiring layout in which the RB wiring and the SEL wiring are arranged in the same wiring layer, but for example, the RB wiring and the SEL wiring may be arranged in different wiring layers. Furthermore, such a wiring layout can also be applied to a single pixel 31 that does not adopt a four-pixel sharing structure.

[0081] The voltage-domain global shutter solid-state imaging element 13 having the pixels 31 configured as described above can suppress degradation in image quality by having the pixels 31 satisfy the coupling constraints described above, thereby capturing images with better image quality.

[0082] <Second Configuration Example of Pixel> A second configuration example of the pixel 31 will be described with reference to FIGS.

[0083] Fig. 7 shows an example of a circuit diagram of a pixel 31a, which is the second configuration example. In the pixel 31a shown in Fig. 7, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0084] As shown in FIG. 7, the pixel 31a has a common configuration with the pixel 31 in FIG. 2 in that it is configured by a pixel circuit 41a and a sample-and-hold circuit 42a and is connected to a constant current source 44 via a vertical signal line 43.

[0085] 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, an amplification gate 56, and a switch gate 57. Furthermore, the pixel circuit 41a is configured to include an overflow gate 73.

[0086] The overflow gate 73 is connected between the photoelectric conversion unit 51 and a power supply VDD, and discharges to the power supply VDD any charge that has overflowed from the photoelectric conversion unit 51. The overflow gate 73 is driven in accordance with a control signal OFG supplied from the vertical scanning circuit 23, and when the overflow gate 73 is turned on, the charge accumulated in the photoelectric conversion unit 51 is discharged to the power supply VDD to reset the photoelectric conversion unit 51, and exposure of the pixel 31 a begins.

[0087] 2 in that it includes a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an RB gate 65, an amplifier gate 66, and a selection gate 67. Furthermore, the sample and hold circuit 42a includes a PC gate 71 and a VB gate 72 instead of the constant current source 68 of FIG.

[0088] The drain of the PC gate 71 is connected to the V1 node, the source of the PC gate 71 is connected to the drain of the VB gate 72, and the source of the VB gate 72 is grounded. The PC gate 71 supplies a constant current to the V1 node that corresponds to the bias voltage PC applied to its gate electrode, and the VB gate 72 supplies a constant current to the V1 node that corresponds to the bias voltage VB applied to its gate electrode. In this way, by cascode-connecting the VB gate 72 to the PC gate 71, which serves as a current source, and supplying different bias voltages PC and VB to the respective gate electrodes, it is possible to reduce noise in the constant current supplied to the V1 node and to reduce fluctuations in the constant current when the power supply voltage fluctuates.

[0089] 8 shows an example of a wiring layout of a wiring layer in which an SR wiring for supplying a control signal SR to the gate electrode of the SR gate 63, an SD wiring for supplying a control signal SD to the gate electrode of the SD gate 64, and a VREG wiring for supplying a power supply VREG are provided. Here, the longitudinal direction of the wiring shown is a direction perpendicular to the vertical signal line 43, and this direction is referred to as the horizontal direction.

[0090] As shown in the figure, there is a parasitic capacitance C between the adjacent SR wiring and VREG wiring. SR-VREG occurs, and a parasitic capacitance C SD-VREG Therefore, the global shutter type solid-state imaging device 13 using the voltage-domain method can suppress deterioration of image quality by adopting a wiring layout that takes into consideration these capacitive couplings.

[0091] That is, as shown in FIG. 8, it is preferable to adopt a wiring layout for pixel 31a in which the SD wiring and SR wiring are line-symmetrical with respect to a dashed line extending horizontally through the center of pixel 31a, and the VREG wiring is line-symmetrical with respect to each other.

[0092] As a result, when the VCR node or the VCD node is connected to the V2 node, the pixel 31a matches the voltage fluctuation of the power supply VREG when the voltage of the SR gate 63 changes (from low to high and from high to low) with the voltage fluctuation of the power supply VREG when the voltage of the SD gate 64 changes (from low to high and from high to low). Therefore, the pixel 31a can match the voltage levels of charge sharing at the VCR node and the V2 node with the voltage levels of charge sharing at the VCD node and the V2 node, and can reduce output fluctuations when a P-phase signal or a D-phase signal is read out from the pixel 31.

[0093] Furthermore, in order to obtain a good image quality in the solid-state imaging device 13, the parasitic capacitance C SR-VREG and the parasitic capacitance C due to capacitive coupling that occurs between the SD wiring and the VREG wiring. SD-VREG Therefore, in practice, the pixel 31a has a parasitic capacitance C SR-VREG and parasitic capacitance C SD-VREG A fifth capacitance ratio C5 is obtained by dividing the difference between ratio is preferably less than 1 / 1000, that is, the following formula (9) is preferably satisfied:

[0094]

[0095] Furthermore, as shown in FIG. 9, the solid-state imaging device 13 can employ a four-pixel sharing structure in which four pixels 31a[0] to 31a[3] in a 2×2 array are shared at the V2 node.

[0096] Figure 10 shows an example of a wiring layout of a wiring layer in a four-pixel sharing structure in which an SR[i] wiring that supplies a control signal SR to the gate electrode of an SR gate 63[i], an SD[i] wiring that supplies a control signal SD to the gate electrode of an SD gate 64[i], and a VREG wiring that supplies a power supply VREG are provided.

[0097] In pixels 31a[0] to 31a[3] of such a four-pixel sharing structure, as with the single pixel 31a described above, it is preferable to adopt a wiring layout in which the SD[i] wiring and SR[i] wiring are line-symmetrical with respect to the dashed line extending horizontally through the center of the 2x2 array, and the VREG wiring is line-symmetrical with respect to each other.

[0098] As a result, when the VCR node [i] or the VCD node [i] is connected to the V2 node, the voltage fluctuation of the power supply VREG when the voltage of the SR gate 63 [i] changes (from low to high and from high to low) and the voltage fluctuation of the power supply VREG when the voltage of the SD gate 64 [i] changes (from low to high and from high to low) are matched in the pixels 31 a [0] to 31 a [3]. Therefore, the pixels 31 a [0] to 31 a [3] can match the voltage levels of the charge sharing at the VCR node [i] and the V2 node with the voltage levels of the charge sharing at the VCD node [i] and the V2 node, thereby reducing output fluctuations when reading out P-phase signals or D-phase signals from the pixels 31 a [0] to 31 a [3].

[0099] That is, in order to obtain a good image quality in the solid-state imaging device 13, the parasitic capacitance C SR[i]-VREG and the parasitic capacitance C due to capacitive coupling occurring between the i-th SD wiring and the VREG wiring. SD[i]-VREG Therefore, in practice, the pixel 31a has a parasitic capacitance C SR[i]-VREG and parasitic capacitance C SD[i]-VREG The sum of capacitance ratios C6 is obtained by dividing the difference between ratiois less than 1 / 1000, that is, it is preferable that the following formula (10) is satisfied.

[0100]

[0101] This allows the solid-state imaging device 13 to suppress deterioration in image quality and capture images with better image quality.

[0102] FIG. 11 shows an example of a gate layout of pixels 31a[0] to 31a[3] in a 2×2 array.

[0103] 11, pixel 31a[0] and pixel 31a[1] are arranged adjacent to each other in the horizontal direction, and pixel 31a[2] and pixel 31a[3] are arranged adjacent to each other in the horizontal direction. Pixels 31a[0] to 31a[3] are arranged in a gate layout in which, for horizontally adjacent pixels 31a[i], SR gate 63[i] and SD gate 64[i] are in a translationally symmetrical relationship (symmetrical with respect to parallel movement), and PC gate 71[i] and VB gate 72[i] are in an axisymmetrical relationship.

[0104] With this gate layout, the SR gate 63[0] is adjacent to the VB gate 72[0] in the pixel 31a[0] located at the bottom left, and the SD gate 64[1] is adjacent to the VB gate 72[1] in the pixel 31a[1] located at the bottom right. Therefore, when looking at the row direction, the parasitic capacitance C SR[0]-VB and the parasitic capacitance C due to capacitive coupling occurring between the SD gate 64[1] and the VB gate 72[1]. SD[1]-VB will be the same.

[0105] Similarly, in the pixel 31a[2] located at the top left, the SR gate 63[2] is adjacent to the VB gate 72[2], and in the pixel 31a[3] located at the top right, the SD gate 64[3] is adjacent to the VB gate 72[3]. Therefore, when focusing on the row direction, the parasitic capacitance C SR[2]-VBand the parasitic capacitance C due to capacitive coupling occurring between the SD gate 64 [3] and the VB gate 72 [3]. SD[3]-VB will be the same.

[0106] As a result, when connecting the VCR node [i] or the VCR node [i] to the V2 node simultaneously in all pixels 31a, and when disconnecting them, the voltage fluctuation of the VB gate 72 [i] due to the change in voltage of the SR gate 63 [i] and the voltage fluctuation of the VB gate 72 [i] due to the change in voltage of the SD gate 64 [i] are aligned, thereby suppressing degradation of image quality.

[0107] In addition, a parasitic capacitance C due to capacitive coupling occurs between the SR gate 63[i] and the VB gate 72[i]. SR[i]-VB and a parasitic capacitance C due to capacitive coupling occurring between the SD gate 64[i] and the VB gate 72[i]. SD[i]-VB Therefore, in practice, the pixel 31a has a parasitic capacitance C SR[i]-VB and parasitic capacitance C SD[i]-VB The total capacitance ratio C7 obtained by dividing the difference between ratio is preferably less than 1 / 1000, that is, the following formula (11) is preferably satisfied:

[0108]

[0109] This allows the solid-state imaging device 13 to suppress deterioration in image quality and capture images with better image quality.

[0110] FIG. 12 shows an example of the layout of the capacitors 61 and 62 and the V1 node provided in the pixels 31a[0] to 31a[3] in a 2×2 array.

[0111] In a 2×2 array as shown in FIG. 12, a parasitic capacitance C V1[i]-VCR[j] and parasitic capacitance C V1[i]-VCD[j] Capacitive coupling occurs.

[0112] Therefore, as shown in FIG. 12, pixels 31a[0] to 31a[3] adopt a layout in which the V1 nodes[i], which are the drain nodes of the constant current sources of vertically adjacent pixels 31a[i], are positioned at positions separated from each other, and capacitors 61[i] and 62[i] are placed between these V1 nodes[i].

[0113] That is, the pixel 31a[0] located at the bottom left has a V1 node[0] located below it, and the pixel 31a[2] located at the top left has a V1 node[2] located above it, with capacitors 61[0] and 62[0], as well as capacitors 61[2] and 62[2], located between the V1 node[0] and the V1 node[2]. Similarly, the pixel 31a[1] located at the bottom right has a V1 node[1] located below it, and the pixel 31a[3] located at the top right has a V1 node[3] located above it, with capacitors 61[1] and 62[1], as well as capacitors 61[3] and 62[3], located between the V1 node[1] and the V1 node[3].

[0114] Furthermore, it is preferable to adopt a layout in which the V1 nodes [i] of vertically adjacent pixels 31a[i] are line-symmetrical with respect to a dashed line extending horizontally through the center of the 2x2 array, and the capacitors 61[i] and capacitors 62[i] of vertically adjacent pixels 31a[i] are line-symmetrical with respect to the dashed line extending horizontally through the center of the 2x2 array.

[0115] By adopting such a layout, the parasitic capacitance C V1[i]-VCR[j] and parasitic capacitance C V1[i]-VCD[j] This can reduce the fluctuation in the held potential of a pixel 31a[i] due to the fluctuation in the potential of another pixel 31a[j] that is vertically adjacent to the pixel 31a[i], thereby reducing the output fluctuation for each pixel 31a[i].

[0116] That is, in order to reduce the output fluctuation of each pixel 31a[i] in the solid-state imaging device 13 and obtain good image quality, in a 2×2 array, the parasitic capacitance C due to capacitive coupling that occurs between the capacitor 61 and the capacitor 62 of a certain pixel 31a[i] and the V1 node of another pixel 31a[j] that is adjacent to the pixel 31a[i] in the vertical direction is reduced. V1[i]-VCR[j] and parasitic capacitance C V1[i]-VCD[j] Therefore, in practice, the pixel 31a[i] has a parasitic capacitance C V1[i]-VCR[j] The capacitance ratio C8 obtained by dividing by the signal holding capacitance C ratio , and the parasitic capacitance C V1[i]-VCD[j] by the signal holding capacitance C ratio is less than 1 / 1000, that is, it is preferable that the following formula (12) is satisfied.

[0117]

[0118] The global shutter solid-state imaging element 13 using the voltage-domain method and having the pixel 31a configured as described above can suppress degradation in image quality and capture images with better image quality by ensuring that the layout of the control lines including the gates as described above and the coupling between the control lines and power supply lines satisfy certain conditions.

[0119] <Third to Tenth Configuration Examples of Pixel> Third to tenth configuration examples of the pixel 31 will be described with reference to FIGS.

[0120] Fig. 13 shows an example of a circuit diagram of a pixel 31b, which is a third configuration example. In the pixel 31b shown in Fig. 13, components common to the pixel 31 in Fig. 2 and the pixel 31a in Fig. 7 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0121] 13, pixel 31b is configured with a pixel circuit 41b and a sample-and-hold circuit 42b, and has a configuration common to pixel 31 in Fig. 2 in that it is connected to a constant current source 44 via a vertical signal line 43. Similar to sample-and-hold circuit 42a in Fig. 7, sample-and-hold circuit 42b is configured with capacitor 61, capacitor 62, SR gate 63, SD gate 64, RB gate 65, amplifier gate 66, selection gate 67, PC gate 71, and VB gate 72.

[0122] 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, a reset gate 54, an amplification gate 56, and a switch gate 57. Furthermore, the pixel circuit 41a includes an overflow gate 73 and a CLP gate 74.

[0123] As shown in FIG. 13, the CLP gate 74 is connected in parallel to the amplifier gate 56 and forms a source follower circuit similar to the amplifier gate 56 .

[0124] The voltage-domain global shutter solid-state imaging element 13 having the pixel 31b configured in this manner satisfies the coupling constraints of the above-described equations (1) to (4), thereby enabling the imaging of higher image quality.

[0125] Fig. 14 shows an example of a circuit diagram of a pixel 31c which is a fourth configuration example. In the pixel 31c shown in Fig. 14, components common to the pixel 31 in Fig. 2 and the pixel 31a in Fig. 7 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0126] As shown in FIG. 14, the pixel 31c has a common configuration with the pixel 31 in FIG. 2 in that it is composed of a pixel circuit 41 and a sample-and-hold circuit 42c and is connected to a constant current source 44 via a vertical signal line 43.

[0127] 2 in that it includes a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an RB gate 65, an amplification gate 66, and a selection gate 67. Furthermore, the sample and hold circuit 42c includes a DIFF gate 75, and a capacitor 76 instead of the constant current source 68 of FIG.

[0128] 14, the drain of the DIFF gate 75 is connected to a V1 node which is a connection point between the source of the switch gate 57 and one end of the capacitor 61. The source of the DIFF gate 75 is connected to a connection point between one end of the capacitor 62 and one end of the capacitor 76, and this connection point is referred to as a V3 node. The other end of the capacitor 76 is connected to a signal line which supplies a ramp signal RAMP.

[0129] In pixel 31c configured in this manner, as charge accumulates in capacitor 76 at a constant rate in accordance with the sawtooth ramp signal RAMP, capacitor 76 is used as a constant current source that supplies a constant current sink current to node V1.

[0130] Furthermore, pixel 31c is provided with a DIFF gate 75, which can reduce leakage during periods when pixel signals are held in capacitors 61 and 62. For example, DIFF gate 75 is driven in accordance with a control signal DIFF, and is turned off during a readout standby period after a global operation period, thereby separating capacitors 61 and 62. On the other hand, during a readout period, a complete global operation period, and / or a complete row readout period, DIFF gate 75 is turned on, thereby connecting capacitors 61 and 62.

[0131] The voltage-domain global shutter solid-state imaging element 13 having the pixel 31c configured in this manner satisfies the coupling constraints of the above-mentioned equations (1) to (4), thereby enabling the imaging of higher image quality.

[0132] Fig. 15 shows an example of a circuit diagram of a pixel 31d, which is a fifth configuration example. In the pixel 31d shown in Fig. 15, components common to the pixel 31 in Fig. 2 and the pixel 31a in Fig. 7 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0133] As shown in FIG. 15, the pixel 31d has a common configuration with the pixel 31 in FIG. 2 in that it is configured by a pixel circuit 41d and a sample-and-hold circuit 42d and is connected to a constant current source 44 via a vertical signal line 43.

[0134] 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, and an amplification gate 56, but differs from the pixel circuit 41 in that it does not include a switch gate 57. Note that the pixel circuit 41d differs from the pixel circuit 41 in that the drain of the amplification gate 56, together with the drain of the reset gate 54, is connected to the power supply VDD.

[0135] The sample-and-hold circuit 42 d includes a switch gate 57 , a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , a PC gate 71 , and a VB gate 72 .

[0136] The drain of the switch gate 57 is connected to the source of the amplifier gate 56 and the drain of the PC gate 71, and this connection point forms the V1 node. The source of the switch gate 57 is connected to the V2 node, which is connected to the drain of the SR gate 63, the drain of the SD gate 64, and the gate electrode of the amplifier gate 66. The source of the SR gate 63 is connected to one end of a capacitor 61, the other end of which is grounded. The source of the SD gate 64 is connected to one end of a capacitor 62, the other end of which is grounded. The drain of the amplifier gate 66 is connected to the power supply VDD, the source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43. The drain of the PC gate 71 is connected to the V1 node, the source of the PC gate 71 is connected to the drain of the VB gate 72, and the source of the VB gate 72 is grounded.

[0137] The voltage-domain global shutter solid-state imaging element 13 having the pixel 31d configured in this manner satisfies the coupling constraints of the above-mentioned equations (1), (2), and (4), and can capture images with better image quality.

[0138] Fig. 16 shows an example of a circuit diagram of a pixel 31e, which is a sixth configuration example. In the pixel 31e shown in Fig. 16, components common to the pixel 31 in Fig. 2 and the pixel 31a in Fig. 7 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0139] 16, pixel 31e has a configuration common to pixel 31 in Fig. 2 in that it is configured with a pixel circuit 41 and a sample-and-hold circuit 42e. Furthermore, pixel 31e is connected to a constant current source 44-1 via a vertical signal line 43-1, and is connected to a constant current source 44-2 via a vertical signal line 43-2.

[0140] The sample-and-hold circuit 42 e includes a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplification gate 66 - 1 and an amplification gate 66 - 2 , a selection gate 67 - 1 and a selection gate 67 - 2 , and a PC gate 71 .

[0141] The drain of the SR gate 63 is connected to the V1 node, and the source of the SR gate 63 is connected to one end of the capacitor 61 and the gate electrode of the amplifier gate 66-1. The drain of the amplifier gate 66-1 is connected to the power supply VDD, and the source of the amplifier gate 66-1 is connected to the drain of the select gate 67-1, and the source of the select gate 67-1 is connected to the vertical signal line 43-1. The drain of the SD gate 64 is connected to the V1 node, and the source of the SD gate 64 is connected to one end of the capacitor 62 and the gate electrode of the amplifier gate 66-2. The drain of the amplifier gate 66-2 is connected to the power supply VDD, and the source of the amplifier gate 66-2 is connected to the drain of the select gate 67-2, and the source of the select gate 67-2 is connected to the vertical signal line 43-2. ​​The drain of the PC gate 71 is connected to the V1 node, and the source of the PC gate 71 is grounded.

[0142] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixel 31e configured in this way can capture images with better image quality.

[0143] Fig. 17 shows an example of a circuit diagram of a pixel 31f which is the seventh configuration example. In the pixel 31f shown in Fig. 17, components common to the pixel 31 in Fig. 2 and the pixel 31a in Fig. 7 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0144] As shown in FIG. 17, a pixel 31f is configured with a pixel circuit 41 and a sample-and-hold circuit 42f, and has a configuration common to the pixel 31 in FIG. 2 in that it is connected to a constant current source 44 via a vertical signal line 43.

[0145] The sample-and-hold circuit 42 f includes a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , and a PC gate 71 .

[0146] The drain of the SR gate 63 is connected to the V1 node, and the source of the SR gate 63 is connected to one end of the capacitor 61 and one end of the capacitor 62. The other end of the capacitor 62 is connected to the V2 node, to which the drain of the SD gate 64 and the gate electrode of the amplifier gate 66 are connected. The drain of the amplifier gate 66 is connected to the power supply VDD, and the source of the amplifier gate 66 is connected to the drain of the select gate 67, the source of which is connected to the vertical signal line 43. The drain of the PC gate 71 is connected to the V1 node, and the source of the PC gate 71 is grounded.

[0147] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixels 31f configured in this way can capture images with better image quality.

[0148] Fig. 18 shows an example of a circuit diagram of a pixel 31g, which is an eighth configuration example. In the pixel 31g shown in Fig. 18, components common to the pixel 31 in Fig. 2 and the pixel 31a in Fig. 7 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0149] As shown in FIG. 18, a pixel 31g has a configuration common to the pixel 31 in FIG. 2 in that it is composed of a pixel circuit 41g and a sample-and-hold circuit 42g and is connected to a constant current source 44 via a vertical signal line 43.

[0150] The pixel circuit 41g is configured similarly to the pixel circuit 41 of Figure 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, and an amplification gate 56, but differs from the pixel circuit 41 of Figure 2 in that it does not include a switch gate 57.

[0151] The sample-and-hold circuit 42 g includes a switch gate 57 , a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , a PC gate 71 , and a VB gate 72 .

[0152] The drain of the switch gate 57 is connected to the source of the amplifier gate 56 and the drain of the PC gate 71, and this connection point forms the V1 node. The source of the switch gate 57 is connected to the V2 node, which is connected to the drain of the SR gate 63, the drain of the SD gate 64, and the gate electrode of the amplifier gate 66. The source of the SR gate 63 is connected to one end of a capacitor 61, the other end of which is grounded. The source of the SD gate 64 is connected to one end of a capacitor 62, the other end of which is grounded. The drain of the amplifier gate 66 is connected to the power supply VDD, the source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43. The drain of the PC gate 71 is connected to the V1 node, the source of the PC gate 71 is connected to the drain of the VB gate 72, and the source of the VB gate 72 is grounded.

[0153] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixels 31g configured in this way can capture images with better image quality.

[0154] Fig. 19 shows an example of a circuit diagram of a pixel 31h, which is a ninth configuration example. In the pixel 31h shown in Fig. 19, components common to the pixel 31 in Fig. 2 and the pixel 31a in Fig. 7 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0155] As shown in FIG. 19, a pixel 31h has a common configuration with the pixel 31 in FIG. 2 in that it is configured with a pixel circuit 41 and a sample-and-hold circuit 42h and is connected to a constant current source 44 via a vertical signal line 43.

[0156] The sample-and-hold circuit 42 h includes a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , and a PC gate 71 .

[0157] The drain of the SR gate 63 is connected to the V1 node, and the source of the SR gate 63 is connected to the drain of the SD gate 64 and one end of the capacitor 61. The source of the SD gate 64 is connected to the gate electrode of the amplifier gate 66 and one end of the capacitor 62. The drain of the amplifier gate 66 is connected to the power supply VDD, and the source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43. The drain of the PC gate 71 is connected to the V1 node, and the source of the PC gate 71 is grounded.

[0158] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixels 31h configured in this way can capture images with better image quality.

[0159] Fig. 20 shows an example of a circuit diagram of a pixel 31i, which is a tenth configuration example. In the pixel 31i shown in Fig. 20, components common to the pixel 31 in Fig. 2 and the pixel 31a in Fig. 7 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0160] As shown in FIG. 20, the pixel 31i is configured with a pixel circuit 41 and a sample-and-hold circuit 42i, and has a configuration common to the pixel 31 in FIG. 2 in that it is connected to a constant current source 44 via a vertical signal line 43.

[0161] The sample-and-hold circuit 42 i includes a capacitor 61 , a capacitor 62 , an RB gate 65 , an amplifier gate 66 , a selection gate 67 , and a PC gate 71 .

[0162] One end of the capacitor 61 is connected to the V1 node, and the other end of the capacitor 61 is connected to one end of the capacitor 62, the source of the RB gate 65, and the gate electrode of the amplifying gate 66. The drain of the RB gate 65 is connected to the power supply VREG, and the drain of the amplifying gate 66 is connected to the power supply VDD. The source of the amplifying gate 66 is connected to the drain of the selecting gate 67, and the source of the selecting gate 67 is connected to the vertical signal line 43. The drain of the PC gate 71 is connected to the V1 node, and the source of the PC gate 71 is grounded.

[0163] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixels 31i configured in this way can capture images with better image quality.

[0164] The pixel 31 may have various configurations other than those shown in FIGS. 13 to 20, as long as the configuration satisfies the coupling constraints described above.

[0165] <Example of Cross-Sectional Configuration of Solid-State Imaging Device> An example of the cross-sectional configuration of the solid-state imaging device 13 will be described with reference to FIGS.

[0166] FIG. 21 shows a cross-sectional configuration of the solid-state imaging device 13 as a first configuration example.

[0167] As shown in FIG. 21, the solid-state imaging element 13 has a two-layer structure in which a first semiconductor substrate 101 and a second semiconductor substrate 102 are stacked, and a plurality of pixels 31 are arranged in a pixel array section 21.

[0168] The first semiconductor substrate 101 is configured by laminating a wiring layer 112 on a semiconductor layer 111, and an on-chip lens 113 for collecting light for each pixel 31 is laminated on the light-receiving surface side of the semiconductor layer 111.

[0169] The semiconductor layer 111 is provided with a photoelectric conversion unit 51 for each pixel 31, as well as various elements (e.g., transfer gates 52, FD gates 53, etc.) that constitute the pixel circuit 41. The semiconductor layer 111 is also provided with an element isolation unit 121 that optically and electrically isolates adjacent pixels 31 from each other.

[0170] The wiring layer 112 is provided with a plurality of wires and a plurality of through electrodes for electrical connection with the second semiconductor substrate 102 for each pixel 31. Furthermore, in the peripheral region of the wiring layer 112 (the region outside the pixel array section 21), pads 122 used for connecting the solid-state imaging element 13 to the outside are arranged, and openings 123 are provided for wire bonding to the pads 122.

[0171] The second semiconductor substrate 102 is configured by laminating a wiring layer 132 on a semiconductor layer 131 .

[0172] The semiconductor layer 131 is provided with various elements (for example, an SR gate 63, an SD gate 64, etc.) that constitute the sample-and-hold circuit 42. The semiconductor layer 131 is also provided with various elements that constitute a logic circuit that drives the solid-state imaging device 13, for example.

[0173] The wiring layer 132 is provided with a plurality of wires and a plurality of through electrodes for electrical connection with the first semiconductor substrate 101 for each pixel 31. In addition, the wiring layer 132 is provided with an MIM (Metal Insulator Metal) structure 143 for forming the capacitors 61 and 62 for each pixel 31.

[0174] The solid-state imaging element 13 having such a stacked structure can be constructed by joining the wiring layer 112 of the first semiconductor substrate 101 and the wiring layer 132 of the second semiconductor substrate 102, as in the configuration example shown in FIG.

[0175] Fig. 22 shows a cross-sectional configuration of a solid-state imaging device 13A as a second configuration example. In the solid-state imaging device 13A shown in Fig. 22, components common to the solid-state imaging device 13 shown in Fig. 21 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0176] 22, the solid-state imaging element 13A has a two-layer structure formed by stacking a first semiconductor substrate 101A and a second semiconductor substrate 102A. In the solid-state imaging element 13A, similar to the solid-state imaging element 13 of FIG. 21, a photoelectric conversion unit 51 is provided in the semiconductor layer 111 of the first semiconductor substrate 101A for each pixel 31, and an MIM structure 143 is provided in the wiring layer 132A of the second semiconductor substrate 102A.

[0177] 21 in that the solid-state imaging element 13A is configured by bonding a wiring layer 112A of a first semiconductor substrate 101A and a semiconductor layer 131A of a second semiconductor substrate 102A together. In the solid-state imaging element 13A, a pad 122A is disposed on the wiring layer 132A, and an opening 123A is provided so as to penetrate the first semiconductor substrate 101A and reach the pad 122A.

[0178] Fig. 23 shows a cross-sectional configuration of a solid-state imaging device 13B, which is a third configuration example. In the solid-state imaging device 13B shown in Fig. 23, components common to the solid-state imaging device 13 shown in Fig. 21 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0179] 23, the solid-state imaging element 13B has a three-layer structure in which a first semiconductor substrate 101, a second semiconductor substrate 102, and a third semiconductor substrate 103 are stacked, and is configured by joining a wiring layer 112 of the first semiconductor substrate 101 and a wiring layer 132 of the second semiconductor substrate 102. In other words, the solid-state imaging element 13B has a configuration in which a third semiconductor substrate 103 in which a wiring layer 152 is stacked on a semiconductor layer 151 is stacked on the first semiconductor substrate 101 and the second semiconductor substrate 102 which are configured in the same manner as the solid-state imaging element 13 in FIG.

[0180] For example, in the solid-state imaging device 13B, various elements constituting the pixel circuit 41 are provided on the first semiconductor substrate 101, and various elements constituting the sample-and-hold circuit 42 are provided on the second semiconductor substrate 102. Then, various elements constituting the logic circuit that drives the solid-state imaging device 13 are provided on the third semiconductor substrate 103.

[0181] Fig. 24 shows a cross-sectional configuration of a solid-state imaging device 13C, which is a fourth configuration example. In the solid-state imaging device 13C shown in Fig. 23, components common to the solid-state imaging device 13 shown in Fig. 21 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0182] 24, the solid-state imaging element 13C has a three-layer structure formed by stacking a first semiconductor substrate 101C, a second semiconductor substrate 102C, and a third semiconductor substrate 103, and is formed by bonding a wiring layer 112C of the first semiconductor substrate 101C to a semiconductor layer 131C of the second semiconductor substrate 102C. In other words, the solid-state imaging element 13C is formed by stacking a third semiconductor substrate 103 formed by stacking a wiring layer 152 on a semiconductor layer 151 on a first semiconductor substrate 101C and a second semiconductor substrate 102C which are formed in the same manner as the first semiconductor substrate 101A and the second semiconductor substrate 102A of the solid-state imaging element 13A in FIG.

[0183] For example, in the solid-state imaging device 13C, various elements constituting the pixel circuit 41 are provided on the first semiconductor substrate 101C, and various elements constituting the sample-and-hold circuit 42 are provided on the second semiconductor substrate 102C. Then, various elements constituting the logic circuit that drives the solid-state imaging device 13 are provided on the third semiconductor substrate 103.

[0184] The solid-state imaging device 13 may employ a layered structure other than the layered structures shown in FIGS.

[0185] <Example of Use of Image Sensor> FIG. 25 is a diagram showing an example of use of the image sensor (solid-state imaging element) described above.

[0186] The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0187] ・Devices for taking images for viewing purposes, such as digital cameras and mobile devices with camera functions. ・Devices for traffic purposes, such as in-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping, and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. ・Devices for home appliances such as TVs, refrigerators, and air conditioners that take images of user gestures and operate the device according to those gestures. ・Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light. ・Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. ・Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp. ・Devices for sports purposes, such as action cameras and wearable cameras for sports, etc. ・Devices for agricultural purposes, such as cameras to monitor the condition of fields and crops.

[0188] <Examples of Combinations of Configurations> The present technology may also be configured as follows: (1) A solid-state imaging device comprising a pixel including: a pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding a voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding a voltage of a pixel signal of a pixel signal level output from the pixel circuit; an amplifier gate that generates a pixel signal according to a charge accumulated at the second node connected to a gate electrode; and a sample and hold circuit having at least: a third node that is a connection point with the other end of the first capacitor, a first gate that connects the second node, and a fourth node that is a connection point with the other end of the second capacitor, and a second gate that connects the second node, wherein a difference between parasitic capacitances caused by capacitive coupling between the two nodes and two gates of the sample and hold circuit is less than a specified value. (2) The solid-state imaging device according to (1), wherein a difference between a first parasitic capacitance caused by capacitive coupling between the first gate and the second node and a second parasitic capacitance caused by capacitive coupling between the second gate and the second node is less than the specified value. (3) The solid-state imaging device according to (2), wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a first capacitance ratio obtained by dividing the difference between the first parasitic capacitance and the second parasitic capacitance by the signal holding capacitance is less than 1 / 1000. (4) The solid-state imaging device according to (3), wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and a difference between a maximum value and a minimum value of the first capacitance ratio of each of the pixels is less than 1 / 1000. (5) The solid-state imaging element according to any one of (1) to (4), wherein a difference between a third parasitic capacitance caused by capacitive coupling between the first gate and the third node and a fourth parasitic capacitance caused by capacitive coupling between the second gate and the fourth node is less than the specified value.(6) The solid-state imaging device according to (5) above, wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a second capacitance ratio obtained by dividing the difference between the third parasitic capacitance and the fourth parasitic capacitance by the signal holding capacitance is less than 1 / 1000. (7) The solid-state imaging device according to (6) above, wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and a difference between the maximum and minimum values ​​of the second capacitance ratios of each of the pixels is less than 1 / 1000. (8) The solid-state imaging device according to any of (1) to (7), further comprising a third gate that resets charges accumulated in the second node, the third node, and the fourth node, and wherein a difference between a fifth parasitic capacitance caused by capacitive coupling occurring between the third gate and the second node and a sixth parasitic capacitance caused by capacitive coupling occurring between the third gate and the second node is less than the specified value. (9) The solid-state imaging device according to (8), wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a third capacitance ratio obtained by dividing a difference between the fifth parasitic capacitance and the sixth parasitic capacitance by the signal holding capacitance is less than 1 / 1000. (10) The solid-state imaging device according to (9), wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and a difference between a maximum value and a minimum value of the third capacitance ratio of each of the pixels is less than 1 / 1000. (11) The solid-state imaging device according to (10), wherein a wiring layout is such that, in a wiring layer in which a first control signal line that supplies a control signal to the third gate is provided, other wiring is arranged between the first control signal line and wiring connected to the third node and the fourth node. (12) A solid-state imaging device according to any one of (1) to (11) above, further comprising a fourth gate that selects the pixel to output the pixel signal generated by the amplification gate, wherein a difference between a seventh parasitic capacitance caused by capacitive coupling between the fourth gate and the second node and an eighth parasitic capacitance caused by capacitive coupling between the fourth gate and the second node is less than the specified value.(13) The solid-state imaging device according to (12), wherein the first capacitor and the second capacitor have approximately the same signal holding capacitance, and a fourth capacitance ratio obtained by dividing the difference between the seventh parasitic capacitance and the seventh parasitic capacitance by the signal holding capacitance is less than 1 / 1000. (14) The solid-state imaging device according to (13), wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and a difference between the maximum and minimum values ​​of the fourth capacitance ratios of each of the pixels is less than 1 / 1000. (15) The solid-state imaging device according to (14), wherein, in a wiring layer in which a second control signal line that supplies a control signal to the fourth gate is provided, other wiring is arranged between the second control signal line and wiring connected to the third node and the fourth node. (16) The solid-state imaging element according to (8), wherein in a wiring layer in which a third control signal line supplying a control signal to the first gate, a fourth control signal line supplying a control signal to the second gate, and a fifth control signal line and a sixth control signal line supplying a control signal to the third gate are provided extending in the same direction, the third control signal line and the fourth control signal line are line-symmetrical with respect to the direction, and the fifth control signal line and the sixth control signal line are line-symmetrical with respect to the direction. (17) The solid-state imaging element according to (16), wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a fifth capacitance ratio obtained by dividing the difference between an eighth parasitic capacitance caused by capacitive coupling between the third control signal line and the fifth control signal line and a ninth parasitic capacitance caused by capacitive coupling between the fourth control signal line and the sixth control signal line by the signal holding capacitance is less than 1 / 1000. (18) The solid-state imaging element according to (17), wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and a difference between a total value of the eighth parasitic capacitance of each of the pixels and a total value of the ninth parasitic capacitance of each of the pixels is less than 1 / 1000.(19) The solid-state imaging device according to (16), wherein a pixel sharing structure is used in which a plurality of the pixels share the second node in a 2×2 array, the first gate and the second gate have a translationally symmetric relationship, and a first current source gate and a second current source gate that supply a constant current of the first node and are cascode-connected have an axisymmetric relationship. (20) The solid-state imaging device according to (19), wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a sixth capacitance ratio obtained by dividing the difference between a sum of tenth parasitic capacitances caused by capacitive coupling between the first gate and the first current source gate in each of the pixels and a sum of eleventh parasitic capacitances caused by capacitive coupling between the second gate and the first current source gate in each of the pixels by the signal holding capacitance is less than 1 / 1000. (21) A solid-state imaging device according to any one of (1) to (20) above, wherein a pixel sharing structure is used in which a plurality of the pixels share the second nodes in a 2x2 array, the first nodes of the pixels adjacent in the vertical direction are line-symmetrical, and the first capacitor and the second capacitor of each of the pixels are arranged between the first nodes. (22) The solid-state imaging element according to (21), wherein the first capacitor and the second capacitor have approximately the same signal holding capacitance, a sixth capacitance ratio obtained by dividing a twelfth parasitic capacitance due to capacitive coupling occurring between the first node of one of the vertically adjacent pixels and the first capacitor of the other of the vertically adjacent pixels by the signal holding capacitance is less than 1 / 1000, and a seventh capacitance ratio obtained by dividing a thirteenth parasitic capacitance due to capacitive coupling occurring between the first node of one of the vertically adjacent pixels and the second capacitor of the other of the vertically adjacent pixels by the signal holding capacitance is less than 1 / 1000.(23) An electronic device comprising a pixel having: a pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding a voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding a voltage of a pixel signal of a pixel signal level output from the pixel circuit; an amplifying gate that generates a pixel signal according to a charge accumulated in the second node connected to a gate electrode; and a sample and hold circuit having at least: a third node that is a connection point with the other end of the first capacitor, a first gate that connects the second node, and a fourth node that is a connection point with the other end of the second capacitor, and a second gate that connects the second node; wherein a difference between parasitic capacitances caused by capacitive coupling generated between the two nodes and two gates of the sample and hold circuit is less than a specified value.

[0189] It should be noted that the present embodiment is not limited to the above-described embodiment, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0190] REFERENCE SIGNS LIST 11 imaging device, 12 optical system, 13 solid-state imaging element, 14 imaging control circuit, 15 signal processing circuit, 16 monitor, 17 memory, 21 pixel array section, 22 timing control circuit, 23 vertical scanning circuit, 24 DAC, 25 load MOS circuit block, 26 column signal processing circuit, 31 pixel, 41 pixel circuit, 42 sample and hold circuit, 43 vertical signal line, 44 constant current source, 51 photoelectric conversion section, 52 transfer gate, 53 FD gate, 54 reset gate, 55 capacitor, 56 amplification gate, 57 switch gate, 61 capacitor, 62 capacitor, 63 SR gate, 64 SD gate, 64, 65 RB gate, 66 amplification gate, 67 selection gate, 68 constant current source

Claims

1. A solid-state imaging device comprising a pixel having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding the voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding the voltage of a pixel signal of a pixel signal level output from the pixel circuit; an amplifier gate that generates a pixel signal according to the charge accumulated at the second node connected to the gate electrode; and a sample and hold circuit having at least a third node that is a connection point with the other end of the first capacitor, a first gate that connects the second node, and a fourth node that is a connection point with the other end of the second capacitor, and a second gate that connects the second node, wherein the difference between the parasitic capacitances caused by capacitive coupling between the two nodes and two gates of the sample and hold circuit is less than a specified value.

2. The solid-state imaging device according to claim 1, wherein the difference between a first parasitic capacitance due to capacitive coupling occurring between the first gate and the second node and a second parasitic capacitance due to capacitive coupling occurring between the second gate and the second node is less than the specified value.

3. The solid-state imaging device according to claim 2, wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a first capacitance ratio obtained by dividing the difference between the first parasitic capacitance and the second parasitic capacitance by the signal holding capacitance is less than 1 / 1000.

4. The solid-state imaging device according to claim 3, wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and the difference between the maximum value and the minimum value of the first capacitance ratio of each of the pixels is less than 1 / 1000.

5. The solid-state imaging device according to claim 1, wherein the difference between a third parasitic capacitance caused by capacitive coupling between the first gate and the third node and a fourth parasitic capacitance caused by capacitive coupling between the second gate and the fourth node is less than the specified value.

6. The solid-state imaging device according to claim 5, wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a second capacitance ratio obtained by dividing the difference between the third parasitic capacitance and the fourth parasitic capacitance by the signal holding capacitance is less than 1 / 1000.

7. The solid-state imaging device according to claim 6, wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and the difference between the maximum value and the minimum value of the second capacitance ratio of each of the pixels is less than 1 / 1000.

8. The solid-state imaging device according to claim 1, further comprising a third gate that resets charges stored in the second node, the third node, and the fourth node, and wherein a difference between a fifth parasitic capacitance caused by capacitive coupling between the third gate and the second node and a sixth parasitic capacitance caused by capacitive coupling between the third gate and the second node is less than the specified value.

9. The solid-state imaging device according to claim 8, wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a third capacitance ratio obtained by dividing the difference between the fifth parasitic capacitance and the sixth parasitic capacitance by the signal holding capacitance is less than 1 / 1000.

10. The solid-state imaging device according to claim 9, wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and the difference between the maximum value and the minimum value of the third capacitance ratio of each of the pixels is less than 1 / 1000.

11. The solid-state imaging device according to claim 10, wherein in a wiring layer in which a first control signal line that supplies a control signal to the third gate is provided, other wiring is arranged between the first control signal line and wiring connected to the third node and the fourth node.

12. The solid-state imaging device according to claim 1, further comprising a fourth gate that selects the pixel to output the pixel signal generated by the amplification gate, wherein a difference between a seventh parasitic capacitance caused by capacitive coupling between the fourth gate and the second node and an eighth parasitic capacitance caused by capacitive coupling between the fourth gate and the second node is less than the specified value.

13. The solid-state imaging device according to claim 12, wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a fourth capacitance ratio obtained by dividing the difference between the seventh parasitic capacitance and the seventh parasitic capacitance by the signal holding capacitance is less than 1 / 1000.

14. The solid-state imaging device according to claim 13, wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and the difference between the maximum value and the minimum value of the fourth capacitance ratio of each of the pixels is less than 1 / 1000.

15. The solid-state imaging device according to claim 14, wherein in a wiring layer in which a second control signal line that supplies a control signal to the fourth gate is provided, other wiring is arranged between the second control signal line and wiring connected to the third node and the fourth node.

16. The solid-state imaging device according to claim 8, wherein in a wiring layer in which a third control signal line that supplies a control signal to the first gate, a fourth control signal line that supplies a control signal to the second gate, and a fifth control signal line and a sixth control signal line that supply a control signal to the third gate are provided extending in the same direction, the third control signal line and the fourth control signal line are line-symmetrical with respect to the direction, and the fifth control signal line and the sixth control signal line are line-symmetrical with respect to the direction.

17. The solid-state imaging device according to claim 16, wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a fifth capacitance ratio obtained by dividing the difference between an eighth parasitic capacitance due to capacitive coupling occurring between the third control signal line and the fifth control signal line and a ninth parasitic capacitance due to capacitive coupling occurring between the fourth control signal line and the sixth control signal line by the signal holding capacitance is less than 1 / 1000.

18. The solid-state imaging device according to claim 17, wherein a pixel sharing structure is used in which a plurality of the pixels share the second node, and the difference between the total value of the eighth parasitic capacitance of each of the pixels and the total value of the ninth parasitic capacitance of each of the pixels is less than 1 / 1000.

19. The solid-state imaging device according to claim 16, wherein a pixel sharing structure is used in which a plurality of the pixels are shared in a 2x2 array at the second node, the first gate and the second gate are in a translationally symmetric relationship, and a first current source gate and a second current source gate that supply a constant current to the first node and are cascode-connected are in an axisymmetric relationship.

20. The solid-state imaging device according to claim 19, wherein the first capacitor and the second capacitor have substantially the same signal holding capacitance, and a sixth capacitance ratio obtained by dividing the difference between the total value of a tenth parasitic capacitance due to capacitive coupling occurring between the first gate and the first current source gate in each of the pixels and the total value of an eleventh parasitic capacitance due to capacitive coupling occurring between the second gate and the first current source gate in each of the pixels by the signal holding capacitance is less than 1 / 1000.

21. The solid-state imaging device according to claim 1, wherein a pixel sharing structure is used in which a plurality of the pixels share the second nodes in a 2x2 array, the first nodes of the pixels adjacent in the vertical direction are line-symmetrical, and the first capacitor and the second capacitor of each of the pixels are arranged between the first nodes.

22. The solid-state imaging device according to claim 21, wherein the first capacitor and the second capacitor have approximately the same signal holding capacitance; a sixth capacitance ratio obtained by dividing a twelfth parasitic capacitance caused by capacitive coupling between the first node of one of the vertically adjacent pixels and the first capacitor of the other of the vertically adjacent pixels by the signal holding capacitance is less than 1 / 1000; and a seventh capacitance ratio obtained by dividing a thirteenth parasitic capacitance caused by capacitive coupling between the first node of one of the vertically adjacent pixels and the second capacitor of the other of the vertically adjacent pixels by the signal holding capacitance is less than 1 / 1000.

23. An electronic device comprising a pixel having: a pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; a first capacitor having one end connected to the first node and holding the voltage of a pixel signal of a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and holding the voltage of a pixel signal of a pixel signal level output from the pixel circuit; an amplifier gate that generates a pixel signal according to the charge accumulated at the second node connected to the gate electrode; and a sample and hold circuit having at least: a third node that is a connection point with the other end of the first capacitor, a first gate that connects the second node, and a fourth node that is a connection point with the other end of the second capacitor, and a second gate that connects the second node; wherein the difference between the parasitic capacitances caused by capacitive coupling between the two nodes and two gates of the sample and hold circuit is less than a specified value.

Images