Battery device, battery management system, and low power mode control method

Abstract

In this battery management system, when a communication failure occurs in a battery monitoring circuit that monitors a battery module, an interrupt is generated in a bridge circuit that transmits a signal between a processor and the battery monitoring circuit. A power circuit wakes up in response to an interrupt inputted to an enable pin and generates a power voltage. The processor operates on the basis of the power voltage, and disables the enable pin when an error flag is set in the case of a communication failure in the battery monitoring circuit.

Description

Battery device, battery management system, and low-power mode control method

[0001] Cross-citation with related applications

[0002] This application claims the benefit of priority from Republic of Korea Patent Application No. 10-2024-0041794, dated March 27, 2024, the entire contents of which are incorporated herein by reference.

[0003] The disclosure relates to a battery device, a battery management system and a low power mode control method.

[0004] Electric vehicles and hybrid vehicles are primarily powered by batteries, which power the motors. Research is actively underway on these vehicles as an alternative to addressing the pollution and energy issues associated with internal combustion engines. Furthermore, batteries are used in a variety of external devices beyond vehicles.

[0005] When external devices do not require battery power, such as when the vehicle is parked, the battery may enter a low-power mode. If the battery is in a low-power mode, unintended behavior of the battery management system may prevent the system from waking up from low-power mode and then returning to low-power mode.

[0006] Certain embodiments may provide a battery device, a battery management system, and a low power mode control method that can return to a low power mode even after being woken up due to an unintended action.

[0007] According to some embodiments, a battery management system for managing a battery module may be provided. The battery management system may include a battery monitoring circuit for monitoring the battery module, a power circuit for waking up in response to an interrupt input to a first enable pin and generating a power voltage, a processor for operating based on the power voltage and disabling the first enable pin when an error flag is set in the case of a communication failure in the battery monitoring circuit, and a bridge circuit for transmitting a signal between the processor and the battery monitoring circuit and generating the interrupt when the communication failure occurs in the battery monitoring circuit.

[0008] In some embodiments, a battery device may include a battery module and a battery management system. The battery management system may include a battery monitoring circuit for monitoring the battery module, a power circuit having a first enable pin, a processor, and a bridge circuit for transmitting signals between the processor and the battery monitoring circuit. When a communication failure occurs in the battery monitoring circuit while the battery management system is in a low power mode, the bridge circuit may generate an interrupt, the power circuit may wake up in response to the interrupt input to the first enable pin and generate a power voltage, and the processor may wake up based on the power voltage to recognize the communication failure, set an error flag indicating the communication failure, and request entry into the low power mode of the battery management system.

[0009] According to some embodiments, a method for controlling a low power mode of a battery management system for managing a battery module may be provided. The method for controlling the low power mode may include a step of generating an interrupt in response to a communication failure occurring when the battery management system is in a low power mode, a step of generating a power voltage in response to the interrupt, a step of setting an error flag indicating the communication failure, and a step of requesting entry of the battery management system into the low power mode.

[0010] FIG. 1 is a block diagram illustrating an example of a battery device according to some embodiments.

[0011] FIG. 2 is a flowchart illustrating an example of a low power mode control method of a battery management system according to some embodiments.

[0012] FIG. 3 is a block diagram illustrating an example of a battery device according to some embodiments.

[0013] FIG. 4 is a block diagram illustrating an example of a battery device according to some embodiments.

[0014] FIG. 5 is a flowchart illustrating an example of a low power mode control method of a battery management system according to some embodiments.

[0015] FIG. 6 is a block diagram illustrating an example of a battery device according to some embodiments.

[0016] Below, with reference to the attached drawings, embodiments of the present invention are described in detail so that those skilled in the art can easily implement the invention. However, the present invention can be implemented in various different forms and is not limited to the embodiments described herein. In addition, in the drawings, parts irrelevant to the description are omitted for clarity of description, and similar parts are designated with similar reference numerals throughout the specification.

[0017] When a component is said to be "connected" to another component, it should be understood that while it may be directly connected to that other component, there may be other components intervening. Conversely, when a component is said to be "directly connected" to another component, it should be understood that there are no other components intervening.

[0018] In the description below, expressions written in the singular may be interpreted as singular or plural, unless explicit expressions such as “one” or “single” are used.

[0019] In the flowchart described with reference to the drawing, the order of operations may be changed, several operations may be merged, some operations may be split, and certain operations may not be performed.

[0020] FIG. 1 is a block diagram illustrating an example of a battery device according to some embodiments.

[0021] Referring to FIG. 1, a battery device (100) may include a battery module (110) and a battery management system (BMS) (120). The battery device (100) may be connected to an external device. The external device may be, for example, a vehicle, an energy storage system (ESS), or an electronic device, and the vehicle may be, for example, a vehicle such as an electric vehicle, a hybrid vehicle, or a smart mobility device. Hereinafter, for convenience of explanation, the external device will be described as a vehicle.

[0022] In some embodiments, the battery device (100) may include a plurality of battery modules (110). The plurality of battery modules (110) may be connected in series or parallel. The battery module (110) may include a plurality of battery cells. The plurality of battery cells may be connected in series, for example.

[0023] A battery management system (120) is connected to a battery module (110) and can monitor and manage the battery module (110). The battery management system (120) may include a battery monitoring circuit (121), a bridge circuit (122), a processor (123), and a power circuit (124).

[0024] The battery monitoring circuit (121) is connected to the battery module (110) and can monitor the status (e.g., cell voltage) of the battery cells included in the battery module (110). In some embodiments, the battery monitoring circuit (121) may include a plurality of battery monitoring circuits (121) each corresponding to a plurality of battery modules (110). In some embodiments, one battery monitoring circuit (121) may correspond to two or more battery modules (110), or two or more battery monitoring circuits (121) may correspond to one battery module (110). For convenience, three battery modules (110) and three battery monitoring circuits (121) are illustrated in FIG. 1. In some embodiments, the battery monitoring circuit (121) may be provided as an integrated circuit (IC), and the battery monitoring circuit (121) provided as an integrated circuit is called a battery monitoring IC (BMIC).

[0025] In some embodiments, a plurality of battery monitoring circuits (121) may be connected in series to communicate. In some embodiments, a plurality of battery monitoring circuits (121) may be connected via a serial peripheral interface (SPI) bus to provide bidirectional communication between two battery monitoring circuits (121). In some embodiments, the SPI bus may be an isolated SPI (ISO-SPI) bus.

[0026] The bridge circuit (122) may translate a signal transmitted from the processor (123) and transmit it to the battery monitoring circuit (121), or translate a signal transmitted from the battery monitoring circuit (121) and transmit it to the processor (123). In some embodiments, the bridge circuit (122) may be connected to the battery monitoring circuit (121), for example, the first battery monitoring circuit (121) among a plurality of battery monitoring circuits (121), via an SPI bus. In some embodiments, the SPI bus may be an ISO-SPI (isolated SPI) bus. In some embodiments, the bridge circuit (122) may be provided as an IC. A bridge circuit (122) provided as an IC is called a bridge IC. When a loss of communication (LOC) occurs in the battery monitoring circuit (121) while the battery management system (120) is in sleep mode, the bridge circuit (122) can recognize the loss of communication and generate an interrupt (INTR) (e.g., an interrupt (INTR) having a high level).

[0027] The processor (123) can control the overall operation of the battery management system (120). The processor (123) is connected to the bridge circuit (122), and transmits a signal for controlling the battery monitoring circuit (121) to the bridge circuit (122) or receives monitoring information provided from the battery monitoring circuit (121) through the bridge circuit (122) to manage the status of the battery module (110) or the status of the battery cells of the battery module (110). The processor (123) may be equipped with a non-volatile memory (NMV) (123a). In some embodiments, the non-volatile memory (123a) may be built into the processor (123). In some embodiments, the non-volatile memory (123a) may be installed outside the processor (123) and connected to the processor (123) via a bus. In some embodiments, the processor (123) and the bridge circuit (122) may be connected via an SPI bus. In some embodiments, the processor (123) may be processing circuitry, for example, a microcontroller unit (MCU).

[0028] The power circuit (124) can supply a power voltage (e.g., 5 V) (VDD) to the processor (123). The power circuit (124) can convert a voltage supplied from an external battery (10), for example, an auxiliary battery (10) of an external device, into the power voltage (VDD). The power circuit (124) can enter a low power mode when the battery management system (120) enters a sleep mode. The power circuit (124) in the low power mode can wake up in response to an interrupt (INTR) from the bridge circuit (122). The power circuit (124) can also wake up in response to a signal (IG) for operating an external device (e.g., a vehicle start signal). In some embodiments, the processor (123) and the power circuit (124) can be connected via an SPI bus.

[0029] In some embodiments, the power circuit (124) may include a power management IC (PMIC). The PMIC (124) may include a power pin (VSUP) and enable pins (EN1, EN2) that receive a power voltage from the auxiliary battery (10). In some embodiments, the voltage of the auxiliary battery (10) may be supplied to the power pin (VSUP) through a diode (D1). A start signal (IG) may be input to the enable pin (EN1), and an interrupt (INTR) may be input to the enable pin (EN2). Accordingly, the PMIC (124) in the low power mode can wake up in response to a start signal (IG) (e.g., a start signal (IG) having a high level) input to the enable pin (EN1) or an interrupt (INTR) (e.g., an interrupt (INTR) having a high level) input to the enable pin (EN2) and convert the voltage input to the power pin (VSUP) into the power voltage (VDD) of the processor (123). Since the processor (123) operates using the power voltage (VDD) as a power source, the battery management system (120) can wake up from the sleep mode.

[0030] In some embodiments, a voltage (Vs) supplied from the auxiliary battery (10) (e.g., a voltage supplied through a diode (D1) from the auxiliary battery (10)) may be provided as the power voltage (Vs) of the bridge circuit (122).

[0031] In some embodiments, a unit (120a) including a battery monitoring circuit (121) may be referred to as a cell monitoring unit (CMU) or a high voltage (HV) unit, and a unit (120b) including a bridge circuit (122), a processor (123), and a power circuit (124) may be referred to as a battery monitoring unit (BMU) or a low voltage (LV) unit.

[0032] FIG. 2 is a flowchart illustrating an example of a low power mode control method of a battery management system according to some embodiments.

[0033] Referring to FIGS. 1 and 2, when a communication failure occurs in the battery monitoring circuit (121) (S210), the bridge circuit (122) can recognize the communication failure (S215). The bridge circuit (122) can generate an interrupt (INTR) in response to the communication failure (S220). The power circuit (124), for example, the PMIC (124), can wake up in response to the interrupt (INTR) and convert the voltage of the auxiliary battery (10) into a power voltage (VDD) (S225).

[0034] The processor (123) can wake up when the power voltage (VDD) is input from the PMIC (124) and operate using the power voltage (VDD) as a power source (S230). Accordingly, the processor (123) can recognize a communication failure of the battery monitoring circuit (121) and refer to the non-volatile memory (123a) mounted on the processor (123) (S235). If an error flag indicating a communication failure of the battery monitoring circuit (121) is not set in the non-volatile memory (123a), the processor (123) can set (i.e., store) an error flag in the non-volatile memory (123a) (S240). Since the battery management system (120) wakes up due to the communication failure, the processor (123) can request that the battery management system (120) enter sleep mode (S245). Accordingly, the PMIC (124) enters a low power mode, and since there is no supply of power voltage (VDD) from the PMIC (124), the processor (123) can also enter a low power mode (S250).

[0035] Meanwhile, if the communication failure of the battery monitoring circuit (121) continues even after the battery management system (120) enters sleep mode (i.e., low power mode), the bridge circuit (122) may generate an interrupt (INTR). Accordingly, the PMIC (124), which has entered the low power mode again, wakes up in response to the interrupt (INTR) (S255), and the processor (123) may also wake up as the power voltage (VDD) from the PMIC (124) is supplied (S260).

[0036] After waking up, the processor (123) may refer to the non-volatile memory (123a), and if an error flag is set in the non-volatile memory (123a), the processor (123) may disable the enable pin (EN2) of the PMIC (124) (S265). That is, if the error flag is set, the processor (123) may disable the reception of an interrupt (INTR) of the PMIC (124) (S265). In some embodiments, the processor (123) may disable the enable pin (EN2) of the PMIC (124) through SPI communication. Since the battery management system (120) has been woken up due to a communication failure, the processor (123) may request that the battery management system (120) enter a sleep mode (S270). Accordingly, the PMIC (124) enters the low power mode, and since there is no supply of power voltage (VDD) from the PMIC (124), the processor (123) can also enter the low power mode (S275). Meanwhile, even if the communication failure of the battery monitoring circuit (121) continues after the battery management system (120) enters the sleep mode, since the enable pin (EN2) of the PMIC (124) is disabled, the PMIC (124) can maintain the low power mode without being woken up by an interrupt (INTR) (S275).

[0037] As described above, if there is no error flag set in the non-volatile memory (123a), the battery management system may not be able to maintain the low power mode due to an unintended failure, such as a communication failure. However, according to some embodiments, if the error flag is set in the non-volatile memory (123a), the interrupt (INTR) reception of the power circuit (124) is disabled, so that the battery management system can maintain the low power mode.

[0038] FIG. 3 is a block diagram illustrating an example of a battery device according to some embodiments.

[0039] Referring to FIG. 3, the battery management system (320) of the battery device (300) may further include a transformer (125) connecting the HV unit (i.e., the first battery monitoring circuit (121)) (320b) and the LV unit (i.e., the bridge circuit (122)) (320a) compared to the battery management system (120) described with reference to FIG. 1. Accordingly, the bridge circuit (122) may receive monitoring information from the battery monitoring circuit (121) through the transformer (125).

[0040] FIG. 4 is a block diagram illustrating an example of a battery device according to some embodiments.

[0041] Referring to FIG. 4, a battery device (400) may include a battery module (410) and a battery management system (420). The battery device (400) may be connected to an external device. In some embodiments, the battery device (400) may include a plurality of battery modules (410).

[0042] A battery management system (420) is connected to a battery module (410) and can monitor and manage the battery module (410). The battery management system (420) may include a battery monitoring circuit (421), a bridge circuit (422), a processor (423), and a power circuit (424).

[0043] The battery module (410), battery monitoring circuit (421), bridge circuit (422), and processor (423) perform the same or similar operations as the battery module (110), battery monitoring circuit (121), bridge circuit (122), and processor (123) described with reference to FIG. 1, and therefore, a detailed description thereof is omitted.

[0044] The power circuit (424) can supply a power voltage (VDD) to the processor (423). The power circuit (424) can convert a voltage supplied from an external battery (40), for example, an auxiliary battery (40) of an external device, into the power voltage (VDD). The power circuit (424) can enter a low power mode as the battery management system (420) enters a sleep mode.

[0045] In some embodiments, the power circuit (424) may include a direct current (DC) / DC converter (424a) and a PMIC (424b). The DC / DC converter (424a) may receive voltage from the auxiliary battery (40) and convert the voltage of the auxiliary battery (40) to a predetermined voltage (e.g., 12 V). The DC / DC converter (424a) may be, for example, a buck / boost converter. The PMIC (424b) may receive a predetermined voltage from the DC / DC converter (424a) and convert the predetermined voltage to a power supply voltage (e.g., 5 V) (VDD).

[0046] The power circuit (424) in low power mode can wake up in response to an interrupt (INTR) from the bridge circuit (422). The power circuit (424) can also wake up in response to a signal (IG) that operates an external device (e.g., a vehicle start signal). In some embodiments, the processor (423) and the power circuit (424), for example, the PMIC (424b), can be connected via an SPI bus.

[0047] In some embodiments, the DC / DC converter (424a) may include a power pin (VN) for receiving the voltage of the auxiliary battery (40) and an enable pin (EN) for enabling the DC / DC converter (424a). In some embodiments, the power circuit (424) may further include a transistor (TR2) that turns on in response to a start signal (IG), a transistor (TR3) that turns on in response to an interrupt (INTR), and a transistor (TR1) that transfers the voltage of the auxiliary battery (40) to the power pin (VN) and enable pin (EN) of the DC / DC converter (424a) in response to turning on the transistor (TR2) or the transistor (TR3).

[0048] For example, the transistors (TR1, TR2, TR3) may be n-channel FETs (field effect transistors). In this case, the drains of the transistors (TR2, TR3) may be connected to the node (N1), and the sources of the transistors (TR2, TR3) may be connected to the ground. Resistors (R1, R2) may be connected in series between the input terminal to which the start signal (IG) is input and the ground terminal, and the contacts of the resistors (R1, R2) may be connected to the gate of the transistor (TR2). That is, the voltage of the start signal (IG) may be divided by the resistors (R1, R2) and input to the gate of the transistor (TR2). An interrupt (INTR) may be input to the gate of the transistor (TR3). Resistors (R3, R4) may be connected in series between the drain of the transistor (TR1) and the node (N1), and the contacts of the resistors (R3, R4) may be connected to the gate of the transistor (TR1). The voltage of the auxiliary battery (40) is supplied to the drain of the transistor (TR1), and the source of the transistor (TR1) can be connected to the power pin (VN) and the enable pin (EN). The source of the transistor (TR1) can be connected to the enable pin (EN) through a resistor (R5). In addition, the voltage of the auxiliary battery (40) can be supplied to the drain of the transistor (TR1) through a diode (D1).

[0049] Accordingly, when a start signal (IG) is input, the transistor (TR1) is turned on, and the voltage of the auxiliary battery (40) divided by the resistors (R3, R4) by the turning on of the transistor (TR1) is applied to the gate of the transistor (TR3), so that the transistor (TR3) can be turned on. Similarly, when an interrupt (INTR) is input, the transistor (TR1) is turned on, and the voltage of the auxiliary battery (40) divided by the resistors (R3, R4) by the turning on of the transistor (TR1) is applied to the gate of the transistor (TR3), so that the transistor (TR3) can be turned on. By the turning on of the transistor (TR3), the voltage of the auxiliary battery (40) is input to the enable pin (EN), so that the DC / DC converter (424a) wakes up and converts the voltage of the auxiliary battery (40) supplied to the power pin (VN) to a predetermined voltage.

[0050] In some embodiments, the PMIC (424b) may include a power pin (VSUP) and enable pins (EN1, EN2) that receive a predetermined voltage from the DC / DC converter (424a). A start signal (IG) may be input to the enable pin (EN1), and an interrupt (INTR) may be input to the enable pin (EN2). Accordingly, the PMIC (424) in the low power mode may wake up in response to the start signal (IG) input to the enable pin (EN1) or the interrupt (INTR) input to the enable pin (EN2) and convert the voltage input to the power pin (VSUP) into the power voltage (VDD) of the processor (423). Since the processor (423) operates using the power voltage (VDD) as a power source, the battery management system (420) may wake up from the sleep mode.

[0051] FIG. 5 is a flowchart illustrating an example of a low power mode control method of a battery management system according to some embodiments.

[0052] Referring to FIGS. 4 and 5, when a communication failure occurs in the battery monitoring circuit (421) (S510), the bridge circuit (422) can recognize the communication failure (S515). The bridge circuit (422) can generate an interrupt (INTR) in response to the communication failure (S520). Among the power circuits (424), the DC / DC converter (424a) wakes up in response to the interrupt (INTR) and can convert the voltage of the auxiliary battery (40) to a predetermined voltage (S525). The PMIC (424b) wakes up in response to the interrupt (INTR) and can convert the predetermined voltage supplied by the DC / DC converter (424a) to a power voltage (VDD) (S530).

[0053] The processor (423) can wake up when the power voltage (VDD) is input from the PMIC (424b) and operate using the power voltage (VDD) as a power source (S535). Accordingly, the processor (423) can recognize a communication failure of the battery monitoring circuit (421) and refer to the non-volatile memory (423a) mounted on the processor (423) (S540). If an error flag indicating a communication failure of the battery monitoring circuit (421) is not set in the non-volatile memory (423a), the processor (423) can set (i.e., store) the error flag in the non-volatile memory (423a) (S545). Since the battery management system (420) wakes up due to the communication failure, the processor (423) can request that the battery management system (420) enter sleep mode (S550). Accordingly, the PMIC (424b) enters a low power mode, and since there is no supply of power voltage (VDD) from the PMIC (424b), the processor (423) may also enter a low power mode (S555). In some embodiments, the DC / DC converter (424a) may also enter a low power mode (S555).

[0054] Meanwhile, if the communication failure of the battery monitoring circuit (421) continues even after the battery management system (420) enters the sleep mode (i.e., low power mode), the bridge circuit (422) may generate an interrupt (INTR). Accordingly, the PMIC (424b) that has entered the low power mode again wakes up in response to the interrupt (INTR) (S560), and the processor (423) may also wake up by the supply of the power voltage (VDD) from the PMIC (424b) (S565). In some embodiments, the DC / DC converter (424a) that has entered the low power mode may also wake up in response to the interrupt (INTR) (S560).

[0055] After waking up, the processor (423) may refer to the non-volatile memory (423a), and if an error flag is set in the non-volatile memory (423a), the processor (423) may disable the enable pin (EN2) of the PMIC (424b) (S570). That is, if the error flag is set, the processor (423) may disable the reception of an interrupt (INTR) of the PMIC (424b) (S570). In some embodiments, the processor (423) may disable the enable pin (EN2) of the PMIC (424b) through SPI communication. Since the battery management system (420) has woken up due to a communication failure, the processor (423) may request the battery management system (420) to enter a sleep mode (S575). Accordingly, the PMIC (424b) enters the low power mode, and since the power voltage (VDD) is not supplied from the PMIC (424b), the processor (423) can also enter the low power mode (S580). Meanwhile, even if the communication failure of the battery monitoring circuit (421) continues after the battery management system (420) enters the sleep mode, since the enable pin (EN2) of the PMIC (424b) is disabled, the PMIC (424b) can maintain the low power mode without being woken up by the interrupt (INTR) (S580).

[0056] As described above, if there is no error flag set in the non-volatile memory (423a), the battery management system may not be able to maintain the low power mode due to an unintended failure, such as a communication failure. However, according to some embodiments, if the error flag is set in the non-volatile memory (423a), the interrupt (INTR) reception of the power circuit (424) is disabled, so that the battery management system can maintain the low power mode.

[0057] FIG. 6 is a block diagram illustrating an example of a battery device according to some embodiments.

[0058] Referring to FIG. 6, the battery management system (620) of the battery device (600) may further include a transformer (625) connecting the HV unit (i.e., the first battery monitoring circuit (621)) and the LV unit (i.e., the bridge circuit (622)) compared to the battery management system (420) described with reference to FIG. 4. Accordingly, the bridge circuit (622) may receive monitoring information from the battery monitoring circuit (121) through the transformer (425).

[0059] Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims also fall within the scope of the present invention.

Claims

1. As a battery management system that manages battery modules, A battery monitoring circuit for monitoring the above battery module, A power circuit that wakes up in response to an interrupt input to the first enable pin and generates a power voltage; A processor that operates based on the power supply voltage and disables the first enable pin when an error flag is set in the battery monitoring circuit when there is a communication failure, and A bridge circuit that transmits a signal between the processor and the battery monitoring circuit and generates an interrupt when a communication failure occurs in the battery monitoring circuit. A battery management system including:

2. In paragraph 1, A battery management system, wherein the processor sets the error flag when the error flag is not set in the event of a communication failure.

3. In paragraph 1, A battery management system, wherein the processor includes non-volatile memory and stores the error flag in the non-volatile memory.

4. In paragraph 1, The above battery management system further includes non-volatile memory, The processor stores the error flag in the non-volatile memory. Battery management system.

5. In paragraph 1, The above processor In response to the above power voltage, it wakes up and recognizes the above communication failure, If the above error flag is not set, after setting the above error flag, a request is made to enter the low power mode of the battery management system, The above power circuit enters the low power mode upon request for entry into the low power mode. Battery management system.

6. In paragraph 5, If the power circuit wakes up again in response to the interrupt, The above processor In response to the above power voltage, it wakes up and recognizes the above communication failure, In response to the above error flag, disable the first enable pin, Requesting entry into low power mode of the above battery management system, The above power circuit enters the low power mode upon request for entry into the low power mode. Battery management system.

7. In paragraph 1, The above power circuit includes a power management integrated circuit that generates the power voltage based on the voltage from an external battery, The above power management integrated circuit A power pin to which voltage from the external battery is input, The above first enable pin, A second enable pin is included to which a ignition signal is input according to the ignition of an external device. Battery management system.

8. In paragraph 1, The above power circuit A DC / DC converter that converts a first voltage from an external battery into a second voltage, and A power management integrated circuit that generates the power supply voltage based on the second voltage, The above power management integrated circuit A first power pin to which the second voltage is input, The above first enable pin, and A second enable pin is included to which a start signal is input according to the start of an external device. Battery management system.

9. In paragraph 8, The power circuit further includes a first transistor that is turned on in response to the start signal or the interrupt to transmit the first voltage from the external battery, The above DC / DC converter A second power pin to which the first voltage is input, and Including an enable pin to which the first voltage is input Battery management system.

10. In paragraph 9, The above power circuit A second transistor that turns on in response to the above start signal, and Further comprising a third transistor that is turned on in response to the above interrupt, The first transistor is turned on in response to the turn-on of the second transistor or the turn-on of the third transistor. Battery management system.

11. Battery module, and Includes a battery management system, The above battery management system, A battery monitoring circuit for monitoring the above battery module, A power circuit having a first enable pin, processor, and A bridge circuit for transmitting signals between the processor and the battery monitoring circuit is included. When a communication failure occurs in the battery monitoring circuit while the battery management system is in low power mode, the bridge circuit generates an interrupt, The power circuit wakes up in response to the interrupt input to the first enable pin and generates a power voltage, The processor wakes up based on the power voltage, recognizes the communication failure, sets an error flag indicating the communication failure, and requests entry into a low power mode of the battery management system. Battery device.

12. In paragraph 11, After the battery management system enters the low power mode, if the communication failure continues in the battery monitoring circuit, the bridge circuit generates the interrupt, The power circuit wakes up in response to the interrupt input to the first enable pin and generates the power voltage, The processor wakes up based on the power voltage, recognizes the communication failure, disables the first enable pin if the error flag is set, and requests entry into the low power mode of the battery management system. Battery device.

13. In paragraph 11, A battery device, wherein the processor includes non-volatile memory and stores the error flag in the non-volatile memory.

14. In paragraph 11, The above battery management system further includes non-volatile memory, The processor stores the error flag in the non-volatile memory. Battery device.

15. In paragraph 11, The above power circuit includes a power management integrated circuit that generates the power voltage based on the voltage from an external battery, The above power management integrated circuit A power pin to which voltage from the external battery is input, The above first enable pin, and A second enable pin is included to which a ignition signal is input according to the ignition of an external device. Battery device.

16. In paragraph 11, The above power circuit A DC / DC converter that converts a first voltage from an external battery into a second voltage, and A power management integrated circuit that generates the power supply voltage based on the second voltage, The above power management integrated circuit A first power pin to which the first voltage is input, The above first enable pin, and A second enable pin is included to which a start signal is input according to the start of an external device. Battery device.

17. A method for controlling a low power mode of a battery management system that manages a battery module, A step of generating an interrupt in response to a communication failure that occurs when the above battery management system is in a low power mode; A step of generating a power voltage in response to the above interrupt, A step of setting an error flag indicating the above communication failure, and A step for requesting entry into the low power mode of the above battery management system A method for controlling a low power mode including:

18. In paragraph 17, After the battery management system enters the low power mode, if the communication failure continues in the battery monitoring circuit, a step of generating the interrupt; A step of generating the power voltage in response to the interrupt, a step of disabling reception of the interrupt if the above error flag is set, and A step for requesting entry into the low power mode of the above battery management system A method for controlling a low power mode further comprising:

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