Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment includes: a first insulation layer including a through-hole; a second insulating layer arranged on the top surface of the first insulating layer and filling a portion of the through-hole; and a third insulating layer arranged on the bottom surface of the first insulating layer and filling the remaining portion of the through-hole, wherein an interface at which the second insulating layer and the third insulating layer are in contact with each other is located between the top surface of the first insulating layer and the bottom surface of the first insulating layer.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards within limited-size semiconductor packages. However, because conventional semiconductor packages typically consist of a single semiconductor device, achieving desired performance is limited.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple circuit boards have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding their concept to semiconductor chiplets as the number of semiconductor elements and / or the size of each semiconductor element increases in line with the trend toward high integration, or as the functional parts of semiconductor elements are divided.

[0005] Meanwhile, the circuit board of the semiconductor package includes a cavity and a connecting member positioned within the cavity. The connecting member may electrically connect multiple semiconductor elements to each other or may function to transmit signals between multiple semiconductor elements. Alternatively, the connecting member may refer to a semiconductor element.

[0006] At this time, according to the prior art, the process of laminating an additional insulating layer and the process of forming an electrode portion are performed while the connecting member is embedded in the circuit board. At this time, as the process of laminating the insulating layer and the process of forming the electrode portion progresses, stress due to heat cycles such as shrinkage and / or expansion may be applied. In addition, continuous stress due to the stress may be applied to the connecting member, and thus, a problem of deterioration in the physical reliability and / or electrical reliability of the connecting member may occur. For example, the adhesion between the insulating layer and the connecting member may be reduced due to the stress, and a lifting phenomenon may occur at the interface between the insulating layer and the connecting member due to the reduced adhesion. In addition, when the interfacial lifting phenomenon occurs, a reliability problem may occur in which the connecting member is not stably electrically connected to the electrode portion, and this may cause a problem in which the connecting member does not operate stably.

[0007] The embodiment provides a circuit board and a semiconductor package including the same that can improve alignment between an electrode and a circuit layer of a connecting member.

[0008] Additionally, the embodiment provides a circuit board capable of improving electrical reliability and a semiconductor package including the same.

[0009] In addition, the embodiment provides a circuit board and a semiconductor package including the same that can efficiently distribute or alleviate stress according to a heat cycle.

[0010] Additionally, the embodiment provides a circuit board with improved warpage characteristics and a semiconductor package including the same.

[0011] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0012] A circuit board according to an embodiment includes a first insulating layer including a through hole; a second insulating layer disposed on an upper surface of the first insulating layer and filling a portion of the through hole; and a third insulating layer disposed on a lower surface of the first insulating layer and filling a remaining portion of the through hole, wherein an interface where the second insulating layer and the third insulating layer contact each other is located between an upper surface of the first insulating layer and a lower surface of the first insulating layer.

[0013] Additionally, the circuit board further includes a connecting member disposed within the through hole, and a side surface of the connecting member includes a first portion covered with the second insulating layer and a second portion covered with the third insulating layer.

[0014] Additionally, the connecting member includes a connecting electrode, and the interface does not overlap the connecting electrode along the horizontal direction.

[0015] Additionally, the interface is positioned closer to the upper surface of the connecting member where the connecting electrode is disposed than to the lower surface of the connecting member.

[0016] Additionally, the interface is a flat surface parallel to the upper or lower surface of the first insulating layer.

[0017] Additionally, the interface includes a convex surface or a concave surface with respect to the upper surface of the first insulating layer.

[0018] Additionally, the interface includes a concave surface provided on one side of the connecting member, and a convex surface provided on the other side of the connecting member, which is different from the one side.

[0019] Additionally, the width of the concave surface in the horizontal direction along the circumferential direction of the side surface of the connecting member and the width of the convex surface in the horizontal direction are different.

[0020] In addition, the circuit board further includes a circuit layer disposed on an upper surface of the first insulating layer, and the upper surface of the circuit layer and the upper surface of the connecting electrode are positioned on the same plane.

[0021] Additionally, the second insulating layer and the third insulating layer include an insulating material different from the insulating material of the first insulating layer.

[0022] Meanwhile, a circuit board according to an embodiment includes a first insulating layer including a through hole; a second insulating layer disposed on an upper surface of the first insulating layer and filling a portion of the through hole; and a third insulating layer disposed on a lower surface of the first insulating layer and filling a remaining portion of the through hole, wherein an interface where the second insulating layer and the third insulating layer contact each other includes at least one of a convex surface convex toward an upper surface of the first insulating layer and a concave surface concave with respect to an upper surface of the first insulating layer.

[0023] Additionally, the interface is located between the upper surface of the first insulating layer and the lower surface of the first insulating layer.

[0024] Additionally, the circuit board further includes a connecting member disposed within the through hole, and a side surface of the connecting member includes a first portion covered with the second insulating layer and a second portion covered with the third insulating layer.

[0025] Additionally, the interface includes a concave surface provided on one side of the connecting member, and a convex surface provided on the other side of the connecting member, which is different from the one side.

[0026] Additionally, the width of the concave surface in the horizontal direction along the circumferential direction of the side surface of the connecting member and the width of the convex surface in the horizontal direction are different.

[0027] Additionally, the second insulating layer and the third insulating layer include an insulating material different from the insulating material of the first insulating layer.

[0028] A circuit board according to an embodiment includes a first insulating layer having a through hole, a second insulating layer disposed on an upper surface of the first insulating layer, and a third insulating layer disposed on a lower surface of the first insulating layer. In addition, a portion of the through hole of the first insulating layer may be filled with the second insulating layer, and a remaining portion of the through hole of the first insulating layer may be filled with the third insulating layer. In this case, the second insulating layer and the third insulating layer may include an interface in direct contact with each other. In addition, the interface may be located within the through hole of the first insulating layer. For example, the interface is located between the upper surface of the first insulating layer and the lower surface of the first insulating layer. Preferably, the interface may be located lower than the upper surface of the first insulating layer and higher than the lower surface of the first insulating layer.

[0029] Through this, the embodiment can prevent the position of the connecting member placed within the through hole from being misaligned in the process of curing the second insulating layer and the third insulating layer by controlling the position of the interface where the second insulating layer and the third insulating layer are in direct contact with each other.

[0030] Specifically, the embodiment allows the interface where the second insulating layer and the third insulating layer contact each other to be located between the upper surface of the first insulating layer and the lower surface of the first insulating layer, thereby preventing the embodiment from overlapping the connection electrode of the connection member along the horizontal direction. Through this, the embodiment can prevent the stress applied in the process of hardening the second insulating layer and the third insulating layer from being transmitted to the connection member and the connection electrode of the connection member, thereby preventing the position of the connection member from being misaligned.

[0031] Specifically, the embodiment allows the above-described interface to be positioned within a through hole, thereby ensuring that the connecting member is positioned accurately within the through hole. This allows the embodiment to ensure that the connecting member is stably positioned within the through hole. Therefore, the embodiment allows the connecting member to operate more stably.

[0032] Furthermore, the embodiment can improve the alignment between the via electrode disposed on the connecting member and the connecting electrode of the connecting member, thereby enabling stable electrical connection between the connecting electrode of the connecting member and the via electrode. Accordingly, the embodiment can further improve the electrical reliability of the circuit board, and thereby, the embodiment can further improve the product characteristics of the circuit board and the semiconductor package including the circuit board. Accordingly, the embodiment can enable products such as servers to which the semiconductor package is applied to operate more stably.

[0033] Additionally, the interface where the second insulating layer and the third insulating layer contact each other may be located closer to either the upper or lower surface of the connecting member. For example, the interface may be located closer to the surface on which the connecting electrode is disposed among the upper and lower surfaces of the connecting member. That is, the connecting electrode is disposed on the upper surface of the connecting member, and thus the interface may be located closer to the upper surface of the connecting member than the lower surface of the connecting member.

[0034] That is, in order to fill the through hole of the first insulating layer, the embodiment may allow the third insulating layer to be laminated before the second insulating layer, thereby allowing the upper surface of the second circuit layer disposed on the upper surface of the first insulating layer and the upper surface of the connecting electrode of the connecting member to be positioned on the same plane. Through this, the interface may be closer to the upper surface of the connecting member where the connecting electrode is disposed than to the lower surface of the connecting member.

[0035] Accordingly, the embodiment can improve the flatness of the via electrode. For example, the via electrode includes a first portion that contacts the circuit layer, and a second portion that contacts the connection electrode of the connection member. In addition, the embodiment can allow the third insulating layer to be disposed before the second insulating layer in the manufacturing process of the circuit board, thereby allowing the interface to be closer to the upper surface of the connection member where the connection electrode is disposed than to the lower surface of the connection member, and further improving the flatness of the upper surface of the connection member and the upper surface of the circuit layer. Accordingly, the embodiment can allow the first portion and the second portion of the via electrode to have the same thickness, thereby improving the flatness of the first portion and the second portion of the second via electrode. Through this, the embodiment can further improve the electrical reliability with the connection member.

[0036] In addition, the second insulating layer and the third insulating layer may include an insulating material different from that of the first insulating layer. For example, the physical properties of the second insulating layer and the third insulating layer filling the through hole of the first insulating layer may be different from those of the first insulating layer. For example, the thermal expansion coefficients of the second insulating layer and the third insulating layer may be different from that of the first insulating layer. For example, the second insulating layer and the third insulating layer may include an insulating material that can more efficiently absorb the above-described stress compared to the first insulating layer. Through this, the embodiment can more efficiently absorb and / or alleviate the stress applied to the connecting member by using the second insulating layer and the third insulating layer. In addition, when the connecting member is provided as an organic bridge, the second insulating layer and the third insulating layer can alleviate damage such as cracks in the circuit board caused by the difference in the thermal expansion coefficients of the connecting member and the first insulating layer.

[0037] In particular, when the connecting member is an organic bridge, the second insulating layer and the third insulating layer can more stably protect the connecting member from stress caused by heat cycles such as shrinkage and / or expansion of the first insulating layer.

[0038] Furthermore, the second insulating layer and the third insulating layer can absorb stress applied to the circuit board, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package. For example, the embodiment provides the second insulating layer and the third insulating layer so as to surround the side of the connecting member within the through hole of the first insulating layer. At this time, the second insulating layer and the third insulating layer can have a thermal expansion coefficient matching function to alleviate the difference in thermal expansion coefficient between the first insulating layer and the connecting member. Through this, the embodiment can further significantly improve the electrical and / or mechanical reliability of the circuit board and the semiconductor package. Through this, the embodiment can enable the semiconductor device to operate stably, and can improve the operating characteristics of electronic products such as semiconductor packages and servers.

[0039] Furthermore, the embodiment can increase the contact area between the second insulating layer and the third insulating layer by making the interface where the second insulating layer and the third insulating layer contact each other concave or convex with respect to the upper surface of the lower build-up layer. Accordingly, the embodiment can further improve the adhesion between the second insulating layer and the third insulating layer, thereby more stably protecting the connecting member positioned within the through hole. Through this, the embodiment can further improve the physical reliability and / or electrical reliability of the circuit board.

[0040] Furthermore, the embodiment may serve to buffer thermal deformation such as expansion and / or contraction acting on the circuit board by making the interface where the second insulating layer and the third insulating layer come into contact concave or convex. For example, the concave or convex surface provided at the interface functions to increase the surface area of ​​the interface. For example, the concave or convex surface provided at the interface functions to increase the surface area of ​​the filling member provided as the second insulating layer and the third insulating layer between the inner wall of the through hole and the side surface of the connecting member. Through this, the embodiment may solve problems such as electrical open problems and / or cracks of the connecting member that may occur due to thermal stress acting on the circuit board. Through this, the embodiment may improve the mechanical reliability and / or electrical reliability of the circuit board.

[0041] For example, heat can be generated during electrical operation of semiconductor devices. The heat generated by the semiconductor devices can subject the circuit board to a heat cycle environment, such as expansion and / or contraction, and the resulting stress can act on the connecting member. If this stress is continuously transmitted to the connecting member, cracks may occur at the electrical joint between the connecting electrode and the circuit layers of the connecting member.

[0042] In contrast, the concave or convex surface provided at the interface between the second insulating layer and the third insulating layer of the embodiment can function to alleviate expansion and / or contraction of the circuit board due to heat cycles, and further, can absorb stress due to thermal deformation. Therefore, the embodiment can minimize the transfer of stress acting on the circuit board to the connecting member by utilizing the concave or convex surface provided at the interface.

[0043] Furthermore, the embodiment may include an interface where the second insulating layer and the third insulating layer come into contact with each other, including a concave surface and a convex surface. For example, the interface where the second insulating layer and the third insulating layer come into contact with each other may have a concave surface on one side of the connecting member, and a convex surface on the other side of the connecting member.

[0044] Through this, the embodiment can more efficiently alleviate and / or absorb stress acting on the circuit board by utilizing the concave and convex surfaces of the interface. This can prevent the circuit board and the semiconductor package including it from being significantly warped in a specific direction. This can enable the semiconductor device to operate more stably, and improve the operating characteristics of electronic products such as semiconductor packages and servers.

[0045] Specifically, the embodiment can adjust the position of the concave surface and the position of the convex surface of the interface in the circumferential direction of the connecting member, taking into account the direction of bending of the circuit board. Through this, the embodiment can further prevent bending of the circuit board by utilizing the concave and convex surfaces of the interface.

[0046] In addition, the embodiment may allow the concave surface and the convex surface to have different widths along the circumferential direction of the side surface of the connecting member. For example, the embodiment may adjust the width of the concave surface in the horizontal direction and the width of the convex surface in the horizontal direction in consideration of the direction in which the circuit board is bent. For example, the embodiment may allow the width of the convex surface in the horizontal direction to be larger than the width of the concave surface in the horizontal direction. Alternatively, the embodiment may allow the width of the concave surface in the horizontal direction to be larger than the width of the convex surface in the horizontal direction.

[0047] Through this, the embodiment can more efficiently alleviate and / or absorb stress acting on the circuit board by utilizing the concave and convex surfaces of the interface having different widths in the horizontal direction. Through this, the embodiment can prevent the circuit board and the semiconductor package including the circuit board from being significantly warped in a specific direction. Through this, the embodiment can enable more stable operation of the semiconductor device and improve the operating characteristics of electronic products such as semiconductor packages and servers.

[0048] Specifically, the embodiment can adjust the horizontal width of the concave surface of the interface and the horizontal width of the convex surface of the interface in the circumferential direction of the connecting member, taking into account the direction of the circuit board's bending. Through this, the embodiment can further prevent the circuit board from bending by utilizing the concave and convex surfaces of the interface having different widths in the horizontal direction.

[0049] FIG. 1a is a cross-sectional view illustrating a circuit board according to the first embodiment.

[0050] FIG. 1b is a cross-sectional view illustrating a circuit board according to the second embodiment.

[0051] Fig. 2 is a plan view illustrating the dummy pattern of Fig. 1a or Fig. 1b.

[0052] Figures 3a to 3c are cross-sectional views illustrating a circuit board according to a third embodiment.

[0053] Figures 4a to 4c are cross-sectional views illustrating a circuit board according to the fourth embodiment.

[0054] FIGS. 5A and 5B are cross-sectional views illustrating a circuit board according to the fifth embodiment.

[0055] FIGS. 6A and 6B are cross-sectional views illustrating a circuit board according to the sixth embodiment.

[0056] Fig. 7 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0057] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0058] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0059] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0060] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0061] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0062] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0063] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0064] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0065]

[0066] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0067]

[0068] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0069] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion for electrically connecting the semiconductor element and the circuit board, a resin portion for filling the space between the semiconductor element and the circuit board, and a molding portion for entirely enclosing the semiconductor element.

[0070] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0071] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0072]

[0073] FIG. 1a is a cross-sectional view illustrating a circuit board according to a first embodiment, FIG. 1b is a cross-sectional view illustrating a circuit board according to a second embodiment, FIG. 2 is a plan view illustrating a dummy pattern of FIG. 1a or FIG. 1b, FIGS. 3a to 3c are cross-sectional views illustrating a circuit board according to a third embodiment, FIGS. 4a to 4c are cross-sectional views illustrating a circuit board according to a fourth embodiment, FIGS. 5a and 5b are cross-sectional views illustrating a circuit board according to a fifth embodiment, FIGS. 6a and 6b are cross-sectional views illustrating a circuit board according to a sixth embodiment, and FIG. 7 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0074]

[0075] Hereinafter, a circuit board and a semiconductor package including the same according to an embodiment will be specifically described with reference to FIGS. 1A to 7.

[0076] Referring to FIGS. 1A and 1B, the circuit board (100) includes an inner build-up layer (101), an upper build-up layer (102), a lower build-up layer (103), an upper protective layer (104), a lower protective layer (105), and a bonding portion (160). In addition, the circuit board (100) includes a connecting member (170) embedded in the inner build-up layer (101). The connecting member (170) includes a connecting electrode (175), and the connecting electrode (175) of the connecting member (170) can be electrically connected to the upper build-up layer (102).

[0077] That is, the circuit board (100) includes a build-up structure, and the build-up structure includes an inner build-up layer (101), an upper build-up layer (102) disposed on one surface of the inner build-up layer (101), and a lower build-up layer (103) disposed on the other surface of the inner build-up layer (101).

[0078] Here, the meaning of being arranged on one side and the other side should not be understood as being limited to a configuration that is in direct contact with the one side and the other side, but should also be understood as having other configurations between the one side and the upper build-up layer (102), and between the other side and the lower build-up layer (103).

[0079] The inner build-up layer (101) includes a plurality of inner insulating layers (141, 143, 144). That is, the inner build-up layer (101) includes a first insulating layer (141), a second insulating layer (143) disposed on the upper surface of the first insulating layer (141), and a third insulating layer (144) disposed on the lower surface of the first insulating layer (141).

[0080] The first insulating layer (141) of the inner build-up layer (101) is composed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing material such as glass fiber, and has the function of improving the rigidity of the circuit board (100).

[0081] As the number of terminals of semiconductor devices arranged on a recent circuit board (100) increases, wiring becomes more complex, and accordingly, the thickness of the upper build-up layer (102) and the lower build-up layer (103) is increasing. Accordingly, the first insulating layer (141) of the inner build-up layer (101) of the present embodiment may have a thickness of 120 μm to 1200 μm in order to improve the overall rigidity of the circuit board (100) and prevent excessive signal loss. That is, the first insulating layer (141) may be referred to as a core insulating layer.

[0082] A via hole penetrating one surface and the other surface may be formed in the first insulating layer (141). The via hole in the first insulating layer (141) may be formed using a mechanical drill process or a CO2 laser, etc. When the via hole in the first insulating layer (141) is formed using a mechanical drill, the slope of the inner wall of the via hole may be perpendicular to the one surface and / or the other surface of the first insulating layer (141), and when the via hole in the first insulating layer (141) is formed using a CO2 laser, the inner wall of the via hole may have a plurality of concave portions and / or convex portions that are alternately stacked along the vertical direction. Here, the concave portion may mean a concave region that is concave in a direction away from the horizontal center of the via hole provided in the first insulating layer (141), and the convex portion may mean a region that protrudes and / or is convex toward the horizontal center of the via hole provided in the first insulating layer (141). And, the concave and convex portions may be alternately provided along the vertical direction of the inner wall forming the via hole of the first insulating layer (141). Here, being alternately provided may mean that the convex portion is provided between a plurality of concave portions, and that the concave portion is provided between a plurality of convex portions. In the case of a via hole formed using a mechanical drilling process, the path for transmitting an electrical signal may be shortened, which may be advantageous for electrical characteristics, but the process cost may increase. In addition, in the case of forming the concave and convex portions on the inner wall of the via hole using a CO2 laser, the thickness of the first via electrode (151) provided on the inner wall of the via hole can be thickened in a subsequent process, which may have the advantage of lowering the impedance and lowering the process cost. Accordingly, the processing method of the via hole provided in the inner build-up layer (101) may be freely selectively used depending on the application field of the semiconductor package.

[0083] A first via electrode (151) may be arranged within the via hole of the first insulating layer (141). The first via electrode (151) functions to electrically connect the upper build-up layer (102) and the lower build-up layer (103). Therefore, it is preferable that the first via electrode (151) densely fill the via hole for the function of resistance or heat dissipation. However, when the thickness of the first insulating layer (141) becomes thick as described above, it may become difficult for the first via electrode (151) to densely fill the via hole. For example, when attempting to fill the via hole provided in the thick first insulating layer (141) as described above according to the plating process, a void may be generated within the first via electrode (151). The void expands due to heat generated during the operation of the semiconductor package, which becomes a factor that lowers the mechanical reliability of the circuit board. Accordingly, a first via electrode (151) having a predetermined thickness is arranged on the inner wall of the via hole of the first insulating layer (141). The thickness of the first via electrode (151) refers to the thickness in the horizontal direction perpendicular thereto, not the thickness in the vertical direction in which the upper build-up layer (102), the first insulating layer (141), and the lower build-up layer (103) are laminated.

[0084] The thickness of the first via electrode (151) may be arranged to have a thickness of 5 μm to 20 μm to prevent a voltage drop that occurs as the thickness of the first insulating layer (141) increases and to prevent the occurrence of voids. It is difficult to densely fill the inside of the first via electrode (151) with metal through a process such as plating, resulting in the creation of empty spaces. The empty spaces may cause a problem in that it is difficult to evenly arrange the upper build-up layer (102) when stacking the upper build-up layer (102).

[0085] At this time, as shown in Fig. 1a, the insulating member (142) can be placed on the inner side of the first via electrode (151), thereby ensuring the flatness of the inner build-up layer (101). For example, the insulating member (142) can be placed in the via hole of the first insulating layer (141), and the first via electrode (151) can surround the side of the insulating member (142) and be placed between the inner wall of the via hole and the outer surface of the insulating member (142).

[0086] The upper surface of the insulating member (142) may be on the same plane as the upper surface of the first insulating layer (141), or may be arranged closer to the upper build-up layer (102) in the vertical direction than the upper surface of the first insulating layer (141). The lower surface of the insulating member (142) may be on the same plane as the lower surface of the first insulating layer (141), or may be arranged closer to the lower build-up layer (103) in the vertical direction than the lower surface of the first insulating layer (141). This can be freely designed to solve the flatness when laminating the upper build-up layer (102) and the lower build-up layer (103), or to secure the flatness of the circuit layers to be described later.

[0087] In addition, as shown in Fig. 1b, the insulating member (142) may be omitted. For example, the via hole provided in the first insulating layer (141) may be formed by performing a laser processing process on each of the upper and lower surfaces of the first insulating layer (141), and through this, the inner wall of the via hole provided in the first insulating layer (141) may have a plurality of slopes. For example, the via hole provided in the first insulating layer (141) may have an hourglass shape. In this case, the first via electrode (151) may densely fill the via hole, and thus the insulating member (142) may be omitted.

[0088] The first insulating layer (141) has a through hole (TH). The through hole (TH) can penetrate the upper and lower surfaces of the first insulating layer (141). The through hole (TH) provided in the first insulating layer (141) can provide a space for arranging a connecting member (170). For example, the through hole (TH) provided in the first insulating layer (141) can function as a cavity in which the connecting member (170) is arranged and embedded.

[0089] The second insulating layer (143) is disposed on the upper surface of the first insulating layer (141). The third insulating layer (144) is disposed on the lower surface of the first insulating layer (141). Each of the second insulating layer (143) and the third insulating layer (144) may be provided to fill the through hole (TH) of the first insulating layer (141).

[0090] In particular, a portion of the through hole (TH) of the first insulating layer (141) may be filled with the second insulating layer (143), and the remaining portion of the through hole (TH) of the first insulating layer (141) may be filled with the third insulating layer (144).

[0091] Accordingly, the first insulating layer (141) can be referred to as a core insulating layer, and the second insulating layer (143) and the third insulating layer (144) can be referred to as filling insulating layers that fill the through hole (TH) provided in the core insulating layer.

[0092] That is, the second insulating layer (143) is provided to fill a portion of the through hole (TH) of the first insulating layer (141), and thus may include a portion overlapping with the first insulating layer (141) along the horizontal direction.

[0093] Additionally, the third insulating layer (144) is provided to fill the remaining portion of the through hole (TH) of the first insulating layer (141), and thus may include a portion overlapping with the first insulating layer (141) in the horizontal direction.

[0094] The second insulating layer (143) and the third insulating layer (144) may include an interface (IS) that directly contacts each other. In this case, the interface (IS) may be a portion where the lower surface of the second insulating layer (143) and the upper surface of the third insulating layer (144) directly contact each other.

[0095] The interface (IS) is located within the through hole (TH) of the first insulating layer (141). For example, the interface (IS) is located between the upper surface of the first insulating layer (141) and the lower surface of the first insulating layer (141). Preferably, the interface (IS) may be located lower than the upper surface of the first insulating layer (141) and higher than the lower surface of the first insulating layer (141).

[0096] Through this, the embodiment can prevent the position of the connecting member (170) placed within the through hole (TH) from being distorted in the process of curing the second insulating layer (143) and the third insulating layer (144) by controlling the position of the interface (IS) where the second insulating layer (143) and the third insulating layer (144) are in direct contact with each other.

[0097] For example, according to the comparative example, the through hole (TH) provided in the first insulating layer (141) is entirely filled with the second insulating layer (143) or the third insulating layer (144). For example, at least one of the second insulating layer (143) and the third insulating layer (144) in the comparative example is not disposed within the through hole (TH) provided in the first insulating layer (141) and does not contact the first insulating layer (141) in the horizontal direction. Therefore, according to the comparative example, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) contact each other is located on the same plane as the upper or lower surface of the first insulating layer (141). That is, according to the comparative example, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) contact each other overlaps with the connecting electrode (175) provided in the connecting member (170) in the horizontal direction. Accordingly, in the comparative example, stress due to the heat cycle is applied in the process of curing the second insulating layer (143) and the third insulating layer (144), and the above-described stress can be directly transmitted to the connecting electrode (175) of the connecting member (170). As a result, in the comparative example, a problem may occur in which the position of the connecting member (170) is misaligned due to the above-described stress, or the position of the connecting electrode (175) of the connecting member (170) is misaligned.

[0098] In contrast, the embodiment is configured such that the interface (IS) where the second insulating layer (143) and the third insulating layer (144) contact each other is located between the upper surface of the first insulating layer (141) and the lower surface of the first insulating layer (141). Through this, the embodiment can efficiently distribute stress.

[0099] For example, the interface (IS) is misaligned along the horizontal direction with respect to the upper and lower surfaces of the first insulating layer (141), thereby dispersing the stress transmitted along the upper or lower surface of the first insulating layer (141).

[0100] Furthermore, the embodiment can prevent the interface (IS) where the second insulating layer (143) and the third insulating layer (144) contact each other from overlapping with the connection electrode (175) of the connection member (170) in the horizontal direction. Through this, the embodiment can prevent the stress applied in the process of hardening the second insulating layer (143) and the third insulating layer (144) from being transmitted to the connection member (170) and the connection electrode (175) of the connection member (170), thereby preventing the position of the connection member (170) from being distorted.

[0101] Specifically, the embodiment can ensure that the position of the interface (IS) described above is located within the through hole (TH), thereby ensuring that the connecting member (170) is positioned accurately within the through hole (TH). Through this, the embodiment can ensure that the connecting member (170) is stably positioned within the through hole (TH). Accordingly, the embodiment can enable the connecting member (170) to operate more stably.

[0102] Furthermore, the embodiment can improve the alignment between the second via electrode (152) disposed on the connecting member (170) and the connecting electrode (175) of the connecting member (170), thereby enabling the connecting electrode (175) of the connecting member (170) and the second via electrode (152) to be stably electrically connected to each other. Accordingly, the embodiment can further improve the electrical reliability of the circuit board, and through this, the embodiment can further improve the product characteristics of the circuit board and the semiconductor package including the same. Accordingly, the embodiment can enable products such as servers to which the semiconductor package is applied to operate more stably.

[0103] In addition, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact with each other may be positioned closer to one of the upper and lower surfaces of the connecting member (170). For example, the interface (IS) may be positioned closer to the surface on which the connecting electrode (175) is positioned among the upper and lower surfaces of the connecting member (170). That is, the connecting electrode (175) is positioned on the upper surface of the connecting member (170), and accordingly, the interface (IS) may be positioned closer to the upper surface of the connecting member (170) than to the lower surface of the connecting member (170).

[0104] That is, in order to fill the through hole (TH) of the first insulating layer (141), the embodiment can allow the third insulating layer (144) to be laminated earlier than the second insulating layer (143) in the manufacturing process of the circuit board, thereby allowing the upper surface of the second circuit layer (146) disposed on the upper surface of the first insulating layer (141) and the upper surface of the connection electrode (175) of the connection member (170) to be positioned on the same plane. Through this, the interface (IS) can be closer to the upper surface of the connection member (170) on which the connection electrode (175) is disposed than to the lower surface of the connection member (170).

[0105] Accordingly, the embodiment can improve the flatness of the second via electrode (152). For example, the second via electrode (152) includes a first portion that contacts the second circuit layer (146), and a second portion that contacts the connection electrode (175) of the connection member (170). In addition, the embodiment can allow the third insulating layer (144) to be disposed earlier than the second insulating layer (143) in the manufacturing process of the circuit board, thereby allowing the interface (IS) to be closer to the upper surface of the connection member (170) on which the connection electrode (175) is disposed than to the lower surface of the connection member (170), and further improving the flatness of the upper surface of the connection member (170) and the upper surface of the second circuit layer (146). Accordingly, the embodiment can make the first and second portions of the second via electrode (152) have the same thickness, thereby improving the flatness of the first and second portions of the second via electrode (152). Through this, the embodiment can further improve the electrical reliability with the connecting member (170).

[0106] In addition, the second insulating layer (143) and the third insulating layer (144) may include an insulating material different from that of the first insulating layer (141). For example, the physical properties of the second insulating layer (143) and the third insulating layer (144) filling the through hole (TH) of the first insulating layer (141) may be different from the physical properties of the first insulating layer (141). For example, the thermal expansion coefficients of the second insulating layer (143) and the third insulating layer (144) may be different from that of the first insulating layer (141). For example, the second insulating layer (143) and the third insulating layer (144) may include an insulating material that can more efficiently absorb the above-described stress compared to the first insulating layer (141). Through this, the embodiment can more efficiently absorb and / or alleviate stress applied to the connecting member (170) by using the second insulating layer (143) and the third insulating layer (144). In addition, when the connecting member (170) is provided as an organic bridge, the second insulating layer (143) and the third insulating layer (144) can alleviate damage such as cracks in the circuit board caused by the difference in thermal expansion coefficients between the connecting member (170) and the first insulating layer (141).

[0107] In particular, when the connecting member (170) is an organic bridge, the second insulating layer (143) and the third insulating layer (144) can more stably protect the connecting member (170) from stress caused by heat cycles such as shrinkage and / or expansion of the first insulating layer (141).

[0108] Furthermore, the second insulating layer (143) and the third insulating layer (144) can absorb stress applied to the circuit board (100), thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package. For example, the embodiment provides the second insulating layer (143) and the third insulating layer (144) to surround the side of the connecting member (170) within the through hole (TH) of the first insulating layer (141). At this time, the second insulating layer (143) and the third insulating layer (144) can have a thermal expansion coefficient matching function to alleviate the difference in thermal expansion coefficient between the first insulating layer (141) and the connecting member (170). Through this, the embodiment can further significantly improve the electrical and / or mechanical reliability of the circuit board and the semiconductor package. Through this, the embodiment can enable the semiconductor device to operate stably, and can improve the operating characteristics of electronic products such as semiconductor packages and servers.

[0109] Additionally, the inner build-up layer (101) may include a plurality of circuit layers (145, 146, 147, 148) and a plurality of via electrodes (151, 152, 153).

[0110] The plurality of circuit layers (145, 146, 147, 148) of the inner build-up layer (101) may include a first circuit layer (145) disposed on the upper surface of the second insulating layer (143), a second circuit layer (146) disposed on the upper surface of the first insulating layer (141), a third circuit layer (147) disposed on the lower surface of the first insulating layer (141), and a fourth circuit layer (148) disposed on the lower surface of the third insulating layer (144).

[0111] The plurality of circuit layers (145, 146, 147, 148) of the inner build-up layer (101) can have the function of electrically connecting with a connecting member (170) or electrically connecting with a semiconductor element placed on a circuit board (100).

[0112] Each of the plurality of circuit layers (145, 146, 147, 148) of the inner build-up layer (101) can be freely designed in consideration of impedance. In addition, via electrodes (151, 152, 153) can be arranged to connect each of the plurality of circuit layers (145, 146, 147, 148) of the inner build-up layer (101).

[0113] That is, the first via electrode (151) can be placed between the second circuit layer (146) and the third circuit layer (147), the second via electrode (152) can be placed between the first circuit layer (145) and the second circuit layer (146), and the third via electrode (153) can be placed between the third circuit layer (147) and the fourth circuit layer (148), thereby electrically connecting the first to fourth circuit layers (145, 146, 147, 148).

[0114] In addition, the inner build-up layer (101) may include a first dummy pattern (146S) and a second dummy pattern (147S). The first dummy pattern (146S) may be disposed on the upper surface of the first insulating layer (141). The first dummy pattern (146S) may be disposed along the circumferential direction of the upper end of the through hole (TH) on the upper surface of the first insulating layer (141). For example, as illustrated in FIG. 2, the first dummy pattern (146S) may have a closed loop shape in which an overlapping region along the vertical direction with the through hole (TH) is open. At this time, the inner wall of the first dummy pattern (146S) may be aligned along the vertical direction with the inner wall of the through hole (TH). Through this, the embodiment can easily control the position and size of the through hole (TH) within the first insulating layer (141) using the first dummy pattern (146S). Additionally, a second dummy pattern (147S) may be arranged on the lower surface of the first insulating layer (141) in correspondence with the first dummy pattern (146S).

[0115] The upper build-up layer (102) can be placed on the inner build-up layer (101).

[0116] The upper build-up layer (102) may include a plurality of circuit layers (114, 115, 116, 117), a plurality of upper insulating layers (106, 107, 108, 109), and a plurality of upper via electrodes (131, 132, 133, 134).

[0117] The plurality of circuit layers (114, 115, 116, 117) of the upper build-up layer (102) may include a first upper circuit layer (114) that is furthest from the inner build-up layer (101), a second upper circuit layer (115) that is arranged closer to the inner build-up layer (101) than the first upper circuit layer (114), a third upper circuit layer (116) that is arranged closer to the inner build-up layer (101) than the second upper circuit layer (115), and a fourth upper circuit layer (117) that is arranged closer to the inner build-up layer (101) than the third upper circuit layer (116). The first to fourth upper circuit layers (114, 115, 116, 117) may have a function of electrically connecting to a connecting member (170), or a function of electrically connecting to a semiconductor element arranged on a circuit board (100).

[0118] Each of the first to fourth upper circuit layers (114, 115, 116, 117) of the upper build-up layer (102) can be freely designed in consideration of impedance. In addition, a plurality of upper via electrodes (131, 132, 133, 134) can be arranged to connect each of the first to fourth upper circuit layers (114, 115, 116, 117) of the upper build-up layer (102).

[0119] The first upper via electrode (131) may be disposed between the first upper circuit layer (114) and the second upper circuit layer (115), the second upper via electrode (132) may be disposed between the second upper circuit layer (115) and the third upper circuit layer (116), the third upper via electrode (133) may be disposed between the third upper circuit layer (116) and the fourth upper circuit layer (117), and the fourth upper via electrode (134) may be disposed between the fourth upper circuit layer (117) and the first circuit layer (145).

[0120] The plurality of upper insulating layers (106, 107, 108, 109) of the upper build-up layer (102) may include a first upper insulating layer (106) that is farthest from the inner build-up layer (101) in a vertical direction, a second upper insulating layer (107) that is closer to the inner build-up layer (101) in a vertical direction than the first upper insulating layer (106), a third upper insulating layer (108) that is closer to the inner build-up layer (101) in a vertical direction than the second upper insulating layer (107), and a fourth upper insulating layer (109) that is closer to the inner build-up layer (101) in a vertical direction than the third upper insulating layer (108).

[0121] The first to fourth upper insulating layers (106, 107, 108, 109) are arranged to vertically insulate between the first to fourth upper circuit layers (114, 115, 116, 117) of the upper build-up layer (102) described above. For example, the first to fourth upper insulating layers (106, 107, 108, 109) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used. However, the embodiment is not limited thereto, and the first to fourth upper insulating layers (106, 107, 108, 109) may be formed of an insulating material having a reinforcing member such as glass fiber.

[0122] The upper protective layer (104) disposed on the upper build-up layer (102) can protect the first upper circuit layer (114) from external moisture or contaminants. In addition, when a semiconductor element is disposed on the circuit board (100) using a material such as solder, the upper protective layer (104) functions to prevent short circuits between solders due to its low wettability with the solder. The upper protective layer (104) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0123] A lower build-up layer (103) is arranged on the other side of the inner build-up layer (101). The lower build-up layer (103) includes a plurality of lower insulating layers (110, 111, 112, 113) and a plurality of lower circuit layers (118, 119, 120, 121). In addition, a lower protective layer (105) is arranged on the lower surface of the lower build-up layer (103).

[0124] The plurality of lower circuit layers (118, 119, 120, 121) of the lower build-up layer (103) may include a first lower circuit layer (118) that is most adjacent to the inner build-up layer (101) in the vertical direction, a second lower circuit layer (119) that is further away from the inner build-up layer (101) in the vertical direction than the first lower circuit layer (118), a third lower circuit layer (120) that is further away from the inner build-up layer (101) in the vertical direction than the second lower circuit layer (119), and a fourth lower circuit layer (121) that is further away from the inner build-up layer (101) in the vertical direction than the third lower circuit layer (120).

[0125] Lower via electrodes (135, 136, 137, 138) may be arranged to electrically connect the first to fourth lower circuit layers (118, 119, 120, 121) to each other. The first lower via electrode (135) may be arranged between the fourth circuit layer (148) and the first lower circuit layer (118), the second lower via electrode (136) may be arranged between the first lower circuit layer (118) and the second lower circuit layer (119), the third lower via electrode (137) may be arranged between the second lower circuit layer (119) and the third lower circuit layer (120), and the fourth lower via electrode (138) may be arranged between the third lower circuit layer (120) and the fourth lower circuit layer (121).

[0126] The plurality of lower insulating layers (110, 111, 112, 113) of the lower build-up layer (103) may include a first lower insulating layer (110) that is most adjacent to the inner build-up layer (101) in the vertical direction, a second lower insulating layer (111) arranged under the first lower insulating layer (110), a third lower insulating layer (112) arranged under the second lower insulating layer (111), and a fourth lower insulating layer (113) arranged under the third lower insulating layer (112). The first to fourth lower insulating layers (110, 111, 112, 113) are arranged to insulate the first to fourth lower circuit layers (118, 119, 120, 121) in the vertical direction. In addition, for example, the first to fourth lower insulating layers (110, 111, 112, 113) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) from Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.

[0127] The lower protective layer (105) disposed on the lower surface of the lower build-up layer (103) can protect the fourth lower circuit layer (121) from external moisture or contaminants. In addition, when a semiconductor element is disposed on the circuit board (100) using a material such as solder, the lower protective layer (105) functions to prevent short circuits between solders due to its low wettability with the solder. The lower protective layer (105) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0128] A bonding portion (160) is disposed on the upper build-up layer (102). The bonding portion (160) may be disposed on the first upper circuit layer (114) that overlaps the opening of the upper protection layer (104) in a vertical direction. For example, the first upper circuit layer (114) has a pad portion that overlaps the opening of the upper protection layer (104) in a vertical direction, and the bonding portion (160) may be disposed on the pad portion of the first upper circuit layer (114). As the density of terminals of semiconductor devices increases, a problem of solder short-circuiting between adjacent pad portions may occur in conventional solder bonding. Therefore, in order to reduce the amount of solder used as the density of terminals of semiconductor devices increases, the semiconductor devices and the circuit board may be bonded to each other through a thermal compression bonding method. When using thermal compression bonding, the circuit board may include a bonding portion (160) protruding on the upper protective layer (104) while penetrating the upper protective layer (104).

[0129] The bonding portion (160) may have a protrusion protruding on the upper protective layer (104) and a penetration portion penetrating the upper protective layer (104) and contacting the pad portion of the first upper circuit layer (114).

[0130] When bonding a circuit board (100) and a semiconductor element using a thermal compression bonding method, a crack may occur in the penetration portion of the bonding portion (160) due to the load generated thereby. Therefore, cracks can be prevented by placing a material having a higher elastic modulus than the elastic modulus of the first upper circuit layer (114) in the penetration portion of the bonding portion (160) adjacent to the first upper circuit layer (114). This material may be nickel (Ni), but a copper layer having a low grain density can be placed by electroless plating.

[0131] A connecting member (170) may be embedded within the inner build-up layer (101). The connecting member (170) may be placed within a through hole (TH) of the first insulating layer (141) of the inner build-up layer (101) and may be sealed with a second insulating layer (143) and a third insulating layer (144).

[0132] The connecting member (170) can function to electrically connect a plurality of semiconductor elements. Recently, as the number of signals that semiconductor elements must process increases, the size of semiconductor elements is trending toward larger areas, but this larger area of ​​semiconductor elements is causing problems in lowering the yield of semiconductor elements. Therefore, there is a trend to divide the pattern size or functional part of semiconductor elements, place chiplets on a circuit board, and embed connecting members (170) that have the function of electrically connecting them within the circuit board. However, the connecting member (170) is not limited thereto, and can also connect semiconductor elements with other functions, such as memory. In addition, the connecting member (170) may also mean a semiconductor element.

[0133]

[0134] Meanwhile, as described above, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact with each other is located between the upper surface of the first insulating layer (141) and the lower surface of the first insulating layer (141), and in particular, is located within the through hole (TH) provided in the first insulating layer (141). This can be achieved by a manufacturing process of a circuit board according to an embodiment as described below.

[0135] The manufacturing process of the circuit board of the embodiment is briefly described as follows.

[0136] First, the embodiment prepares a first insulating layer (141) and forms a through hole (TH) in the first insulating layer (141). Thereafter, the embodiment places a carrier board on the upper surface of the first insulating layer (141). Thereafter, the embodiment places a connecting member (170) in the through hole. Thereafter, the embodiment laminates a third insulating layer (144) on the lower surface of the first insulating layer (141) to fill a portion of the through hole (TH). At this time, the embodiment can adjust the thickness of the third insulating layer (144) so ​​that the third insulating layer (144) fills only a portion, not the entire, of the through hole (TH). Thereafter, the embodiment performs a process of curing the third insulating layer (144). Next, the embodiment removes the carrier board. Thereafter, the embodiment laminates a second insulating layer (143) on the first insulating layer (141) to fill the remaining portion of the through hole (TH). Thereafter, the embodiment can proceed with a process of simultaneously curing the second insulating layer (143) and the third insulating layer (144). Therefore, the embodiment can make the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact with each other be located between the upper surface of the first insulating layer (141) and the lower surface of the first insulating layer (141), while being located within the through hole (TH) provided in the first insulating layer (141) through the process described above.

[0137] Below, various embodiments of the shape of the interface according to the embodiment are described.

[0138] First, referring to FIGS. 1A and 1B, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact with each other may be flat. For example, the interface (IS) may be a flat surface parallel to the upper surface of the first insulating layer (141) or the lower surface of the first insulating layer (141).

[0139] In contrast, the embodiment can change the shape of the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact with each other by controlling the volume and / or curing conditions of the third insulating layer (144) that is preferentially laminated during the process of laminating the second insulating layer (143) and the third insulating layer (144).

[0140] In particular, referring to FIGS. 3a, 3b and 3c, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) contact each other may be concave.

[0141] For example, referring to FIG. 3a, the interface (IS) may be a concave surface. In this case, the interface (IS) may have a concave shape in which the height decreases from the inner wall of the through hole (TH) toward the side of the connecting member (170) and then increases again.

[0142] Additionally, referring to FIG. 3b, the interface (IS) may have a concave shape in which the height increases toward the side of the connecting member (170) from the inner wall of the through hole (TH).

[0143] Additionally, referring to FIG. 3c, the interface (IS) may have a concave shape with a height that decreases toward the side of the connecting member (170) from the inner wall of the through hole (TH).

[0144] Through this, the embodiment can increase the contact area between the second insulating layer (143) and the third insulating layer (144) by making the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact concave with respect to the upper surface of the lower build-up layer (103).

[0145] Accordingly, the embodiment can further improve the adhesion between the second insulating layer (143) and the third insulating layer (144), thereby more stably protecting the connecting member (170) positioned within the through hole (TH). Through this, the embodiment can further improve the physical reliability and / or electrical reliability of the circuit board.

[0146] Furthermore, the embodiment may serve to buffer thermal deformation such as expansion and / or contraction acting on the circuit board by making the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact concave. For example, the concave surface provided at the interface (IS) functions to increase the surface area of ​​the interface (IS). For example, the concave surface provided at the interface (IS) functions to increase the surface area of ​​the filling member provided as the second insulating layer (143) and the third insulating layer (144) between the inner wall of the through hole (TH) and the side surface of the connecting member (170). Through this, the embodiment may solve problems such as electrical open problems and / or cracks of the connecting member that may occur due to thermal stress acting on the circuit board. Through this, the embodiment may improve the mechanical reliability and / or electrical reliability of the circuit board.

[0147] For example, heat may be generated during electrical operation of a semiconductor device. The circuit board may be subjected to a heat cycle environment, such as expansion and / or contraction, due to the heat generated from the semiconductor device, and the resulting stress may act on the connecting member (170). In this case, if the stress is continuously transmitted to the connecting member (170), cracks may occur in the electrical connection portion between the connecting electrode (175) of the connecting member (170) and the circuit layers.

[0148] In contrast, the concave surface provided at the interface (IS) between the second insulating layer (143) and the third insulating layer (144) of the embodiment can function to alleviate expansion and / or contraction of the circuit board due to heat cycles, and further, can absorb stress due to thermal deformation. Therefore, the embodiment can minimize the transfer of stress acting on the circuit board to the connecting member by utilizing the concave surface provided at the interface (IS).

[0149] Also, referring to FIGS. 4a, 4b and 4c, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) contact each other may be convex.

[0150] For example, referring to FIG. 4a, the interface (IS) may be a convex surface. In this case, the interface (IS) may have a convex shape in which the height increases from the inner wall of the through hole (TH) toward the side of the connecting member (170) and then decreases again.

[0151] Additionally, referring to FIG. 4b, the interface (IS) may have a convex shape with a height that increases toward the side of the connecting member (170) from the inner wall of the through hole (TH).

[0152] Additionally, referring to FIG. 4c, the interface (IS) may have a convex shape with a height that decreases toward the side of the connecting member (170) from the inner wall of the through hole (TH).

[0153] Through this, the embodiment can increase the contact area between the second insulating layer (143) and the third insulating layer (144) by making the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact convex with respect to the upper surface of the lower build-up layer (103).

[0154] Accordingly, the embodiment can further improve the adhesion between the second insulating layer (143) and the third insulating layer (144), thereby more stably protecting the connecting member (170) positioned within the through hole (TH). Through this, the embodiment can further improve the physical reliability and / or electrical reliability of the circuit board.

[0155] Furthermore, the embodiment can serve to buffer thermal deformation such as expansion and / or contraction acting on the circuit board by making the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact convex.

[0156] For example, the convex surface provided at the interface (IS) functions to increase the surface area of ​​the interface (IS). For example, the convex surface provided at the interface (IS) functions to increase the surface area of ​​the filling member provided as the second insulating layer (143) and the third insulating layer (144) between the inner wall of the through hole (TH) and the side surface of the connecting member (170). Through this, the embodiment can solve problems such as electrical open problems and / or cracks of the connecting member that may occur due to thermal stress acting on the circuit board. Through this, the embodiment can improve the mechanical reliability and / or electrical reliability of the circuit board.

[0157] In addition, the convex surface provided at the interface (IS) of the second insulating layer (143) and the third insulating layer (144) of the embodiment can function to alleviate expansion and / or contraction of the circuit board due to heat cycles, and further, can absorb stress due to thermal deformation. Therefore, the embodiment can minimize the transfer of stress acting on the circuit board to the connecting member by utilizing the convex surface provided at the interface (IS).

[0158] In addition, according to the embodiments of FIGS. 5A and 5B, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact may include a concave surface (IS1) and a convex surface (IS2). For example, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact may have a concave surface (IS1) that is concave on one side of the connecting member (170) and a convex surface (IS2) that is convex on the other side of the connecting member (170) that is different from the one side.

[0159] That is, referring to Fig. 5b, the interface (IS) can be convex or concave in different directions along the circumferential direction of the connecting member (170). Fig. 5b is a drawing showing a plan view of the interface along the AA' direction of Fig. 5a.

[0160] Specifically, the interface (IS) is provided along the circumferential direction of the connecting member (170). In addition, the interface (IS) provided along the circumferential direction of the connecting member (170) may include a concave surface (IS1) and a convex surface (IS2).

[0161] Through this, the embodiment can more efficiently alleviate and / or absorb stress acting on the circuit board (100) by utilizing the concave surface (IS1) and the convex surface (IS2) of the interface (IS). Through this, the embodiment can prevent the circuit board and the semiconductor package including the circuit board from being significantly bent in a specific direction. Through this, the embodiment can enable the semiconductor element to operate more stably, and can improve the operating characteristics of the semiconductor package and electronic products such as servers.

[0162] Specifically, the embodiment can adjust the position of the concave surface (IS1) and the position of the convex surface (IS2) of the interface (IS) in the circumferential direction of the connecting member (170) in consideration of the bending direction of the circuit board (100). Through this, the embodiment can further prevent bending of the circuit board by using the concave surface (IS1) and the convex surface (IS2) of the interface (IS).

[0163] In addition, according to the embodiments of FIGS. 6A and 6B, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact may include a concave surface (IS1) and a convex surface (IS2). For example, the interface (IS) where the second insulating layer (143) and the third insulating layer (144) come into contact may have a concave surface (IS1) that is concave on one side of the connecting member (170) and a convex surface (IS2) that is convex on the other side of the connecting member (170) that is different from the one side.

[0164] That is, referring to Fig. 6b, the interface (IS) can be convex or concave in different directions along the circumferential direction of the connecting member (170). Fig. 6b is a drawing showing a plan view of the interface along the BB' direction of Fig. 6a.

[0165] Specifically, the interface (IS) is provided along the circumferential direction of the connecting member (170). In addition, the interface (IS) provided along the circumferential direction of the connecting member (170) may include a concave surface (IS1) and a convex surface (IS2).

[0166] At this time, the concave surface (IS1) and the convex surface (IS2) may have different widths in the horizontal direction. For example, the embodiment may adjust the width of the concave surface (IS1) in the horizontal direction and the width of the convex surface (IS2) in the horizontal direction in consideration of the direction in which the circuit board is bent. For example, the embodiment may make the width of the convex surface (IS2) in the horizontal direction larger than the width of the concave surface (IS1) in the horizontal direction. Alternatively, the embodiment may make the width of the concave surface (IS1) in the horizontal direction larger than the width of the convex surface (IS2) in the horizontal direction.

[0167] Through this, the embodiment can more efficiently alleviate and / or absorb stress acting on the circuit board (100) by utilizing the concave surface (IS1) and the convex surface (IS2) of the interface (IS) having different widths in the horizontal direction. Through this, the embodiment can prevent the circuit board and the semiconductor package including the same from being significantly bent in a specific direction. Through this, the embodiment can enable the semiconductor element to operate more stably, and can improve the operating characteristics of the semiconductor package and electronic products such as servers.

[0168] Specifically, the embodiment can adjust the width of the concave surface (IS1) of the interface (IS) in the horizontal direction and the width of the convex surface (IS2) in the horizontal direction in the circumferential direction of the connecting member (170) in consideration of the direction in which the circuit board (100) is bent. Through this, the embodiment can further prevent bending of the circuit board by using the concave surface (IS1) and the convex surface (IS2) of the interface (IS) having different widths in the horizontal direction.

[0169] Also, referring to FIG. 7, a semiconductor element (220, 230) may be placed on a circuit board according to an embodiment. That is, the semiconductor package may include a connecting member (210) placed on a bonding portion (160) of the circuit board (100).

[0170] In addition, a first semiconductor element (220) and a second semiconductor element (230) spaced apart in the horizontal direction can be arranged on the connecting member (210).

[0171] The terminal (225) of the first semiconductor element (220) and the terminal of the second semiconductor element (230) can be electrically connected to the circuit board (100) through the connecting member (210).

[0172]

[0173] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying power to semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0174] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0175] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0176] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulating layer including through hole; A second insulating layer disposed on the upper surface of the first insulating layer and filling a portion of the through hole; and A third insulating layer is disposed on the lower surface of the first insulating layer and fills the remaining portion of the through hole, A circuit board, wherein the interface where the second insulating layer and the third insulating layer contact each other is located between the upper surface of the first insulating layer and the lower surface of the first insulating layer.

2. In paragraph 1, Further comprising a connecting member disposed within the above through hole, A circuit board, wherein the side of the above connecting member includes a first portion covered with the second insulating layer and a second portion covered with the third insulating layer.

3. In paragraph 2, The above connecting member includes a connecting electrode, A circuit board wherein the above interface does not overlap the above connecting electrode along the horizontal direction.

4. In paragraph 3, A circuit board, wherein the interface is located closer to the upper surface of the connecting member on which the connecting electrode is arranged than to the lower surface of the connecting member.

5. In paragraph 1, A circuit board, wherein the above interface is a flat surface parallel to the upper or lower surface of the first insulating layer.

6. In paragraph 2, A circuit board, wherein the interface includes a convex surface or a concave surface with respect to the upper surface of the first insulating layer.

7. In paragraph 6, A circuit board, wherein the interface includes a concave surface provided on one side of the connecting member and a convex surface provided on the other side of the connecting member.

8. In paragraph 7, A circuit board, wherein the horizontal width of the concave surface along the circumferential direction of the side surface of the connecting member and the horizontal width of the convex surface are different.

9. In paragraph 3, Further comprising a circuit layer disposed on the upper surface of the first insulating layer, A circuit board in which the upper surface of the circuit layer and the upper surface of the connection electrode are located on the same plane.

10. In paragraph 1, A circuit board, wherein the second insulating layer and the third insulating layer include an insulating material different from the insulating material of the first insulating layer.

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