Data-aware neural network configuration technology in deep learning-based object detection systems

Abstract

Systems, apparatuses and methods may provide for technology that extracts distribution statistics of one or more object characteristics from training data, generates bounding box proposals based on the distribution statistics, and configures a neural network model based on the bounding box proposals.

Description

[0001] DATA -A WARE NEURAL NETWORK CONFIGURATION TECHNOLOGY IN DEEP LEARNING-BASED OBJECT DETECTION SYSTEMS

[0002] BACKGROUND

[0003] Computer vision tasks such as object detection may involve the use of deep learning (DL) models. DL models deploy neural networks that operate in accordance with various hyperparameters, which are variables that determine the structure of the neural network as well as how the network is trained. One type of hyperparameter is the configuration of bounding boxes used to detect objects. Current solutions to configuring bounding boxes (e.g., region-based convolutional neural network / R-CNN, single shot detector / SSD, you only look once / YOLO, fully convolutional one stage / FCOS, adaptive training sample selection / ATSS, manual hyperparameter tuning, grid search, random search and / or ensemble techniques) may be complex and result in relatively slow training, inference and post-processing (e.g., non-maxima suppression) operations.

[0004] BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various advantages of the embodiments will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:

[0006] FIG. 1 is an illustration of an example of an object detector according to an embodiment;

[0007] FIG. 2 is an illustration of an example of a model training pipeline according to an embodiment;

[0008] FIG. 3 A is a flowchart of an example of a method of managing hyperparameters for a neural network model according to an embodiment;

[0009] FIG. 3B is a flowchart of an example of a method of conducting inference operations according to an embodiment;

[0010] FIG. 4 is an illustration of an example of distribution statistics and corresponding bounding boxes for a fish dataset according to an embodiment;

[0011] FIG. 5 is an illustration of an example of distribution statistics and corresponding bounding boxes for a pothole dataset according to an embodiment;

[0012] FIG. 6 is a block diagram of an example of a performance-enhanced computing system according to an embodiment; FIG. 7 is an illustration of an example of a semiconductor package apparatus according to an embodiment;

[0013] FIG. 8 is a block diagram of an example of a processor according to an embodiment; and

[0014] FIG. 9 is a block diagram of an example of a multi -processor based computing system according to an embodiment.

[0015] DETAILED DESCRIPTION

[0016] The ability to automatically determine the appropriate hyperparameters for a deep learning (DL) model configuration has a direct relationship to model performance. These hyperparameters can encompass critical aspects of model behavior, such as the aspect ratio and scale of bounding box proposals during both training and inference. In the context of object detection, accurately identifying and delineating objects in images depends on the precise configuration of bounding boxes. The technology described herein derives these model configuration parameters from data statistics, which ensures that the model can efficiently adapt to a wide range of object sizes and shapes. More particularly, embodiments create a data statistics- aware model configuration system that can efficiently adapt model parameters to accommodate diverse object attributes.

[0017] Using data statistics to intelligently adjust model configuration parameters enables the DL model to accurately and robustly detect objects of various sizes, shapes, and orientations in images. This approach not only enhances the accuracy and efficiency of object detection but also significantly reduces the need for manual parameter tuning. As a result, the technology described herein streamlines the model training process, making training more accessible and adaptable to real- world applications.

[0018] Turning now to FIG. 1, an object detector 10 is shown in which an image 12 is input to a convolutional neural network (CNN) 14, which downsamples the image 12 to various resolutions (e.g., lx, 2x, 4x). The CNN 14 uses k anchor boxes 16 within a sliding window 18 across a convolution (“conv”) feature map 20, wherein the anchor boxes 16 are bounding boxes around anchors, with each anchor being located at a pixel of the convolution feature map 20. The CNN 14 determines data for an intermediate layer 22, scores for a classification (“cis”) layer 24 and coordinates for a regression (“reg”) layer 26. In the illustrated example, the anchor boxes 16 are automatically generated based on distribution statistics (e.g., mean, median, variance, etc.) of one or more object characteristics (e.g., object size, aspect ratio and / or location). As will be discussed in greater detail, generating the anchor boxes 16 based on the distribution statistics is less complex than conventional solutions and results in relatively faster training, inference and post-processing operations. For example, use of the distribution statistics can eliminate the occurrence of redundant bounding boxes for a single object, which enables non-maxima suppression to be bypassed during post-processing. Accordingly, latency is reduced (e.g., enhancing performance).

[0019] Previous solutions often fall short in terms of adaptability to varying data statistics and efficient automatic model configuration. The technology described herein overcomes these limitations by providing a data statistics-aware model configuration system that dynamically adjusts model parameters based on real-time analysis of data statistics during training (e.g., offering a more accurate and flexible approach).

[0020] For example, FIG. 2 shows a training pipeline 30 (30a-30d) that includes a data ingestion stage 30a, a data analysis stage 30b, a model configuration stage 30c and a model training stage 30d. Thus, embodiments propose a data-aware model configuration procedure to training a model as well as deploying the trained model. The technology described herein considers not only the original architecture characteristics (e.g., receptive field size per feature pyramid and grid anchor generation), but also data statistics such as object size over image resolution or object aspect ratio. By solving the proposed optimization problem, the technology described herein selects the model configurations from data statistics.

[0021] By appropriately selecting model configurations that align with precalculated data statistics, the model can be trained more effectively, facilitating faster convergence during the training process. In addition, this approach naturally reduces the number of predictions in a cost-efficient manner during inference. Moreover, this approach diminishes the reliance on post-processing techniques such as non-maxima suppression, which streamlines the analysis process and in turn makes analysis more straightforward.

[0022] Embodiments provide a direct relationship between data and the model during the model configuration (e.g., selection) phase 30c, which encompasses data statistics extraction, model configuration decision-making, and the final model selection. Additionally, the model configuration phase 30c is designed to return predefined bounding box proposals from a model, focusing on the structure rather than the context of an interesting object. Embodiments may also provide users with the capability to choose detailed model configurations, such as the number and depth of feature pyramids (e.g., feature maps at different scales) or anchor generators, or an autoconfiguration feature.

[0023] Data Statistics

[0024] Relative scale of object size to image size

[0025] The technology described herein may begin by extracting meaningful data statistics from an overall dataset (e.g., training data), a process closely tied to the model architecture. Conventional CNN architectures for object detection tasks may investigate the object size relative to image resolution. Traditionally, CNN models determine receptive field sizes (e.g., size of the region in the input that produces a feature) based on backbone architectures (e.g., portion of an object detector that extracts and encodes features from the input data), while the image is resized during the data augmentation phase. For example, when receptive field size of a model is 32, and the image is fed into the model with dimensions 1024x1024, the minimal object size for detection without noise pixels is 16x16. This result implies that objects smaller than 16x16 naturally contain noise pixels within a patch (e.g., subsection of an image), making such objects challenging to detect accurately. Consequently, the technology described herein gathers statistics on object size relative to image resolution. This approach may involve upscaling the image resolution for model input, using tiling augmentation, or opting for a different backbone architecture with a smaller receptive field size.

[0026] Object size (S)

[0027] While the ratio of object size to image resolution highlights the minimal detectable object size, the distribution of object sizes determines how large objects can potentially be detected. Representative values of the distribution statistics include the mean, median, and variance of the distribution. In cases of a relatively wide distribution, the technology described herein ensures that the representative values do not overlap. This condition is imposed due to the distinct coverage between feature pyramids (e.g., lower-level features are more attuned to smaller objects, whereas higher-level features possess a larger receptive field). Additionally, the technology described herein provides the flexibility to design different model configurations for each feature pyramid level.

[0028] Object aspect ratio (R) The distribution of object aspect ratio is the ratio of width to height. Most modem detectors define the aspect ratio to refine the shape of bounding box proposals. Typically, the set of aspect ratios is established as [1 / 2, 1, 2] to detect objects elongated either horizontally or vertically “in the wild.” In practical artificial intelligence (Al) applications, however, the norm is to encounter objects with stereotypical shapes, resulting in aspect ratios that follow heavy-tailed distributions. Accordingly, the technology described herein considers aspect ratio statistics in the architecture of a neural network model. Employing a fixed aspect ratio irrespective of data statistics may lead to the detection of abnormal objects (e.g., wider or longer than the specified aspect ratio) through post-processing methods such as non-maximum suppression. Such an approach, in turn, could potentially degrade model accuracy and compromise defect analysis capabilities.

[0029] Object location (P)

[0030] Certain industrial datasets exhibit positional bias. In transmission electron microscopy (TEM) images, for example, an intriguing foreground often adheres to a specific position with a discernible pattern. Consequently, an object detector as described herein is tailored to account for the locations of these interesting objects. By contrast, contemporary detectors commonly rely on a “greedy” anchor generator to create uniformly distributed bounding box proposals across an image. Each proposal is then processed by a head network (e.g., portion of an object detector that produces the final prediction based on the information extracted by the backbone and neck) to determine both existence and class probability, resulting in computational inefficiencies. To address this issue, the technology described herein includes an object position-aware anchor generator. This approach specifies the probability of generating a bounding box proposal for each grid in a feature map. Implementing this technique reduces the number of feedforward operations to the head network, which reduces both time and power consumption while maintaining model accuracy.

[0031] Model Configuration (Optimization Solution)

[0032] Considering a modern object detector, it can be assumed that an image is fed into a given feature extractor backbone f and extracted feature maps are transferred to multiple feature pyramids g. Lastly, a predefined anchor generator h creates bounding box proposals to detect foreground objects and proposals. Regardless of the head network, a similarity score can be computed between bounding box proposals from g and h and ground truth gttof an image i. Concretely, the object scale is dependent on both the feature pyramid g and the anchor generator h (see, FIG. 1), while the object ratio is only related to the anchor generator h. As a result, the optimization problem can be formulated as, max^iED^jEFPN.kEAGsim(hk(gj(f(imgi)>),gti>), (1) where D is the overall dataset, FPN is the feature pyramid network, and AG is the anchor generator.

[0033] Instead of solving the equation (1) directly, the technology described herein reformulates the problem with precomputed data statistics R, S, and P, which are denoted as object ratio, scale and position, respectively. Since an output of feature pyramids and an anchor generator can be calculated mathematically, the problem is reparameterized into a simple form by replacing h(g ( (•))) = m^n,iEDsim(tR S P(d),gti') where d is a dummy image with the same resolution. A dummy image may be used to take explicit object statistics (e.g., size, aspect ratio, and location) into consideration rather than implicit object context (e.g., appearance or shape). Embodiments shed more light on non-leamable hyperparameter optimization such as the use of FPN layers and the implementation of a custom anchor generator, etc. Image context and related features are learned through model parameters during training. Furthermore, the use of a dummy image can reduce the optimization time dramatically.

[0034] FIG. 3 A shows a method 40 of managing hyperparameters for a neural network model (e.g., DL and / or CNN model). The method 40 may be implemented in one or more modules as a plurality of logic instructions stored in a machine- or computer- readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in hardware, or any combination thereof. For example, hardware implementations may include configurable logic, fixed-functionality logic, or any combination thereof. Examples of configurable logic (e.g., configurable hardware) include suitably configured programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and general purpose microprocessors. Examples of fixed-functionality logic (e.g., fixed-functionality hardware) include suitably configured application specific integrated circuits (ASICs), combinational logic circuits, and sequential logic circuits. The configurable or fixed- functionality logic can be implemented with complementary metal oxide semiconductor (CMOS) logic circuits, transistor-transistor logic (TTL) logic circuits, or other circuits.

[0035] For example, computer program code to carry out operations shown in the method 40 can be written in any combination of one or more programming languages, including an object oriented programming language such as JAVA, SMALLTALK, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. Additionally, logic instructions might include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, statesetting data, configuration data for integrated circuitry, state information that personalizes electronic circuitry and / or other structural components that are native to hardware (e.g., host processor, central processing unit / CPU, microcontroller, etc.).

[0036] Illustrated block 42 provides for extracting distribution statistics of one or more object characteristics from training data. In one example, block 42 excludes an object context (e.g., appearance) from the object characteristic(s). Additionally, the object characteristic(s) may include an object size, an object aspect ratio, an object location, etc., or any combination thereof. Moreover, the distribution statistics can include one or more of a mean, a median or a variance of the object characteristic(s).

[0037] Block 44 generates bounding box proposals (e.g., anchor boxes) based on the distribution statistics. In an embodiment, the bounding box proposals are non-uniform across images in the training data. Additionally, block 46 configures the neural network model based on the bounding box proposals. The method 40 therefore enhances performance at least to the extent that generating the bounding boxes based on the distribution statistics is less complex than conventional solutions and results in relatively faster training, inference and post-processing operations. For example, use of the distribution statistics can enable non-maxima suppression to be bypassed during post-processing. Accordingly, latency is reduced (e.g., further enhancing performance).

[0038] FIG. 3 shows a method 41 of conducting inference operations. The method 41 may be implemented in one or more modules as a plurality of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in hardware, or any combination thereof. Illustrated processing block 43 provides for detecting, by a neural network model (e.g., DL and / or CNN model), an object in an image based on bounding box proposals, wherein the bounding box proposals are associated with distribution statistics of one or more object characteristics extracted from training data. Block 45 bypasses non-maxima suppression operations with respect to the detected object. In this regard, the bounding box proposals can eliminate or reduce the occurrence of overlapping bounding boxes corresponding to the same object. The method 41 therefore enhances performance at least to the extent that bypassing the non-maxima suppression operations reduces latency.

[0039] Execution of the proposed data-aware model configuration using a single shot detector (SSD) architecture on target- specific fish and pothole datasets demonstrated the advantages of the technology described herein. A pretrained model was finetuned on SSD for 28 epochs, employing a learning rate of 0.001. Given the association between the relative scale of object size to image size and the selection of a suitable backbone model for an adequate receptive field size, the focus was on simulating the effects of anchor scale and ratio during anchor generation.

[0040] FIG. 4 shows a set of images 50 with bounding boxes, a ratio distribution 52, a scale distribution 54, a three-dimensional (3D) histogram 56 of object statistics, and an object location distribution (e.g., heatmap) 58 for the fish dataset. The fish dataset includes a single class for detecting underwater fishes, where objects are typically small and wide. Notably, fish are predominantly located at the bottom of the set of images 50, as indicated by the location distribution 58.

[0041] FIG. 5 shows a set of images 60 with bounding boxes, a ratio distribution 62, a scale distribution 64, a 3D histogram 66 of object statistics, and an object location distribution 68 for the pothole dataset. The pothole dataset focuses on detecting potholes in road scenes. Objects in this dataset undergo affine transformations from various geometric viewpoints, resulting in wide aspect ratios and diverse scales. This characteristic is visually demonstrated in the set of images 60 and the object location distribution 68.

[0042] The mean average precision (mAP) scores for the technology described herein improved relative to conventional solutions (e.g., nine bounding box proposals per anchor; [1 / 2, 1, 2] ratios and [128, 256, 512] scales) for anchor ratio optimization, anchor scale optimization and joint anchor ratio / scale optimization in both the fish dataset example and the pothole dataset example. Furthermore, the proposed solution involves 2x fewer feedforwarding operations to a head network (e.g., nine proposals per anchor is reduced to up to four proposals per anchor), which significantly reduces computation overhead.

[0043] Turning now to FIG. 6, a performance-enhanced computing system 280 is shown. The system 280 may generally be part of an electronic device / platform having computing functionality (e.g., personal digital assistant / PDA, notebook computer, tablet computer, convertible tablet, server), communications functionality (e.g., smart phone), imaging functionality (e.g., camera, camcorder), media playing functionality (e.g., smart television / TV), wearable functionality (e.g., watch, eyewear, headwear, footwear, jewelry), vehicular functionality (e.g., car, truck, motorcycle), robotic functionality (e.g., autonomous robot), Internet of Things (loT) functionality, drone functionality, etc., or any combination thereof.

[0044] In the illustrated example, the system 280 includes a host processor 282 (e.g., central processing unit / CPU) having an integrated memory controller (IMC) 284 that is coupled to a system memory 286 (e.g., dual inline memory module / DIMM). In an embodiment, an IO module 288 is coupled to the host processor 282. The illustrated IO module 288 communicates with, for example, a display 290 (e.g., touch screen, liquid crystal display / LCD, light emitting diode / LED display), and a network controller 292 (e.g., conducting wired and / or wireless communications). The host processor 282 may be combined with the IO module 288, a graphics processor 294, and an Al accelerator 296 into a system on chip (SoC) 298.

[0045] In an embodiment, the Al accelerator 296, the host processor 282 and / or the SoC 298 executes a plurality of executable program instructions 300 retrieved from mass storage 302 and / or the system memory 286 to perform one or more aspects of the method 40 (FIG. 3A) and / or the method 41 (FIG. 3B), already discussed. Thus, execution of the instructions 300 causes the Al accelerator 296, the host processor 282 and / or the SoC 298 to extract distribution statistics (e.g., mean, median and / or variance) of one or more object characteristics (e.g., object size / scale, aspect ratio and / or location), generate bounding box proposals based on the distribution statistics and configure a neural network model (e.g., DL and / or CNN model) based on the bounding box proposals.

[0046] The computing system 280 is therefore considered performance-enhanced at least to the extent that generating the bounding boxes based on the distribution statistics is less complex than conventional solutions and results in faster training, inference and post-processing operations. For example, use of the distribution statistics can enable non-maxima suppression to be reduced or bypassed altogether during post-processing. Accordingly, latency is reduced (e.g., further enhancing performance).

[0047] FIG. 7 shows a semiconductor apparatus 350 (e.g., chip, die, package). The illustrated apparatus 350 includes one or more substrates 352 (e.g., silicon, sapphire, gallium arsenide) and logic 354 (e.g., transistor array and other integrated circuit / IC components) coupled to the substrate(s) 352. In an embodiment, the logic 354 implements one or more aspects of the method 40 (FIG. 3 A) and / or the method 41 (FIG. 3B), already discussed.

[0048] The logic 354 may be implemented at least partly in configurable or fixed- functionality hardware. In one example, the logic 354 includes transistor channel regions that are positioned (e.g., embedded) within the substrate(s) 352. Thus, the interface between the logic 354 and the substrate(s) 352 may not be an abrupt junction. The logic 354 may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate(s) 352.

[0049] In an embodiment, the method 40 (FIG. 3A) and / or the method 41 (FIG. 3B) are incorporated into an INTEL GETI software platform, which builds computer vision models. In such a case, the use of distribution statistics as described herein enhances model training and optimization tasks across the model development process.

[0050] FIG. 8 illustrates a processor core 400 according to one embodiment. The processor core 400 may be the core for any type of processor, such as a micro-processor, an embedded processor, a digital signal processor (DSP), a network processor, or other device to execute code. Although only one processor core 400 is illustrated in FIG. 8, a processing element may alternatively include more than one of the processor core 400 illustrated in FIG. 8. The processor core 400 may be a single-threaded core or, for at least one embodiment, the processor core 400 may be multithreaded in that it may include more than one hardware thread context (or “logical processor”) per core.

[0051] FIG. 8 also illustrates a memory 470 coupled to the processor core 400. The memory 470 may be any of a wide variety of memories (including various layers of memory hierarchy) as are known or otherwise available to those of skill in the art. The memory 470 may include one or more code 413 instruction(s) to be executed by the processor core 400, wherein the code 413 may implement the method 40 (FIG. 3 A) and / or the method 41 (FIG. 3B), already discussed. The processor core 400 follows a program sequence of instructions indicated by the code 413. Each instruction may enter a front end portion 410 and be processed by one or more decoders 420. The decoder 420 may generate as its output a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals which reflect the original code instruction. The illustrated front end portion 410 also includes register renaming logic 425 and scheduling logic 430, which generally allocate resources and queue the operation corresponding to the convert instruction for execution.

[0052] The processor core 400 is shown including execution logic 450 having a set of execution units 455-1 through 455-N. Some embodiments may include a number of execution units dedicated to specific functions or sets of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic 450 performs the operations specified by code instructions.

[0053] After completion of execution of the operations specified by the code instructions, back end logic 460 retires the instructions of the code 413. In one embodiment, the processor core 400 allows out of order execution but requires in order retirement of instructions. Retirement logic 465 may take a variety of forms as known to those of skill in the art (e.g., re-order buffers or the like). In this manner, the processor core 400 is transformed during execution of the code 413, at least in terms of the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic 425, and any registers (not shown) modified by the execution logic 450.

[0054] Although not illustrated in FIG. 8, a processing element may include other elements on chip with the processor core 400. For example, a processing element may include memory control logic along with the processor core 400. The processing element may include I / O control logic and / or may include I / O control logic integrated with memory control logic. The processing element may also include one or more caches.

[0055] Referring now to FIG. 9, shown is a block diagram of a computing system 1000 embodiment in accordance with an embodiment. Shown in FIG. 9 is a multiprocessor system 1000 that includes a first processing element 1070 and a second processing element 1080. While two processing elements 1070 and 1080 are shown, it is to be understood that an embodiment of the system 1000 may also include only one such processing element. The system 1000 is illustrated as a point-to-point interconnect system, wherein the first processing element 1070 and the second processing element 1080 are coupled via a point-to-point interconnect 1050. It should be understood that any or all of the interconnects illustrated in FIG. 9 may be implemented as a multi-drop bus rather than point-to-point interconnect.

[0056] As shown in FIG. 9, each of processing elements 1070 and 1080 may be multicore processors, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b). Such cores 1074a, 1074b, 1084a, 1084b may be configured to execute instruction code in a manner similar to that discussed above in connection with FIG. 8.

[0057] Each processing element 1070, 1080 may include at least one shared cache 1896a, 1896b. The shared cache 1896a, 1896b may store data (e.g., instructions) that are utilized by one or more components of the processor, such as the cores 1074a, 1074b and 1084a, 1084b, respectively. For example, the shared cache 1896a, 1896b may locally cache data stored in a memory 1032, 1034 for faster access by components of the processor. In one or more embodiments, the shared cache 1896a, 1896b may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and / or combinations thereof.

[0058] While shown with only two processing elements 1070, 1080, it is to be understood that the scope of the embodiments are not so limited. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of processing elements 1070, 1080 may be an element other than a processor, such as an accelerator or a field programmable gate array. For example, additional processing element(s) may include additional processors(s) that are the same as a first processor 1070, additional processor(s) that are heterogeneous or asymmetric to processor a first processor 1070, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processing element. There can be a variety of differences between the processing elements 1070, 1080 in terms of a spectrum of metrics of merit including architectural, micro architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processing elements 1070, 1080. For at least one embodiment, the various processing elements 1070, 1080 may reside in the same die package. The first processing element 1070 may further include memory controller logic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, the second processing element 1080 may include a MC 1082 and P-P interfaces 1086 and 1088. As shown in FIG. 9, MC’s 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory locally attached to the respective processors. While the MC 1072 and 1082 is illustrated as integrated into the processing elements 1070, 1080, for alternative embodiments the MC logic may be discrete logic outside the processing elements 1070, 1080 rather than integrated therein.

[0059] The first processing element 1070 and the second processing element 1080 may be coupled to an I / O subsystem 1090 via P-P interconnects 1076 1086, respectively. As shown in FIG. 9, the I / O subsystem 1090 includes P-P interfaces 1094 and 1098. Furthermore, VO subsystem 1090 includes an interface 1092 to couple VO subsystem 1090 with a high performance graphics engine 1038. In one embodiment, bus 1049 may be used to couple the graphics engine 1038 to the VO subsystem 1090. Alternately, a point-to-point interconnect may couple these components.

[0060] In turn, I / O subsystem 1090 may be coupled to a first bus 1016 via an interface 1096. In one embodiment, the first bus 1016 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation VO interconnect bus, although the scope of the embodiments are not so limited.

[0061] As shown in FIG. 9, various VO devices 1014 (e.g., biometric scanners, speakers, cameras, sensors) may be coupled to the first bus 1016, along with a bus bridge 1018 which may couple the first bus 1016 to a second bus 1020. In one embodiment, the second bus 1020 may be a low pin count (LPC) bus. Various devices may be coupled to the second bus 1020 including, for example, a keyboard / mouse 1012, communication device(s) 1026, and a data storage unit 1019 such as a disk drive or other mass storage device which may include code 1030, in one embodiment. The illustrated code 1030 may implement the method 40 (FIG. 3A) and / or the method 41 (FIG. 3B), already discussed. Further, an audio VO 1024 may be coupled to second bus 1020 and a battery 1010 may supply power to the computing system 1000.

[0062] Note that other embodiments are contemplated. For example, instead of the point-to-point architecture of FIG. 9, a system may implement a multi-drop bus or another such communication topology. Also, the elements of FIG. 9 may alternatively be partitioned using more or fewer integrated chips than shown in FIG. 9. Additional Notes and Examples:

[0063] Example 1 includes a performance-enhanced computing system comprising a network controller, a processor coupled to the network controller, and a memory coupled to the processor, the memory including a plurality of executable program instructions, which when executed by the processor, cause the processor to extract distribution statistics of one or more object characteristics from training data, generate bounding box proposals based on the distribution statistics, and configure a neural network model based on the bounding box proposals.

[0064] Example 2 includes the computing system of Example 1 , wherein the plurality of instructions, when executed, further cause the computing system to exclude an object context from the one or more object characteristics.

[0065] Example 3 includes the computing system of Example 1, wherein the one or more object characteristics are to include an object size.

[0066] Example 4 includes the computing system of Example 1 , wherein the one or more object characteristics are to include an object aspect ratio.

[0067] Example 5 includes the at least one computer readable storage medium of any one of Examples 1 to 4, wherein the one or more object characteristics are to include an object location.

[0068] Example 6 includes at least one computer readable storage medium comprising a plurality of executable program instructions, which when executed by a computing system, cause the computing system to extract distribution statistics of one or more object characteristics from training data, generate bounding box proposals based on the distribution statistics, and configure a neural network model based on the bounding box proposals.

[0069] Example 7 includes the at least one computer readable storage medium of Example 6, wherein the plurality of instructions, when executed, further cause the computing system to exclude an object context from the one or more object characteristics.

[0070] Example 8 includes the at least one computer readable storage medium of Example 6, wherein the one or more object characteristics are to include an object size.

[0071] Example 9 includes the at least one computer readable storage medium of Example 6, wherein the one or more object characteristics are to include an object aspect ratio. Example 10 includes the at least one computer readable storage medium of Example 6, wherein the one or more object characteristics are to include an object location.

[0072] Example 11 includes the at least one computer readable storage medium of any one of Examples 6 to 10, wherein the distribution statistics are to include one or more of a mean, a median or a variance of the one or more object characteristics.

[0073] Example 12 includes the at least one computer readable storage medium of any one of Examples 6 to 1 1 , wherein the bounding box proposals are to be non-uniform across images in the training data.

[0074] Example 13 includes a semiconductor apparatus comprising one or more substrates, and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to extract distribution statistics of one or more object characteristics from training data, generate bounding box proposals based on the distribution statistics, and configure a neural network model based on the bounding box proposals.

[0075] Example 14 includes the semiconductor apparatus of Example 13, wherein the logic is further to exclude an object context from the one or more object characteristics.

[0076] Example 15 includes the semiconductor apparatus of Example 13, wherein the one or more object characteristics are to include an object size.

[0077] Example 16 includes the semiconductor apparatus of Example 13, wherein the one or more object characteristics are to include an object aspect ratio.

[0078] Example 17 includes the semiconductor apparatus of Example 13, wherein the one or more object characteristics are to include an object location.

[0079] Example 18 includes the semiconductor apparatus of Example 13, wherein the distribution statistics are to include one or more of a mean, a median or a variance of the one or more object characteristics.

[0080] Example 19 includes the semiconductor apparatus of any one of Examples 13 to 18, wherein the bounding box proposals are to be non-uniform across images in the training data.

[0081] Example 20 includes the semiconductor apparatus of any one of Examples 13 to 18, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

[0082] Example 21 includes a method of operating a performance-enhanced computing system, the method comprising extracting distribution statistics of one or more object characteristics from training data, generating bounding box proposals based on the distribution statistics, and configuring a neural network model based on the bounding box proposals.

[0083] Example 22 includes a method of operating a performance-enhanced computing system, the method comprising detecting, by a neural network model, an object in an image based on bounding box proposals, wherein the bounding box proposals are associated with distribution statistics of one or more object characteristics extracted from training data and bypassing non-maxima suppression operations with respect to the detected object.

[0084] Example 23 includes an apparatus comprising means for performing the method of any one of Examples 21 to 22.

[0085] The technology described herein therefore enhances the data analysis and model configuration stages of a training pipeline by providing various types of data statistics for model configurations. The technology described herein also enhances the scope of model configurations (e.g., data preprocessing, model selection, and anchor generation hyperparameters) and enhances the approach to choosing adequate model configurations from data statistics).

[0086] Embodiments are applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD / NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and / or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and / or single-ended lines.

[0087] Example sizes / models / values / ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power / ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the computing system within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0088] The term “coupled” may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms “first”, “second”, etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.

[0089] As used in this application and in the claims, a list of items joined by the term “one or more of’ may mean any combination of the listed terms. For example, the phrases “one or more of A, B or C” may mean A; B; C; A and B; A and C; B and C; or A, B and C.

[0090] Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments can be implemented in a variety of forms. Therefore, while the embodiments have been described in connection with particular examples thereof, the true scope of the embodiments should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.

Claims

CLAIMSWe claim:

1. A performance-enhanced computing system comprising: a network controller; a processor coupled to the network controller; and a memory coupled to the processor, the memory including a plurality of executable program instructions, which when executed by the processor, cause the processor to: extract distribution statistics of one or more object characteristics from training data, generate bounding box proposals based on the distribution statistics, and configure a neural network model based on the bounding box proposals.

2. The computing system of claim 1, wherein the plurality of instructions, when executed, further cause the computing system to exclude an object context from the one or more object characteristics.

3. The computing system of claim 1 , wherein the one or more object characteristics are to include an object size.

4. The computing system of claim 1 , wherein the one or more object characteristics are to include an object aspect ratio.

5. The at least one computer readable storage medium of any one of claims 1 to 4, wherein the one or more object characteristics are to include an object location.

6. At least one computer readable storage medium comprising a plurality of executable program instructions, which when executed by a computing system, cause the computing system to:extract distribution statistics of one or more object characteristics from training data; generate bounding box proposals based on the distribution statistics; and configure a neural network model based on the bounding box proposals.

7. The at least one computer readable storage medium of claim 6, wherein the plurality of instructions, when executed, further cause the computing system to exclude an object context from the one or more object characteristics.

8. The at least one computer readable storage medium of claim 6, wherein the one or more object characteristics are to include an object size.

9. The at least one computer readable storage medium of claim 6, wherein the one or more object characteristics are to include an object aspect ratio.

10. The at least one computer readable storage medium of claim 6, wherein the one or more object characteristics are to include an object location.

11. The at least one computer readable storage medium of claim 6, wherein the distribution statistics are to include one or more of a mean, a median or a variance of the one or more object characteristics.

12. The at least one computer readable storage medium of any one of claims 1 to 6, wherein the bounding box proposals are to be non-uniform across images in the training data.

13. A semiconductor apparatus comprising: one or more substrates; and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to: extract distribution statistics of one or more object characteristics from training data; generate bounding box proposals based on the distribution statistics; andconfigure a neural network model based on the bounding box proposals.

14. The semiconductor apparatus of claim 13, wherein the logic is further to exclude an object context from the one or more object characteristics.

15. The semiconductor apparatus of claim 13, wherein the one or more object characteristics are to include an object size.

16. The semiconductor apparatus of claim 13, wherein the one or more object characteristics are to include an object aspect ratio.

17. The semiconductor apparatus of claim 13, wherein the one or more object characteristics are to include an object location.

18. The semiconductor apparatus of claim 13, wherein the distribution statistics are to include one or more of a mean, a median or a variance of the one or more object characteristics.

19. The semiconductor apparatus of any one of claims 13 to 18, wherein the bounding box proposals are to be non-uniform across images in the training data.

20. The semiconductor apparatus of any one of claims 13 to 18, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

Images