Sampling jitter and skew tolerant analog-to-digital converters

WO2025207273A1PCT designated stage Publication Date: 2025-10-02OMNI DESIGN TECH
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Patent Information

Application Number
PCT/US2025/017772
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-03-28
Filing Date
2025-02-28
Publication Date
2025-10-02

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Abstract

A derivative measurement circuit is configured to sample the input voltage of an input line to determine the time-derivative of the input voltage. A plurality of time-interleaved analog-to-digital converters (ADCs) are configured to convert respective input-voltage samples that are sampled at different times. The ADCs do not convert the input-voltage samples having respective time-derivatives that are above a predetermined threshold magnitude or that are relatively high to limit sampling clock jitter and sampling clock skew.
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Description

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Claims

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Citation Information

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