Electronic module and electronic device

Abstract

The present application provides an electronic module and an electronic device. The electronic module comprises a printed circuit board and an electronic unit. The printed circuit board comprises a wiring layer, and one side surface of the printed circuit board is a first surface, the first surface being provided with first connection points connected to the wiring layer. An electronic unit of the electronic module is connected to a set of first connection points on the first surface. The electronic unit comprises a first die stack and a second die stack, the first die stack comprising a plurality of dies, and the plurality of dies being sequentially stacked in a direction away from the printed circuit board. Adjacent dies in the first die stack are connected by means of leads, the first die stack and the second die stack are connected to a same set of first connection points, and only dies adjacent to the printed circuit board in the first die stack and the second die stack are connected to the first connection points. A signal transmission path is shortened, the signal integrity is improved, the data transmission speed is high, high-speed read and write performance is better, and the integration of the electronic module is also improved.

Description

Electronic module and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on March 30, 2024, with application number 202410396232.7 and invention name "An electronic module and electronic device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of electronic equipment, and in particular to an electronic module and an electronic device. Background Art

[0004] The storage module is an important component structure in electronic devices, and the capacity of the storage module has a significant impact on the performance of electronic devices. With the technological development of electronic devices, the demand for the capacity of the storage module is also increasing.

[0005] Traditional storage modules are implemented in the form of memory bars or by directly welding on-board particles onto the board. In order to seek higher capacity density, the capacity density can be improved by moving from traditional 2D to 3D three-dimensional stacking. In the prior art, three-dimensional stacked storage modules require the use of a substrate to achieve module packaging. Specifically, the memory dies are mounted on a substrate for stacking and packaged into modules. In order to realize data transmission between the module and other electronic devices, balls are planted on the above-mentioned substrate, which is connected to a printed circuit board using the ball planting, and then connected to other electronic devices using the printed circuit board. The preparation process is relatively complex and the data path is long, which has certain limitations on improving data transmission speed and signal integrity. Summary of the Invention

[0006] The present application provides an electronic module and an electronic device, which simplifies the structure of the electronic module, shortens the signal transmission path, improves the data transmission speed and signal integrity, and also improves the integration of the electronic module.

[0007] In a first aspect, the present application provides an electronic module. The electronic module includes a printed circuit board and an electronic module, wherein the printed circuit board includes a circuit layer and a dielectric layer, the circuit layer being fixed to the dielectric layer. One side surface of the printed circuit board is a first surface, and the first surface is provided with a first connection point, which is connected to the circuit layer. Specifically, the first connection point can be a structure such as a solder pad for connecting to a bare chip. An electronic module of the electronic module is connected to a group of first connection points on the first surface.

[0008] Specifically, the electronic module includes a first die stack and a second die stack, each comprising a plurality of die stacked sequentially in a direction away from the printed circuit board, with any adjacent die stacks connected via leads. The first die stack and the second die stack are connected to the same set of first connection points, with only the die adjacent to the printed circuit board in the first die stack and the second die stack being connected to the first connection points. The first die stack and the second die stack are connected to the circuit layer via a set of first connection points, with each first connection point connected to two leads. Thus, the two first die stacks are connected using a set of first connection points, which reduces the number of connection points used for connection to the electronic module, enabling connection to the circuit layer via a single set of first connection points. This also reduces the length of the line resulting from merging lines from different connection points, further shortening the signal transmission path. Insertion loss along the transmission path is reduced, thereby improving signal integrity. Furthermore, a shorter signal transmission path results in higher data transmission speeds and better high-speed read and write performance. In addition, by increasing the number of first bare die stacks, the height of the first bare die stack is reduced, the link length of signal transmission is shortened to a significant extent, the signal integrity and data transmission speed are improved, and the high-speed reading and writing performance of the electronic module is better.

[0009] Furthermore, in the embodiments of the present application, the electronic module is directly connected to the printed circuit board, eliminating the need for a substrate. This reduces costs, reduces the size of the electronic module, and improves its integration. Removing the substrate also simplifies the electronic module's structure, shortens the signal transmission path, and improves signal integrity and data transmission speed.

[0010] Specifically, the first and second die stacks are symmetrically arranged on either side of the first connection point. This allows for more uniform stress distribution within the electronic module, minimizes the number of die in each of the first and second die stacks, reduces the height of the die stacks, and thus shortens the signal transmission link length. Furthermore, the two die stacks are stacked symmetrically with respect to the first connection point, further enhancing uniform stress distribution within the electronic module.

[0011] When stacking the first die stack, any two adjacent die in the first die stack include a first die and a second die arranged away from the circuit board. The surface of the first die facing away from the circuit board includes a first connection area and a first stacking area, which are arranged away from the first connection point. The second die covers the first stacking area, and the first connection area is connected to the lead. The two first die stacks are arranged in a V-shape, which is structurally stable and helps improve stress uniformity in the electronic module.

[0012] In one implementation, the second die stack is located on a side of the first die stack away from the printed circuit board (PCB). The second die stack is connected to the first die stack, and only the die adjacent to the PCB in the first die stack is connected to the first connection point. Any two adjacent die in the first die stack include a third die and a fourth die arranged in a direction away from the PCB. The third die includes a second connection area and a second stacking area arranged in a direction away from the first connection point. The fourth die covers the second stacking area, and the second connection area is connected to the lead. Any two adjacent die in the second die stack include a fifth die and a sixth die arranged in a direction away from the PCB. The sixth die includes a third connection area and a third stacking area arranged in a direction away from the first connection point. The fifth die covers the third stacking area, and the third connection area is connected to the lead. The first die stack and the second die stack are connected so that the second die stack is connected to the circuit layer of the PCB through the first die stack. The two die sub-stacks are tilted in opposite directions, resulting in a smaller dimension of the first die stack parallel to the first surface of the printed circuit board. This facilitates the placement of a large number of electronic modules on a single printed circuit board. This also improves the balance of the first die stack and helps minimize warpage.

[0013] In a further technical solution, the number of dies included in the first die stack and the number of dies included in the second die stack are the same or differ by one. This minimizes the area of ​​the orthographic projection of the first die stack on the first surface of the printed circuit board, facilitating the installation of a larger number of electronic modules on a single printed circuit board.

[0014] Specifically, a support plate is disposed between the first and second die stacks. The support plate covers the stacking area of ​​the die adjacent to the second die stack in the first die stack, as well as the stacking area of ​​the die adjacent to the first die stack in the second die stack. The connection area of ​​the die adjacent to the second die stack in the first die stack is separated by a predetermined distance from the connection area of ​​the die adjacent to the first die stack in the second die stack, and the two are connected via wires. In this solution, the provision of the support plate simplifies the connection process between the first and second die stacks.

[0015] In one implementation, the second die stack is located on a side of the first die stack away from the printed circuit board (PCB). The first and second die stacks are connected, and only the die in the first die stack adjacent to the PCB are connected to the first connection point. This implementation differs from the above implementation in the location of the leads. Specifically, any two adjacent die in the first die stack include a seventh die and an eighth die arranged away from the PCB. The seventh die includes a fourth connection region and a fourth stacking region arranged away from the first connection point. The eighth die overlaps the fourth stacking region, and the fourth connection region is connected to the leads. Any two adjacent die in the second die stack include a ninth die and a tenth die arranged away from the PCB. The ninth die includes a fifth connection region and a fifth stacking region arranged toward the first connection point. The tenth die overlaps the fifth stacking region, and the fifth connection region is connected to the leads. In other words, the first die stack is tilted away from the first connection point and connected by leads on the side facing the first connection point. The second die stack is tilted in a direction close to the first connection point and is connected by wires on a side away from the first connection point.

[0016] Because the leads of the first die stack and the leads of the second die stack are on opposite sides of the first die stack, the first die stack also includes an adapter plate to connect the first and second die stacks. Specifically, the adapter plate includes a dielectric plate and a circuit located on the dielectric plate. One end of the circuit is connected to the die in the first die stack that is adjacent to the second die stack, and the other end is connected to the die in the second die stack that is adjacent to the first die stack. This solution is also convenient for arranging a large number of electronic modules on a single printed circuit board. Improving the balance between the first and second die stacks helps optimize warpage.

[0017] Furthermore, the adapter board includes a silicon substrate and circuits on the silicon substrate, that is, the dielectric plate of the adapter board is a silicon substrate. Since the process precision of preparing circuits on silicon substrates is relatively high, this solution is conducive to improving the precision of the circuits on the adapter board.

[0018] There are multiple options for routing the aforementioned circuits on the dielectric board. For example, one end of the circuit can be connected to the first die stack on the surface of the adapter board facing the first die stack, and the other end can be connected to the second die stack on the surface of the adapter board facing the second die stack. Alternatively, one end of the circuit can be connected to the first die stack on the surface of the adapter board facing the second die stack, and the other end can be connected to the second die stack on the surface of the adapter board facing the second die stack. The structure of the adapter board can be selected based on the structures of the first and second die stacks to simplify the electronic module manufacturing process.

[0019] Specifically, the number of dies included in the first die stack and the number of dies included in the second die stack are the same or differ by one. This minimizes the orthographic projection areas of the first die stack and the second die stack on the first surface of the printed circuit board, facilitating the installation of a larger number of electronic modules on a single printed circuit board.

[0020] In a further embodiment, the electronic module further comprises a third die stack, the third die stack being located on a side of the second die stack away from the printed circuit board, and the third die stack being connected to the second die stack. That is, in this application, a greater number of die stacks may be included. Regardless of the number of die stacks, all are connected to the circuit layer on the first surface of the printed circuit board via a set of first connection points.

[0021] Specifically, any two adjacent die in the third die stack include an eleventh die and a twelfth die arranged in a direction away from the printed circuit board. The eleventh die includes a sixth connection region and a sixth stacking region arranged in a direction away from the first connection point, the twelfth die overlaps the sixth stacking region, and the sixth connection region is connected to the lead. Alternatively, the twelfth die includes a seventh connection region and a seventh stacking region arranged in a direction toward the first connection point, the eleventh die overlaps the seventh stacking region, and the seventh connection region is connected to the lead. The stacking method of the multiple die in the third die stack can be selected according to needs.

[0022] The printed circuit board also includes a second surface, facing away from the first surface, and provided with a second connection point. The second connection point is connected to the first connection point connected to the same electronic module, thereby connecting the same electronic module to the same point on the circuit layer. The electronic module also includes a fourth die stack and a fifth die stack, each comprising a plurality of die stacked sequentially in a direction away from the printed circuit board, with any adjacent die stacked being connected via leads. The fourth and fifth die stacks are connected to the same set of second connection points, and only the die adjacent to the printed circuit board in the fourth and fifth die stacks are connected to the second connection points. For electronic modules with the same number of die, the die stacks are distributed on both sides of the printed circuit board, forming a larger number of die stacks. This results in a shorter die stack, or in other words, a smaller number of die stacked. This shortens the distance between the die in the die stack and the connection points, shortens the signal transmission path, improves signal integrity and data transmission speed, and enhances high-speed read and write performance of the electronic module. This solution is particularly suitable for electronic modules with a large number of die.

[0023] In one implementation, the orthographic projection of the first connection point on the second surface and the second connection point at least partially overlap. This allows for shorter wiring when connecting the first connection point to the second connection point, further shortening the signal transmission path, improving signal integrity and data transmission speed, and enhancing high-speed read and write performance of the electronic module.

[0024] When configuring the electronic module, the fourth die stack is symmetrically positioned with the first die stack on either side of the printed circuit board, while the fifth die stack is symmetrically positioned with the second die stack on either side of the printed circuit board. The fourth die stack contains the same number of die as the first die stack, and the fifth die stack contains the same number of die as the second die stack. Furthermore, the fourth die stack has the same stacking method or structure as the first die stack, and the fifth die stack has the same stacking method or structure as the second die stack. This ensures more uniform stress distribution and minimizes the stacking height of each die stack, thereby shortening the signal transmission link length.

[0025] Specifically, the total number of bare chips included in the electronic module is greater than or equal to 8. Then the advantages of the technical solution in this application are more obvious, and the effect of improving the reading rate is more obvious.

[0026] Specifically, the electronic module provided in the embodiment of the present application is a storage module, and the bare die is a memory chip. By stacking multiple bare chips, a storage module with a large storage capacity is formed, which is conducive to improving the data reading rate of the storage module.

[0027] The printed circuit board is also connected to electronic components and connection ports, which are respectively connected to the circuit layer. The connection ports serve as ports for connecting the electronic module to the outside to achieve signal transmission between the electronic module and other devices.

[0028] In one technical solution, the connection port of the electronic module is a gold finger connector, which is convenient for connection with other connectors.

[0029] The electronic module includes at least two electronic modules, and all the electronic modules are arranged on the same printed circuit board to improve the performance of the electronic module, for example, to improve the storage capacity of the electronic module.

[0030] In a second aspect, the present application further provides an electronic device, which includes a housing and the electronic module provided in the first aspect, wherein the electronic module is disposed in the housing. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

[0032] FIG2 is a schematic structural diagram of an electronic module in an embodiment of the present application;

[0033] FIG3 is a schematic diagram of a cross-sectional structure of an electronic module in an embodiment of the present application;

[0034] FIG4 is a schematic structural diagram of an electronic module in the prior art;

[0035] FIG5 is another structural schematic diagram of an electronic module in the prior art;

[0036] FIG6 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application;

[0037] FIG7 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application;

[0038] FIG8 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application;

[0039] FIG9 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application;

[0040] FIG10 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application;

[0041] FIG11 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application;

[0042] FIG12 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application;

[0043] FIG13 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application.

[0044] Reference numerals: 1-electronic module; 11-printed circuit board; 111-dielectric layer; 112-circuit layer; 113-first surface; 114-second surface; 115-first connection point; 116-second connection point; 12-electronic module; 121-first die stack; 122-second die stack; 123-third die stack; 124-fourth die stack; 125-fifth die stack; 13-electronic component; 14-connection port; 15-substrate; 16-die; 161-first die; 1611-first connection area; 1612-first stacking area; 162-second die; 163-third die; 1631-second connection area; 1632-second stacking area; 164-fourth die; 165-fifth die; 166-sixth die; 1661 - third connection area; 1662 - third stacking area; 167 - seventh die; 1671 - fourth connection area; 1672 - fourth stacking area; 168 - eighth die; 169 - ninth die; 1691 - fifth connection area;1692 - fifth stacking area; 1610 - tenth bare die; 17 - leads; 18 - support plate; 19 - adapter plate; 191 - dielectric board; 192 - circuit board; 2 - housing; 3 - electronic assembly; 31 - circuit board; 32 - electronic device; 33 - opposite end connector. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.

[0046] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and appended claims of this application, the singular expressions "a", "an", "above", "the", and "this" are intended to also include expressions such as "one or more", unless the context clearly indicates otherwise.

[0047] References in this specification to "one embodiment" or "a specific embodiment" mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. The terms "including," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically stated.

[0048] To facilitate understanding of the electronic modules and electronic devices provided in the embodiments of the present application, the following first introduces their application scenarios.

[0049] The electronic devices in the embodiments of the present application may be electronic devices such as information and communications technology (ICT) devices, communication devices (such as routers), computing devices (such as servers), network devices (such as switches), or storage devices (such as storage arrays), or may be electronic devices such as optical modules, vehicle-mounted devices, or terminal devices. The present application does not limit the specific type of electronic device; as long as the electronic device includes an electronic module, the technical solutions provided in the present application may be adopted.

[0050] FIG1 is a structural diagram of an electronic device in an embodiment of the present application. As shown in FIG1 , in one embodiment, the electronic device may include an electronic module 1 and a housing 2, and the electronic module 1 is disposed in the housing 2 of the electronic device. The electronic module 1 is assembled in the housing 2. In a specific embodiment, the electronic module 1 can be accommodated inside the housing 2, so that the housing 2 can protect the electronic module 1. In another specific embodiment, the electronic module 1 can also be disposed on the outside of the housing 2, which can be designed according to the actual product structure, and the present application does not impose any restrictions on this.

[0051] Continuing with FIG1 , in a specific embodiment, the electronic device may include an electronic assembly 3, which may be a single board. The electronic assembly 3 includes a circuit board 31, an electronic device 32, and an electronic module 1. The electronic device 32 and the electronic module 1 are both disposed on the circuit board 31 and electrically connected via the circuit board 31 to implement the functions of the electronic assembly 3.

[0052] In one application scenario, the electronic module 1 provided in an embodiment of the present application can be a memory module for storing data in an electronic device. The electronic module 1 provided by the technical solution of the present application has a high storage density and a low cost. In other application scenarios, the electronic module 1 provided in an embodiment of the present application can also be other electronic modules to improve the performance of the electronic module 1.

[0053] Figure 2 is a schematic diagram of the structure of an electronic module in an embodiment of the present application, and Figure 3 is a schematic diagram of the cross-sectional structure of the electronic module in an embodiment of the present application. Specifically, Figure 3 is a schematic diagram of the cross-sectional structure at AA in Figure 2. As shown in Figures 2 and 3, the electronic module 1 provided in the present application includes a printed circuit board 11 and an electronic module 12. The printed circuit board 11 includes a dielectric layer 111 and a circuit layer 112, and the circuit layer 112 is fixed to the dielectric layer 111. The electronic module 1 in the embodiment of the present application also includes electronic components 13 and a connection port 14. The electronic components 13 and the connection port 14 are respectively connected to the circuit layer 112. The connection port 14 can be connected to the electronic module 12 through the circuit layer 112. The connection port 14 serves as a port for connecting the electronic module 12 to the outside world, thereby enabling signal transmission between the electronic module 12 and other devices. In this embodiment, the electronic module 1 can be a card or a strip, etc., and can be directly connected to the motherboard via a connector for operation. For example, the electronic module 1 can be a memory card or a memory stick.

[0054] Specifically, as shown in FIG1 , the connection port 14 may include a connector that connects to the opposite connector 33 on the circuit board. Furthermore, the specific type of the connector is not limited; for example, it may be a plug-in connector or a gold finger connector. In some embodiments, the connection port 14 may also be a pin or solder ball. The electronic component 13 may be a capacitor, inductor, or switch.

[0055] As shown in Figures 2 and 3 , in the embodiments of the present application, the number of electronic modules 12 included in the electronic module 1 can be one, two, or more, and this application does not impose any restrictions on this. When the electronic module includes at least two electronic modules 12, the at least two electronic modules 12 are both disposed on the same printed circuit board 11. For example, if the electronic module 1 is a memory module, this embodiment can help increase the storage capacity of the memory module.

[0056] Referring to Figures 2 and 3 , in the embodiment of the present application, the two side surfaces of the printed circuit board 11 are respectively a first surface 113 and a second surface 114. It is understood that the first surface 113 and the second surface 114 are oriented in opposite directions. The first surface 113 is provided with a first connection point 115, which is connected to the circuit layer 112. Connection to the first connection point 115 establishes a connection to the circuit layer 112. The electronic module 12 is connected to the circuit layer 112 of the printed circuit board 11. Specifically, each electronic module 12 is connected to a set of first connection points 115 on the first surface 113. That is, for each electronic module 12, only one set of first connection points 115 exists on the first surface 113 for connecting to the electronic module 12. This solution reduces the number of connection points for connecting to the electronic module 12. Connection to the circuit layer 112 is achieved through a set of first connection points 115, shortens the signal transmission path, reduces insertion loss along the transmission path, and improves signal integrity. In addition, the shorter the signal transmission path, the higher the data transmission speed and the better the high-speed reading and writing performance.

[0057] Furthermore, in the embodiment of the present application, the electronic module 12 is directly connected to the printed circuit board 11, eliminating the need for a substrate 15. This reduces costs, reduces the size of the electronic module 1, and improves the integration of the electronic module 1. Removing the substrate 15 also simplifies the structure of the electronic module 1, shortens the signal transmission path, and improves signal integrity and data transmission speed.

[0058] In an optional embodiment, when the printed circuit board 11 is connected to multiple electronic modules 12 , the first surface 113 of the printed circuit board 11 includes multiple groups of first connection points 115 , and one electronic module 12 is connected to a group of first connection points 115 on the first surface 113 .

[0059] Figure 4 is a schematic diagram of one structure of an electronic module in the prior art, and Figure 5 is a schematic diagram of another structure of an electronic module in the prior art. As shown in Figures 4 and 5, the electronic module 12 in the prior art includes a substrate 15 and a bare die 16. The bare die 16 is fixed to one side of the substrate 15, and the other side of the substrate 15 includes solder balls. The bare die 16 is connected to the solder balls on the substrate 15 via leads 17, and the solder balls are then soldered to the printed circuit board 11, thus connecting the electronic module 12 to the printed circuit board 11 in one step. This solution is relatively complex and costly to implement, and the electronic module 1 is relatively large, making it difficult to achieve miniaturization. In addition, one side surface of the printed circuit board 11 includes at least two sets of connection points, which are connected to the circuit layer 112 via wiring within the printed circuit board 11. This makes the entire signal transmission path longer and causes significant losses, which has a negative impact on signal integrity and data transmission speed.

[0060] The technical solution of this application effectively solves the aforementioned problems by directly stacking the bare die 16 on the surface of the printed circuit board 11, eliminating the need for a substrate 15. Furthermore, this application allows an electronic module 12 to be connected to only one set of first connection points 115 on one surface of the printed circuit board 11, eliminating the need for further wiring within the printed circuit board 11 for aggregation. This also shortens the signal transmission path, improving signal integrity and data transmission speed.

[0061] FIG6 is a schematic diagram of a partial structure of an electronic module according to an embodiment of the present application. As shown in FIG6 , in a specific implementation of the present application, the electronic module 12 includes a first die stack 121 and a second die stack 122. The first die stack 121 and the second die stack 122 each include multiple die 16 stacked sequentially in a direction away from the printed circuit board 11. Specifically, the multiple die 16 in the first die stack 121 are stacked sequentially in a direction away from the first surface, and the multiple die 16 in the second die stack 122 are also stacked sequentially in a direction away from the first surface. Adjacent die 16 in the first and second die stacks 121, 122 are connected via leads 17. The first and second die stacks 121, 122 are connected to the same set of first connection points 115. Furthermore, only the die 16 adjacent to the first surface 113 of the first and second die stacks 121, 122 are connected to the same set of first connection points 115. In this embodiment, only the die 16 adjacent to the first surface 113 of the printed circuit board 11 is directly connected to the first connection point 115, and the multiple die 16 in the first die stack 121 and the second die stack 122 are connected in pairs. Then, all the die 16 can be connected to the circuit layer 112 through the die 16 adjacent to the first surface 113 of the printed circuit board 11.

[0062] In this embodiment, the first connection point 115 is connected to at least two leads 17, so that the first die stack 121 and the second die stack 122 are connected by a group of first connection points 115, so as to reduce the number of connection points, thereby reducing the length of the line generated by merging different connection point lines, and further shortening the signal transmission path.

[0063] In an optional embodiment, the specific type of the above-mentioned bare chip 16 is not limited. For example, the above-mentioned bare chip 16 can be a memory chip or a high-power chip.

[0064] When the bare die 16 in the embodiment of the present application is a memory chip, a plurality of bare chips 16 can be stacked to form an electronic module 1 with a large storage capacity. This electronic module 1 is a memory module. In this embodiment, a high-integration, large-capacity memory module can be prepared, which is conducive to improving the data read rate of the memory module.

[0065] In a specific embodiment, the number of die 16 included in an electronic module 12 is 4n, where n is a positive integer. In other words, the number of die 16 included in an electronic module 12 is an integer multiple of 4. For example, the electronic module 12 may include 4, 8, 12, 16, 32, or 64 die. Furthermore, if the total number of die 16 included in the electronic module 12 is at least 8, the advantages of this solution are even more significant, and the effect of improving the reading rate is more obvious.

[0066] Continuing with FIG6 , in one embodiment, the die 16 adjacent to the printed circuit board 11 in the first die stack 121 are connected to the first connection points of the printed circuit board 11, and the die 16 adjacent to the printed circuit board 11 in the second die stack 122 are connected to the same set of first connection points of the printed circuit board 11. When the number of die 16 is the same, stacking the same number of die 16 into two stacks, the first die stack 121 and the second die stack 122, can reduce the height of the first die stack 121 and the second die stack 122, and shorten the distance between the die 16 in the first die stack 121 and the second die stack 122 and the first connection points 115, compared to stacking the die 16 into one stack. Because the die 16 in the first die stack 121 and the second die stack 122 need to transmit signals to the circuit board through all the die 16 stacked below, the higher the first die stack 121 and the second die stack 122, the more die 16 there are under the die 16 closer to the top layer, and the more leads 17 are required to transmit signals. In this embodiment, the height of the first die stack 121 and the second die stack 122 is significantly reduced, further shortening the signal transmission path. In summary, in this application, by increasing the number of die stacks, the height of the first die stack 121 and the second die stack 122 is reduced, and there is no need to increase the number of first connection points 115. The first die stack 121 and the second die stack 122 can reuse the first connection point 115, significantly shortening the signal transmission link length, improving signal integrity and data transmission speed, and achieving excellent high-speed read and write performance of the electronic module 1.

[0067] Furthermore, the smaller number of dies 16 in a first die stack 121 or a second die stack 122 also simplifies the manufacturing process. Disposing the first die stack 121 and the second die stack 122, respectively connected to the first connection points, on the first surface 113 of the printed circuit board 11 also helps balance the stress distribution of the electronic module 1 and control warping of the entire electronic module 1.

[0068] Furthermore, as shown in FIG6 , in a specific embodiment, the first die stack 121 and the second die stack 122 are symmetrically arranged on either side of the first connection point 115. It will be appreciated that, in order to achieve symmetry between the first die stack 121 and the second die stack 122, the number of die 16 included in the first die stack 121 and the second die stack 122 may be substantially the same, or differ by only one. For example, if the number of die 16 on one side of the first surface 113 of the printed circuit board 11 of the electronic module 1 is an even number, the number of die 16 included in the first die stack 121 and the second die stack 122 may be the same, each being half the total number. If the number of die 16 on one side of the first surface 113 of the printed circuit board 11 of the electronic module 1 is an odd number, the number of die 16 included in the first die stack 121 and the second die stack 122 may differ by one. In short, the number of die 16 included in the first die stack 121 and the second die stack 122 may be as close as possible. This improves stress uniformity within the electronic module 1 and minimizes the number of first die stacks 121, reducing the height of each first die stack 121 and, consequently, shortening the signal transmission link length. Furthermore, the two die stacks are stacked symmetrically relative to the first connection point 115, further enhancing the uniformity of stress distribution within the electronic module 1. For example, in one embodiment, two identical die stacks can be prepared and then mirror-mounted on either side of the first connection point 115.

[0069] There are various options for stacking the first die stack 121. For example, referring to FIG. 6 , in one embodiment, any two adjacent die 16 in the first die stack 121 include a first die 161 and a second die 162 arranged away from the circuit board. The surface of the first die 161 facing away from the circuit board includes a first connection region 1611 and a first stacking region 1612. The first connection region 1611 and the first stacking region 1612 are arranged away from the first connection point 115. The second die 162 covers the first stacking region 1612. The first connection region 1611 is connected to the lead 17. As shown in FIG. 6 , the plurality of die 16 in the first die stack 121 are arranged diagonally, and any adjacent die 16 are staggered. Specifically, the second die 162 of the two adjacent die 16 are staggered away from the first connection point 115, so that the portion of the first die 161 not covered by the second die 162 is available for connection to the lead 17. The angle between the inclined direction and the first surface 113 is acute. The multiple dies 16 in a first die stack 121 are arranged in one direction, and the entire first die stack 121 is inclined in one direction, specifically, in a direction away from the first connection point 115 .

[0070] The second die stack 122 can be arranged symmetrically with the first die stack 121, such that the second die stack 122 is tilted away from the first die stack 121, and the first die stack 121 and the second die stack 122 are arranged in a V-shape. This provides a more stable structure for the electronic module, which helps improve stress uniformity.

[0071] FIG7 is a schematic diagram of a partial structure of an electronic module according to an embodiment of the present application. As shown in FIG7 , in a specific implementation of the present application, the second die stack 122 is located on a side of the first die stack 121 away from the circuit board. Any two adjacent die 16 in the first die stack 121 include a third die 163 and a fourth die 164 arranged in a direction away from the circuit board. The third die 163 includes a second connection region 1631 and a second stacking region 1632 arranged in a direction away from the first connection point 115. The fourth die 164 covers the second stacking region 1632, and the second connection region 1631 is connected to the lead 17. The first die stack 121 is arranged diagonally, specifically tilted away from the first connection point 115, and is connected by the lead 17 on the side facing the first connection point 115. Any two adjacent die 16 in the second die stack 122 include a fifth die 165 and a sixth die 166 arranged away from the circuit board. The sixth die 166 includes a third connection region 1661 and a third stacking region 1662 arranged away from the first connection point 115. The fifth die 165 covers the third stacking region 1662, and the third connection region 1661 is connected to the lead 17. The second die stack 122 is also arranged diagonally, but tilted toward the first connection point 115. The second die stack 122 is also connected by the lead 17 on the side facing the first connection point 115. This creates a stacked shape between the first die stack 121 and the second die stack 122. The first die stack 121 and the second die stack 122 are electrically connected, forming a single, integrated first die stack 121.

[0072] In this embodiment, by arranging the first die stack 121 and the second die stack 122 in opposite directions, the dimensions of the first die stack 121 and the second die stack 122 along a direction parallel to the first surface 113 of the printed circuit board 11 are reduced. In other words, the orthographic projection areas of the first die stack 121 and the second die stack 122 on the first surface 113 of the printed circuit board 11 are reduced. This solution facilitates the installation of a large number of electronic modules 12 on a single printed circuit board 11. It also helps improve the balance of the electronic modules 12 and reduces warpage.

[0073] Specifically, the electrical connection method between the first die stack 121 and the second die stack 122 is not specifically limited. For example, wire bonding 17 may be used to connect the two die 16. Continuing with FIG7 , in one embodiment, a support plate 18 is further disposed between the first die stack 121 and the second die stack 122. This support plate 18 supports the first die stack 121 and the second die stack 122, ensuring a certain gap between the fourth die 164 in the first die stack 121 facing the second die stack 122 and the fifth die 165 in the second die stack 122 facing the first die stack 121. Specifically, the support plate 18 covers the stacking area of ​​the die adjacent to the second die stack 122 in the first die stack 121, as well as the stacking area of ​​the die 16 adjacent to the first die stack 121 in the second die stack. This exposes the connection area of ​​the fourth die 164 and the connection area of ​​the fifth die 165. In this embodiment, the connection area of ​​the fourth die 164 in the first die stack 121, which faces the second die stack 122, faces the aforementioned gap, while the connection area of ​​the fifth die 165 in the second die stack 122, which faces the first die stack 121, faces the aforementioned gap. Furthermore, the support plate 18 ensures a predetermined distance between the connection area of ​​the fourth die 164 in the first die stack 121, which faces the second die stack 122, and the connection area of ​​the fifth die 165 in the second die stack 122, which faces the first die stack 121. This predetermined distance enables wire bonding between these two connection areas. Wires 17 are then used to connect these two connection areas, thereby achieving electrical connection between the first die stack 121 and the second die stack 122.

[0074] In a specific embodiment, the number of dies 16 included in the first die stack 121 and the number of dies 16 included in the second die stack 122 are the same or differ by one. For example, if the number of dies 16 in the first die stack 121 is an even number, the number of dies 16 included in the first die stack 121 and the second die stack 122 can be the same, each being half the total number. If the number of dies 16 in the first die stack 121 is an odd number, the number of dies 16 included in the first die stack 121 and the second die stack 122 can differ by one. In short, the number of dies 16 included in the first die stack 121 and the second die stack 122 is kept as close as possible. This allows for a more uniform stress distribution of the electronic module 1 and minimizes the dimensions of the first die stack 121 and the second die stack 122 in a direction parallel to the first surface 113 of the printed circuit board 11. In other words, the areas of the orthographic projections of the first die stack 121 and the second die stack 122 on the first surface 113 of the printed circuit board 11 are minimized. This facilitates the arrangement of a larger number of electronic modules 12 on one printed circuit board 11.

[0075] FIG8 is a schematic diagram of a partial structure of an electronic module according to an embodiment of the present application. As shown in FIG8 , in a specific implementation of the present application, the second die stack 122 is located on a side of the first die stack 121 away from the circuit board. Any two adjacent die 16 in the first die stack 121 include a seventh die 167 and an eighth die 168 arranged in a direction away from the circuit board. The seventh die 167 includes a fourth connection region 1671 and a fourth stacking region 1672 arranged in a direction away from the first connection point 115. The eighth die 168 covers the fourth stacking region 1672. The fourth connection region 1671 is connected to the lead 17. The first die stack 121 is arranged diagonally, specifically tilted away from the first connection point 115, and is connected by the lead 17 on the side facing the first connection point 115. Any two adjacent die 16 in the second die stack 122 include a ninth die 169 and a tenth die 1610 arranged away from the circuit board. The ninth die 169 includes a fifth connection region 1691 and a fifth stacking region 1692 arranged toward the first connection point 115. The tenth die 1610 covers the fifth stacking region 1692. The fifth connection region 1691 is connected to the lead 17. The second die stack 122 is also arranged diagonally, but is tilted toward the first connection point 115 and connected by leads 17 on the side facing away from the first connection point 115. This creates a stacked shape between the first die stack 121 and the second die stack 122. The first die stack 121 and the second die stack 122 are electrically connected, forming a single, integrated first die stack 121.

[0076] Similarly, in this embodiment, by arranging the first die stack 121 and the second die stack 122 in oppositely inclined directions and stacking them, the dimensions of the first die stack 121 and the second die stack 122 parallel to the first surface 113 of the printed circuit board 11 are reduced. In other words, the orthographic projection areas of the first die stack 121 and the second die stack 122 on the first surface 113 of the printed circuit board 11 are reduced. This solution facilitates the installation of a large number of electronic modules 12 on a single printed circuit board 11. It also helps improve the balance of the first die stack 121 and reduces warpage.

[0077] The difference from the above embodiment is that in this embodiment, the first die stack 121 and the second die stack 122 are connected via a transfer board 19 . Specifically, the connection area of ​​the eighth die 168 adjacent to the first die stack 121 and the second die stack 122 is located on a side facing away from the printed circuit board 11. The connection area of ​​the ninth die 169 adjacent to the second die stack 122 and the first die stack 121 is also located on a side facing away from the printed circuit board 11. Furthermore, the connection area of ​​the eighth die 168 is located on the side of the first die stack 121 facing the first connection point 115, and the connection area of ​​the ninth die 169 is located on the side of the second die stack 122 facing away from the first connection point 115. Therefore, to connect these two connection areas, an adapter board 19 is used. One end of the adapter board 19 is connected to the connection area of ​​the eighth die 168 adjacent to the first die stack 121 and the second die stack 122, and the other end is connected to the connection area of ​​the ninth die 169 adjacent to the second die stack 122 and the first die stack 121. This allows for electrical connection between the first die stack 121 and the second die stack 122.

[0078] The present application does not impose any specific limitations on the structure of the adapter board 19. For example, as shown in FIG8 , the adapter board 19 may include a dielectric board 191 and a circuit 192 located on the dielectric board 191. The circuit 192 connects the first die stack 121 and the second die stack 122. Specifically, one end of the circuit 192 is connected to a die in the first die stack 121 that is adjacent to the second die stack, and the other end is connected to a die in the second die stack that is adjacent to the first die stack.

[0079] In a further embodiment, FIG9 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application. As shown in FIG9 , the adapter board 19 may further include a silicon dielectric plate and a circuit 192 located on a silicon substrate. That is, the dielectric plate 191 of the adapter board 19 is a silicon substrate. Since the process for fabricating the circuit 192 on a silicon substrate is highly precise, this solution can improve the precision of the circuit 192 on the adapter board 19.

[0080] 9 , in one embodiment of the present application, one side surface of the transfer plate 19 is pressed against the first die stack 121 , and the other side surface is fixed to the second die stack 122 via a film on wire die attach film (FOW DAF) that can cover the leads.

[0081] When configuring the adapter board, as shown in FIG8 , in one embodiment, one end of the line 192 is connected to the first die stack 121 on the surface of the adapter board 19 facing the first die stack 121, and the other end is connected to the second die stack 122 on the surface of the adapter board 19 facing the second die stack 122. Alternatively, as shown in FIG9 , in one embodiment, one end of the line 192 is connected to the first die stack 121 on the surface of the adapter board 19 facing the second die stack 122, and the other end is also connected to the second die stack 122 on the surface of the adapter board 19 facing the second die stack 122.

[0082] Similarly, in a specific embodiment, the number of dies 16 included in the first die stack 121 and the number of dies 16 included in the second die stack 122 are the same or differ by one. For example, if the number of dies 16 in the first die stack 121 is an even number, the number of dies 16 included in the first die stack 121 and the second die stack 122 can be the same, each being half the total number. If the number of dies 16 in the first die stack 121 is an odd number, the number of dies 16 included in the first die stack 121 and the second die stack 122 can differ by one. In short, the number of dies 16 included in the first die stack 121 and the second die stack 122 is kept as close as possible. This allows for a more uniform stress distribution of the electronic module 1 and minimizes the dimensions of the first die stack 121 and the second die stack 122 in a direction parallel to the first surface 113 of the printed circuit board 11. In other words, the areas of the orthographic projections of the first die stack 121 and the second die stack 122 on the first surface 113 of the printed circuit board 11 are minimized. This facilitates the arrangement of a larger number of electronic modules 12 on one printed circuit board 11.

[0083] FIG10 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application, and FIG11 is a schematic diagram of a partial structure of an electronic module in an embodiment of the present application. As shown in FIG10 and FIG11 , the electronic module further includes a third die stack 123. The third die stack 123 is located on a side of the second die stack away from the printed circuit board, and the third die stack 123 is connected to the second die stack. That is, in the embodiment of the present application, a larger number of die stacks may be included. Regardless of the number of die stacks, they are all connected to the circuit layer on the first surface of the printed circuit board via a set of first connection points. The stacking and connection method of the third die stack 123 and the second die stack are similar to the stacking and connection method of the second die stack and the first die stack, and will not be described in detail here.

[0084] For example, any two adjacent die in the third die stack 123 include an eleventh die and a twelfth die arranged in a direction away from the printed circuit board. As shown in FIG10 , in one embodiment, the eleventh die includes a sixth connection area and a sixth stacking area arranged in a direction away from the first connection point, the twelfth die covers the sixth stacking area, and the sixth connection area is connected to the lead. As shown in FIG11 , in another embodiment, the twelfth die includes a seventh connection area and a seventh stacking area arranged in a direction toward the first connection point, the eleventh die covers the seventh stacking area, and the seventh connection area is connected to the lead. The stacking method of the third die stack 123 can be selected according to actual needs.

[0085] In addition, a support plate or an adapter plate may be disposed between the third die stack 123 and the second die stack.

[0086] FIG12 is a schematic diagram of a partial structure of an electronic module according to an embodiment of the present application. Referring to FIG7 to FIG9 and FIG12, in a specific implementation of the present application, the electronic module 12 further includes a fourth die stack 124 and a fifth die stack 125. The fourth die stack 124 and the fifth die stack 125 each include multiple die stacked sequentially in a direction away from the printed circuit board, with any adjacent die stacks connected by leads. To connect the fourth die stack 124 and the fifth die stack 125, the second surface 114 of the printed circuit board 11 is provided with second connection points 116. The die 16 adjacent to the second surface 114 are connected to a set of second connection points 116. The second connection points 116 are connected to the first connection points 115 connected to the same electronic module 12, and the second connection points 116 are also connected to the circuit layer 112. The fourth die stack 124 and the fifth die stack 125 are connected to the same set of second connection points, and only the die adjacent to the printed circuit board in the fourth die stack 124 and the fifth die stack 125 are connected to the second connection points. The fourth die stack 124 is similar to the first die stack 121 and can have the technical features of the first die stack 121 in the above embodiment. The fifth die stack 125 is similar to the second die stack 122 and can have the technical features of the second die stack 122 in the above embodiment, which will not be described in detail here.

[0087] It can be understood that the first die stack 121, the second die stack 122, the fourth die stack 124 and the fifth die stack 125 in an electronic module 12 are respectively connected to the same circuit through a group of first connection points 115 and a group of second connection points 116, so that the die 16 of the electronic module 12 work together to form a complete electronic module 12.

[0088] In this embodiment, electronic module 1 has an equal number of dies 16. These dies 16 are distributed on both sides of printed circuit board 11, stacked into a larger number of die stacks. This results in a lower die stack height, or in other words, a smaller number of die 16 stacked. This shortens the distance between the die 16 and the connection points in the die stack, shortens the signal transmission path, improves signal integrity and data transmission speed, and enhances high-speed read and write performance of electronic module 1.

[0089] Please continue to refer to Figures 7 to 9 and 12. In the embodiment of the present application, the orthographic projection of the first connection point 115 on the second surface 114 and the second connection point 116 at least partially overlap. Specifically, the overlapping first connection point 115 and second connection point 116 refer to connection points connected to the same circuit of the circuit layer 112 of the printed circuit board 11, or in other words, the overlapping first connection point 115 and second connection point 116 refer to connection points for transmitting the same signal. Therefore, when the first connection point 115 and the second connection point 116 are connected, the wiring is shorter, which is conducive to further shortening the signal transmission path, improving signal integrity and data transmission speed, and the high-speed reading and writing performance of the electronic module 1 is better.

[0090] Referring to Figures 7-9 and 12, in the embodiment of the present application, the fourth die stack 124 is symmetrically arranged on either side of the printed circuit board with the first die stack, and the fifth die stack 125 is symmetrically arranged on either side of the printed circuit board with the second die stack. It is understood that to achieve symmetry between the first die stack 121 and the fourth die stack 124, stress distribution within the electronic module 1 is more uniform, the number of die stacks can be minimized, and the height of the first die stack 121 and the second die stack 122 can be reduced, thereby shortening the signal transmission link length. Furthermore, this solution reduces the total orthographic projection area of ​​the electronic modules 12 on the first surface 113 of the printed circuit board 11, facilitating the placement of a larger number of electronic modules 12 on a single printed circuit board 11.

[0091] FIG13 is a schematic diagram of a partial structure of an electronic module according to an embodiment of the present application. As shown in FIG13 , in one embodiment, the die stacks on both sides of the printed circuit board 11 may not be symmetrically arranged. As shown in FIG13 , the number of die included in the first die stack 121 is different from the number of die 16 included in the fourth die stack 124, and the number of die included in the second die stack 122 is different from the number of die 16 included in the fifth die stack 125. Specific designs can be made based on actual product requirements.

[0092] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An electronic module, characterized in that: Consists of a printed circuit board and an electronic module, wherein: The printed circuit board includes a circuit layer; the printed circuit board includes a first surface, the first surface is provided with a first connection point, and the first connection point is connected to the circuit layer; The electronic module includes a first die stack and a second die stack, wherein the first die stack and the second die stack respectively include a plurality of die stacked in sequence in a direction away from the printed circuit board, and any adjacent stacked die are connected by leads; The first die stack and the second die stack are connected to the same set of the first connection points, and only the dies adjacent to the printed circuit board in the first die stack and the second die stack are connected to the first connection points.

2. The electronic module according to claim 1, wherein: The first die stack and the second die stack are symmetrically arranged on both sides of the first connection point.

3. The electronic module according to claim 1 or 2, wherein: Any two adjacent bare chips in the first bare chip stack include a first bare chip and a second bare chip arranged in a direction away from the printed circuit board, a surface of the first bare chip facing away from the printed circuit board includes a first connection area and a first stacking area, the first connection area and the first stacking area are arranged in a direction away from the first connection point, the second bare chip covers the first stacking area, and the first connection area is connected to the lead.

4. The electronic module according to claim 1, wherein: The second die stack is located on a side of the first die stack away from the printed circuit board, the second die stack is connected to the first die stack, and only the die adjacent to the printed circuit board in the first die stack is connected to the first connection point; Any two adjacent die in the first die stack include a third die and a fourth die arranged in a direction away from the printed circuit board, the third die includes a second connection area and a second stacking area arranged in a direction away from the first connection point, the fourth die covers the second stacking area, and the second connection area is connected to the lead; Any two adjacent die in the second die stack include a fifth die and a sixth die arranged in a direction away from the printed circuit board, the sixth die includes a third connection area and a third stacking area arranged in a direction away from the first connection point, the fifth die covers the third stacking area, and the third connection area is connected to the lead.

5. The electronic module according to claim 4, wherein: A support plate is provided between the first die stack and the second die stack, the support plate covering a stacking area of ​​dies adjacent to the second die stack in the first die stack and a stacking area of ​​dies adjacent to the first die stack in the second die stack; The connection region of the die adjacent to the second die stack in the first die stack is spaced apart from the connection region of the die adjacent to the first die stack in the second die stack by a predetermined distance and is connected via wires.

6. The electronic module according to claim 1, wherein: The second die stack is located on a side of the first die stack away from the printed circuit board, the first die stack and the second die stack are connected, and only the die in the first die stack adjacent to the printed circuit board is connected to the first connection point; Any two adjacent die in the first die stack include a seventh die and an eighth die arranged in a direction away from the printed circuit board, the seventh die includes a fourth connection area and a fourth stacking area arranged in a direction away from the first connection point, the eighth die covers the fourth stacking area, and the fourth connection area is connected to the lead; Any two adjacent bare chips in the second bare chip stack include a ninth bare chip and a tenth bare chip arranged in a direction away from the printed circuit board, the ninth bare chip includes a fifth connection area and a fifth stacking area arranged in a direction toward the first connection point, the tenth bare chip covers the fifth stacking area, and the fifth connection area is connected to the lead.

7. The electronic module according to claim 6, wherein: An adapter board is provided between the first die stack and the second die stack. The adapter board includes a dielectric board and a circuit located on the dielectric board. One end of the circuit is connected to a die adjacent to the second die stack in the first die stack, and the other end of the circuit is connected to a die adjacent to the first die stack in the second die stack.

8. The electronic module according to claim 7, wherein: The dielectric plate is a silicon substrate.

9. The electronic module according to claim 7 or 8, wherein: One end of the circuit is connected to the first die stack on a surface of the adapter plate facing the first die stack, and the other end is connected to the second die stack on a surface of the adapter plate facing the second die stack; Alternatively, one end of the line is connected to the first die stack on a surface of the interposer facing the second die stack, and the other end is also connected to the second die stack on a surface of the interposer facing the second die stack.

10. The electronic module according to any one of claims 1 to 9, wherein: The number of dies included in the first die stack and the number of dies included in the second die stack are the same or differ by one.

11. The electronic module according to any one of claims 1 to 10, wherein: The electronic module further includes a third die stack located on a side of the second die stack away from the printed circuit board, and the third die stack is connected to the second die stack.

12. The electronic module according to claim 11, wherein: Any two adjacent die in the third die stack include an eleventh die and a twelfth die arranged in a direction away from the printed circuit board, wherein: The eleventh die includes a sixth connection area and a sixth stacking area arranged in a direction away from the first connection point, the twelfth die covers the sixth stacking area, and the sixth connection area is connected to the lead; Alternatively, the twelfth die includes a seventh connection region and a seventh stacking region arranged in a direction toward the first connection point, the eleventh die covers the seventh stacking region, and the seventh connection region is connected to a lead.

13. The electronic module according to any one of claims 1 to 12, wherein: The printed circuit board further includes a second surface, the second surface being away from the first surface, the second surface being provided with a second connection point, the second connection point being connected to the first connection point connected to the same electronic module; The electronic module further includes a fourth die stack and a fifth die stack, wherein the fourth die stack and the fifth die stack respectively include a plurality of die stacked sequentially in a direction away from the printed circuit board, and any adjacent stacked die are connected by leads; The fourth die stack and the fifth die stack are connected to the same set of the second connection points, and only the dies adjacent to the printed circuit board in the fourth die stack and the fifth die stack are connected to the second connection points.

14. The electronic module according to claim 13, wherein: The orthographic projection of the first connection point on the second surface at least partially coincides with the second connection point.

15. The electronic module according to claim 13 or 14, wherein: The fourth die stack and the first die stack are symmetrically arranged on two sides of the printed circuit board, and the fifth die stack and the second die stack are symmetrically arranged on two sides of the printed circuit board.

16. The electronic module according to any one of claims 1 to 15, wherein: The total number of bare chips included in the electronic module is greater than or equal to 8.

17. The electronic module according to any one of claims 1 to 16, wherein: The electronic module is a storage module, and the bare chip is a storage chip.

18. The electronic module according to any one of claims 1 to 17, wherein: The printed circuit board is further connected with electronic components and connection ports, and the electronic components and the connection ports are respectively connected to the circuit layer.

19. The electronic module according to claim 18, wherein: The connection port is a gold finger connector.

20. The electronic module according to any one of claims 1 to 19, wherein: The electronic module includes at least two electronic modules, and all the electronic modules are arranged on the same printed circuit board.

21. An electronic device, characterized in that: The electronic module comprises a housing and the electronic module according to any one of claims 1 to 20, wherein the electronic module is arranged in the housing.

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