Pixel structure with floating transfer gate for charge sensing

Abstract

The present invention relates to a pixel structure (1) comprising a photosensitive device (16), adapted for generating charges on incidence of radiation, such as a pinned photodiode, a photogate or a CCD element, and a floating gate (12) that is touching the photosensitive device. The pixel structure (1) is adapted to measure charge at or under the floating gate (12), and this repeatedly and non-destructively.

Description

[0001] Pixel structure with floating transfer gate for charge sensing

[0002] Technical field of the invention

[0003] The present invention relates to the field of image sensors, and more particularly to pixel structures and the readout of said pixel structures.

[0004] Background of the invention

[0005] The field of imaging technology has seen remarkable advancements over the years, particularly in the development of sensors capable of capturing images with high resolution and sensitivity. A critical component of many imaging sensors is the photosensitive device, which may, for example, be a pinned photodiode, a photogate or a CCD element, which converts radiation, e.g., light, into an electrical charge. Among the various types of photosensitive devices, the pinned photodiode has become a staple in modern imaging due to its low dark current and high quantum efficiency.

[0006] The process of reading out charges generated in a photosensitive device is a delicate task that requires precision and accuracy. The goal is to measure the generated charge or photocharge with minimal noise and distortion, ensuring that the resulting image is as close to the original scene as possible. This is particularly important in applications where image quality is paramount, such as in scientific imaging, astronomy, medical diagnostics, and high-end photography.

[0007] In the realm of photosensitive device readout, noise is a significant challenge. Various types of noise, including thermal noise, shot noise, and 1 / f noise, can degrade the quality of the signal read from the photodiode. Reducing noise is therefore a critical objective in the design of readout circuits and systems.

[0008] Another challenge in the field is the complexity of the readout circuitry. Furthermore, the speed of readout is an important factor, especially for applications requiring high frame rates or real-time imaging. The readout circuit must be able to operate quickly without sacrificing the accuracy of the charge measurement.

[0009] Despite the progress made in the field, including the integration of non-destructive readout capabilities and the development of techniques to reduce readout noise, there remains a need for further advancements. These advancements would ideally address the challenges of noise reduction, circuit complexity, and readout speed, without compromising the accuracy and quality of the charge measurement in photosensitive devices. The pursuit of such improvements continues to drive innovation in the field of imaging sensor technology.

[0010] There is thus still a need in the art for devices and methods that address at least some of the above problems.

[0011] Summary of the invention

[0012] It is an object of embodiments of the present invention to enhance the accuracy of charge readout from a photosensitive device, adapted for generating charges on incidence of radiation, such as a pinned photodiode, a photogate or a CCD element. This objective is accomplished by a pixel structure with a photosensitive device and a floating gate in contact with the photosensitive device according to the invention, and by a method for reading out such pixel structure.

[0013] It is an advantage of embodiments of the present invention that a simplified pixel structure can be realized by incorporating a single floating gate that interacts with a photosensitive device such as a pinned photodiode, thereby streamlining the design and potentially reducing manufacturing complexity. It is an advantage of embodiments of the present invention that modulation of the floating gate voltage can facilitate the non-destructive transfer of charges or charge packets between the photosensitive device and the (inversion layer or charge packet under the) floating gate, allowing for repeated measurements without loss of charge, which can be beneficial for applications requiring high precision.

[0014] It is an advantage of embodiments of the present invention that the ability to measure the mirror charge on the floating gate both in the presence and absence of the charges at or under the floating gate can lead to an accurate determination of the amount of charges under the floating gate (so of the amount of (photo)charges generated in the photosensitive device), contributing to a reduction in readout noise and an improvement in signal fidelity. It is an advantage of embodiments of the present invention that the averaging of multiple measurements of the difference in mirror charges can significantly reduce the impact of 1 / f noise and other types of interference, resulting in cleaner and more reliable data.

[0015] In a first aspect, embodiments of the present invention relate to a pixel structure comprising a photosensitive device, adapted for generating charges on incidence of radiation, such as a pinned photodiode, a photogate or a CCD element, and a floating gate in contact with the photosensitive device. The pixel structure is adapted to measure charge at or underthe floating gate. A floating gate is a conductive node that is electrically isolated within a semiconductor device. Since it is not directly connected to any circuit, it may retain charge for a long period of time. In the context of the present invention, the floating gate can be temporarily connected to other components, for instance by means of a switch, but can also be decoupled and left floating. The floating gate may be a drainless transfer gate, hence a structure built up like a typical transfer gate, but without drain being present.

[0016] Said being in contact, or touching, of the floating gate and the photosensitive device means that the pixel structure is adapted so that charges may move between the photosensitive device and the floating gate. More in particular, said touching typically indicates the capability for charge transfer between the photosensitive device and an inversion layer or charge packet of or under the floating gate. Preferably, charges may move directly between the photosensitive device and an inversion layer or charge packet of or under the floating gate. This capability allows for non-destructive back and forth transfer of charge between the photosensitive device and the floating gate.

[0017] In embodiments of the present invention, “radiation” may be interpreted as radiation of any type. The radiation can be electro-magnetic or of particle nature. The radiation may for instance be X-rays or gamma rays, or radiation within the range between far infrared to ultraviolet such as for instance visible light. Alternatively, the radiation may be particles, including low or high energy electrons, photons, hadrons or other particles.

[0018] In embodiments, the pixel structure may comprise a modulation arrangement adapted for modulating a voltage at the floating gate between at least a first voltage level (e.g. high ) and a second voltage level (e.g. low ) to control transfer of charges between the photosensitive device and the floating gate. The pixel structure may further comprise a measurement arrangement adapted for measuring an electrical parameter related to charge, such as an integrated charge at or current through the floating gate, when the floating gate is at a first state and when it is at a second state. The pixel structure may further comprise a processing arrangement configured to determine a difference between the measurements corresponding to the first and second states, wherein the difference represents the amount of charge generated by the photosensitive device.

[0019] In embodiments, the modulation arrangement is adapted for modulating said voltage on the floating gate between the first voltage level being a high voltage level which is sufficiently high to be able to attract the charges, when present, from the photosensitive device to an inversion layer of or charge packet under the floating gate, and the second voltage level being a low voltage level which is sufficiently low to repel the charges (from the inversion layer or charge packet) into the photosensitive device, wherein movement of (negative = electrons) charges is induced in the direction of the higher voltage. This embodiment provides the advantage of enabling the modulation of the floating gate's voltage to control the transfer of charge, which can improve the accuracy of charge measurement by averaging a plurality of measurements. The electrical parameter related to charge, e.g. the integrated charge at or current through the floating gate, may be measured both in the first state, in this embodiment when the floating gate is at the first (high) voltage level, when the charges are attracted to the floating gate or present at (or under) the floating gate, and in the second state, in this embodiment when the floating gate is at the second (low) voltage level, when the charges are repelled from the floating gate. By, thus, modulating between the high and low state, thereby moving the charges back and forth between the photosensitive device and the floating gate a plurality of times, and measuring the integrated charge at or current through the floating gate each time the floating gate is at the first and second state, the electrical parameter related to charge (integrated charge at or current through the floating gate), and thus the charge in the photosensitive device (typically generated by said incident radiation), may be averaged over a plurality of measurements. Thereby, a determination of the charge in the photosensitive device at a low 1 / f noise may be obtained.

[0020] In embodiments, the modulation arrangement may be adapted for applying said voltage modulation at the floating gate by applying a modulation voltage to the substrate under the floating gate. In alternative embodiments, the modulation arrangement may be adapted for applying said voltage modulation at the floating gate by applying a modulation voltage directly to the floating gate.

[0021] In particular embodiments, the modulation arrangement may comprise a charge transimpedance amplifier, a capacitive coupling, or a direct connection to a voltage.

[0022] The modulation arrangement may be adapted for applying said voltage modulation via a virtual ground of the charge transimpedance amplifier, wherein said measured electrical parameter is based on a voltage across a capacitor in a feedback loop of the charge transimpedance amplifier. The advantage of this embodiment is that it allows for precise charge measurement through the use of a charge transimpedance amplifier, which can result in improved signal-to-noise ratio.

[0023] In embodiments, the pixel structure may comprise a charge transimpedance amplifier that includes a first transistor at the pixel, and further transistors in a column amplifier. This embodiment provides the advantage of localized amplification at the pixel level, which can lead to reduced readout noise and improved image quality.

[0024] In embodiments, the charge transimpedance amplifier may be a differential amplifier. A differential amplifier provides good noise rejection.

[0025] In alternative embodiments, the charge transimpedance amplifier is a class A amplifier. The class A amplifier may comprise a negative input being the gate of a first transistor and a positive input from a source terminal of said first transistor. The advantage of this embodiment is the stable operation of the charge transimpedance amplifier, which can contribute to consistent and reliable charge measurement.

[0026] In embodiments, said first transistor may be adapted to be reconfigured to serve as a source follower for classic pixel readout through a transfer gate and a floating diffusion. The advantage of this embodiment is the flexibility of the pixel structure, allowing for different readout modes to suit various imaging applications. The readout method using the floating gate yields low noise at the cost of multiple readout, thus low speed. The “classic” readout (using the source follower) offers high speed yet higher noise, and can have a large full well charge. The combination of the signals of the method using the floating gate and the classic readout can result in a “high dynamic range” signal.

[0027] In embodiments, the charge transimpedance amplifier is a differential amplifier.

[0028] In embodiments, the processing arrangement may be adapted for determining the voltage difference between measurements at an output of the charge transimpedance amplifier, corresponding to said first state and said second state, a plurality of times. Although the voltage difference may be influenced directly by said setting voltage modulation, the measured voltage difference may be influenced by the presence of the integrated charge at or current through the floating gate, so that the amount of charge generated in the photosensitive device may be determined from said voltage difference.

[0029] In embodiments, the modulation arrangement may be adapted for applying said voltage modulation at the floating gate by applying a modulated voltage on a positive input of the charge transimpedance amplifier.

[0030] In embodiments, the measurement arrangement may be adapted for measuring a mirror charge (which is a mirror charge on the floating gate resulting from the charges under the floating gate) by measuring a potential difference on the floating gate by measuring an output of the charge transimpedance amplifier. The advantage of this embodiment is the simplified control of the charge transimpedance amplifier, which can facilitate easier integration into imaging systems. This embodiment offers the advantage of direct measurement of the mirror charge, which can lead to a more accurate determination of the amount of charges or photocharges under the floating gate.

[0031] In embodiments, the measurement arrangement is adapted to measure a voltage across a capacitor in a feedback loop of the charge transimpedance amplifier.

[0032] In embodiments, the measurement arrangement may be adapted for sensing the electrical parameter relating to charge, e.g. the charge or charge difference, at the floating gate by detecting a voltage at the floating gate by a charge or voltage amplifier, or a buffer amplifier such as for instance a source follower. The advantage of this embodiment is simplicity and enhanced sensitivity to charge variations at the floating gate, which can improve the dynamic range of the sensor.

[0033] In embodiments, the floating gate may be “floating” in the sense that it may be “floating” with respect to an applied modulated voltage. In embodiments, the pixel structure may be adapted for modulating said voltage on the floating gate by capacitive coupling. In embodiments, the floating gate is called “floating” as it is, at least during part of the cycle (e.g., at least when the voltage modulation is in the high state and preferably also when it is in the low state) or during the complete cycle, typically not electrically connected to a voltage or current source, except by capacitive coupling. Floating gate is a historical term from the CCD era, wherein one presets a gate or CCD gate to a certain potential, and then leaves it floating (e.g., disconnected from any voltage supply). Eventual deposition of charges to the other side of the gate (thus the CCD channel for a CCD, or the inversion layer for a MOS structure) will cause a potential shift (e.g., as a result of mirror charge) to the gate, and can thus be sensed by a voltage follower or by a charge transimpedance amplifier (which may in fact be also a voltage follower, but with a feedback to keep the gate potential constant). In embodiments of the present invention, the modulated voltage may be applied via a capacitive coupling to the floating gate, so that the floating gate may be conceived as “floating” with respect to the applied modulated voltage. The voltage on the floating gate itself is influenced by the presence of the (photo)charge at or under the floating gate (e.g., via mirror charges on the floating gate resulting from said photocharge), which may therefore be sensed to determine the (photo)charge at or under the floating gate.

[0034] In embodiments of the present invention, the floating gate may also be called a floating “transfer” gate. A transfer gate on its own is typically a MOS structure. A transfer gate plus, e.g., the photosensitive device, such as the pinned photodiode, acting as source, and a drain which is typically an n-junction, is a full MOSFET. In embodiments of the present invention, the floating gate is typically not a full MOSFET as the floating gate or floating transfer gate typically contains no drain. The drain could result in charges from the floating gate being lost via said drain, which is unwanted. A floating gate that is touching a pinned photodiode may be called a “floating transfer gate” (FTG). The floating gate or floating transfer gate of embodiments of the present invention lacking a drain may be seen as an incomplete transistor. The photosensitive device may touch (or act as source for) the floating gate or floating transfer gate partially, or may completely surround it.

[0035] In embodiments, the floating gate is a vertical transfer gate. Vertical transfer gates are seen recently in very small pixels as used in smartphone cameras. The advantage of this embodiment is the potential for reduced pixel size and increased pixel density, which can lead to implementation on higher resolution imaging sensors. In embodiments, the floating gate is a depletion transistor, a buried channel transistor, a CCD electrode, a SOI transistor, a FINFET, or a JFET.

[0036] In embodiments, the photosensitive device is any of a pinned photodiode, a photogate and a CCD element.

[0037] In embodiments, the photosensitive device is a storage node of a global shutter pixel. The advantage of this embodiment is the ability to capture images without distortion caused by motion, which is particularly beneficial for high-speed imaging applications. The storage node as in global shutter pixels, may be used as sample and hold stages in the pixel for various purposes, and may even be used not for global shutter operation, rather rolling shutter operation or other modes of operation.

[0038] The pixel structure according to embodiments of the present invention may further comprise a flush gate for removing charge from the photosensitive device to a drain region.

[0039] The pixel structure according to embodiments of the present invention may further comprise a nonfloating transfer gate adjacent to the photosensitive device. The non-floating transfer gate may be configured to transfer charges to and from the photosensitive device by being biased between a high voltage and a low voltage. In embodiments, the measurement arrangement may be adapted for measuring the electrical parameter related to charge when the floating gate is at the first state, being a high voltage level at the floating gate while the non-floating gate is biased high, and when it is at the second state, being a high voltage level at the floating gate when the non-floating gate is being or has been biased or pulsed low.

[0040] In a pixel structure according to embodiments of the present invention, the processing arrangement may be configured to perform multiple cycles of the modulating and measuring steps and to average the determined differences to reduce noise.

[0041] In the second aspect, embodiments of the present invention relate to an image sensor comprising an array of pixel structures in accordance with any embodiments of the first aspect.

[0042] In embodiments, multiple of the pixel structures in the array may share a single modulation arrangement and a single measurement arrangement. The modulation arrangement and the measurement arrangement may be implemented, together, as a charge transimpedance amplifier or voltage amplifier.

[0043] In the third aspect, embodiments of the present invention relate to a method for determining an amount of charge generated by a photosensitive device. The method comprises alternatingly biasing the voltage at a floating gate in contact with the photosensitive device between at least a first and a second voltage level to control transfer of charges between the photosensitive device and the floating gate. The method further comprises measuring an electrical parameter related to the charge at the floating gate, e.g. integrated charge at or current through the floating gate, both when the floating gate is at a first state and when the floating gate is at a second state. The method further comprises determining a difference between the measurements corresponding to the first and second states, said difference being representative for the amount of charge attracted and repelled by the floating gate.

[0044] In embodiments, measuring the electrical parameter related to charge at the floating gate when the floating gate is at the first state may comprise measuring the electrical parameter when the floating gate biased to a high voltage level and measuring the electrical parameter related to the charge at the floating gate when the floating gate is at the second state may comprise measuring the electrical parameter when the floating gate is biased to a low voltage level.

[0045] In alternative embodiments, the method may further comprise alternatingly biasing the voltage at a non-floating gate in contact with the photosensitive device between at least a first voltage level and a second voltage level to control transfer of charges between the photosensitive device and the non-floating gate. In such embodiments, measuring the electrical parameter related to the charge at the floating gate when the floating gate is at the first state may comprise measuring the electrical parameter when the floating gate is biased to a high voltage level while the non-floating gate is biased high, and measuring the electrical parameter related to the charge at the floating gate when the floating gate is at the second state may comprise measuring the electrical parameter when the floating gate is biased to a high voltage level when the non-floating gate is being or has been biased or pulsed low.

[0046] Said cycle of said biasing, said measuring and said determining the difference may be repeated a number (e.g., from 1 to several thousands) of times, hence multiple times. By averaging the difference results for the different cycles, an accurate value for the charge generated in the photosensitive device may be obtained, as noise may be reduced. Thereafter, the charge in the photosensitive device may be flushed towards a drain.

[0047] In embodiments of the third aspect, measuring the electrical parameter may comprise measuring a voltage across a capacitor in a feedback loop of a charge transimpedance amplifier. The method may then further comprise resetting the voltage across the capacitor prior to biasing the voltage at the floating gate.

[0048] When, in embodiments of the present invention, is spoken of an inversion layer or charge packet of the floating gate, reference is typically be made to an inversion layer or charge packet associated with the floating gate, that may be formed in the proximity of the floating gate, e.g., under the floating gate, such as in a substrate over which the floating gate is located. A normal floating gate or photogate typically has an inversion layer, whereas a buried channel CCD typically does not have an inversion layer, rather a charge packet in the buried channel. The location where the charge may be located at or under the floating gate in absence of an inversion layer, e.g., in case of a buried channel CCD (when the voltage at the floating gate is high), is, here, called the charge packet.

[0049] In a further aspect, embodiments of the present invention relate to the use of a pixel structure according to embodiments of the first aspect in an imaging device.

[0050] Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0051] The above and other characteristics, features and advantages of embodiments of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. This description is given for the sake of example only, without limiting the scope of the invention. The reference figures quoted below refer to the attached drawings.

[0052] Brief description of the drawings

[0053] FIG. 1 is a schematic diagram of the cross section of a first exemplary pixel structure with a photosensitive device in accordance with embodiments of the present invention.

[0054] FIG. 2 is a timing diagram illustrating the operation of the first exemplary pixel structure of FIG. 1 .

[0055] FIG. 3A and 3B are a schematic diagram of the cross section of a second exemplary pixel structure with a photosensitive device in accordance with embodiments of the present invention, when the modulated voltage is high and low, respectively.

[0056] FIG. 4 is a schematic diagram of the cross section of a third exemplary pixel structure with a photosensitive device in accordance with embodiments of the present invention, wherein the charge transimpedance amplifier is a class A amplifier.

[0057] FIG. 5A is a schematic diagram of the cross section of a fourth exemplary pixel structure with a photosensitive device in accordance with embodiments of the present invention, using a CCD-type of floating gate readout.

[0058] FIG. 5B is a timing diagram illustrating the operation of the fourth exemplary pixel structure of FIG. 5B.

[0059] FIG. 6A and 6B are schematic representations of, respectively, a top view and vertical cross- sectional view of part a pixel structure in accordance with embodiments of the present invention, wherein the pixel structure surrounds the floating gate, wherein the photosensitive device is a pinned photodiode.

[0060] FIG. 7A and 7B are schematic representations of, respectively, a top view and vertical cross- sectional view of part a pixel structure in accordance with embodiments of the present invention, wherein the pixel structure surrounds the floating gate, wherein the photosensitive device is a photogate or surface channel CCD.

[0061] FIG. 8A and 8B are schematic representations of, respectively, a top view and vertical cross- sectional view of part a pixel structure in accordance with embodiments of the present invention, wherein the pixel structure surrounds the floating gate, wherein the photosensitive device is a buried channel CCD.

[0062] FIG. 9 is a schematic representation of a top view of a pixel structure in accordance with embodiments of the present invention, wherein the floating gate is touching the photosensitive device but is not surrounded thereby.

[0063] FIG. 10 to 12 are schematic representations of pixel structures in accordance with embodiments of the present invention, using different types of circuitry in the periphery to achieve a different type of signal readout from the pixel structures.

[0064] FIG. 13 contains an upper graph showing the signal or voltage that is applied to the pixel structure, and a lower graph that shows the signal at the output of the charge transimpedance amplifier as a function of the number of charges under the floating gate.

[0065] FIG. 14 is a schematic diagram of a pixel structure expanded with an overflow capacitor for high dynamic range operation according to embodiments of the present invention.

[0066] FIG. 15 is a schematic diagram of a pixel structure where the diode to which the floating gate is connected is the storage node of a global shutter pixel according to embodiments of the present invention, wherein the storage node is similar to a pinned photodiode and is located between the global shutter transfer gate (TG1 ) and the serial readout transfer gate (TG2). FIG. 16 is a schematic diagram of a pixel structure where the diode to which the FTG is connected is the storage node of a global shutter pixel according to embodiments of the present invention, wherein the storage node is similar to a pinned photodiode and is located partially below the global shutter transfer gate (TG1 ).

[0067] FIG. 17 is a schematic diagram of a pixel structure where the diode to which the FTG is connected is the storage node of a global shutter pixel according to embodiments of the present invention, wherein the storage node is a CCD gate between the global shutter transfer gate and serial readout transfer gate.

[0068] FIG. 18 is a schematic diagram illustrating a plurality of pixel structures sharing a single charge transimpedance amplifier according to embodiments of the present invention.

[0069] FIG. 19 is a schematic diagram of a pixel structure with a second non-floating drainless transfer gate according to embodiments of the present invention.

[0070] FIG. 20A is a schematic diagram of a pixel structure variant with the floating gate biased low by connecting to a low voltage according to embodiments of the present invention.

[0071] FIG. 20B is a schematic diagram of the pixel structure of FIG. 20A with the floating gate biased high according to embodiments of the present invention.

[0072] FIG. 21 is a timing diagram for the operation of the pixel structures of FIG. 20A and FIG. 20B according to embodiments of the present invention.

[0073] FIG. 22A is a schematic diagram of a pixel structure with a second non-floating gate and the floating gate readout by a sense amplifier according to embodiments of the present invention. FIG. 22B is a schematic diagram of the pixel structure of FIG. 22A in a different phase of operation according to embodiments of the present invention.

[0074] FIG. 23 is a timing diagram for the operation of the pixel structures of FIG. 22A and FIG. 22B according to embodiments of the present invention.

[0075] In the different figures, the same reference signs refer to the same or analogous elements.

[0076] Description of illustrative embodiments

[0077] The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.

[0078] Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, eithertemporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

[0079] Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.

[0080] It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. The term “comprising” therefore covers the situation where only the stated features are present and the situation where these features and one or more other features are present. The word “comprising” according to the invention therefore also includes as one embodiment that no further components are present. Thus, the scope of the expression “a device comprising means A and B” should not be interpreted as being limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

[0081] Similarly, it is to be noticed that the term “coupled”, also used in the claims, should not be interpreted as being restricted to direct connections only. The terms “coupled” and “connected”, along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Thus, the scope of the expression “a device A coupled to a device B” should not be limited to devices or systems wherein an output of device A is directly connected to an input of device B. It means that there exists a path between an output of A and an input of B which may be a path including other devices or means. “Coupled” may mean that two or more elements are either in direct physical or electrical contact, or that two or more elements are not in direct contact with each other but yet still co-operate or interact with each other.

[0082] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0083] Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

[0084] Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0085] Furthermore, some of the embodiments are described herein as a method or combination of elements of a method that can be implemented by a processor of a computer system or by other means of carrying out the function. Thus, a processor with the necessary instructions for carrying out such a method or element of a method forms a means for carrying out the method or element of a method. Furthermore, an element described herein of an apparatus embodiment is an example of a means for carrying out the function performed by the element for the purpose of carrying out the invention.

[0086] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well- known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0087] The following terms are provided solely to aid in the understanding of the invention.

[0088] As used herein, and unless otherwise specified, the term "floating gate" refers to a gate electrode that is electrically isolated and capable of storing electrical charge, thereby influencing the conductivity of the underlying semiconductor material without direct electrical connection.

[0089] As used herein, and unless otherwise specified, the term "non-floating transfer gate" refers to a gate electrode that is directly connected to a control voltage source and is not electrically isolated like a floating gate. It is used to control the transfer of charges by being biased between different voltage levels.

[0090] As used herein, and unless otherwise specified, the term "photosensitive device" refers to a component that generates electrical charges in response to incident radiation, such as light. Examples of photosensitive devices include photodiodes, pinned photodiodes, photogates, and charge-coupled device (CCD) elements.

[0091] As used herein, and unless otherwise specified, the phrase "in contact with" refers to a configuration where the floating gate and the photosensitive device are arranged such that charge can be transferred between them. This includes direct physical contact, electrical coupling, or proximity sufficient for charge interaction.

[0092] As used herein, and unless otherwise specified, the term "modulation arrangement" refers to a system or circuitry configured to vary or modulate the voltage at the floating gate between at least two voltage levels (high and low) to control the transfer of charges between the photosensitive device and the floating gate.

[0093] As used herein, and unless otherwise specified, the term "measurement arrangement" refers to a system or circuitry adapted to measure an electrical parameter related to the charge at the floating gate. This can include measuring voltage, current, or accumulated charge, using devices such as amplifiers, capacitors, or analog-to-digital converters.

[0094] As used herein, and unless otherwise specified, the term "processing arrangement" refers to a system or circuitry configured to process measurement data, specifically to determine a difference between measurements corresponding to different voltage levels at the floating gate. This can include microprocessors, digital signal processors, or dedicated hardware.

[0095] As used herein, and unless otherwise specified, the phrase "electrical parameter related to charge" refers to any measurable electrical quantity that reflects the amount of charge, such as voltage across a capacitor, current flowing through a component, or accumulated charge at a node.

[0096] As used herein, and unless otherwise specified, the term "inversion layer" refers to a region in a semiconductor material underneath a gate where the type of charge carriers is inverted due to an applied electric field, creating a conductive channel under the gate that can attract and store charges.

[0097] As used herein, and unless otherwise specified, the term "charge packet" refers to a discrete quantity of electrical charge that can be transferred between components within the pixel structure, such as between the photosensitive device and the floating gate.

[0098] As used herein, and unless otherwise specified, the terms "high voltage" and "low voltage" refer to specific voltage levels applied to the floating gate. The "high voltage" is a voltage level adapted to attract charges from the photosensitive device to the floating gate, while the "low voltage" is a voltage level adapted to repel charges from the floating gate back to the photosensitive device. As used herein, and unless otherwise specified, the term "charge transimpedance amplifier" refers to an amplifier that converts input charge into an output voltage, typically using a feedback element like a capacitor to measure the charge transferred to or from the floating gate.

[0099] As used herein, and unless otherwise specified, the phrase "virtual ground of a charge transimpedance amplifier" refers to a node within the amplifier circuitry that is maintained at a constant reference potential, allowing accurate measurement of currents or charges by providing a stable point for charge transfer.

[0100] As used herein, and unless otherwise specified, the term "pinned photodiode" refers to a type of photodiode with a specific structure that reduces dark current and improves image quality by "pinning" the voltage at the photodiode's surface to a fixed potential, typically through the use of a doping profile that creates a potential well for photo-generated carriers. This term encompasses all variations of photodiodes that use a pinning layer or technique to achieve low dark current and noise characteristics.

[0101] As used herein, and unless otherwise specified, the term "mirror charge" refers to a charge that is induced on a conductive structure, such as the floating gate, as a result of capacitive coupling with another charge. This term includes the concept of a charge that is not directly transferred but is instead mirrored or replicated on the floating gate due to the electrical potential difference between the floating gate and another charged entity, such as (the charge from) the photosensitive device or the pinned photodiode being present at the floating gate (e.g., in the inversion layer under the floating gate).

[0102] As used herein, and unless otherwise specified, the phrase "capacitive coupling" refers to the transfer of energy or signals between two electrical conductors through a capacitance between them, without direct electrical contact.

[0103] As used herein, and unless otherwise specified, the term "vertical transfer gate" refers to a gate structure that allows charge transfer in a direction perpendicular to the substrate surface, facilitating movement of charge carriers vertically within the semiconductor material.

[0104] As used herein, and unless otherwise specified, the term "buffer amplifier" refers to an amplifier used to isolate the input signal from the output, providing high input impedance and low output impedance. A "source follower" is a specific type of buffer amplifier where the output voltage follows the input voltage, often implemented using a field-effect transistor.

[0105] As used herein, and unless otherwise specified, the term "global shutter pixel" refers to a pixel architecture in which all pixels in an image sensor capture light simultaneously, and the term "storage node" refers to a component within the pixel structure that temporarily holds the generated charges before readout.

[0106] As used herein, and unless otherwise specified, the term "flush gate" refers to a gate electrode used to remove or "flush" excess charges from the photosensitive device to a drain region, effectively resetting the device. The "drain region" is a part of the semiconductor where charges are collected and removed from the pixel structure.

[0107] As used herein, and unless otherwise specified, the phrase "perform multiple cycles of the modulating and measuring steps and to average the determined differences to reduce noise" refers to repeating the modulation and measurement process several times and calculating the average of the measurements to minimize random noise and improve signal accuracy.

[0108] As used herein, and unless otherwise specified, the phrase "alternatingly biasing" refers to the process of varying the voltage applied to the floating gate between at least a first voltage level and a second voltage level in an alternating sequence to control the transfer of charges.

[0109] As used herein, and unless otherwise specified, the phrase "resetting the voltage across the capacitor prior to biasing the voltage at the floating gate" refers to discharging or initializing the capacitor in the feedback loop of the charge transimpedance amplifier to a known starting voltage before commencing the modulation of the floating gate voltage.

[0110] As used herein, and unless otherwise specified, the term "substrate" refers to the base material, typically a semiconductor material such as for instance silicon or silicon germanium, a lll-V semiconductor material such as gallium arsenide, or a lll-VI semiconductor material such as gallium selenide, upon which the pixel structure and associated components are fabricated, providing structural support and electrical properties necessary for device operation. In hybrid detectors, two substrates may be present, a first substrate on or in which the photosensitive element is provided, and a second substrate on or in which the readout circuitry is built (e.g. CMOS ROIC).

[0111] It will be clear for a person skilled in the art that wherever n-type or -doped layers or devices, e.g., nMOSFETs, are mentioned, equivalent circuits can be devised with p-type or -doped layers or devices, e.g., pMOSFETs, and vice versa. Similarly, it will be clear for a person skilled in the art that wherever n-doped regions touching p-doped regions are mentioned, equivalent circuit with inversed polarity can be devised, i.e. , p-doped regions touching n-doped regions.

[0112] The invention will now be described by a detailed description of several embodiments of the invention. It is clear that other embodiments of the invention can be configured according to the knowledge of persons skilled in the art without departing from the technical teaching of the invention, the invention being limited only by the terms of the appended claims.

[0113] In a first aspect, embodiments of the present invention relate to a pixel structure comprising a photosensitive device, adapted for generating charges on incidence of radiation, such as a pinned photodiode, a photogate or a CCD element, and a floating gate that is touching the photosensitive device.

[0114] In the second aspect, embodiments of the present invention relate to an array of pixels in accordance with any embodiments of the first aspect.

[0115] In the third aspect, embodiments of the present invention relate to a method for determining a charge in a photosensitive device, comprising alternatingly biasing a floating gate to a high and a low voltage level to control transfer of charges between the photosensitive device and the floating gate, measuring an integrated charge at or current through the floating gate both when the floating gate is at a first state and when it is at a second state, and determining a difference between the measurements, e.g. measured integrated charge or current, corresponding to the first and second states, said difference being representative for the amount of charge attracted and repelled by the floating gate.

[0116] In the fourth aspect, embodiments of the present invention relate to the used of a pixel structure according to embodiments of the first aspect in an imaging device.

[0117] We now refer to FIG. 1 , which is a schematic diagram of the cross section of a pixel structure (1 ) with a photosensitive device that is, in the example illustrated, a pinned photodiode (16) and a floating gate (12) according to embodiments of the present invention. In the example illustrated, the pinned photodiode (16) is embedded in a semiconducting substrate, in the present example, a p- substrate (19). The photosensitive device thus at least partially surrounds the floating gate. This configuration allows for efficient transfer of charges between the photosensitive device (16) and the floating gate (12). In the example illustrated, the pinned photodiode (16) comprises a p+ pinning layer (160).

[0118] In the example illustrated, the pinned photodiode (16) surrounds, and touches, the floating gate The pinned photodiode (16) is depicted as the primary active region for ionized carrier collection. The pinned photodiode (16) generates a charge or charges as a result of incident radiation, i.e. , the pinned photodiode (16) generates photocharges.

[0119] The pixel structure (1 ) further comprises:

[0120] - a modulation arrangement (100) adapted for modulating a voltage at the floating gate (12) between at least a first voltage level and a second voltage level to control transfer of charges between the photosensitive device (16) and the floating gate (12),

[0121] - a measurement arrangement (110) adapted for measuring an electrical parameter related to charge when the floating gate (12) is at a first state and when it is at a second state, and

[0122] - a processing arrangement (120) configured to determine a difference between the measurements corresponding to the first and second states, wherein the difference represents the amount of charge generated by the photosensitive device (16).

[0123] This pixel structure (1 ) allows determining the amount of charge generated in the photosensitive device (16) in a non-destructive manner by measuring the charge at the floating gate (12) at different voltage levels.

[0124] The pixel structure (1 ) is adapted for modulating a voltage at the floating gate (12) between a first voltage level, e.g. a high voltage, and a second voltage level, e.g. a low voltage, and for measuring an integrated charge at or current through the floating gate (12). The modulated voltage is applied to the positive input of a charge transimpedance amplifier (4), wherein the floating gate (12) is coupled to the negative input of the charge transimpedance amplifier (4) so that the floating gate is “floating” (thus not connected to any low-impedant source except by capacitive coupling) with respect to the applied modulated voltage. This modulation of the voltage of the floating gate (12) controls the transfer of charge between the pinned photodiode (16) and the floating gate (12). Said transfer of charge is indicated by the dashed arrows in FIG. 1.

[0125] We now simultaneously refer to FIG. 2, which is a timing diagram illustrating the operation of the pixel structure (1 ). The operation of the pixel structure involves modulating the voltage at the floating gate (12) and measuring the integrated charge at or current through the floating gate. The timing diagram includes a series of voltage levels applied to the positive input of the charge transimpedance amplifier (4) and, via the negative input of the charge transimpedance amplifier (4), to the floating gate (12) over time, with high states (S) and low states (R) respectively resulting in the attraction and repulsion of charges to and from the floating gate (12).

[0126] In the example illustrated, the voltage modulation at the floating gate (that is, with respect to the voltage of the substrate (19)) is achieved by applying a voltage modulation on a positive input of a charge transimpedance amplifier (4). The negative input of the charge transimpedance amplifier (4) is, in the example illustrated, connected to the floating gate (12). It will be clear for a person skilled in the art that keeping the voltage applied to the positive input of the charge transimpedance amplifier (4) constant (DC voltage) and modulated voltage applied to the substrate (19), e.g., locally under the floating gate (12), is equivalent and may be performed instead.

[0127] By applying a voltage modulation, the voltage on the floating gate (12) is biased between:

[0128] - the first voltage level being a high voltage level adapted for attracting charges, when present, from the photosensitive device (16) to an inversion layer or charge packet under the floating gate (12), and

[0129] - the second voltage level being a low voltage level adapted for repelling charges, when present, from the inversion layer or charge packet of the floating gate (12) to the photosensitive device (16). Modulating the voltage on the floating gate (12) in this manner enables controlling the transfer of charges back and forth between the photosensitive device (16) and the floating gate (12).

[0130] During both the high state (S) and the low state (R), the total or integrated charge (i.e. , photocharge) or current at the floating gate (12) is measured by measuring the mirror charge on the floating gate (12). A difference is determined between the integrated charge at or current through the floating gate (12) when in the high state (S) and in the low state (R). The measured current or integrated charge may be based on or represented as a voltage across a capacitor (20) in the feedback of the charge transimpedance amplifier (4).

[0131] In the example illustrated, the pixel structure (1 ) may, thus, be adapted for applying voltage modulation via a virtual ground of a charge transimpedance amplifier (4), wherein the measured integrated charge or current is based on a voltage across a capacitor in a feedback of the charge transimpedance amplifier (4).

[0132] The voltage across or the charge on the capacitor (20) may be reset by opening a switch (21 ) in parallel with the capacitor (20), e.g., by the RESET signal shown in FIG. 2. Said resetting may be performed before said modulating the voltage on the floating gate (12).

[0133] The movement of charge between the inversion layer (22) and the pinned photodiode (16) may be repeated a plurality of times, with each time the difference in integrated charge or current being measured. The measured integrated charge or current from this plurality of measurements may be averaged, whereby the precision of the measurement of the charge in the pinned photodiode (16) may be enhanced.

[0134] The pixel structure (1 ) further comprises a FLUSH gate (23) for removing charge from the photosensitive device, e.g. pinned photodiode (16), towards a drain (24). Said charge removal may be performed when the charge generated in the photosensitive device (16) has been measured a sufficient number, e.g., a plurality, of times. The subsequent removal of charges via the FLUSH gate (23) (indicated by the FLUSH signal in FIG. 2) may ensure that the photosensitive device (16) is ready for the next cycle of charge accumulation (e.g., by incident radiation, indicated by Qphoto in FIG. 2) and measurement.

[0135] A variation on the pixel structure (1 ) of FIG. 1 is explained with reference to FIG. 3A and FIG. 3B. (For simplicity, the voltages at different components are indicated in the figures.)

[0136] Also in this embodiment, the modulation arrangement (100) is adapted to modulate the voltage at the floating gate (12) by applying a modulated voltage to a positive input of a charge transimpedance amplifier (4) connected to the floating gate (12).

[0137] The pixel structure (1 ) of FIG. 3A furthermore contains a compensation node (24), capacitively coupled (in the present example: over a capacitor having a capacitance of 5fF ) to the negative input of the charge transimpedance amplifier (4).

[0138] The compensation voltage (in the illustrated example: 3V) that may be applied to the compensation node (24) may be a modulated voltage and may serve to compensate for the crosstalk of the charge transimpedance amplifier (4) output (26) and the REF input to the positive input of the charge transimpedance amplifier (4), when the REF voltage is modulated (in this example, in FIG. 3A, the high state is 2V).

[0139] As is indicated in FIG. 3A by the dashed arrow, when the voltage at the floating gate (12) is in the high state, charges are induced to move from the photosensitive device (16) towards the floating gate (12), so that they enter or reside in an inversion layer (22) in the substrate (19) underneath the floating gate (12).

[0140] A mirror charge may be generated on the floating gate (12), generated by the charges in the inversion layer (22). This may result in a voltage change across a capacitor (25) (having, in the present example, a capacitance of 0.5fF) in a feedback loop of the charge transimpedance amplifier (4). This voltage change, in turn, influences the voltage measured at the output (26) of the charge transimpedance amplifier (4). Thus, the voltage at the output (26) of the charge transimpedance amplifier (4) is dependent on the amount of charges in the inversion layer (22).

[0141] Reference is made to FIG. 3B. When the voltage is set to the low state (in the present example: OV) so that the charges move back from the floating gate (12) to the photosensitive device (16) (and no longer generate a mirror charge in the floating gate (12)), and the compensation is in the present example set to OV, an empty state voltage may be generated at the output (26) of the charge transimpedance amplifier (4) with which the voltage at said output (26) when the modulation voltage was in the high state may be compared by the processing arrangement. Therefore, based on the voltage difference between the output voltage in the high and in the low state, a measure of the electrical parameter related to charge, for instance integrated charge or current, may be derived (which is, then, in turn, based on the voltage across the capacitor (25) in the feedback of the charge transimpedance amplifier (4)).

[0142] FIG. 4 is a schematic representation of a pixel structure (1 ) comprising another type of charge transimpedance amplifier (4) that is, in this example, a class A amplifier, providing a comparatively simple way of applying the voltage to the floating gate (12). A class A amplifier provides a simple way to implement the charge transimpedance amplifier with low noise. This configuration may be applied in a pixel with a particularly small area budget. The charge transimpedance amplifier (4) may be located inside a single pixel (1 ) (indicated by the dashed line surrounding the charge transimpedance amplifier (4) and the floating gate (12) and photosensitive device (16), all contained in the same pixel (1 )). The load (27) of the charge transimpedance amplifier (4) may be put far outside the pixel (1 ), e.g., at the end of a column output wire (28).

[0143] In the example illustrated, the charge transimpedance amplifier (4) comprises a first transistor (29) at, e.g., inside or near, the pixel (1 ). Further transistors may be located in a column amplifier (although in the example illustrated, some further transistors are located in the pixel (1 )). Placing part of the amplifier inside the pixel helps reduce noise. The class A amplifier comprises a negative input being the gate of the first transistor (29) and a positive input from a source terminal of the first transistor (29). The floating gate (12) is in contact with the photosensitive device (16), which is adapted for generating charges upon incidence of radiation. In this configuration, the floating gate (12) is "floating" with respect to the applied modulated voltage due to capacitive coupling in the first transistor (29). Similarly as in the above example (FIG. 3A and 3E3) a mirror charge may be generated on the floating gate (12), generated by the charges in the inversion layer (22), and resulting in a voltage change across a capacitor (25) (having, in the present example, a capacitance of 0.5fF) in a feedback of the charge transimpedance amplifier (4).

[0144] The pixel structure (1 ) of FIG. 4 contains a compensation node (24), on which a modulated compensation voltage may be applied to compensate for the crosstalk between the charge transimpedance amplifier (4) output (26) and the REF input or applied to its input (28).

[0145] Capacitive coupling between the modulated voltage applied at the input (28) and the floating gate (12) is provided by the capacitive coupling in the first transistor (29). The load (27) of the charge transimpedance amplifier (4) is positioned outside the pixel (1 ), at the end of a column output wire (28), to save space in the pixel area. The movement of charges between the photosensitive device (16) and the floating gate (12) is indicated by the dashed arrows in Figure 4.

[0146] The invention is not limited to charge transimpedance amplifiers for applying voltage modulation and reading out the (photo)charges at the floating gate.

[0147] Reference is made to FIG. 5A, which is a schematic representation of another pixel structure (1 ) in accordance with embodiments of the present invention, and, simultaneously, to FIG. 5B, which is a sequence of signals that may be applied to the pixel structure (1 ). Instead of a charge transimpedance amplifier, one can use a concept similar to the CCD-type of floating gate readout.

[0148] A voltage is initially applied to the floating gate (12) via a switch (30) controlled by a RESET signal, allowing an initial voltage to be applied to the floating gate (12). Adjacent to the floating gate (12), a capacitive coupling (31 ) is depicted, which is responsible for modulating the voltage at the floating gate (12). A field effect transistor (32) is positioned near the floating gate (12), with its gate connected to the floating gate (12). This transistor (32) acts as a source follower (SF), which senses the potential shift on the floating gate (12) caused by the (photo)charge. The source follower (32) is connected to a column output. In particular, the voltage on the floating gate may be sensed by a gate of a field effect transistor (32) that may, in this example, act as source follower (SF), and that may exhibit a change in conductance by said potential shift, thereby generating a signal that is dependent on the (photo)charge and that may be outputted to the column output. FIG. 5A illustrates how the floating gate (12) can be used to sense photocharge indirectly by detecting the potential shift through the source follower (32). The modulation of the voltage at the floating gate (12) via the capacitive coupling (31 ) and the initial voltage application through the switch (30) controlled by the RESET signal are aspects of this pixel structure. The source follower (32) converts the potential shift into a readable signal, which is then output to the column output, enabling the detection and measurement of the photocharge.

[0149] Reference is made to FIG. 6A and 6B, which are schematic representations of, respectively, a top view and vertical cross-sectional view (along the dashed dotted line in FIG. 6A) of part a pixel structure (1 ) in accordance with embodiments of the present invention. In this example, the floating gate (12) touches and is surrounded by the photosensitive device (16) that is a pinned photodiode (16) comprising a pinning layer (160). It is an advantage of this configuration that efficient transfer of charges between the photosensitive device (16) and the inversion layer under the floating gate (12) may take place. In this example, the flush gate (23) for removing the charges from the photosensitive device (16) to a drain region (24) is a “normal” transfer gate. The charge thus removed by the flush gate (23), e.g., into a floating diffusion, may be subsequently readout in the “classic” way (e.g., in addition to the readout by the floating gate (12)).

[0150] Although above, the photosensitive device is a pinned photodiode, this is not required.

[0151] Reference is made to FIG. 7A and 7B, which are schematic representations of, respectively, a top view and vertical cross-sectional view (along the dashed dotted line in FIG. 7A) of part a pixel structure (1 ) in accordance with embodiments of the present invention. In this example, the photosensitive device is a photogate or surface channel CCD, containing an electrode (33) over the substrate (19), instead of a pinned photodiode. The pixel structure includes a p-type substrate (19) on which various components are formed. An electrode (33) forming part of the photogate or surface channel CCD controls the potential in the substrate (19) underneath it and facilitates charge movement. Surrounded by this electrode, there is a floating transfer gate (FTG) in contact with the photosensitive device. The voltage applied to the FTG is modulated to control the transfer of charges between the photosensitive device and the floating gate. Double arrows labeled Qphoto indicate the movement of photocharges back and forth between the photosensitive device and the floating gate, facilitated by this voltage modulation. At the far right of the figure, a shallow trench isolation (STI) region electrically isolates the pixel structure from adjacent structures.

[0152] The functioning of this alternative pixel structure (1 ) is similar as above, wherein charges or photocharges from the photosensitive device, generated in the substrate (19) underneath the electrode (33), may be moved back and forth (as indicated by the double-arrows indicated by Qphoto) to and from the floating gate (12) by voltage modulation for sensing the charges. A flush gate (23) may have the same function as explained in other embodiments of the present invention.

[0153] Reference is made to FIG. 8A and 8B, which are schematic representations of, respectively, a top view and vertical cross-sectional view (along the dashed dotted line in FIG. 8A) of part a pixel structure (1 ) in accordance with embodiments of the present invention. Still alternatively, the photosensitive device may be a buried channel CCD comprising a buried channel (34) underneath the electrode (33). The buried channel extends underneath the floating gate (12) and the flush gate (23). The buried channel (34) is formed in a p- substrate (19) and is designed to transport photo-generated charges (Qphoto) along its length. The floating transfer gate (FTG) is positioned above the buried channel (34) and is surrounded by an electrode

[0154] (33). A flush gate (23) is located to the left of the floating gate (12) and is also positioned above the buried channel (34). The flush gate (23) transfers charges from the buried channel (34) to a floating diffusion (FD) region. The buried channel (34) extends from the floating diffusion (FD) region on the left to a shallow trench isolation (STI) region on the right. The p- substrate (19) is shown as a dotted area beneath the buried channel

[0155] (34). The buried channel CCD not comprising an inversion layer, the charges are moved back and forth between the photosensitive device (the buried channel under the electrode (33)), and a charge packet (37) of, or underneath, the floating gate (12). This configuration allows for efficient charge transfer and readout, contributing to the overall functionality of the pixel structure in capturing and processing image data.

[0156] FIG. 9 is a schematic representation of a top view of another pixel structure (1 ) in accordance with embodiments of the present invention, wherein the floating gate (12) is touching the photosensitive device (16) but is not completely but only partially surrounded thereby. The floating gate (12) is located at a side of the photosensitive device (16), e.g., adjacent a flush gate (23). The flush gate (23) is used for removing charge from the photosensitive device (16) to a drain region.

[0157] In the context of the invention, the floating gate (12) has a modulated voltage to control the transfer of charges between the photosensitive device (16) and the floating gate (12). This configuration allows for efficient charge transfer while maintaining a compact layout. This embodiment demonstrates an alternative layout where the floating gate (12) is not completely surrounded by the photosensitive device (16), which can be advantageous for certain design constraints and applications.

[0158] FIG. 10 and 11 are schematic representations of a pixel structure (1 ) wherein the charge transimpedance amplifier (4) is a class A amplifier. The charge transimpedance amplifier (4) may be located inside a single pixel (1 ) (indicated by the dashed line surrounding the charge transimpedance amplifier (4) and the floating gate (12) and photosensitive device (16), all contained in the same pixel (1 )).

[0159] As shown in the figures, signals for the different components may be provided by circuits in the periphery, i.e., outside of the pixel structure (1 ). In each of the figures, the pixel structure (1 ) is the same, but the circuitry in the periphery, for providing signals to the pixel structure (1 ) and for reading signals from the pixel structure (1 ), are different.

[0160] In the example illustrated, the charge transimpedance amplifier (4) comprises a first transistor (29) at, i.e., inside, the pixel (1 ). Furthertransistors may be located in a column amplifier (although in the example illustrated, some further transistors are located in the pixel (1 )). The class A amplifier comprises a negative input being the gate of the first transistor (29) and a positive input from a source terminal of the first transistor (29).

[0161] In this example, the flush gate (23) for removing the charges from the photosensitive device (16) to a drain region, for instance to a floating diffusion (35) is a “normal” transfer gate. The charge thus removed by the flush gate (23) into the floating diffusion (35) may be subsequently readout in the “classic” way with a source follower (in addition to the readout by the floating gate (12)). Herein, said first transistor (29) may be reconfigured to serve as a source follower for classic pixel readout through a flush gate (23), i.e., transfer gate, and a floating diffusion (35). Thereby, the pixel structure (1 ) can be read out, in principle, both the nondestructive way using the floating gate (12) with a charge transimpedance amplifier (4), and in the “normal mode” or “classical mode” or “destructive way” with the flush gate (23) and floating diffusion (35) and a source follower.

[0162] In particular, in FIG. 10, the circuitry in the periphery is configured for reading out the pixel structure (1 ) using the charge transimpedance amplifier (4) for reading from the floating gate (12), similarly as in FIG. 4 (with the dashed arrow indicating the back and forth movement of the charges between the photosensitive device (16) and (inversion layer under) the floating gate (12). The further switch (36) may in principle remain opened so that no charges may pass the further switch (36). Different levels of compensation voltage may be applied to the compensation node (24), depending on the voltage level of the modulated voltage applied, via the REF wire, to the first transistor. Signal readout from the pixel structure (1 ) may occur via the column wire, which may comprise a column amplifier for amplifying the signal.

[0163] In FIG. 11 , the circuitry in the periphery is configured for reading out the pixel structure (1 ) in the “classical mode”, wherein the charges or photocharges in the photosensitive device (16) are transferred via the flush gate (23) as transfer gate to the floating diffusion (35) (wherein the movement of said charges is indicated by the dashed arrow). The further switch (36) may in principle remain closed so that charges may pass the further switch (36), from the floating diffusion (35) to the first transistor (29) that is, in this example, configured to serve as a source follower. In that mode of operation no voltage modulation at the floating gate (12) takes place and the first transistor (29) may receive a constant (DC) voltage from the REF wire. The compensation node (24) may therefore receive a constant (DC) voltage as well.

[0164] The circuit of FIG. 12 is a variant on the circuit of FIG. 10 and FIG. 11 , wherein the charges from the photosensitive device (16) may be read out both non-destructively using the floating gate (12), using the circuitry in a corresponding way as in FIG. 10, and in the “classical mode”, using the flush gate (23) as transfer gate and the floating diffusion (35), similar as in FIG. 11. In the example of FIG. 12, additional circuitry (compared to the circuit shown in FIG. 10 and 11 ) is provided inside the pixel structure (1 ) for said reading out in the “classical mode”. Herein, the signals from both the readout from the floating gate (12) and using the flush gate (23) may be transferred via the column output wire (“COLUMN WIRE”), which is thus shared. The pixel structure (1 ) also features a reset transistor (44) connected to a supply voltage (VDDpix), enabling the resetting of the floating diffusion node (35).

[0165] The periphery circuits used for normal readout include the select normal and reset transistors, which regulate standard pixel operations such as selection and resetting.

[0166] For FTG readout, also referred to as Non-Destructive Readout (NDR), additional periphery circuits are employed. These include a current source connected to the supply voltage (VDD) and control signals labeled Null and Select FTG, which enable non-destructive signal retrieval. The FTG readout is further supported by reference signals, REF high and REF low, which ensure modulation of the floating gate (12), as well as compensation signals, Comp null, Comp low, and Comp high, which may be applied depending on the voltage level of the modulated voltage applied, via the REF signal, to the first transistor (29).

[0167] Signal readout from the pixel structure (1 ) may occur via the column wire, which may comprise a column amplifier for amplifying the signal for further processing.

[0168] The combination of normal readout and FTG readout ensures a flexible and high-performance pixel operation. Reference is made to FIG. 13. A simulation was performed to check the functioning of the pixel structure using the floating gate in accordance with embodiments of the present invention. In the present example, a same circuit and operation as in FIG. 3A and 3B using a compensation is modelled.

[0169] The upper graph of FIG. 13 shows the applied compensation voltage (40) to the compensation node as a function of time. Furthermore, FIG. 13 shows the applied modulation voltage (41 ) applied to the REF (cfr. FIG. 3A), i.e., to the positive input of the charge transimpedance amplifier.

[0170] The lower graph of FIG. 13 shows the signal at the output of the charge transimpedance amplifier. It may be observed that, when the applied modulation voltage (41 ) is high, the signal at said output is dependent on the amount of charges that are present under the floating gate when the applied modulation voltage (41 ) is high. In FIG. 13, the signal change with increasing amount of charges (from 0 electrons to 5k or 5000 electrons) under the floating gate is indicated by the dashed arrow. As the signal (or the difference of the output signal between the full and empty states, or between the REF high and REF low states) is dependent on the amount of charges under the floating gate, it is thus verified that the amount of (photo)charges generated in the photosensitive device may be derived from this output signal.

[0171] In embodiments, as for instance illustrated in FIG. 14, which is similar to FIG. 12 - hence incorporating a "classical mode" readout mechanism -, the pixel structure (1 ) may further comprise an overflow capacitor (CM) connected to the floating diffusion (35) used for readout in this “classical mode” readout, for high dynamic range (HDR) operation, to store excess charge when the charge exceeds the capacity of the photosensitive device (16), for instance a pinned photodiode (PPD). A charge quantity that is too large to be contained in the photosensitive device (16) can overflow to the overflow capacitor (CM).

[0172] This can be implemented for instance by the overflow capacitor (CM) being connected to the photosensitive device (16) via a flush gate (23) that can be biased at an intermediate voltage (in between the low voltage for blocking transfer of charges from the photosensitive device (16) to the floating diffusion (35) and the high voltage for transferring all charges from the photosensitive device (16) to the floating diffusion (35)). The three-level transfer gate thus regulates charge transfer between the photosensitive device (16) and the floating diffusion node (35), allowing excess charge from the photosensitive device (16) to flow into the overflow capacitor when the accumulated charge exceeds a threshold.

[0173] Alternatively, the HDR operation may be obtained via a merge transistor (45) being biased at an intermediate level, facilitating controlled charge redistribution.

[0174] The combination of normal readout and FTG readout ensures a flexible and high-performance pixel operation. The incorporation of the overflow capacitor (CM) significantly extends the pixel's dynamic range by preventing charge saturation in the photosensitive device (16) while maintaining accurate signal integrity. This feature is particularly advantageous in applications requiring high dynamic range imaging, where bright and dark regions must be captured with minimal signal loss.

[0175] FIG. 15 illustrates a schematic cross-section of a pixel structure (1 ) according to embodiments of the present invention, implementing a "GS" (global shutter) technology. In this design, a storage node (SN) is introduced as a diode structure similar to a pinned photodiode (PPD), but with a higher depletion voltage or pinning voltage. The SN is strategically positioned between a global shutter transfer gate (TG1 ) and a serial readout transfer gate (TG2), enabling efficient charge storage and readout.

[0176] The photosensitive device (16), in the example illustrated a pinned photodiode (PPD), formed in a p-substrate and covered by a p+ pinning layer, serves as the primary photodetector, collecting photo- generated charge. The global shuter transfer gate (TG1 ) regulates charge transfer from the photodiode (PPD) to the storage node (SN), ensuring that signal electrons are stored in the storage node (SN) while preventing leakage back into the photodiode (PPD). The storage node (SN) acts as an intermediate charge storage site, holding the collected charge during the measurement operations.

[0177] The voltage at the floating gate (12) is modulated as for instance explained with respect to FIG. 4, between a first voltage level and a second voltage level to control transfer of the charges from underneath the floating gate (12) to a position where they are repelled from underneath the floating gate (12).

[0178] An electrical parameter related to the charge present at the floating gate (12) may be measured both when the floating gate (12) is at a first state (biased at the first voltage level), and when it is at the second state (biased at the second voltage level). The difference between the measurements corresponding to the first and second states is representative for the amount of charge generated by the photosensitive device (16).

[0179] The serial readout transfer gate (TG2) governs the transfer of charge from the SN to a floating diffusion (FD) node, which may for instance ultimately interface with further readout circuitry.

[0180] The interaction of these elements enables efficient charge capture, storage, and readout in a global shuter architecture. By implementing a storage node (SN) with a higher depletion voltage, the design enhances charge handling capabilities, reducing the risk of charge overflow and improving signal preservation. This configuration ensures high-performance imaging, particularly in applications requiring precise temporal control and low image lag.

[0181] FIG. 16 illustrates a schematic cross-section of a pixel according to embodiments of the present invention, incorporating a variant of a global shuter architecture where a storage node (SN) is positioned partially under a first transfer gate (TG1 ). This transfer gate (TG1 ) structure is designed with two distinct regions: a normal threshold voltage (Vth) region adjacent to the photosensitive device (16), illustrated as a pinned photodiode (PPD) in FIG. 16, and a low threshold voltage (Vth) region on the side of the storage node (SN). The low threshold voltage region may for instance be obtained by implantation of different dopants in different gate regions, for instance by a buried n-layer underneath part of the transfer gate; of by using different oxide thicknesses under the distinct regions of the first transfer gate. The transfer gate structure with two distinct regions allows for more efficient charge transfer and storage.

[0182] The photosensitive device (16), illustrated as a pinned photodiode (PPD) in FIG. 16, located within a p-substrate (19) and covered by a p+ pinning layer, serves as the primary charge collection site, accumulating photo-generated carriers. The first transfer gate (TG1 ) regulates the transfer of charge from the photosensitive device (16) to the storage node (SN). Moreover, when the first transfer gate (TG1 ) is at a high voltage , charge stored in the storage node (SN) can partially or fully redistribute under the first transfer gate (TG1 ). Conversely, when the first transfer gate (TG1 ) is set to a very low voltage, the storage node charge is repelled away from the first transfer gate region and resides in the portion of the storage node (SN) that is not beneath the first transfer gate (TG1 ). The alternate biasing of the voltage at the first transfer gate (TG1 ) allows measuring an electrical parameter related to the charge at the first transfer gate (TG1 ) both when the transfer gate (TG1 ) is biased high and biased low. A difference between the measurements corresponding to the different voltage levels may be determined, said different being representative for the amount of charge generated by the photosensitive device (16).

[0183] FIG. 17 illustrates a schematic cross-section of a pixel according to embodiments of the present invention, wherein the storage node is implemented as a charge pocket located beneath an electrode of a short charge-coupled device (CCD), which may be configured as either a surface or buried channel CCD. This configuration enables precise charge modulation and sensing within the same node, distinguishing it from conventional skipper CCD designs, where sensing and modulation typically occur at separate locations.

[0184] A photosensitive device (16), illustrated as a pinned photodiode (PPD) in FIG. 17, positioned within a substrate (19), for instance a p-substrate, and covered by a pinning layer, for instance a p+ pinning layer, serves as the primary photoelectric charge collector. The charge collected in the PPD is transferred through a first transfer gate (TG1 ) to a storage node (SN).

[0185] Above part of the storage node (SN), a floating gate (12) is provided, to control position of the charges in the storage node (SN). The floating gate (12) may be biased between a first voltage level (e.g. high) and a second voltage level (e.g. low). When biased high, the floating gate (12) attracts charges to an inversion layer or charge packet underneath it; when biased low, it repels the charges. The difference between the measurements corresponding to the first and second states, which - in this embodiment - correspond to the floating gate being biased to the first and second voltage levels, respectively, may be determined, this difference being representative for the amount of charge generated by the photosensitive device.

[0186] A DC voltage electrode, adjacent to the storage node and adjacent to the floating gate (12), applies a constant potential to attract the charges that are repelled by the floating gate (12) when biased low.

[0187] A second transfer gate (TG2) facilitates the transfer of charge from the storage node (SN) to a floating diffusion (FD) node

[0188] FIG. 18 illustrates a schematic cross-section of two pixels according to embodiments ofthe present invention, implementing a shared modulation arrangement (100) and measurement arrangement (110), where multiple floating gates (12) are connected - in the example illustrated - to a single capacitive transimpedance amplifier (CTIA). This approach allows the CTIA to sequentially read out signals from multiple floating gates (12), resembling the concept of shared pixels commonly used in small consumer imaging sensors. Typically, a shared pixel group consists of two to four pixels, optimizing area efficiency and readout performance.

[0189] Each pixel can be a pixel according to embodiments of the present invention, each with their own photosensitive device (16) and floating gate (12), but with shared modulation arrangement (100), measurement arrangement (110) and processing arrangement (120).

[0190] By allowing multiple FTGs to interface with a single CTIA, or in general with shared modulation arrangement (100), measurement arrangement (110), this architecture reduces pixel area while maintaining high readout efficiency. The ability to read multiple pixels in sequence enhances imaging performance, particularly in applications requiring compact pixel layouts and efficient charge transfer. This shared pixel concept may be suitable for high-resolution imaging applications where space constraints are critical.

[0191] FIG. 19 illustrates a schematic cross-section of a pixel according to embodiments of the present invention, incorporating a second, non-floating transfer gate (NFTG) alongside a first floating gate (12) to enable an advanced charge measurement and noise-reduction technique. The photosensitive device (16), illustrated in FIG. 19 as pinned photodiodes (PPDs), positioned within a substrate (19) such as a p-substrate and covered by a pinning layer, e.g. a p+ pinning layer, serve as primary charge collection sites. The nonfloating transfer gate (NFTG), unlike the floating gate (12), is driven by a voltage and does not float, allowing it to selectively capture or release photocharge based on its biasing state. When the non-floating transfer gate (NFTG) is biased high, it captures a portion of the photocharge generated in the photosensitive device (16), preventing this charge from reaching the floating gate (12). This results in a "zero photocharge" measurement, establishing a baseline for readout. When the non-floating transfer gate (NFTG) is biased low, it no longer captures charge and instead repels any previously collected charge, allowing it to be sensed by the floating gate (12) as "signal charge." This two-step process enables differentiation between background noise and actual photo-induced charge.

[0192] Charge can be actively moved between the floating gate (12) and non-floating transfer gate (NFTG) through bias control. By forcing the floating gate (12) low in any suitable way, for instance either via an external switch or by lowering the reference (REF) input of the charge transimpedance amplifier (CTIA); and simultaneously biasing the non-floating transfer gate (NFTG) high, charge initially held under the floating gate (12) can be transferred back to the non-floating transfer gate (NFTG). This bidirectional charge transfer allows the measurement process to be repeated multiple times, providing a mechanism for non-destructive charge readout.

[0193] The floating gate (12), in direct contact with and at least partially surrounded by the photosensitive device (16), transfers photocharge between its inversion layer and the inversion layer beneath the nonfloating transfer gate (NFTG). Each transfer event results in a potential change that is sensed by a potential sensing amplifier of any kind, for instance a CTIA. By repeatedly moving the charge back and forth between the non-floating transfer gate (NFTG) and the floating gate (12), while recording the potential difference each time, the system enables multi-sampling of both full and empty charge states. Averaging these measurements over multiple cycles significantly reduces 1 / f noise and other low-frequency noise components, enhancing the precision of the readout. This makes this design particularly beneficial for high- sensitivity imaging applications requiring ultra-low noise performance, such as scientific imaging, astronomy, and medical imaging.

[0194] FIG. 20A and FIG. 20B illustrate a schematic cross-section of a pixel according to embodiments of the present invention, which is structurally similar to the embodiment of FIG. 19 except that the low level on the floating gate (12) is directly enforced by connecting it to a low voltage source, such as ground (GND) or a supply voltage (VSS). To obtain this, the pixel structure incorporates a switching mechanism to impose the low voltage on the floating gate (12).

[0195] In the example illustrated, the low voltage connection is established through a switch (46), which may for instance be implemented as an nMOSFET. This configuration eliminates the need to modulate the reference (REF) input of the charge transimpedance amplifier (CTIA), as explained in previous embodiments, simplifying the design by allowing the omission of the compensation capacitor.

[0196] In FIG. 20A, the switch is in a closed state, causing the floating gate (12) to be pulled to a low potential. A photosensitive device (16), such as a pinned photodiode (PPD), located in substrate (19) e.g. a p-substrate and covered by a p+ pinning layer, serves as the primary charge collection site. A non-floating transfer gate (NFTG), separated from the floating gate (12) by the photosensitive device (16), operates as a controllable barrier for charge transfer. When the non-floating transfer gate (NFTG) is biased high, it captures a portion of the photocharge, preventing it from being sensed by the floating gate (12), effectively enabling a “zero photocharge” measurement. The measurement arrangement, e.g. charge transimpedance amplifier (CTIA), detects the potential level corresponding to this state.

[0197] In FIG. 20B, the switch (46) is in an open state, allowing the floating gate (12) to float. This change enables the non-floating transfer gate (NFTG), now biased low, to release previously captured charge, which then transfers to the floating gate (12). The measurement arrangement subsequently senses the full signal charge, providing the actual photo-induced signal measurement.

[0198] The alternating process of closing and opening the switch (46), allows repeated charge transfer cycles between the non-floating transfer gate (NFTG) and floating gate (12), facilitating multiple nondestructive measurements. Since the low potential at the floating gate (12) is imposed directly by the switch (46), the modulation of a reference signal (REF) is not needed, and the compensation capacitor can be omitted, thus simplifying the circuit operation and reducing design complexity.

[0199] FIG. 21 illustrates a timing diagram corresponding to the pixel circuit described in FIG. 20A and FIG. 20B. The diagram details the sequence of control signals used to operate the pixel, including the flush signal, the non-floating transfer gate (NFTG) signal, the switch control signal, the reset signal, the floating transfer gate (FTG) signal, and the output of the charge transimpedance amplifier (CTIA). The sequence is designed to enable repeated non-destructive sampling of the charge stored under the FTG while minimizing noise.

[0200] A flush signal is applied initially to clear any residual charge from the pinned photodiode (PPD) before charge integration begins. The NFTG signal is then activated, modulating the charge transfer behaviour between the photosensitive device (16), the non-floating transfer gate (NFTG), and the floating gate (12). When the non-floating transfer gate (NFTG) is biased high, a portion of the photocharge (Qphoto) is captured under the non-floating transfer gate (NFTG), preventing it from being measured by the floating gate (12), thus creating a reference or "zero charge" state. The switch control signal is toggled to impose a low potential on the floating gate (12) when necessary, ensuring controlled charge transfer. The reset signal clears the floating gate (12) before measurement, ensuring that no residual charge remains from previous cycles.

[0201] As the floating gate (12) signal modulates, charge moves between the non-floating transfer gate (NFTG) and floating gate (12), producing a measurable change in potential. The CTIA output reflects these transitions, showing alternating "zero charge" (Z) and "signal charge" (S) states. The sampling process records each of these states in sequence, allowing for multiple measurements of the same charge packet. By averaging these repeated measurements, the system reduces low-frequency noise, particularly 1 / f noise, significantly improving signal fidelity. The periodicity of the timing signals ensures consistent charge transfer and readout, enabling accurate photocharge detection while maintaining low noise operation.

[0202] The interaction of these control signals enables a high-precision, low-noise readout mechanism, making this approach particularly suitable for applications requiring repeated charge measurements, such as high-sensitivity imaging and scientific instrumentation. The ability to alternately store and release charge under the non-floating transfer gate (NFTG) and floating gate (12) while recording the resulting potential difference at the CTIA output ensures that the system can effectively mitigate noise while enhancing charge measurement accuracy.

[0203] FIG. 22A and FIG. 22B illustrate a schematic cross-section of a pixel according to further embodiments of the present invention, implementing a variant method for imposing a low potential on the floating gate (12), by controlling the reference (REF) voltage applied to the floating gate (12). This design is functionally similar to FIG. 20A and FIG. 20B, with the key difference that the voltage level at the floating gate (12) is enforced by connecting the reference node to the floating gate (12) via a switch (47), for instance a MOSFET switch. This configuration again allows the compensation capacitor to be omitted, simplifying the circuit architecture. In FIG. 22A, a photosensitive device (16) collects the photocharge. The photosensitive device (16), surrounding a non-floating transfer gate (NFTG) separates the non-floating transfer gate (NFTG) from the floating gate (12). The non-floating transfer gate (NFTG) is initially biased high, thus collecting charges from the photosensitive device (16). The switch 47 is closed, while the REF voltage is at a low level, thereby biasing the floating gate (12) to a low potential. The non-floating transfer gate (NFTG) by being biased high, prevents charge migration. Under these conditions, the charge remains trapped under the non-floating transfer gate (NFTG), while the floating gate (12) remains at a low potential. In this embodiment, a source follower circuit is used to sense this empty-state charge, providing a reference measurement, which is read out through the closed select switch.

[0204] In FIG. 22B, the REF voltage is brought to a high level, thereby biasing the floating gate (12) high. The switch (47) is then opened, leaving the floating gate (12) floating. Although the floating gate (12) is now at a higher voltage, the charge under the non-floating transfer gate (NFTG) does not immediately migrate, as it remains attracted to the non-floating transfer gate (NFTG). The measurement arrangement, in the embodiment illustrated the source follower, senses this empty state and transmits the readout through the closed select switch. In a subsequent phase, the non-floating transfer gate (NFTG) is biased low, forcing the stored photocharge to migrate into the photosensitive device (16). This charge is then transferred beneath the floating gate (12). The measurement arrangement then senses this charge and performs another readout when the select switch is closed. Instead of using a source follower, it is apparent to those skilled in the art that any other charge or voltage sensing amplifier could be employed to achieve similar results.

[0205] Following this third phase, the process can cycle back to the first phase, enabling multiple nondestructive reads ofthe same photocharge. This repeated readout sequence significantly reduces noise and enhances signal fidelity. By leveraging controlled charge migration and sequential sensing, this architecture optimizes signal integrity while maintaining the ability to perform multiple non-destructive read cycles, making it particularly advantageous for high-precision imaging applications requiring ultra-low noise performance.

[0206] FIG. 23 illustrates a timing diagram corresponding to the pixel circuit described in FIG. 22A and FIG. 22B, showing the sequence of applied control signals and their resulting effects on the floating gate (12) and output signals. The timing diagram represents the process of repeated non-destructive charge measurement, with alternating sampling of a zero-charge reference state (Z) and a signal charge state (S). The process occurs under both illuminated conditions, where a photocharge (Qphoto) is present, and dark conditions, where Qphoto is zero.

[0207] A flush signal is initially applied to remove any residual charge from the pinned photodiode (PPD) before the charge integration phase begins. A non-floating transfer gate (NFTG) signal follows, modulating the behaviour of charge transfer between the photodiode (PPD) and the floating gate (12). A switch control signal is used for closing the switch (47) to enforce a low voltage at the floating gate (12) through a reference voltage (REF) connection. The reference voltage (REF) is toggled between low and high states, controlling the potential at the floating gate (12), which determines the charge transfer sequence.

[0208] As the floating gate (12) alternates between being held at a defined potential and floating, charge is periodically moved between the non-floating transfer gate (NFTG) and floating gate (12), influencing the output signal. The resulting output waveform shows repeated instances of zero charge (Z) (sample taken while photo charge is under NFTG) and signal charge (S) (sample taken while photo charge under floating gate (12)) states. During each sampling phase, the output signal is recorded, first measuring the zero charge state when the non-floating transfer gate (NFTG) retains the charge, and then measuring the signal charge state when the charge is transferred to the floating gate (12). This cycle continues, allowing for multiple nondestructive reads of the same charge packet.

[0209] By averaging the difference between these repeated zero and signal measurements, the system significantly reduces noise, particularly 1 / f noise, and improves signal integrity. Under dark conditions, where no photocharge is present, the same timing sequence is applied, but no charge is transferred, ensuring a stable reference level. This method allows for highly precise charge sensing while maintaining the ability to re-sample the charge multiple times, making it particularly advantageous for high-sensitivity imaging applications requiring low noise and high dynamic range performance. It is to be understood that although preferred embodiments, specific constructions and configurations, as well as materials, have been discussed herein for devices according to embodiments of the present invention, various changes or modifications in form and detail may be made without departing from the scope of this invention. Steps may be added or deleted to methods described within the scope of the present invention.

Claims

Claims1 . A pixel structure (1 ) comprising a photosensitive device (16), adapted for generating charges on incidence of radiation, and a floating gate (12) in contact with the photosensitive device (16), the pixel structure being adapted to measure charge at or under the floating gate (12).

2. The pixel structure (1 ) according to claim 1 , wherein the floating gate (12) is a drainless transfer gate.

3. The pixel structure (1 ) according to any of the previous claims, wherein the photosensitive device at least partially surrounds the floating gate.

4. The pixel structure (1 ) according to any of the previous claims, further comprising a modulation arrangement (100) adapted for modulating a voltage at the floating gate (12) between at least a first voltage level and a second voltage level to control transfer of charges between the photosensitive device and the floating gate, and a measurement arrangement (110) adapted for measuring an electrical parameter related to charge when the floating gate (12) is at a first state and when it is at a second state, and a processing arrangement (120) configured to determine a difference between the measurements corresponding to the first an second states, wherein the difference represents the amount of charge generated by the photosensitive device (16).

5. The pixel structure (1 ) according to claim 4, wherein the modulation arrangement is adapted for modulating said voltage on the floating gate between: the first voltage level being a high voltage level adapted for attracting charges, when present, from the photosensitive device to an inversion layer of or charge packet under the floating gate, and the second voltage level being a low voltage level adapted for repelling charges, when present, from the inversion layer or charge packet of the floating gate to the photosensitive device.

6. The pixel structure (1 ) according to any of claims 4 or 5, wherein the modulation arrangement is adapted for modulating said voltage on the floating gate by means of a charge transimpedance amplifier, or a capacitive coupling, or a direct connection to a voltage.

7. The pixel structure (1 ) according to claim 6, wherein the modulation arrangement is adapted for applying said voltage modulation via a virtual ground of a charge transimpedance amplifier, wherein said measured electrical parameter is based on a voltage across a capacitor in a feedback loop of the charge transimpedance amplifier.

8. The pixel structure (1 ) according to any of claims 6 or 7, wherein the charge transimpedance amplifier comprises a first transistor at the pixel, and further transistors in a column amplifier.

9. The pixel structure (1 ) according to any of claims 7 or 8, wherein the charge transimpedance amplifier is a differential amplifier.

10. The pixel structure (1 ) according to any of claims 7 or 8, wherein the charge transimpedance amplifier is a class A amplifier located inside the pixel structure.

11. The pixel structure (1 ) according to claim 10, wherein the class A amplifier comprises a negative input being the gate of a first transistor and a positive input from a source terminal of said first transistor.

12. The pixel structure (1 ) according to any of claims 8 to 11 , wherein said first transistor is adapted to be reconfigured to serve as a source follower for classic pixel readout through a transfer gate and a floating diffusion.

13. The pixel structure (1 ) according to any of claims 7 to 12, wherein the modulation arrangement is adapted to modulate the voltage at the floating gate by applying a modulated voltage to a positive input of the charge transimpedance amplifier connected to the floating gate.

14. The pixel structure (1 ) according to any of claims 6 to 13, wherein the processing arrangement is adapted for determining the difference between measurements corresponding to the first and second states, at an output of the charge transimpedance amplifier a plurality of times.

15. The pixel structure (1 ) according to any of claims 6 to 14, wherein the measurement arrangement is adapted for measuring a mirror charge of the charge under the floating gate by measuring a potential difference on the floating gate by measuring an output of the charge transimpedance amplifier.

16. The pixel structure (1 ) according to any of claims4to 15, wherein the measurement arrangement is adapted for sensing the electrical parameter relating to charge at the floating gate by detecting a voltage at the floating gate by a charge or voltage amplifier, or a buffer amplifier such as a source follower.

17. The pixel structure (1 ) according to any of the previous claims, wherein the floating gate (12) is a vertical transfer gate.

18. The pixel structure (1 ) according to any of the previous claims, wherein the floating gate (12) is a depletion transistor, a buried channel transistor, a CCD electrode, a SOI transistor, a FINFET, or a JFET.

19. The pixel structure (1 ) according to any of the previous claims, wherein the photosensitive device (16) is any of a pinned photodiode, a photogate, and a CCD element.

20. The pixel structure (1 ) according to any of the previous claims, wherein the photosensitive device (16) is a storage node of a global shutter pixel.

21. The pixel structure (1 ) according to any of the previous claims, further comprising a flush gate (23) for removing charge from the photosensitive device to a drain region.

22. The pixel structure (1 ) according to any of the preceding claims, further comprising a non-floating transfer gate (NFTG) adjacent to the photosensitive device (16).

23. The pixel structure (1 ) according to claim 22, wherein the non-floating transfer gate (NFTG) is configured to transfer charges to and from the photosensitive device (16) by being biased between a high voltage and a low voltage.

24. The pixel structure (1 ) according to claim 23, wherein the measurement arrangement (110) is adapted for measuring the electrical parameter related to charge when the floating gate (12) is at the first state being a high voltage level while the non-floating gate (NFTG) is biased high, and when it is at a second state being a high voltage level when the non-floating gate (NFTG) is being or has been biased or pulsed low.

25. The pixel structure (1 ) according to any one of claims 4 to 24, wherein the processing arrangement (120) is configured to perform multiple cycles of the modulating and measuring steps and to average the determined differences to reduce noise.

26. An image sensor comprising an array of pixel structures (1 ) in accordance with any of the previous claims.

27. The image sensor according to claim 26, wherein multiple pixel structures share a single modulation arrangement (100) and a single measurement arrangement (110).

28. A method for determining an amount of charge generated by a photosensitive device (16), comprising:a) alternatingly biasing the voltage at a floating gate (12) in contact with the photosensitive device (16) between at least a first and a second voltage level to control transfer of charges between the photosensitive device and the floating gate, b) measuring an electrical parameter related to the charge at the floating gate both when the floating gate is at a first state and when the floating gate is at a second state, and c) determining a difference between the measurements corresponding to the first and second states, said difference being representative for the amount of charge generated by the photosensitive device (16).

29. The method according to claim 28, wherein measuring an electrical parameter related to the charge at the floating gate (12) when the floating gate (12) is at the first state comprises measuring the electrical parameter when the floating gate (12) is biased to a high voltage level, and wherein measuring an electrical parameter related to the charge at the floating gate (12) when the floating gate (12) is at the second state comprises measuring the electrical parameter when the floating gate (12) is biased to a low voltage level.

30. The method according to claim 28, further comprising alternatingly biasing the voltage at a nonfloating gate (NFTG) in contact with the photosensitive device (16) between at least a first voltage level and a second voltage level to control transfer of charges between the photosensitive device (16) and the non-floating gate (NFTG).31 . The method according to claim 30, wherein measuring an electrical parameter related to the charge at the floating gate (12) when the floating gate (12) is at the first state comprises measuring the electrical parameter when the floating gate (12) is biased to a high voltage level while the nonfloating gate (NFTG) is biased high, and wherein measuring an electrical parameter related to the charge at the floating gate (12) when the floating gate (12) is at the second state comprises measuring the electrical parameter when the floating gate (12) is biased to a high voltage level when the non-floating gate is being or has been biased or pulsed low.

32. The method according to any of claims 28 to 31 , further comprising repeating the method steps multiple times and averaging the determined differences to reduce noise.

33. The method according to any of claims 28 to 32, wherein measuring the electrical parameter comprises measuring a voltage across a capacitor in a feedback loop of a charge transimpedance amplifier.

34. Use of the pixel structure (1 ) according to any of claims 1 to 25 in an imaging device.

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