Semiconductor device and production method for same

Abstract

The present invention provides a semiconductor device that uses a high-quality semiconductor film. The present invention provides a high-performance semiconductor device. The semiconductor device comprises first and second transistors, first and second insulation layers, and first and second single crystal substrates. In the first transistor, a channel is formed in a first single crystal semiconductor of the first single crystal substrate. The second transistor is positioned above the first transistor. In the second transistor, a channel is formed in a second single crystal semiconductor that contacts the first single crystal substrate. The second single crystal substrate is positioned above the second transistor. The first insulation layer is positioned between the first transistor and the second transistor. The second insulation layer is positioned between the first insulation layer and the second transistor and has a first joining surface that contacts the first insulation layer. The first single crystal semiconductor contains silicon, and the second single crystal semiconductor contains a metal oxide.

Description

Semiconductor device and manufacturing method thereof

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, semiconductor devices have been developed and are mainly used in LSIs, CPUs, memories, etc. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0005] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] It is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current property of a transistor including an oxide semiconductor. Patent Document 2 discloses a memory device that uses an oxide semiconductor and can retain stored data for a long period of time.

[0007] Also, Non-Patent Document 1 reports a polycrystalline indium oxide film exhibiting high hole mobility and a transistor using the same.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, Nature Communications 13, 1078, (2022).

[0010] An object of one embodiment of the present invention is to provide a semiconductor device using a high-quality semiconductor film. Another object is to provide a semiconductor device using a single-crystal oxide semiconductor film. Another object is to provide a high-performance semiconductor device. Another object is to provide a semiconductor device having favorable electrical characteristics. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device that can be easily highly integrated. Another object is to provide a semiconductor device with low power consumption.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device having a novel structure, and to alleviate at least one of the problems of the prior art.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, a second insulating layer, a first single crystal substrate, and a second single crystal substrate. The first transistor has a channel formed in a first single crystal semiconductor included in the first single crystal substrate. The second transistor is located above the first transistor and has a channel formed in a second single crystal semiconductor in contact with the second single crystal substrate. The second single crystal substrate is located above the second transistor. The first insulating layer is located between the first transistor and the second transistor. The second insulating layer is located between the first insulating layer and the second transistor and has a first bonding surface in contact with the first insulating layer. The first single crystal semiconductor contains silicon. The second single crystal semiconductor contains a metal oxide.

[0014] In the above, it is preferable that the second single crystal substrate have a cubic crystal structure, and the second single crystal semiconductor have a cubic crystal structure.

[0015] In the above, the second single crystal substrate preferably includes an oxide containing yttrium and zirconium, and the second single crystal semiconductor preferably includes indium oxide.

[0016] In the above, the second single crystal semiconductor preferably has a lattice mismatch of −5% to 5% with respect to the second single crystal substrate.

[0017] In the above, it is preferable that the semiconductor device further includes a first conductive layer and a second conductive layer. In this case, it is preferable that the first conductive layer is connected to one of a source electrode and a drain electrode of the first transistor and is embedded in the first insulating layer. It is also preferable that the second conductive layer is connected to one of a source electrode and a drain electrode of the second transistor, is embedded in the second insulating layer, and has a second junction surface in contact with the first conductive layer.

[0018] Another embodiment of the present invention is a method for manufacturing a semiconductor device, the method including: preparing a first single crystal substrate including a first single crystal semiconductor, the first single crystal substrate including a first transistor and a first insulating layer over the first transistor; preparing a second single crystal substrate; forming a semiconductor film including the second single crystal semiconductor over the second single crystal substrate; processing the semiconductor film into an island shape to form a semiconductor layer; forming a gate insulating layer, a gate electrode, a source electrode, and a drain electrode over the semiconductor layer to manufacture a second transistor; forming a second insulating layer over the second transistor;

[0019] In the above, the first single crystal semiconductor preferably contains silicon, and the second single crystal semiconductor preferably contains metal oxide.

[0020] In the above, it is preferable that the second single crystal substrate have a cubic crystal structure, and the second single crystal semiconductor have a cubic crystal structure.

[0021] In the above, the second single crystal substrate preferably includes an oxide containing yttrium and zirconium, and the second single crystal semiconductor preferably includes indium oxide.

[0022] In the above, the second single crystal semiconductor preferably has a lattice mismatch of −5% to 5% with respect to the second single crystal substrate.

[0023] According to one embodiment of the present invention, a semiconductor device using a high-quality semiconductor film can be provided. Alternatively, a semiconductor device using a single-crystal oxide semiconductor film can be provided. Alternatively, a high-performance semiconductor device can be provided. Alternatively, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device that can be easily highly integrated can be provided. Alternatively, a low-power semiconductor device can be provided.

[0024] Advantageous Effects of Invention According to one aspect of the present invention, it is possible to provide a semiconductor device having a novel configuration, and it is possible to at least alleviate at least one of the problems of the prior art.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0026] FIGS. 1A to 1I are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 2A to 2D are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 3A and 3B are schematic diagrams illustrating the vicinity of a bonding surface. FIGS. 4A and 4B are schematic diagrams illustrating the vicinity of a bonding surface. FIGS. 5A to 5E are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 6A to 6D are structural examples of a semiconductor device. FIG. 7 is a structural example of a semiconductor device. FIG. 8 is a structural example of a semiconductor device. FIGS. 9A to 9D are structural examples of a semiconductor device. FIGS. 10A to 10D are structural examples of a semiconductor device. FIGS. 11A1 to 11D2 are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 12A1 to 12C2 are diagrams illustrating a manufacturing method of a semiconductor device. FIG. 13 is a structural example of a memory device. FIGS. 14A and 14B are structural examples of a memory device. FIGS. 15A to 15D are structural examples of a memory device. FIG. 16 is a structural example of a memory device. FIGS. 17A and 17B are configuration examples of a display device. FIG. 18 is a configuration example of a display device. FIGS. 19A to 19C are configuration examples of a display device. FIGS. 20A and 20B are configuration examples of a display device. FIGS. 21A to 21D are configuration examples of an electronic device. FIGS. 22A to 22F are configuration examples of an electronic device. FIGS. 23A to 23G are configuration examples of an electronic device. FIGS. 24A and 24B are configuration examples of an electronic component. FIGS. 25A to 25C are configuration examples of a mainframe computer. FIGS. 26A and 26B are cross-sectional images according to an embodiment. FIGS. 27A and 27B are cross-sectional images according to an embodiment.

[0027] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0029] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0030] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0031] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0032] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0033] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0034] In this specification, when two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film, this is not considered to be an "electrical connection."

[0035] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0036] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0037] In the following description, expressions indicating directions such as "upper" and "lower" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a supporting surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "lower" and the laminate side as "upper."

[0038] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0039] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0040] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described.

[0041] One embodiment of the present invention has a structure in which a first transistor having a channel formed in a part of a first single crystal substrate and a second transistor having a channel formed in a single crystal semiconductor film are stacked above the first transistor. The semiconductor film of the second transistor is preferably made of a metal oxide.

[0042] The semiconductor film having a single crystal structure used in the second transistor is preferably obtained by forming it by an epitaxial method using a second single crystal substrate other than the first single crystal substrate as a base material. If the crystal structure of the second single crystal substrate and the crystal structure of the semiconductor film are the same crystal system, the lattice mismatch between them is small, and therefore a semiconductor film with good crystallinity can be obtained. Note that even if the crystal structures of the two are different, this does not apply when epitaxial growth is performed.

[0043] As the metal oxide used for the semiconductor film, it is preferable to use an oxide containing indium, zinc, tin, or the like. It is particularly preferable to use a metal oxide that is easily crystallized. For example, indium oxide is preferable because it easily crystallizes at low temperatures and can form a single-crystal film with good crystallinity. Furthermore, single-crystal or polycrystalline indium oxide is preferable because it exhibits extremely high reliability. A single-crystal indium oxide film is particularly preferable. For example, in a polycrystalline film, impurities such as hydrogen may be unevenly distributed at the grain boundaries. The hydrogen generates carriers in the semiconductor film, which increases the carrier concentration in the semiconductor film, which may cause fluctuations in the threshold voltage of the transistor. Therefore, by using a single-crystal indium oxide film for the semiconductor film, a transistor with extremely good electrical characteristics can be realized.

[0044] For example, when a cubic oxide film such as indium oxide is used as the semiconductor film, it is preferable to use a single crystal substrate of the same cubic crystal system as the second single crystal substrate. For example, it is preferable to use a cubic single crystal substrate such as a YSZ (yttria-stabilized zirconia) substrate, a zirconium oxide substrate, or a silicon substrate. Alternatively, a semiconductor film having a cubic single crystal structure can be formed using a tetragonal single crystal substrate. The material and crystal structure of the second single crystal substrate can be appropriately selected depending on the crystal structure of the target semiconductor film. For example, a single crystal substrate such as silicon carbide, gallium nitride, or gallium oxide can also be used. Even when the crystal structures of the second single crystal substrate and the target semiconductor film are different, epitaxial growth may be possible by providing a buffer layer to relieve strain between them.

[0045] Furthermore, the smaller the lattice mismatch between the second single-crystal substrate and the semiconductor film, the more preferable. Here, the lattice mismatch corresponds to the difference between the length of the unit lattice vector of the substrate and the length of the unit lattice vector of the thin film, divided by the length of the unit lattice vector of the substrate, when epitaxially growing a thin film on the substrate. Instead of the unit lattice vector, the lattice constant can also be used. For example, when the substrate and the thin film have the same crystal structure, the lattice mismatch can be the difference between the two lattice constants divided by the lattice constant of the substrate. The smaller the lattice mismatch between the second single-crystal substrate and the semiconductor film, the more preferable it is, for example, −5% to 5%, preferably −4% to 4%, more preferably −3% to 3%, and even more preferably −2% to 2%. Here, the lattice mismatch takes a positive value when the unit lattice vector of the thin film is larger than that of the substrate, and a negative value when it is smaller. When the buffer layer is provided, increasing the thickness of the buffer layer may enable epitaxial growth even with a combination with a large lattice mismatch. In this case, the lattice mismatch can be less than −5% or more than 5%. For example, the lattice mismatch between the second single-crystal substrate and the semiconductor film may be −20% to 20%, −15% to 15%, or −10% to 10%.

[0046] The first single crystal substrate can be a semiconductor substrate. Typically, a single crystal silicon substrate is preferably used. Alternatively, a semiconductor substrate made of a single element, a compound semiconductor substrate, or an insulating substrate on which a single crystal semiconductor thin film is formed can be used. A first transistor having a channel formed in a part of the first single crystal substrate can be provided on the first single crystal substrate. A first insulating layer having a bonding surface with the second single crystal substrate is provided on the first transistor.

[0047] After forming a single-crystal semiconductor film on a second single-crystal substrate, the semiconductor film is processed into an island shape. By forming a gate insulating layer, a gate electrode, and source and drain electrodes on the island-shaped semiconductor film (hereinafter also referred to as a semiconductor layer), a transistor in which a channel is formed in the single-crystal semiconductor can be manufactured on the second single-crystal substrate. Then, a second insulating layer having a bonding surface with the first single-crystal substrate is formed on the transistor.

[0048] Next, the first single crystal substrate and the second single crystal substrate are bonded together. At this time, the surfaces of the first insulating layer and the second insulating layer are bonded together so that they are in contact with each other. Using the same material for the first insulating layer and the second insulating layer is preferable because it increases the bonding strength. Furthermore, since the surfaces of the first insulating layer and the second insulating layer are preferably as flat as possible, it is preferable to perform a planarization treatment beforehand. After bonding, the surface of the first insulating layer facing the second insulating layer and the surface of the second insulating layer facing the first insulating layer each form a bonding surface.

[0049] Through the above steps, a semiconductor device can be manufactured in which a first transistor having a channel formed in a part of a first single crystal substrate and a second transistor having a channel formed in a single crystal semiconductor film are stacked. In this case, the stacked structure including the first transistor and the stacked structure including the second transistor are upside down across the junction plane.

[0050] After bonding the first single crystal substrate and the second single crystal substrate, the second single crystal substrate may be removed, or the second single crystal substrate may be thinned by grinding (also referred to as back-grinding). Furthermore, functional elements such as light-emitting elements, light-receiving elements, sensor elements, and transistors may be fabricated on the back surface of the second single crystal substrate (the surface opposite to the second transistor). In this case, the functional elements may be connected to the second transistor through plugs provided in the second single crystal substrate. This allows for the fabrication of a highly functional semiconductor device. For example, when a display element is used as the functional element, it is possible to stack the circuit and the display element, thereby realizing a display device with a small chip area, extremely high resolution, and high display quality.

[0051] A more specific example will be described below with reference to the drawings.

[0052] 1A to 2D are schematic cross-sectional views illustrating steps of a manufacturing method of a semiconductor device according to one embodiment of the present invention.

[0053] First, a substrate 11 is prepared ( FIG. 1A ). The substrate 11 can be a single crystal substrate. For example, a single crystal substrate such as YSZ, zirconium oxide, silicon, silicon carbide, gallium nitride, or gallium oxide can be used. Rare earth oxides and lanthanide oxides, such as yttrium oxide, erbium oxide, gadolinium oxide, and ytterbium oxide, can also be used. In particular, when indium oxide is used for the semiconductor film 21f, it is preferable to use yttrium oxide or erbium oxide. The substrate 11 can be made of a material that has a small lattice mismatch with the semiconductor film 21f to be formed later. Furthermore, if the substrate 11 is to be removed later, it is not limited to an insulating substrate; a conductive substrate or a semiconductor substrate can also be used.

[0054] Next, a semiconductor film 21f is formed on the substrate 11 (FIG. 1B). A metal oxide can be used for the semiconductor film 21f. In particular, it is preferable to use an oxide film containing indium, tin, or zinc as a main component. Among these, single-crystal indium oxide is particularly preferable because it combines high mobility and high reliability.

[0055] The semiconductor film 21f can be formed by a method such as atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), pulsed laser deposition (PLD), molecular beam epitaxy (MBE), or a wet method.

[0056] The semiconductor film 21f is preferably formed while the substrate 11 is heated. This allows for a single-crystal film with fewer defects. Furthermore, a higher heating temperature for the substrate 11 is preferable because it can purify the surface of the substrate 11 and reduce lattice defects. On the other hand, if the temperature of the substrate 11 during film formation is too high, oxygen in the film may be desorbed, potentially preventing the formation of a film with the desired composition. Therefore, the temperature of the substrate 11 during film formation can be set to between room temperature and 1200°C, preferably between 100°C and 600°C. Alternatively, the substrate 11 can be preheated to a high temperature (1000°C or higher) in a film formation apparatus, and then the surface temperature of the substrate 11 can be lowered to 600°C or lower without exposing it to the atmosphere, allowing the semiconductor film 21f to be formed.

[0057] In particular, indium oxide is preferably used as the semiconductor film 21f. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor. Furthermore, by using indium oxide having a single crystal structure for the channel formation region of the transistor, a highly reliable transistor can be realized. The band gap of indium oxide is 2.5 eV or more and 3.7 eV or less. By using indium oxide with a wide band gap for the channel formation region of the transistor, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0058] When a film having a cubic crystal structure, such as indium oxide, is used for the semiconductor film 21f, it is preferable to use a substrate having a cubic crystal structure for the substrate 11. This allows the semiconductor film 21f to be epitaxially grown, thereby improving the crystallinity of the semiconductor film 21f. For example, zirconium oxide or yttria-stabilized zirconia (YSZ), which are cubic crystal structures, can be used for the substrate 11. Note that when the semiconductor film 21f and the substrate 11 have the same crystal structure, the crystal orientation of the surface of the substrate 11 is not particularly limited. For example, the crystal orientation of the surface of the substrate 11 may be

[100] ,

[110] , or

[111] . Note that when a YSZ substrate is used for the substrate 11 and an indium oxide film is used for the semiconductor film 21f, it is particularly preferable to use a YSZ substrate having a surface crystal orientation of

[100] or

[111] for the substrate 11, in terms of lattice mismatch, as described below. The substrate 11 may also be a substrate whose surface is tilted from a specific crystal plane, ie, a substrate whose off angle is 0° or more.

[0059] It is also preferable that there is a small lattice mismatch between the semiconductor film 21f and the substrate 11. By selecting a material for the substrate 11 that reduces the lattice mismatch, the crystallinity of the semiconductor film 21f can be improved.

[0060] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (e.g., semiconductor film 21f) with respect to the crystals of the film to be formed (e.g., substrate 11) is expressed as Δa=((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the film to be formed.

[0061] The smaller the absolute value of the lattice mismatch Δa between the substrate 11 and the semiconductor film 21f, the more preferable, and it is most preferably 0. For example, Δa is preferably −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less. The smaller the lattice mismatch Δa, the smaller the distortion of the semiconductor film 21f can be, and the larger the critical film thickness for misfit dislocations, so that even if the semiconductor film 21f is thick, it can be a film with high crystallinity.

[0062] For example, indium oxide with a cubic crystal structure (bixbyite type) has a lattice constant of 1.0117 nm (see ICSD (Inorganic Crystal Structure Database) col.code.14387). ０．９ Y ０．１ O １．９５ ) has a lattice constant of 0.51481 nm (see ICSD coll.code.248790). Therefore, the lattice mismatch of the crystal grains of the indium oxide film with respect to the crystal grains of YSZ is −1.74%. Here, since the lattice constant of YSZ changes depending on the yttrium content, by setting the yttrium content in YSZ to 2 atomic % or more and 15 atomic % or less, preferably 5 atomic % or more and 10 atomic % or less, the lattice mismatch between YSZ and indium oxide can be reduced, and a single-crystal indium oxide film with few defects can be formed.

[0063] It should be noted that the crystal orientation of the substrate 11 and that of the semiconductor film 21f may not necessarily be the same. For example, a film having crystals of a hexagonal or trigonal structure may be used under indium oxide having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the substrate 11 to

[001] and the crystal orientation of the underside of the semiconductor film 21f to

[111] , the requirements regarding the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe３ O ７ There are various types of structures, including modified structures.

[0064] The semiconductor film 21f is not limited to indium oxide, and a metal oxide film containing indium, tin, or zinc as its main component can be used. Here, the term "main component" refers to a metal oxide in which the ratio of the target atoms to the total number of atoms of the metal elements that make up the metal oxide is 0.1% or more. Elements with a ratio of less than 0.1% are sometimes called impurities.

[0065] 3A and 3B are schematic cross-sectional views of the semiconductor film 21f near the interface between the substrate 11. Fig. 3A corresponds to the case where the lattice constant of the semiconductor film 21f is smaller than that of the substrate 11, i.e., Δa<0, and Fig. 3B corresponds to the case where Δa>0.

[0066] In the substrate 11, elements 15s are periodically arranged, and in the semiconductor film 21f formed on the substrate 11, elements 15f are periodically arranged. Because the lattice constants differ between the substrate 11 and the semiconductor film 21f, the lattice is distorted in the semiconductor film 21f near the substrate 11, thereby maintaining the continuity of the lattice at the interface. The thicker the region of the semiconductor film 21f where the lattice is distorted, the easier it is to relax the distortion, and the less likely dislocations and the like will occur. The thickness of this region can be as thin as one atomic layer or as thick as several μm.

[0067] At this time, the lattice of the semiconductor film 21f may be distorted so as to expand or contract in the in-plane direction, but may not be distorted much in the film thickness direction. For example, in the general relationship between stress and strain, when an external force is applied to an object and it expands in a certain direction, it generally contracts in the direction perpendicular to that (and vice versa when it contracts due to an external force), but the semiconductor film 21f may show a different tendency.

[0068] 4A and 4B show an example in which an intermediate layer 16 is present between the substrate 11 and the semiconductor film 21f. The intermediate layer 16 functions as a buffer layer to relieve stress associated with lattice mismatch between the substrate 11 and the semiconductor film 21f. The presence of the intermediate layer 16 relieves strain in the semiconductor film 21f, thereby reducing defects such as dislocations and improving the crystallinity of the semiconductor film 21f. The intermediate layer 16 may be a low-density region due to the presence of sites where no atoms exist. Furthermore, the element 15m located in the intermediate layer 16 may be a mixture of elements constituting the semiconductor film 21f and elements constituting the substrate 11. In this case, the intermediate layer 16 may also be referred to as a mixed layer.

[0069] The intermediate layer 16 can be confirmed, for example, in an image obtained by high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) of a cross section near the interface between the substrate 11 and the semiconductor film 21f. The intermediate layer 16 can be observed as a layer with lower contrast than other regions. The thickness of the intermediate layer 16 varies depending on the crystal orientation of the substrate 11, and may be one atomic layer, two atomic layers, or more.

[0070] Next, a conductive film 24f is formed on the semiconductor film 21f (FIG. 1C). The conductive film 24f can be made of a conductive material that is less likely to diffuse oxygen, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. This prevents oxidation by oxygen contained in the semiconductor film 21f and other materials, which can reduce the conductivity. The conductive film 24f can be formed by a method such as sputtering, ALD, or CVD.

[0071] Next, a resist mask is formed on the conductive film 24f, and unnecessary portions of the conductive film 24f and the semiconductor film 21f are removed by etching to form island-shaped conductive layers 24 and semiconductor layers 21 (FIG. 1D). The resist mask is then removed. While dry etching or wet etching can be used for the etching, dry etching is preferred because it facilitates fine processing.

[0072] Next, an insulating layer 32 functioning as a barrier film and an insulating layer 33a functioning as an interlayer insulating film are formed in this order to cover the conductive layer 24 and the semiconductor layer 21 (FIG. 1E). The insulating layer 32 and the insulating layer 33a can be formed by a sputtering method, an ALD method, a CVD method, or the like.

[0073] It is preferable to use an insulating material such as silicon nitride, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) for the insulating layer 32. These materials have barrier properties against oxygen, hydrogen, and water, and can therefore prevent these impurities from diffusing into the semiconductor layer 21.

[0074] The insulating layer 33a is preferably made of an insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc. By using a material with a low dielectric constant for the insulating layer 33a, parasitic capacitance can be reduced.

[0075] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen atoms are more abundant than nitrogen atoms. A nitride oxide refers to a material having a composition in which nitrogen atoms are more abundant than oxygen atoms. For example, silicon oxynitride refers to a material having a composition in which oxygen atoms are more abundant than nitrogen atoms, and silicon nitride oxide refers to a material having a composition in which nitrogen atoms are more abundant than oxygen atoms.

[0076] Next, the insulating layer 33a, the insulating layer 32, and a portion of the conductive layer 24 are removed by etching to form a groove that reaches the semiconductor layer 21 and the substrate 11 ( FIG. 1F ). At this time, the conductive layer 24 is divided into two at the groove. An insulating film 22f is then formed along the groove ( FIG. 1G ). A conductive film that becomes the conductive layer 23 is then formed on the insulating film 22f to fill the groove. Next, a planarization process is performed by CMP until the insulating layer 33a is exposed, thereby forming the insulating layer 22 and the conductive layer 23 in the groove ( FIG. 1H ). The insulating layer 22 functions as a gate insulating layer, and the conductive layer 23 functions as a gate electrode. Furthermore, the pair of conductive layers 24 divided on the semiconductor layer 21 function as a source electrode and a drain electrode, respectively. In this manner, the transistor 10 can be fabricated.

[0077] A single layer or a laminate of insulating materials such as silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, hafnium aluminate, etc. can be used as the insulating layer 22. The insulating layer 22 can be formed by a film formation method such as sputtering, CVD, or ALD, but the ALD method, which has high step coverage, is preferred from the viewpoint of withstand voltage because it allows the layer to be formed to a uniform thickness even inside the trench.

[0078] It is preferable to use a low-resistance conductive material such as tungsten, molybdenum, copper, or aluminum for the conductive layer 23. It is also preferable to form the conductive layer 23 in a laminated structure, and to provide a film of a conductive material that is difficult for oxygen to diffuse into, which can be used for the conductive layer 24, on the side in contact with the insulating layer 22. This makes it possible to prevent the conductive layer 23 from being oxidized by oxygen diffusing from the insulating layer 22 or the like, and thereby preventing a decrease in conductivity.

[0079] Thereafter, an insulating layer 33b is formed to cover the transistor 10 and the insulating layer 33a. The insulating layer 33b functions as an interlayer insulating film and can be formed by the same method as the insulating layer 33a. Next, openings reaching the conductive layer 24 are formed in the insulating layers 33b, 33a, and 32. Next, a conductive film is formed to fill these openings, and then a planarization process is performed by CMP until the insulating layer 33b is exposed, thereby forming a plug 61c connecting to the conductive layer 24. The conductive film is preferably formed by CVD.

[0080] Next, a conductive film is formed and unnecessary portions are removed by etching to form a conductive layer 71c (FIG. 1I). The conductive layer 71c is connected to the conductive layer 24 via the plug 61c.

[0081] Next, an insulating layer 33c is formed to cover the insulating layer 33b and the conductive layer 71c. Then, an opening is formed in the insulating layer 33c down to the conductive layer 71c, and a plug 61d is formed in the opening. Next, a conductive layer 71d is formed on the insulating layer 33c. An insulating film is then formed to cover the insulating layer 33c and the conductive layer 71d, and a planarization process is performed until the top surface of the conductive layer 71d is exposed, thereby forming the insulating layer 33d ( FIG. 2A ). This allows the conductive layer 71d to be embedded in the insulating layer 33d, and the top surfaces of these layers are planarized and aligned at the same height.

[0082] This completes the process on the substrate 10 side.

[0083] Next, a substrate 51 on which a transistor 50 is provided is prepared (FIG. 2B).

[0084] The substrate 51 is a single-crystal semiconductor substrate, and the transistor 50 is provided thereon. The transistor 50 has a semiconductor region 51c formed in a part of the substrate 51. The substrate 51 can typically be made of single-crystal silicon. Alternatively, a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, gallium nitride, or the like can be used. Furthermore, a semiconductor substrate having an insulator region within the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, can also be used. Alternatively, a substrate having a thin semiconductor film provided on an insulating substrate such as a glass substrate, a quartz substrate, a sapphire substrate, a YSZ substrate, or a resin substrate can also be used.

[0085] The transistor 50 is provided on a substrate 51 and includes a conductive layer 53 functioning as a gate, an insulating layer 52 functioning as a gate insulating layer, a semiconductor region 51c formed of part of the substrate 51, and a pair of low-resistance regions 54 functioning as a source region and a drain region. The transistor 50 has a channel formed in the single-crystal semiconductor of the substrate 51. The transistor 50 may be either a p-channel type or an n-channel type. An element isolation layer 81 is provided in the substrate 51 between two adjacent transistors 50.

[0086] The transistor 50 has a semiconductor region 51c in which a channel is formed that has a convex shape (fin shape). Although not shown in FIG. 2B , a conductive layer 53 is provided to cover the side and top surfaces of the semiconductor region 51c in the depth direction via an insulating layer 52. Such a transistor 50 is also called a FIN-type transistor.

[0087] An insulating layer 82 is provided to cover a portion of the transistor 50, and insulating layers 83a to 83d are provided in this order on the insulating layer 82. The conductive layer 71a is buried in the insulating layer 83b and is connected to the low-resistance region 54 via a plug 61a that penetrates the insulating layer 83a and the insulating layer 82. The conductive layer 71b is buried in the insulating layer 83d and is connected to the conductive layer 71a via a plug 61b that penetrates the insulating layer 83c.

[0088] The upper surface of the insulating layer 83d is preferably planarized by CMP because it serves as a bonding surface, thereby enabling the upper surfaces of the insulating layer 83d and the conductive layer 71b to be planarized and to be at the same height.

[0089] Next, the substrate 51 and the substrate 11 are bonded together (FIG. 2C).

[0090] The substrates 51 and 11 are joined by overlapping the two substrates so that the insulating layers 33d and 83d face each other. At this time, it is important to adjust the positions so that the conductive layers 71d and 71b come into contact with each other.

[0091] It is preferable that the insulating layer 33d and the insulating layer 83d are a combination that allows bonding. In particular, it is preferable that they are made of the same material. In particular, using silicon oxide for each layer is preferable because it allows for a strong bond. It is also preferable that the conductive layer 71b and the conductive layer 71d are made of the same material because it allows for a lower contact resistance. In particular, using copper for each layer allows for easy bonding and allows for a low contact resistance.

[0092] When bonding, pressing one point on substrate 51 or substrate 11 can spread van der Waals bonds, hydrogen bonds, and the like from that point across the entire bonding surface. If one or both of the bonding surfaces have a hydrophilic surface, hydroxyl groups, water molecules, and the like act as adhesives, and subsequent heat treatment causes the water molecules to diffuse, with the remaining components forming silanol groups (Si—OH) and forming a bond through hydrogen bonds. Furthermore, as hydrogen escapes from this bond, siloxane bonds (O—Si—O) are formed, which become covalent bonds, resulting in a stronger bond.

[0093] Through the above steps, a semiconductor device can be manufactured.

[0094] The semiconductor device illustrated in FIG. 2D has a stacked structure of a transistor 50 whose channel is formed in part of a single crystal substrate and a transistor 10 whose channel is formed in a single crystal oxide semiconductor.

[0095] [Second Example of Manufacturing Method of Semiconductor Device] Hereinafter, an example of a manufacturing method of a semiconductor device will be described, in which a semiconductor film formation method different from the above is used.

[0096] First, a substrate 11a is prepared (FIG. 5A). A single crystal semiconductor substrate is used as the substrate 11a. It is preferable to select a substrate having a small lattice mismatch with the underlying film 12 to be formed later. Here, a case where a silicon substrate is used as the substrate 11a will be described.

[0097] Next, a single-crystal base film 12 is formed on the substrate 11a. The base film 12 can be formed using the same film formation method as the semiconductor film 21f. The base film 12 can be epitaxially grown on the substrate 11a to obtain a high-quality single-crystal film. The base film 12 is preferably an insulating film. In other words, the base film 12 is preferably a film containing a single-crystal insulator.

[0098] Typically, oxides such as YSZ and zirconium oxide can be used for the underlayer 12. Also, rare earth oxides such as yttrium oxide, erbium oxide, gadolinium oxide, and ytterbium oxide, and lanthanoid oxides can also be used. Particularly when indium oxide is used for the semiconductor film 21f, it is preferable to use yttrium oxide or erbium oxide.

[0099] For example, a silicon substrate may be used as the substrate 11a, and a YSZ film may be used as the underlayer 12. However, the underlayer 12 is not limited thereto, and may be any of an insulating film, a conductive film, and a semiconductor film. It is preferable to select a film having a small lattice mismatch with both the substrate 11a and the semiconductor film 21f as the underlayer 12. For example, the underlayer 12 is preferably selected so that the lattice mismatch Δa with both the substrate 11a and the semiconductor film 21f is in the range of −20% to 20%, preferably −10% to 10%, more preferably −7% to 7%, even more preferably −5% to 5%, and even more preferably −4% to 4%. A buffer layer for relieving strain may be provided between the substrate 11a and the underlayer 12 and between the underlayer 12 and the semiconductor film 21f, or both.

[0100] When a silicon substrate is used as the substrate 11a, a native oxide film is formed on the surface of the substrate 11a. Therefore, a step of removing the native oxide film may be added before forming the base film 12. The native oxide film can be removed by wet etching using an acid such as hydrofluoric acid. Alternatively, it can be removed by dry etching. When using dry etching, it is preferable to form the base film 12 immediately after etching without exposing the substrate 11a to the atmosphere. This makes it possible to prevent a native oxide film from being formed again on the substrate 11a.

[0101] Alternatively, the underlayer 12 may be formed without removing the native oxide film of the substrate 11a. Even if a native oxide film is provided, it may be possible to form the underlayer 12 having a crystalline structure that reflects the crystallinity of the substrate 11a. In this case, a layer 12a that functions as a buffer layer may be formed between the substrate 11a and the underlayer 12. By providing the layer 12a between the substrate 11a and the underlayer 12, it is possible to alleviate lattice distortion in the underlayer 12 due to lattice mismatch between the substrate 11a and the underlayer 12, and to form the underlayer 12 having a high-quality single-crystal structure.

[0102] Next, a semiconductor film 21f having a single crystal structure is formed on the base film 12 (FIG. 5B). Because the base film 12 has a single crystal structure, the semiconductor film 21f can be epitaxially grown in the same manner as described above, and can be made into a film having a high-quality single crystal structure.

[0103] Thereafter, similarly to the above, a semiconductor layer 21, a conductive layer 24, an insulating layer 32, an insulating layer 33a, an insulating layer 22, and a conductive layer 23 are formed to manufacture the transistor 10. Furthermore, similarly to the above, an insulating layer 33d and a conductive layer 71d are formed (FIG. 5C).

[0104] Next, the substrate 51 and the substrate 11a are bonded together so that the insulating layer 33d and the insulating layer 83d are bonded together (FIG. 5D).

[0105] The semiconductor device can be fabricated by the above steps. By using the method described here, the range of materials that can be selected for the substrate 11a is widened, and expensive materials are no longer required, thereby reducing costs. For example, a single-crystal silicon substrate can be used for the substrate 11a.

[0106] Thereafter, as shown in FIG. 5E , the substrate 11a may be removed. For example, the substrate 11a can be removed by applying upward force to the edge of the substrate 11a, so that the area with the poorest adhesion becomes the peeling surface, and the substrate 11a can be peeled off. In this case, it is preferable that peeling occurs between the substrate 11a and the underlayer 12. Furthermore, if a layer 12a is present between the substrate 11a and the underlayer 12, peeling may occur inside the layer 12a, at the interface between the layer 12a and the substrate 11a, or at the interface between the layer 12a and the underlayer 12.

[0107] Alternatively, the substrate 11a can be removed by chemical techniques such as etching, physical techniques such as grinding, polishing, or sandblasting, or a combination of these. Separation may also be caused at the interface between the substrate 11a and the semiconductor film 21f by injecting a liquid such as water or alcohol into the interface. In this case, the substrate 11a may be immersed in the liquid, or the liquid may be brought into contact with the side surfaces of the substrate 11a and the base film 12. Furthermore, using a conductive liquid (such as an ionic liquid or water containing carbon dioxide) is preferable because it can suppress the generation of static electricity during the peeling process.

[0108] If layer 12a remains on base film 12 after removing substrate 11a, it is preferable to remove it by etching, CMP, or the like. Also, a damaged layer may be formed on the surface of base film 12 or in its vicinity. In such a case, it is preferable to remove the upper part of base film 12 by etching, CMP, or the like. Alternatively, base film 12 may be completely removed to expose semiconductor layer 21 and insulating layer 32, and a new insulating layer may be provided in contact with the surface.

[0109] After removing the substrate 11a, a functional element such as a light-emitting element, a light-receiving element, a sensor element, or a transistor can be fabricated above the transistor 10 (above the base film 12 in FIG. 5E).

[0110] Although the substrate 11a is removed here, the substrate 11a may be thinned by back-grinding or the like. In this case, it is preferable to thin the substrate 11a to a thickness that allows the formation of vias for embedding plugs. For example, the thickness of the substrate 11a can be set to 1 μm or more and 100 μm or less, preferably 1 μm or more and 50 μm or less, and more preferably 1 μm or more and 20 μm or less.

[0111] The above is a description of an example of the manufacturing method.

[0112] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0113] Embodiment 2 In this embodiment, a structure example and a manufacturing method example of a transistor that can be used in a semiconductor device of one embodiment of the present invention will be described.

[0114] [Configuration Example of Semiconductor Device] Figures 6A to 6D are top views and cross-sectional views of a transistor 200. Figure 6A is a top view of the transistor 200, and Figures 6B to 6D are schematic cross-sectional views corresponding to the cutting lines A1-A2, A3-A4, and A5-A6 in Figure 6A, respectively. Figure 6B corresponds to a cross section of the transistor 200 in the channel length direction, and Figures 6C and 6D correspond to cross sections in the channel width direction, respectively. Figure 7 is an enlarged view of Figure 6B. Note that some components shown in Figure 7 are omitted in Figures 6A and the like.

[0115] The transistor 200 includes a semiconductor layer 230 provided over an insulating layer 201 provided over a substrate (not shown), conductive layers 242a and 242b over the semiconductor layer 230, an insulating layer 250 over the semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. An insulating layer 275 is provided to cover the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, and an insulating layer 280 is provided over the insulating layer 275. A groove reaching the semiconductor layer 230 is provided in the insulating layer 280 and the insulating layer 275, and the conductive layer 242a and the conductive layer 242b are separated from each other by the groove. The insulating layer 250 is provided inside the groove along surfaces of the insulating layer 280, the insulating layer 275, the conductive layer 242a, the conductive layer 242b, and the semiconductor layer 230. The conductive layer 260 is provided over the insulating layer 250 so as to fill the groove. In addition, an insulating layer 282, an insulating layer 283, and an insulating layer 285 are provided in this order to cover the insulating layer 280, the insulating layer 250, and the conductive layer 260.

[0116] The semiconductor layer 230 functions as a channel formation region of the transistor 200. The conductive layer 260 functions as a gate electrode of the transistor 200. The insulating layer 250 functions as a gate insulator of the transistor 200.

[0117] The conductive layer 242a functions as one of a source electrode and a drain electrode of the transistor 200, and the conductive layer 242b functions as the other.

[0118] The conductive layer 242a and the conductive layer 242b preferably have a stacked structure. A conductor that is resistant to oxidation, such as a metal nitride, is preferably used on the side in contact with the semiconductor layer 230. This can prevent the conductive layer 242a and the conductive layer 242b from being excessively oxidized by oxygen contained in the semiconductor layer 230. Furthermore, a metal or alloy having higher conductivity than the layer in contact with the semiconductor layer 230 is preferably used on the side not in contact with the semiconductor layer 230. This allows the conductive layer 242a and the conductive layer 242b to function as wirings or electrodes with high conductivity.

[0119] In the conductive layers 242a and 242b, a metal nitride is preferably used on the side in contact with the semiconductor layer 230, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when they absorb oxygen.

[0120] The insulating layer 201 is a layer in contact with the semiconductor layer 230, and a material having a single crystal structure can be used. For example, single crystal materials such as YSZ, zirconium oxide, silicon, silicon carbide, gallium nitride, and gallium oxide can be used. In particular, it is preferable to use an oxide insulating material such as zirconium oxide or YSZ. Furthermore, oxides of rare earth elements and oxides of lanthanides such as yttrium oxide, erbium oxide, gadolinium oxide, and ytterbium oxide can also be used. In particular, when indium oxide is used for the semiconductor layer 230, it is preferable to use yttrium oxide or erbium oxide.

[0121] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the semiconductor layer 230. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 230 refer to, for example, elements other than the main components constituting the semiconductor layer 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0122] The semiconductor layer 230 is preferably made of a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0123] The band gap of a metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. A transistor having a metal oxide in a channel formation region like this is called an OS transistor. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0124] It is preferable to use indium oxide as the semiconductor layer 230. In particular, it is preferable to use a single-crystal indium oxide film. Note that it is preferable to use a crystalline film for the semiconductor layer 230, and it is particularly preferable to use indium oxide having a single-crystal structure. However, indium oxide having a polycrystalline structure or a microcrystalline structure can also be used. By using indium oxide having a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

[0125] When indium oxide having a polycrystalline structure is used, it is preferable that no crystal grain boundaries be observed at least in the channel formation region (the region overlapping with the conductive layer 260). Thus, even indium oxide having a polycrystalline structure can achieve the same effects as in the case of indium oxide having a single crystal structure.

[0126] The thickness of the semiconductor layer 230 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. By setting the thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be improved.

[0127] Among oxide semiconductors with high crystallinity, indium oxide is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO (In—Ga—Zn—O-based oxide) film. Therefore, indium oxide can be said to be a film through which one or both of hydrogen and oxygen are more easily supplied and discharged than, for example, an IGZO film. This can be said to make it difficult for excess oxygen or excess hydrogen, which can become carriers or fixed charges, to accumulate in the semiconductor layer 230, thereby making it possible to provide a transistor with good electrical characteristics and reliability.

[0128] The semiconductor layer 230 preferably has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0129] Furthermore, since gallium has the property of easily bonding with excess oxygen atoms, a large gallium content may result in a large variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, the gallium concentration in the semiconductor layer 230 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0130] Other metal oxides that can be used for the semiconductor layer 230 include tin oxide, zinc oxide, indium tin oxide, indium titanium oxide, indium gallium oxide, indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, and indium gallium aluminum zinc oxide. Alternatively, indium tin oxide, gallium tin oxide, aluminum tin oxide, and the like containing silicon can also be used. When these are used, the film preferably has at least crystallinity, and more preferably has a single crystal structure.

[0131] The insulating layer 250 functioning as a gate insulating layer preferably has a function of capturing and fixing hydrogen, which can reduce the hydrogen concentration in the channel formation region of the semiconductor layer 230. As a result, the channel formation region can be made i-type or substantially i-type.

[0132] Here, the insulating layer 250 preferably has a stacked structure of a first layer in contact with the semiconductor layer 230, a second layer over the first layer, and a third layer over the second layer. In this case, it is preferable that the first layer has a function of capturing hydrogen and fixing hydrogen.

[0133] Examples of insulators capable of capturing and fixing hydrogen include metal oxides having an amorphous structure. For the first layer, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0134] Furthermore, it is preferable to use a high dielectric constant (high-k) material for the first layer. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the first layer makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0135] For the first layer, it is preferable to use an oxide containing one or both of aluminum and hafnium, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0136] Next, the second layer preferably uses an insulator having a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0137] Alternatively, a fourth layer may be provided on the second layer. In this case, the fourth layer may be an insulator that can be used for the first layer. For example, hafnium oxide may be used for the fourth layer. Here, by providing the fourth layer between the third layer and the second layer, hydrogen contained in the second layer and the like can be more effectively captured and fixed.

[0138] The third layer preferably has a barrier property against oxygen. The third layer is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260, and between the insulating layer 280 and the conductive layer 260. This structure can prevent oxygen contained in the channel formation region of the semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, it can prevent oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The third layer is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the third layer. In this case, the third layer is an insulator containing at least nitrogen and silicon.

[0139] Furthermore, the third layer preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0140] The insulating layer 275 preferably has a barrier property against oxygen. The insulating layer 275 is provided between the insulating layer 280 and the conductive layer 242a and between the insulating layer 280 and the conductive layer 242b. This structure can prevent oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242a and the conductive layer 242b. Therefore, it is possible to prevent the conductive layer 242a and the conductive layer 242b from being oxidized by oxygen contained in the insulating layer 280, thereby increasing the resistivity and reducing the on-current. The insulating layer 275 is preferably at least less permeable to oxygen than the insulating layer 280. For example, it is preferable to use silicon nitride as the insulating layer 275. In this case, the insulating layer 275 becomes an insulator containing at least nitrogen and silicon.

[0141] In addition to the above structure, in this embodiment, the semiconductor device preferably has a structure that suppresses hydrogen from being mixed into the transistor 200 and the like. For example, an insulator that has a function of suppressing hydrogen diffusion is preferably provided so as to cover the transistor 200. In the semiconductor device described in this embodiment, the insulator is, for example, an insulating layer 282 or an insulating layer 283. Alternatively, a similar film may be provided under the transistor 200.

[0142] It is preferable that one or more of the insulating layers 282 and 283 function as a barrier insulator that prevents impurities such as water and hydrogen from diffusing into the transistor 200 from above the transistor 200. Therefore, one or more of the insulating layers 282 and 283 can prevent impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0143] The insulating layers 282 and 283 preferably include an insulator that has a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulating layer 283 is preferably made of silicon nitride, which has a higher hydrogen barrier property. Furthermore, the insulating layer 282 preferably includes aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen. This can suppress diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulating layer 283 to the transistor 200 and the like. Furthermore, oxygen contained in the insulating layer 280 and the like can be suppressed from diffusing upward from the transistor 200 and the like through the insulating layer 282 and the like. Furthermore, providing a film similar to one or both of the insulating layers 282 and 283 below the transistor 200 can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 and the like.

[0144] The insulating layers 271a and 271b are inorganic insulators that function as etching stoppers and protect the conductive layers 242a and 242b when the conductive layers 242a and 242b are processed. Furthermore, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, respectively, they are preferably inorganic insulators that do not easily oxidize the conductive layers 242a and 242b. For example, the insulating layers 271a and 271b may have a stacked structure, with silicon nitride used on the side in contact with the conductive layers 242a and 242b and silicon oxide used on the other side.

[0145] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, 275, and 271a, and the conductive layer 240a and the insulating layer 241a are provided in the openings. The insulating layer 241a is provided in contact with the sidewall of the opening, and the conductive layer 240a is provided inside the insulating layer 241a. Furthermore, openings reaching the conductive layer 242b are formed in the insulating layers 285, 283, 282, 280, 275, and 271b, and the conductive layer 240b and the insulating layer 241b are provided in the openings. The insulating layer 241b is provided in contact with the sidewall of the opening, and the conductive layer 240b is provided inside the insulating layer 241b. The conductive layers 240 a and 240 b function as vias that connect a wiring or the like provided over the transistor 200 to the source or drain of the transistor 200 .

[0146] The conductive layers 240a and 240b are preferably made of a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layers 240a and 240b may have a stacked structure.

[0147] 7, the conductive layer 240a and the conductive layer 240b may have a two-layer laminated structure. The conductive layer 240a has a conductive layer 240a1 formed along the opening and a conductive layer 240a2 formed inside the conductive layer 240a1. The conductive layer 240b has a conductive layer 240b1 formed along the opening and a conductive layer 240b2 formed inside the conductive layer 240b1.

[0148] The conductive layers 240a1 and 240b1 are preferably made of a conductive material such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, which has a function of suppressing the permeation of impurities such as water and hydrogen. Furthermore, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. Providing the conductive layers 240a1 and 240b1 can suppress impurities such as water and hydrogen from entering the semiconductor layer 230 through the conductive layers 240a2 and 240b2. Note that the conductive layers 240a2 and 240b2 may be made of the same conductive materials that can be used for the conductive layers 240a and 240b.

[0149] 6B, the upper surfaces of the conductive layers 240a and 240b may be formed to coincide or substantially coincide with the upper surface of the insulating layer 285. As shown in FIG. 7, the lower portion of the conductive layer 240a may be formed to be embedded in the conductive layer 242a. Similarly, the lower portion of the conductive layer 240b may be formed to be embedded in the conductive layer 242b.

[0150] The insulating layers 241a and 241b may be formed using a barrier insulator that can be used for the insulating layer 275, for example. For example, silicon nitride may be used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, and 275, as well as the insulating layer 271a or 271b, respectively. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 from entering the semiconductor layer 230 through the conductive layers 240a and 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 240a and 240b.

[0151] The conductive layer 260 functions as a gate electrode of the transistor 200. Here, the conductive layer 260 is preferably provided to extend in the channel width direction as shown in Figures 6A and 6C. With this structure, when a plurality of transistors are provided, the conductive layer 260 functions as a wiring.

[0152] The conductive layer 260 may have a stacked structure. Figure 7 shows an example in which the conductive layer 260 includes a conductive layer 260a located on the side in contact with the insulating layer 250 and a conductive layer 260b thereon. In this case, the conductive layer 260a is preferably made of a conductive material that is resistant to oxidation, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, or a conductive material that has a function of suppressing oxygen diffusion. The conductive layer 260b is preferably made of a low-resistance conductive material, such as tungsten, copper, or aluminum.

[0153] The insulating layer 280 preferably has a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 280 preferably includes one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide with vacancies. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0154] [Modification] The following describes an example in which the configuration is partially different from the above-described configuration example, and the description of parts that overlap with the above will be omitted.

[0155] 8 illustrates an example in which a transistor 200 includes a conductive layer 205 that functions as a back gate. The structure illustrated in FIG.

[0156] The conductive layer 205 is provided so as to be embedded in the insulating layer 202. The insulating layer 201 is provided so as to cover the insulating layer 202 and the conductive layer 205.

[0157] The conductive layer 205 functions as a second gate (back gate) of the transistor 200. The conductive layer 205 is provided in a region overlapping with the conductive layer 260 with the semiconductor layer 230 interposed therebetween. By providing the conductive layer 205 and applying an appropriate potential to the conductive layer 205, the threshold voltage of the transistor 200 can be controlled. Furthermore, since the potential on the back channel side of the semiconductor layer 230 can be fixed, variation in the electrical characteristics of the transistor 200 can be reduced. The conductive layer 205 may be applied with the same potential or signal as any one of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260.

[0158] The conductive layer 205 can be formed using a material that can be used for the conductive layer 260. The conductive layer 205 may have a stacked structure.

[0159] At this time, the insulating layer 201 functions as a second gate insulating layer.

[0160] A silicon oxide film can be used for the insulating layer 202. Note that it is preferable to provide an insulating film having a barrier property against oxygen, such as silicon nitride or aluminum oxide, between the insulating layer 202 and the conductive layer 205 because oxidation of the conductive layer 205 can be suppressed.

[0161] 9A to 9D show examples of a transistor 200 that is partially different from the above-described structure. FIG. 9A is a top view, and FIGS. 9B to 9D are cross-sectional views, respectively. The structure shown in FIGS. 9A to 9D differs from the above-described structure mainly in that an insulating layer 255 is included. Furthermore, the insulating layer 250 is in contact with a side surface of the insulating layer 255.

[0162] Here, each of the conductive layers 242a and 242b is shown to have a two-layer structure. The conductive layer 242a has a stacked structure of a conductive layer 242a1 and a conductive layer 242a2 over the conductive layer 242a1. The conductive layer 242b has a stacked structure of a conductive layer 242b1 and a conductive layer 242b2 over the conductive layer 242b1.

[0163] Insulating layer 255 is disposed inside an opening formed in insulating layer 280 or the like, and contacts the side surface of insulating layer 280, the side surface of conductive layer 242a2, the side surface of conductive layer 242b2, the top surface of conductive layer 242a1, the top surface of conductive layer 242b1, and the top surface of insulating layer 201 in the opening. In other words, insulating layer 255 can be said to be formed in a sidewall shape in contact with the side wall of the opening formed in insulating layer 280 or the like. Here, the side wall of the opening corresponds to, for example, the side surface of insulating layer 280 or the like in the opening.

[0164] The insulating layer 255 preferably has a barrier property against oxygen. The insulating layer 255 having a barrier property against oxygen can prevent the side surfaces of the conductive layers 242a and 242b from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200. The insulating layer 255 can be formed using a barrier insulator that can be used for the insulating layer 275, for example. For example, silicon nitride can be used for the insulating layer 255.

[0165] The opening in the insulating layer 280 overlaps the region between the conductive layer 242a2 and the conductive layer 242b2. In a top view, the side surfaces of the insulating layer 280 in the opening coincide or substantially coincide with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2. Furthermore, portions of the conductive layers 242a1 and 242b1 are formed to protrude into the opening. In other words, the portion of the conductive layer 242a1 on which the insulating layer 255 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242a1) protrudes toward the conductive layer 260 more than the conductive layer 242a2. Similarly, the portion of the conductive layer 242b1 on which the insulating layer 255 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242b1) protrudes toward the conductive layer 260 more than the conductive layer 242b2.

[0166] Here, a portion of the top surface of the conductive layer 242a1 is in contact with the conductive layer 242a2, and a portion of the top surface of the conductive layer 242b1 is in contact with the conductive layer 242b2. Therefore, inside the opening, the insulating layer 255 is in contact with another portion of the top surface of the conductive layer 242a1, another portion of the top surface of the conductive layer 242b1, a side surface of the conductive layer 242a2, and a side surface of the conductive layer 242b2. Furthermore, the insulating layer 250 is in contact with the top surface of the semiconductor layer 230, the side surface of the conductive layer 242a1, the side surface of the conductive layer 242b1, and the side surface of the insulating layer 255.

[0167] The insulating layer 255 is formed by anisotropic etching to have a sidewall shape in contact with the side wall of the opening provided in the insulating layer 280. The insulating layer 255 is formed in contact with the side surface of the conductive layer 242a2 and the side surface of the conductive layer 242b2 and has a function of protecting the conductive layer 242a2 and the conductive layer 242b2.

[0168] 10A to 10D show examples of the structure of a transistor 200. The structure shown in FIGS. 10A to 10D differs from the above-described modification 2 mainly in that the insulating layer 255 is not provided.

[0169] In a configuration in which the insulating layer 255 is not provided, a part of the insulating layer 250 is arranged to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Also, a part of the conductive layer 260 may be arranged to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Here, the protruding portions of the conductive layer 242a1 and the conductive layer 242b1 are in contact with the insulating layer 250. Also, the side surface of the insulating layer 250 is in contact with the side surface of the insulating layer 280, the side surface of the conductive layer 242a2, and the side surface of the conductive layer 242b2.

[0170] The portions of the insulating layer 250 that are disposed in the openings provided in the insulating layer 280 are formed to reflect the shape of the openings, and therefore the insulating layer 250 is formed to reflect the shapes of the conductive layers 242a1 and 242b1 that protrude into the openings.

[0171] 10B , in a cross-sectional view of the transistor 200 in the channel length direction, the distance between the conductive layer 242a1 and the conductive layer 242b1 is smaller than the distance between the conductive layer 242a2 and the conductive layer 242b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0172] [Manufacturing Method Example] An example of a manufacturing method of a transistor of one embodiment of the present invention will be described below, taking the transistor 200 illustrated in the above "Structure Example of Semiconductor Device" and in FIGS.

[0173] 11A1, 11B1, 11C1, 11D1, 12A1, 12B1, and 12C1 are cross-sectional schematic views at various stages of an exemplary fabrication method described below, and FIGS. 11A2, 11B2, 11C2, 11D2, 12A2, 12B2, and 12C2 are perspective views. Note that the perspective views are partially cut away. In addition, in the perspective views, only the outlines of some components (such as insulating layers) are indicated by dashed lines.

[0174] First, a structure is prepared in which a semiconductor film 230f is formed on an insulating layer 201. The insulating layer 201 corresponds to the substrate 11 or the base film 12 in Embodiment 1. The semiconductor film 230f corresponds to the semiconductor film 21f in Embodiment 1, and its manufacturing method can be referred to. Note that this point corresponds to the stage of FIG. 1B in Embodiment 1.

[0175] It is preferable to perform heat treatment on the semiconductor film 230f. For example, the heat treatment can be performed at 450° C. for one hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. The heat treatment can improve the crystallinity of the semiconductor film 230f. Furthermore, the heat treatment can supply oxygen into the semiconductor film 230f and reduce oxygen vacancies in the semiconductor film 230f. This can improve the reliability of the transistor 200. The heat treatment can also remove hydrogen from the semiconductor film 230f.

[0176] Next, a conductive film 242f is formed on the semiconductor film 230f (FIGS. 11A1 and 11A2). After the semiconductor film 230f is formed, the conductive film 242f is formed on and in contact with the semiconductor film 230f without an etching process or the like. This makes it possible to protect the top surface of the semiconductor film 230f with the conductive film 242f. This makes it possible to suppress diffusion of impurities into the semiconductor layer 230 that constitutes the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0177] The conductive film 242f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0178] In this embodiment, tantalum nitride is deposited as the conductive film 242f by sputtering. Note that heat treatment may be performed before the deposition of the conductive film 242f. The heat treatment may be performed under reduced pressure, and the conductive film 242f may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the semiconductor film 230f can be removed, and the moisture and hydrogen concentrations in the semiconductor film 230f can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0179] Next, the semiconductor film 230f and the conductive film 242f are processed into island shapes by lithography to form the semiconductor layer 230 and the conductive layer 242 (FIG. 11B1 and FIG. 11B2).

[0180] The above processing can be performed by dry etching or wet etching. Dry etching is suitable for fine processing. The semiconductor film 230f and the conductive film 242f may be processed under different conditions.

[0181] Further, a layer functioning as a hard mask may be formed over the conductive film 242f. The use of a hard mask is preferable because it improves processability and makes it easier to process the conductive film 242f into a desired shape.

[0182] Here, the semiconductor layer 230 and the conductive layer 242 are preferably processed together into an island shape. At this time, it is preferable that the side edge of the conductive layer 242 coincides or substantially coincides with the side edge of the semiconductor layer 230. With such a structure, the number of steps for manufacturing a semiconductor device according to one embodiment of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0183] 11B1 , the side surfaces of the semiconductor layer 230 and the conductive layer 242 may be tapered. The taper angle of the side surfaces of the semiconductor layer 230 and the conductive layer 242 may be, for example, 60° or more and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulating layer 275 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0184] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left behind using a developer to form a resist mask. Next, an etching process is performed through the resist mask, allowing a conductor, semiconductor, or insulator to be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be required.

[0185] The resist mask that is no longer needed after processing can be removed by performing a dry etching treatment such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), a wet etching treatment, a dry etching treatment followed by a wet etching treatment, or a wet etching treatment followed by a dry etching treatment.

[0186] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed on the conductive film 242f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. For example, tungsten may be used as the hard mask material. Etching of the conductive film 242f and the like may be performed after removing the resist mask or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching of the semiconductor film 230f and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0187] Alternatively, a spin-on-carbon (SOC) film and a spin-on-glass (SOG) film may be formed between the workpiece and the resist mask. Using the SOC film and the SOG film as a mask can improve adhesion with the resist mask and improve the durability of the mask pattern. For example, a lithography method can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0188] Next, an insulating layer 275 is formed to cover the semiconductor layer 230 and the conductive layer 242, and an insulating layer 280 is further formed on the insulating layer 275 (FIGS. 11C1 and 11C2).

[0189] As the insulating layer 280, it is preferable to form an insulator having a flat upper surface by forming an insulating film that will become the insulating layer 280 and performing CMP treatment on the insulating film. Note that it is also possible to form a silicon nitride film on the insulating layer 280 by, for example, a sputtering method and perform CMP treatment on the silicon nitride until it reaches the insulating layer 280.

[0190] The insulating layer 275 and the insulating layer 280 can each be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0191] The insulating layer 275 is preferably an insulator having a function of suppressing oxygen permeation. For example, it is preferable to form a silicon nitride film by a PEALD method as the insulating layer 275. Alternatively, the insulating layer 275 may be formed by forming an aluminum oxide film by a sputtering method and then forming a silicon nitride film thereon by a PEALD method. The insulating layer 275 having the above structure can improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0192] Furthermore, it is preferable to form the insulating layer 280 using silicon oxide by a sputtering method. The insulating layer 280 containing excess oxygen can be formed by forming the insulating layer 280 by a sputtering method in an oxygen-containing atmosphere. Furthermore, the hydrogen concentration in the insulating layer 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the formation of the insulating layer. The heat treatment may be performed under reduced pressure, and the insulating layer may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulating layer 275 can be removed. The heat treatment conditions described above can be used for the heat treatment.

[0193] Next, the conductive layer 242, the insulating layer 275, and the insulating layer 280 are processed by lithography to form openings (also referred to as grooves) that reach the semiconductor layer 230 and the insulating layer 201 ( FIGS. 11D1 and 11D2 ). Here, the conductive layer 242 is divided to form conductive layers 242a and 242b. The openings formed in the insulating layer 280 and the insulating layer 275 overlap with the semiconductor layer 230.

[0194] Next, the insulating layer 250 is formed so as to cover the openings formed in the insulating layer 280 and the like. Here, the insulating layer 250 is formed along the openings of the insulating layer 280. The insulating layer 250 is in contact with the insulating layer 280, the conductive layer 242a, the conductive layer 242b, the insulating layer 201, and the semiconductor layer 230.

[0195] The insulating layer 250 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Since the insulating layer 250 is preferably formed to have a thin film thickness, it is preferable to form the insulating layer 250 by an ALD method, which has excellent coverage and is easy to control the film thickness.

[0196] When the insulating layer 250 is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using HCl, etc. as an oxidizing agent, hydrogen diffusing into the semiconductor layer 230 can be reduced.

[0197] It is preferable to perform microwave treatment before, after, or during the formation of the insulating layer 250 .

[0198] More specifically, microwave treatment is preferably performed in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using, for example, a device having a power source that generates high-density plasma using microwaves. In this specification and the like, microwave refers to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0199] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves, for example. The frequency of the microwave treatment device can be typically 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves in the microwave treatment device is preferably 1000 W or more and 10,000 W or less, and preferably 2000 W or more and 5,000 W or less. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the semiconductor layer 230.

[0200] The microwave treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

[0201] Next, a conductive film to be the conductive layer 260 is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. For example, a titanium nitride film and a tungsten film may be stacked by a CVD method.

[0202] Next, the conductive film that will become the insulating layer 250 and the conductive layer 260 is polished by CMP until the insulating layer 280 is exposed. That is, the insulating layer 250 and the portions of the conductive film that are exposed in the openings are removed. This forms the insulating layer 250 and the conductive layer 260 in the openings that reach the semiconductor layer 230 (FIGS. 12A1 and 12A2).

[0203] As a result, the insulating layer 250 is provided in the opening in contact with the conductive layer 242a, the conductive layer 242b, the semiconductor layer 230, and the insulating layer 201. The conductive layer 260 is also arranged to fill the opening with the insulating layer 250 interposed therebetween. In this manner, the transistor 200 is formed.

[0204] Next, an insulating layer 282 is formed over the insulating layer 250, the conductive layer 260, and the insulating layer 280. The insulating layer 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating layer 282 is preferably formed by a sputtering method. The hydrogen concentration in the insulating layer 282 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas.

[0205] Here, by depositing the insulating layer 282 in an atmosphere containing oxygen by a sputtering method, oxygen can be added to the insulating layer 280 during deposition. Thus, the insulating layer 280 can contain excess oxygen.

[0206] Next, an insulating layer 285 is formed over the insulating layer 282 (FIGS. 12B1 and 12B2). The insulating layer 285 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating layer 285 is preferably formed by a sputtering method. The hydrogen concentration in the insulating layer 285 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas.

[0207] Next, openings reaching the conductive layers 242a and 242b are formed in the insulating layer 275, the insulating layer 280, the insulating layer 282, and the insulating layer 285, respectively. The openings may be formed by lithography. The openings are preferably formed by processing the workpiece by dry etching. The shape of the openings in top view can be a circle, a substantially circle such as an ellipse, a polygon such as a rectangle, or a polygon with rounded corners such as a rectangle.

[0208] Next, after the openings are formed, heat treatment can be performed. The temperature for the heat treatment is 100° C. or higher and 600° C. or lower, preferably 250° C. or higher and 550° C. or lower, more preferably 350° C. or higher and 450° C. or lower. Note that the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. Furthermore, since the heat treatment is performed in a state in which the conductive layers 242a and 242b are exposed, the heat treatment is preferably performed in an atmosphere that does not contain an oxidizing gas or oxygen gas. For example, the heat treatment is preferably performed in a nitrogen gas atmosphere at 400° C. for one hour. Note that the heat treatment may be performed under reduced pressure. By the heat treatment, oxygen contained in the insulating layer 280 can be supplied to the semiconductor layer 230 through the insulating layer 250. Furthermore, by performing the heat treatment after the openings are formed in the insulating layer 280, part of the oxygen contained in the insulating layer 280 can be released, and the amount of oxygen contained in the insulating layer 280 can be adjusted. This prevents reliability from being impaired by excess oxygen.

[0209] Next, insulating films to become the insulating layers 241a and 241b are formed along the shapes of the openings. The insulating films can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating films to become the insulating layers 241a and 241b are preferably formed by an ALD method because they are formed in openings with a large aspect ratio. Furthermore, it is preferable to use an insulating film that has a function of suppressing oxygen permeation as the insulating film to become the insulating layers 241a and 241b. For example, it is preferable to form a silicon nitride film by a PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0210] Next, the insulating film is anisotropically etched to form insulating layers 241a and 241b. Here, the insulating layer 241a is formed to cover the sidewalls of the openings over the conductive layer 242a, and the insulating layer 241b is formed to cover the sidewalls of the openings over the conductive layer 242b. Dry etching or the like may be used for anisotropically etching the insulating films that will become the insulating layers 241a and 241b. For example, reactive ion etching is preferably performed. Providing the insulating layers 241a and 241b on the sidewalls of the openings can suppress oxygen permeation from the outside and prevent oxidation of the conductive layers 240a and 240b to be formed next. Furthermore, impurities such as water and hydrogen contained in the insulating layer 280 can be prevented from diffusing into the conductive layers 240a and 240b. Note that the anisotropic etching may form recesses in parts of the top surfaces of the conductive layers 242a and 242b.

[0211] Next, conductive films to be the conductive layers 240a and 240b are formed. The conductive films preferably have a stacked structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, the conductive films can be stacked layers of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive films to be the conductive layers 240a and 240b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0212] Next, CMP treatment is performed to remove parts of the conductive film that will become the conductive layers 240a and 240b, thereby exposing the top surface of the insulating layer 285 (FIGS. 12C1 and 12C2). As a result, the conductive film remains only in the openings, and the conductive layers 240a and 240b can be formed with flat top surfaces. Note that the CMP treatment may remove part of the top surface of the insulating layer 285.

[0213] After the conductive layers 240a and 240b are formed, heat treatment may be further performed. The heat treatment may be performed under the same conditions as those of the above-described heat treatment. By performing the heat treatment, the amount of oxygen supplied to the semiconductor layer 230 can be adjusted. This can improve the electrical characteristics and reliability of the transistor 200.

[0214] Through the above steps, the transistor 200 shown in FIGS. 6A to 6D can be manufactured.

[0215] The transistor 200 described as an example in this embodiment can be replaced with the transistor 10 described as an example in Embodiment 1. This makes it possible to realize a semiconductor device in which a transistor whose channel is formed in a single crystal substrate and a transistor whose channel is formed in an oxide semiconductor film are stacked.

[0216] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0217] 13 to 16. In this embodiment, a configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided will be described.

[0218] The transistors included in the driver circuits including the sense amplifiers described below can be the transistors whose channels are formed in a single crystal substrate (referred to as Si transistors) described in Embodiment 1. The transistors included in the memory cells can be the transistors whose channels are formed in a single crystal oxide semiconductor (referred to as OS transistors) described in Embodiment 1.

[0219] 13 is a block diagram illustrating a configuration example of a memory device 480 according to one embodiment of the present invention. The memory device 480 illustrated in FIG. 13 includes a layer 420 and a stacked layer 470.

[0220] The layer 420 is a layer including a Si transistor. The layer 470 includes stacked element layers 430[1] to 430[m] (m is an integer of 2 or more). The element layers 430[1] to 430[m] include OS transistors. The layer 470 including stacked layers including OS transistors can be provided over the layer 420.

[0221] Elements such as OS transistors and capacitors included in the element layers 430[1] to 430[m] constitute memory cells. In FIG. 13, the element layers 430[1] to 430[m] each include a plurality of memory cells 432 arranged in a matrix of m rows and n columns (n ​​is an integer of 2 or greater).

[0222] In FIG. 13 , the memory cell 432 in the first row and first column is indicated as memory cell 432[1,1], and the memory cell 432 in the mth row and nth column is indicated as memory cell 432[m,n]. In addition, in this embodiment and the like, an arbitrary row may be referred to as row i. In addition, an arbitrary column may be referred to as column j. Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to n. In addition, in this embodiment and the like, the memory cell 432 in the ith row and jth column is indicated as memory cell 432[i,j]. In addition, in this embodiment and the like, when "i+α" (α is a positive or negative integer) is used, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is used, "j+α" is not less than 1 or more than n.

[0223] 13 illustrates, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n]. Note that the number of element layers 430[1] to 430[m] does not necessarily have to be the same as the number of wirings WL (and wirings PL).

[0224] The memory cells 432 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 432 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0225] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conducting state or non-conducting state) of an access transistor that functions as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a wiring for transmitting a back gate potential can be provided separately.

[0226] The memory cells 432 included in each of the element layers 430[1] to 430[m] are connected to a sense amplifier 446 (sense amplifier) ​​via a wiring BL. The wiring BL can be arranged in a direction parallel to or perpendicular to the surface of the substrate on which the layer 420 is provided. The wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] can be configured as wirings arranged vertically in addition to wirings arranged horizontally on the surface of the substrate, thereby shortening the length of the wiring between the element layer 430 and the sense amplifier 446. The signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay. This can reduce the power consumption and signal delay of the memory device 480. Furthermore, the memory cell 432 can operate even if the capacitance of the capacitor included in the memory cell 432 is reduced. This can reduce the size of the memory device 480.

[0227] The layer 420 includes a PSW 471 (power switch), a PSW 472, and a peripheral circuit 422. The peripheral circuit 422 includes a drive circuit 440, a control circuit 473, and a voltage generation circuit 474. Each circuit included in the layer 420 includes a Si transistor.

[0228] In the memory device 480, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0229] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 473.

[0230] The control circuit 473 is a logic circuit having the function of controlling the overall operation of the memory device 480. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 480. Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 so that this operation mode is executed.

[0231] The voltage generation circuit 474 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0232] The driver circuit 440 is a circuit for writing and reading data to and from the memory cells 432. The driver circuit 440 includes a row decoder 442, a column decoder 444, a row driver 443, a column driver 445, an input circuit 447, an output circuit 448, and the sense amplifier 446 described above.

[0233] The row decoder 442 and the column decoder 444 have a function of decoding the signal ADDR. The row decoder 442 is a circuit for specifying a row to be accessed, and the column decoder 444 is a circuit for specifying a column to be accessed. The row driver 443 has a function of selecting a wiring WL specified by the row decoder 442. The column driver 445 has a function of writing data to the memory cell 432, a function of reading data from the memory cell 432, a function of holding the read data, and the like.

[0234] The input circuit 447 has a function of holding a signal WDA. The data held by the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is data (Din) to be written to the memory cell 432. The data (Dout) read from the memory cell 432 by the column driver 445 is output to the output circuit 448. The output circuit 448 has a function of holding Dout. In addition, the output circuit 448 has a function of outputting Dout to the outside of the memory device 480. The data output from the output circuit 448 is a signal RDA.

[0235] The PSW 471 has a function of controlling the supply of VDD to the peripheral circuit 422. The PSW 472 has a function of controlling the supply of VHM to the row driver 443. In this example, the high power supply potential of the memory device 480 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to set the word line to a high level and is higher than VDD. The on / off of the PSW 471 is controlled by a signal PON1, and the on / off of the PSW 472 is controlled by a signal PON2. In FIG. 13, the number of power domains to which VDD is supplied in the peripheral circuit 422 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0236] The element layers 430[1] to 430[m] can be stacked on the layer 420. Figure 14A is a perspective view of a memory device 480 showing five (m = 5) element layers 430[1] to 430[5] stacked on the layer 420.

[0237] 14A, the element layer 430 provided in the first layer is shown as element layer 430[1], the element layer 430 provided in the second layer is shown as element layer 430[2], and the element layer 430 provided in the fifth layer is shown as element layer 430[5]. Also shown in FIG. 14A are wirings WL and PL extending in the X direction, and wirings BL and BLB extending in the Y direction and Z direction (directions perpendicular to the surface of the substrate on which the driver circuit is provided). The wiring BLB is an inverted bit line. Note that, to make the drawing easier to understand, the wirings WL and PL included in each element layer 430 are partially omitted.

[0238] 14B is a schematic diagram illustrating a configuration example of the sense amplifier 446 connected to the wiring BL and the wiring BLB shown in FIG. 14A and the memory cells 432 included in the element layers 430[1] to 430[5] connected to the wiring BL and the wiring BLB. Note that a configuration in which a plurality of memory cells (memory cells 432) are electrically connected to one wiring BL and one wiring BLB is also referred to as a "memory string."

[0239] 14B illustrates an example of a circuit configuration of the memory cell 432 connected to the wiring BLB. The memory cell 432 includes a transistor 437 and a capacitor 438. The transistor 437, the capacitor 438, and the wirings (BL, WL, etc.) may also be referred to as wirings BL[1] and WL[1], for example.

[0240] In the memory cell 432, one of the source and the drain of the transistor 437 is connected to a wiring BL. The other of the source and the drain of the transistor 437 is connected to one electrode of a capacitor 438. The other electrode of the capacitor 438 is connected to a wiring PL. The gate of the transistor 437 is connected to a wiring WL.

[0241] The wiring PL is a wiring that applies a constant potential for maintaining the potential of the capacitor 438. The number of wirings can be reduced by connecting a plurality of wirings PL to each other and using them as one wiring.

[0242] In one embodiment of the present invention, OS transistors are stacked, and a wiring functioning as a bit line is arranged perpendicular to the surface of the substrate on which the layer 420 is provided. Additionally, the transistor 437 and the capacitor 438 included in the memory cell 432 are arranged side by side in the perpendicular direction to the surface of the substrate on which the layer 420 is provided. By providing each element and each wiring perpendicular to the surface of the substrate, the length of the wiring between element layers can be shortened and the density of elements provided per unit area can be increased. Therefore, a memory device with excellent storage capacity and reduced power consumption can be obtained.

[0243] 15A and 15B show circuit diagrams corresponding to the memory cell 432 described above and circuit block diagrams corresponding to the circuit diagrams. As shown in FIGS. 15A and 15B, the memory cell 432 may be represented as a block in the drawings. Note that the wiring BL shown in FIGS. 15A and 15B can be similarly represented when replaced with wiring BLB.

[0244] 15C and 15D show a circuit diagram corresponding to the sense amplifier 446 and a circuit block diagram corresponding to the circuit diagram. The sense amplifier 446 includes a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplifier circuit 485. The wirings BL and BLB, as well as wirings SA_OUT and SA_OUTB for outputting signals to be read out, are also shown.

[0245] 15C, the switch circuit 482 includes, for example, N-channel transistors 482_1 and 482_2. The transistors 482_1 and 482_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.

[0246] 15C, the precharge circuit 483 is formed of N-channel transistors 483_1 to 483_3. The precharge circuit 483 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD / 2 in response to a signal EQ.

[0247] 15C, the precharge circuit 484 is configured with P-channel transistors 484_1 to 484_3. The precharge circuit 484 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD / 2 in response to a signal EQB.

[0248] 15C , the amplifier circuit 485 includes P-channel transistors 485_1 and 485_2 and N-channel transistors 485_3 and 485_4 connected to a wiring SAP or a wiring SAN. The wiring SAP or the wiring SAN has a function of supplying VDD or VSS. The transistors 485_1 to 485_4 are transistors that form an inverter loop.

[0249] 15D shows a circuit block diagram corresponding to the sense amplifier 446 described in Fig. 15C etc. As shown in Fig. 15D, the sense amplifier 446 may be represented as a block in the drawings etc.

[0250] Fig. 16 is a circuit diagram of the memory device 480 of Fig. 13. Fig. 16 illustrates the circuit blocks described in Fig. 15A to Fig. 15D.

[0251] 16, the layer 470 including the element layer 430[m] includes a memory cell 432. The memory cell 432 illustrated in FIG. 16 is connected to a pair of wirings BL[1] and BLB[1] or a pair of wirings BL[2] and BLB[2], for example. The memory cell 432 connected to the wiring BL is a memory cell to which data is written or read.

[0252] The wiring BL[1] and the wiring BLB[1] are connected to a sense amplifier 446[1], and the wiring BL[2] and the wiring BLB[2] are connected to a sense amplifier 446[2]. The sense amplifier 446[1] and the sense amplifier 446[2] can read data in response to various signals described with reference to FIG.

[0253] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0254] Embodiment 4 In this embodiment, a structural example of a display device to which a transistor of one embodiment of the present invention can be applied will be described.

[0255] Since the transistor of one embodiment of the present invention can be made extremely small, a display device using the transistor of one embodiment of the present invention can have extremely high resolution. For example, the display device of one embodiment of the present invention can be used in a display portion of a wristwatch-type or bracelet-type information terminal (wearable device), a VR device such as a head-mounted display, and a head-mounted display (HMD), such as a glasses-type AR device.

[0256] In a display device according to one embodiment of the present invention, a driver circuit and a pixel circuit can be provided so as to overlap each other. In this case, the transistor in which a channel is formed in a single crystal substrate, which is described in Embodiment 1 as an example, can be used as a transistor in the driver circuit, and the transistor in which a channel is formed in a single crystal oxide semiconductor can be used as a transistor in the pixel.

[0257] 17A shows a perspective view of a display module 580. The display module 580 includes a display device 500A and an FPC 590.

[0258] The display module 580 has a substrate 591 and a substrate 592. The display module 580 has a display unit 581. The display unit 581 is an area for displaying an image.

[0259] 17B is a perspective view schematically illustrating the configuration on the substrate 591 side. A circuit portion 582, a pixel circuit portion 583 on the circuit portion 582, and a pixel portion 584 on the pixel circuit portion 583 are stacked on the substrate 591. A terminal portion 585 for connecting to an FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel portion 584. The terminal portion 585 and the circuit portion 582 are electrically connected by a wiring portion 586 composed of a plurality of wirings.

[0260] The pixel section 584 has a plurality of periodically arranged pixels 584a. An enlarged view of one pixel 584a is shown on the right side of Fig. 17B. The pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0261] The pixel circuit portion 583 has a plurality of pixel circuits 583a arranged periodically. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices included in one pixel 584a. One pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit 583a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0262] The circuit portion 582 includes a circuit for driving each pixel circuit 583a of the pixel circuit portion 583. For example, it preferably includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 582 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be composed of a transistor included in the pixel circuit portion 583 and a transistor included in the circuit portion 582.

[0263] The FPC 590 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 582. An IC may be mounted on the FPC 590.

[0264] The display module 580 can be configured such that one or both of the pixel circuit portion 583 and the circuit portion 582 are provided overlapping below the pixel portion 584, thereby enabling the aperture ratio (effective display area ratio) of the display portion 581 to be extremely high. For example, the aperture ratio of the display portion 581 can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 584a can be arranged at extremely high density, enabling the resolution of the display portion 581 to be extremely high. For example, the pixels 584a are preferably arranged in the display portion 581 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0265] Because such a display module 580 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays, or eyeglass-type AR devices. For example, even in a configuration in which the display unit of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display unit 581, so even when the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 580 is not limited to this, and can be suitably used in electronic devices with relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0266] Display Device 500A The display device 500A shown in FIG. 18 includes a substrate 301, a light emitting element 110R, a light emitting element 110G, a light emitting element 110B, a capacitor 540, a transistor 310, and a transistor 320.

[0267] The transistor 310 corresponds to the transistor 50 in which a channel is formed in a single crystal substrate, as exemplified in Embodiment 1. The transistor 320 corresponds to the transistor 10 or the transistor 200 in which a channel is formed in a single crystal oxide semiconductor, as exemplified in Embodiment 1 and Embodiment 2. Any of the various transistors exemplified in Embodiment 2 can be used as the transistor 320.

[0268] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0269] An element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0270] The transistor 320 includes a semiconductor layer 351 , an insulating layer 353 , a conductive layer 354 , a pair of conductive layers 355 , an insulating layer 360 , and a conductive layer 357 .

[0271] A wiring layer 371 and a wiring layer 361 are provided between a layer in which the transistor 310 is provided and a layer in which the transistor 320 is provided. The wiring layer 371 has at least an insulating layer 372 and a conductive layer 373 embedded in the insulating layer 372 at the top. The wiring layer 361 has at least an insulating layer 362 and a conductive layer 363 embedded in the insulating layer 362 at the bottom. The display device 500A is manufactured by bonding the wiring layer 361 and the wiring layer 371. That is, the insulating layer 372, the conductive layer 373, the insulating layer 362, and the conductive layer 363 each have a bonding surface. The connection between the conductive layer 363 and the conductive layer 373 allows the transistor 310 and the transistor 320 to be electrically connected to each other through various wirings.

[0272] The stacked structure from the insulating layer 360 to the wiring layer 361 is formed in order from the insulating layer 360 side, and then the surface of the wiring layer 361 is used as a bonding surface to bond to the substrate 301. Therefore, the stacked structure from the insulating layer 360 to the wiring layer 361 is upside down relative to the transistor 310 and the like.

[0273] The transistor 320 is sandwiched between an insulating layer 352 and an insulating layer 359. The insulating layer 352 and the insulating layer 359 preferably have a barrier property against hydrogen and oxygen, which can prevent impurities from diffusing into the transistor 320 and oxygen from being released from the semiconductor layer 351. The insulating layer 352 and the insulating layer 359 can be formed using a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0274] An insulating layer 356 and a conductive layer 357 embedded in the insulating layer 356 are provided closer to the substrate 301 than the insulating layer 352. An insulating layer 360 is provided between the conductive layer 357 and the semiconductor layer 351. The conductive layer 357 functions as a second gate electrode of the transistor 320, and part of the insulating layer 360 functions as a second gate insulating layer.

[0275] The insulating layer 360 is in contact with the semiconductor layer 351. The insulating layer 360 can correspond to the substrate 11 or the base film 12. Alternatively, the insulating layer 360 may be an insulating film separate from the substrate 11 and the base film 12. Note that when the substrate 11 is used for the insulating layer 360 and it is difficult to reduce the thickness, a structure without providing a back gate may be used.

[0276] The semiconductor layer 351 is provided on the substrate 301 side of the insulating layer 360. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 355 is provided in contact with the semiconductor layer 351 and functions as a source electrode and a drain electrode.

[0277] An insulating layer 358 and an insulating layer 350 are provided to cover the pair of conductive layers 355, the semiconductor layer 351, and the like. The insulating layer 358 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and prevents oxygen from being released from the semiconductor layer 351. The insulating layer 358 can be formed using an insulating film similar to the insulating layer 352. The insulating layer 350 functions as an interlayer insulating layer.

[0278] An opening reaching the semiconductor layer 351 is provided in the insulating layer 358 and the insulating layer 350. An insulating layer 353 in contact with a top surface of the semiconductor layer 351 and a conductive layer 354 are buried in the opening. The conductive layer 354 functions as a first gate electrode, and the insulating layer 353 functions as a first gate insulating layer.

[0279] The top surfaces (surfaces on the substrate 301 side) of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that their heights are the same or approximately the same, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 320. The insulating layer 359 can be an insulating film similar to the insulating layer 352.

[0280] The transistor 320 has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the transistor may be driven by supplying the same signal to them. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0281] An insulating layer 565 is provided to cover the insulating layer 359. The insulating layer 565 functions as an interlayer insulating layer.

[0282] A plug 575 electrically connected to one of the conductive layers 355 is provided so as to be embedded in the insulating layer 565, the insulating layer 359, the insulating layer 350, and the insulating layer 358. Here, the plug 575 preferably includes a conductive layer 575a covering the side surfaces of the opening of the insulating layer 565 or the like and a part of the conductive layer 355, and a conductive layer 575b in contact with the conductive layer 575a. In this case, the conductive layer 575a is preferably made of a conductive material through which oxygen does not easily diffuse.

[0283] The conductive layer 364 is provided on the substrate 301 side of the insulating layer 565. The plug 575 connects the conductive layer 355 and the conductive layer 364.

[0284] Furthermore, a capacitor 540 is provided on the insulating layer 564. The capacitor 540 includes a conductive layer 541, a conductive layer 545, and an insulating layer 543 located therebetween. The conductive layer 541 functions as one electrode of the capacitor 540, the conductive layer 545 functions as the other electrode of the capacitor 540, and the insulating layer 543 functions as a dielectric of the capacitor 540.

[0285] The conductive layer 541 is embedded in an insulating layer 554 provided over the insulating layer 564. The conductive layer 541 is electrically connected to the conductive layer 364 by a plug 574. The insulating layer 543 is provided to cover the conductive layer 541. The conductive layer 545 is provided in a region overlapping with the conductive layer 541 with the insulating layer 543 interposed therebetween. The conductive layer 541 is connected to the conductive layer 355 of the transistor 320 via the plug 574, the conductive layer 364, and the plug 575.

[0286] The plug 574 includes a conductive layer 574 a and a conductive layer 574 b and is provided to be embedded in the insulating layer 564, the insulating layer 352, the insulating layer 356, the insulating layer 358, the insulating layer 350, the insulating layer 359, and the insulating layer 565. The conductive layer 574 a is preferably made of a conductive material through which oxygen does not easily diffuse.

[0287] An insulating layer 555a is provided to cover the capacitor 540, an insulating layer 555b is provided over the insulating layer 555a, and an insulating layer 555c is provided over the insulating layer 555b.

[0288] An inorganic insulating film can be preferably used for each of the insulating layers 555a, 555b, and 555c. For example, it is preferable to use a silicon oxide film for the insulating layer 555a and the insulating layer 555c, and a silicon nitride film for the insulating layer 555b. This allows the insulating layer 555b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 555c is etched to form a recess, but the insulating layer 555c does not necessarily have to have a recess.

[0289] The light emitting elements 110R, 110G, and 110B are provided on the insulating layer 555c.

[0290] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0291] The organic layer 112R of the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G of the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B of the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B can also be called EL layers, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

[0292] The display device 500A has a separate light-emitting device for each emitted color, so there is little change in chromaticity between light emitted at low and high luminance. Furthermore, because the organic layers 112R, 112G, and 112B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. This makes it possible to realize a high-resolution, high-quality display panel.

[0293] In the region between adjacent light emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.

[0294] The pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B of the light-emitting element are electrically connected to the conductive layer 355 of the transistor 320 by a plug 556 embedded in the insulating layers 555a, 555b, and 555c, a conductive layer 541 embedded in the insulating layer 554, and a plug 574. The height of the top surface of the insulating layer 555c and the height of the top surface of the plug 556 are the same or approximately the same. Various conductive materials can be used for the plug.

[0295] A protective layer 121 is provided on the light emitting elements 110R, 110G, and 110B. A substrate 170 is attached to the protective layer 121 with an adhesive layer 171.

[0296] There is no insulating layer covering the upper end of each pixel electrode 111 between two adjacent pixel electrodes 111. This allows the distance between adjacent light-emitting elements to be extremely narrow, resulting in a high-definition or high-resolution display device.

[0297] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0298] In this embodiment, a structural example of a display device that can be used for a display device manufactured using a transistor of one embodiment of the present invention will be described. The display device exemplified below can be used for the pixel portion 584 in Embodiment 4, for example.

[0299] In one embodiment of the present invention, an EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a fine metal mask (FMM). This makes it possible to realize a display device with high definition and a large aperture ratio, which have been difficult to achieve until now. Furthermore, since the EL layer can be individually fabricated, a display device with extremely vivid images, high contrast, and high display quality can be realized. Note that, for example, the EL layer may be processed into a fine pattern using both a metal mask and photolithography.

[0300] Furthermore, the EL layer can be partially or entirely separated physically. This can suppress leakage current between adjacent light-emitting elements through a layer shared between the light-emitting elements (also referred to as a common layer). This can prevent crosstalk caused by unintended light emission, thereby realizing a display device with extremely high contrast. In particular, a display device with high current efficiency at low luminance can be realized.

[0301] One embodiment of the present invention can also be a display device that combines a white-emitting light-emitting element and a color filter. In this case, light-emitting elements provided in pixels (subpixels) that emit light of different colors can have the same configuration, and all layers can be common layers. Furthermore, part or all of each EL layer can be separated by photolithography. This suppresses leakage current through the common layer, thereby achieving a display device with high contrast. In particular, in an element having a tandem structure in which multiple light-emitting layers are stacked via a highly conductive intermediate layer, leakage current through the intermediate layer can be effectively prevented, thereby achieving a display device that combines high brightness, high definition, and high contrast.

[0302] When the EL layer is processed by photolithography, a portion of the light-emitting layer may be exposed, which may cause deterioration. Therefore, it is preferable to provide an insulating layer that covers at least the side surfaces of the island-shaped light-emitting layer. The insulating layer may also be configured to cover a portion of the top surface of the island-shaped EL layer. The insulating layer is preferably made of a material that has barrier properties against water and oxygen. For example, an inorganic insulating film that is less likely to diffuse water or oxygen can be used. This suppresses deterioration of the EL layer, thereby achieving a highly reliable display device.

[0303] Furthermore, there is a region (recess) between two adjacent light-emitting elements where the EL layer of either light-emitting element is not provided. When a common electrode, or a common electrode and a common layer, is formed to cover the recess, a phenomenon in which the common electrode is separated by a step at the edge of the EL layer (also called a step discontinuity) may occur, resulting in insulation of the common electrode on the EL layer. Therefore, it is preferable to use a configuration in which the local step located between two adjacent light-emitting elements is filled with a resin layer functioning as a planarization film (also called LFP: Local Filling Planarization). The resin layer functions as a planarization film. This suppresses step discontinuity of the common layer or common electrode, thereby achieving a highly reliable display device.

[0304] A more specific example of the structure of the display device of one embodiment of the present invention will be described below with reference to the drawings.

[0305] 19A shows a schematic top view of a display device 100 of one embodiment of the present invention. The display device 100 includes a plurality of light-emitting elements 110R that exhibit red light, a plurality of light-emitting elements 110G that exhibit green light, and a plurality of light-emitting elements 110B that exhibit blue light, over a substrate 101. In FIG. 19A , the symbols R, G, and B are assigned within the light-emitting regions of the light-emitting elements to easily distinguish the light-emitting elements from one another.

[0306] The light emitting elements 110R, 110G, and 110B are arranged in a matrix. Fig. 19A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light emitting elements is not limited to this, and arrangement methods such as an S-stripe arrangement, a delta arrangement, a Bayer arrangement, or a zigzag arrangement may also be used, or a pentile arrangement, a diamond arrangement, or the like may also be used.

[0307] As the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) is preferably used. Examples of the light-emitting substance contained in the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material). As the light-emitting substance contained in the EL element, not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.

[0308] 19A also shows a connection electrode 111C that is electrically connected to the common electrode 113. The connection electrode 111C is given a potential (e.g., an anode potential or a cathode potential) to be supplied to the common electrode 113. The connection electrode 111C is provided outside the display area where the light-emitting elements 110R and the like are arranged.

[0309] The connection electrode 111C can be provided along the periphery of the display area. For example, it may be provided along one side of the periphery of the display area, or it may be provided over two or more sides of the periphery of the display area. That is, when the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be a strip shape (rectangle), an L-shape, a U-shape (square bracket shape), a square shape, or the like.

[0310] 19B and 19C are schematic cross-sectional views corresponding to dashed dotted lines A1-A2 and A3-A4 in Fig. 19A, respectively. Fig. 19B shows a schematic cross-sectional view of light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B, and Fig. 19C shows a schematic cross-sectional view of connection portion 140 where connection electrode 111C and common electrode 113 are connected.

[0311] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0312] The organic layer 112R of the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G of the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B of the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B can also be called EL layers, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

[0313] Hereinafter, when describing matters common to light emitting element 110R, light emitting element 110G, and light emitting element 110B, they may be referred to as light emitting element 110. Similarly, when describing matters common to components distinguished by alphabets, such as organic layer 112R, organic layer 112G, and organic layer 112B, they may be described using symbols without the alphabets.

[0314] The organic layer 112 and the common layer 114 may each independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 may have a stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 111 side, and the common layer 114 may have an electron injection layer.

[0315] The pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are provided for each light-emitting element. The common electrode 113 and common layer 114 are provided as a continuous layer common to each light-emitting element. A conductive film transmissive to visible light is used for either the pixel electrode or the common electrode 113, and a conductive film reflective to visible light is used for the other. By making each pixel electrode transmissive and the common electrode 113 reflective, a bottom-emission display device can be obtained. Conversely, by making each pixel electrode reflective and the common electrode 113 transmissive, a top-emission display device can be obtained. Note that by making both the pixel electrodes and the common electrode 113 transmissive, a dual-emission display device can be obtained.

[0316] A protective layer 121 is provided on the common electrode 113 to cover the light emitting elements 110R, 110G, and 110B. The protective layer 121 has a function of preventing impurities such as water from diffusing from above into each light emitting element.

[0317] The edge of the pixel electrode 111 preferably has a tapered shape. When the edge of the pixel electrode 111 has a tapered shape, the organic layer 112 provided along the edge of the pixel electrode 111 can also have a tapered shape. By tapering the edge of the pixel electrode 111, the coverage of the organic layer 112 provided over the edge of the pixel electrode 111 can be improved. Furthermore, by tapering the side surface of the pixel electrode 111, foreign matter (for example, also referred to as dust or particles) during the manufacturing process can be easily removed by a process such as cleaning, which is preferable.

[0318] For example, it is preferable to have a region where the angle between the inclined side surface and the substrate surface (also called the taper angle) is less than 90°.

[0319] The organic layer 112 is processed into an island shape by photolithography. As a result, the angle between the top surface and the side surface of the organic layer 112 at its edge is close to 90 degrees. On the other hand, an organic film formed using a fine metal mask (FMM) or the like tends to become gradually thinner as it approaches the edge. For example, the top surface is formed in a sloped shape over a range of 1 μm to 10 μm up to the edge, making it difficult to distinguish between the top surface and the side surface.

[0320] Between two adjacent light emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.

[0321] Between two adjacent light-emitting elements, the side surfaces of the organic layers 112 face each other with the resin layer 126 sandwiched therebetween. The resin layer 126 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each organic layer 112 and the region between the two organic layers 112. The resin layer 126 has a smooth, convex upper surface, and a common layer 114 and a common electrode 113 are provided to cover the upper surface of the resin layer 126.

[0322] The resin layer 126 functions as a planarization film that fills in a step between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent a phenomenon (also called step disconnection) in which the common electrode 113 is divided by a step at the end of the organic layer 112, resulting in insulation of the common electrode on the organic layer 112. The resin layer 126 can also be called an LFP (Local Filling Planarization) layer.

[0323] An insulating layer containing an organic material can be suitably used as the resin layer 126. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, precursors of these resins, etc. can be used as the resin layer 126. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used as the resin layer 126.

[0324] Furthermore, a photosensitive resin can be used as the resin layer 126. A photoresist can be used as the photosensitive resin. The photosensitive resin can be a positive-type material or a negative-type material.

[0325] The resin layer 126 may contain a material that absorbs visible light. For example, the resin layer 126 itself may be made of a material that absorbs visible light, or the resin layer 126 may contain a pigment that absorbs visible light. For example, the resin layer 126 may be a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light, or a resin that contains carbon black as a pigment and functions as a black matrix.

[0326] The insulating layer 125 is provided in contact with the side surface of the organic layer 112. The insulating layer 125 is also provided to cover the upper end portion of the organic layer 112. A portion of the insulating layer 125 is provided in contact with the upper surface of the substrate 101.

[0327] The insulating layer 125 is located between the resin layer 126 and the organic layer 112, and functions as a protective film to prevent the resin layer 126 from contacting the organic layer 112. If the organic layer 112 and the resin layer 126 come into contact with each other, the organic layer 112 may be dissolved by an organic solvent or the like used when forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, it is possible to protect the side surfaces of the organic layer 112.

[0328] The insulating layer 125 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 125. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, by using an inorganic insulating film such as a metal oxide film, an aluminum oxide film, or a silicon oxide film formed by an ALD method as the insulating layer 125, an insulating layer 125 with few pinholes and excellent protection of the EL layer can be formed.

[0329] The insulating layer 125 can be formed by a sputtering method, a CVD method, a PLD method, an ALD method, or the like. The insulating layer 125 is preferably formed by an ALD method because it has good coverage.

[0330] Furthermore, a reflective film (e.g., a metal film containing one or more selected from silver, palladium, copper, titanium, aluminum, etc.) may be provided between the insulating layer 125 and the resin layer 126, so that the light emitted from the light-emitting layer is reflected by the reflective film, thereby improving the light extraction efficiency.

[0331] The layer 128 is a remaining portion of a protective layer (also referred to as a mask layer or a sacrificial layer) for protecting the organic layer 112 during etching of the organic layer 112. The layer 128 can be made of a material that can be used for the insulating layer 125. In particular, it is preferable to use the same material for the layer 128 and the insulating layer 125 because a common processing device or the like can be used for both.

[0332] In particular, inorganic insulating films such as metal oxide films such as aluminum oxide films and hafnium oxide films, or silicon oxide films formed by the ALD method have few pinholes and therefore have an excellent function of protecting the EL layer, and can be suitably used for the insulating layer 125 and the layer 128.

[0333] The protective layer 121 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, the protective layer 121 may be made of a semiconductor material or a conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide.

[0334] The protective layer 121 may also be a laminated film of an inorganic insulating film and an organic insulating film. For example, a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films is preferable. Furthermore, it is preferable that the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties. Furthermore, since the upper surface of the protective layer 121 is flat, when a structure (e.g., a color filter, a touch sensor electrode, a lens array, etc.) is provided above the protective layer 121, the influence of uneven shapes caused by the structure below can be reduced, which is preferable.

[0335] 19C shows a connection portion 140 where the connection electrode 111C and the common electrode 113 are electrically connected. In the connection portion 140, an opening is provided in the insulating layer 125 and the resin layer 126 above the connection electrode 111C. The connection electrode 111C and the common electrode 113 are electrically connected in the opening.

[0336] 19C shows a connection portion 140 where the connection electrode 111C and the common electrode 113 are electrically connected, but the common electrode 113 may be provided on the connection electrode 111C via the common layer 114. In particular, when a carrier injection layer is used for the common layer 114, the electrical resistivity of the material used for the common layer 114 is sufficiently low and the common layer 114 can be formed thin, so there are many cases where no problem occurs even if the common layer 114 is located at the connection portion 140. This allows the common electrode 113 and the common layer 114 to be formed using the same masking mask, thereby reducing manufacturing costs.

[0337] [Configuration Example 2] The following describes a display device that has a configuration that is partially different from that of the above-described configuration example 1. Note that parts that are common to the above-described configuration example 1 will be referred to, and descriptions thereof may be omitted.

[0338] 20A shows a schematic cross-sectional view of a display device 100a. The display device 100a differs from the display device 100 mainly in that the configuration of the light-emitting element is different and that a colored layer is provided.

[0339] The display device 100a includes a light-emitting element 110W that emits white light. The light-emitting element 110W includes a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W may be configured to include two or more light-emitting materials whose emitted light colors are complementary to each other. For example, the organic layer 112W may be configured to include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. Alternatively, the organic layer 112W may be configured to include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.

[0340] The organic layers 112W are separated between two adjacent light-emitting elements 110W. This makes it possible to suppress leakage current flowing between adjacent light-emitting elements 110W via the organic layers 112W, thereby suppressing crosstalk caused by the leakage current. As a result, a display device with high contrast and color reproducibility can be realized.

[0341] An insulating layer 122 that functions as a planarizing film is provided on the protective layer 121, and a coloring layer 116R, a coloring layer 116G, and a coloring layer 116B are provided on the insulating layer 122.

[0342] An organic resin film or an inorganic insulating film with a planarized upper surface can be used as the insulating layer 122. The insulating layer 122 forms the surface on which the colored layers 116R, 116G, and 116B are formed, and therefore, by having a planar upper surface of the insulating layer 122, the thickness of the colored layers 116R and the like can be made uniform, thereby improving color purity. Note that if the thickness of the colored layers 116R and the like is uneven, the amount of light absorption varies depending on the location of the colored layer 116R, which may result in a decrease in color purity.

[0343] Configuration Example 3 FIG. 20B shows a schematic cross-sectional view of a display device 100b.

[0344] The light-emitting element 110R has a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. The conductive layer 115R, the conductive layer 115G, and the conductive layer 115B each have light-transmitting properties and function as an optical adjustment layer.

[0345] A microresonator (microcavity) structure can be realized by using a film that reflects visible light for the pixel electrode 111 and a film that is both reflective and transparent to visible light for the common electrode 113. In this case, by adjusting the thicknesses of the conductive layers 115R, 115G, and 115B so as to provide optimal optical path lengths, even when the organic layer 112 that emits white light is used, light of different wavelengths that are intensified can be obtained from the light-emitting elements 110R, 110G, and 110B.

[0346] Furthermore, colored layers 116R, 116G, and 116B are provided on the optical paths of the light emitting elements 110R, 110G, and 110B, respectively, so that light with high color purity can be obtained.

[0347] An insulating layer 123 is provided to cover the edges of the pixel electrode 111 and the conductive layer 115. The edges of the insulating layer 123 preferably have a tapered shape. By providing the insulating layer 123, coverage by the organic layer 112W, the common electrode 113, the protective layer 121, and the like formed thereon can be improved.

[0348] The organic layer 112W and the common electrode 113 are each provided as a continuous film in common to each light-emitting element, which is preferable because it can greatly simplify the manufacturing process of the display device.

[0349] Here, it is preferable that the edge of the pixel electrode 111 has a shape that is nearly vertical. This allows a steeply inclined portion to be formed on the surface of the insulating layer 123, and it is possible to form a thin portion in a part of the organic layer 112W that covers this portion, or to divide a part of the organic layer 112W. Therefore, it is possible to suppress leakage current that occurs through the organic layer 112W between adjacent light-emitting elements without processing the organic layer 112W by a photolithography method or the like.

[0350] The above is a description of an example of the configuration of the display device.

[0351] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0352] Embodiment 6 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

[0353] The electronic devices of this embodiment include a display panel (display device) in which the transistor of one embodiment of the present invention is used in a display portion. The display device of one embodiment of the present invention can easily achieve high definition and high resolution and can also achieve high display quality. Therefore, the display device of one embodiment of the present invention can be used in the display portion of various electronic devices.

[0354] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0355] In particular, the display panel of one embodiment of the present invention can have high resolution and thus can be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0356] The display panel of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display panel of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display panel having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, there is no particular limitation on the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention. For example, the display panel can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0357] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0358] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0359] 21A to 21D , examples of wearable devices that can be worn on the head will be described. These wearable devices have one or both of a function to display AR content and a function to display VR content. Note that these wearable devices may also have a function to display SR or MR content in addition to AR and VR. By having an electronic device have a function to display at least one of AR, VR, SR, and MR content, it is possible to enhance the user's sense of immersion.

[0360] The electronic device 700A shown in FIG. 21A and the electronic device 700B shown in FIG. 21B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0361] A display panel of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided.

[0362] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0363] Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of them as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0364] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0365] Furthermore, the electronic device 700A and the electronic device 700B are provided with batteries, which can be charged wirelessly and / or by wire.

[0366] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation or a slide operation by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can expand the range of operations.

[0367] Various touch sensors can be used as the touch sensor module. For example, various types of touch sensors can be used, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, it is preferable to use a capacitance type or an optical type sensor in the touch sensor module.

[0368] When an optical touch sensor is used, a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light receiving device (also called a light receiving element). The active layer of the photoelectric conversion device can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0369] The electronic device 800A shown in Figure 21C and the electronic device 800B shown in Figure 21D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0370] A display panel of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided, which allows a user to feel a high sense of immersion.

[0371] The display unit 820 is provided inside the housing 821 at a position that can be viewed through the lens 832. In addition, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0372] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0373] It is preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the left and right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.

[0374] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that, in Fig. 21C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0375] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0376] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0377] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0378] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0379] The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 700A shown in FIG. 21A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, the electronic device 800A shown in FIG. 21C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0380] The electronic device may also have an earphone unit. Electronic device 700B shown in Fig. 21B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0381] Similarly, the electronic device 800B shown in Fig. 21D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be disposed inside the housing 821 or the attachment unit 823. The earphone unit 827 and the attachment unit 823 may also have magnets. This allows the earphone unit 827 to be fixed to the attachment unit 823 by magnetic force, which is preferable as it makes storage easier.

[0382] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0383] As described above, as electronic devices of one embodiment of the present invention, both glasses-type devices (such as the electronic devices 700A and 700B) and goggle-type devices (such as the electronic devices 800A and 800B) are suitable.

[0384] The electronic device 6500 shown in FIG. 22A is a portable information terminal that can be used as a smartphone.

[0385] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. The display portion 6502 has a touch panel function. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.

[0386] The display panel of one embodiment of the present invention can be applied to the display portion 6502 .

[0387] FIG. 22B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0388] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0389] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0390] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0391] The display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0392] 22C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0393] 22C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0394] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0395] 22D shows an example of a laptop personal computer. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, and the like. A display portion 7000 is incorporated in the housing 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 7000, the control device 7216, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 7216 is preferable because power consumption can be reduced.

[0396] 22E and 22F show an example of digital signage.

[0397] 22E includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0398] 22F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0399] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it will attract people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0400] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0401] 22E and 22F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. By operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0402] Furthermore, the digital signage 7300 or the digital signage 7400 can be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0403] 22C to 22F, a display panel of one embodiment of the present invention can be applied to the display portion 7000.

[0404] The electronic device shown in Figures 23A to 23G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including the function of detecting, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0405] The electronic devices shown in Figures 23A to 23G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on a display unit, etc.

[0406] The electronic devices shown in FIGS. 23A to 23G will be described in detail below.

[0407] FIG. 23A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 23A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0408] 23B is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is placed in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0409] 23C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games, for example. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of a housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0410] FIG. 23D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a wirelessly capable headset. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0411] 23E to 23G are perspective views showing a foldable mobile information terminal 9201. Also, FIG. 23E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 23G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 23F is a perspective view of a state in the process of changing from one of FIGS. 23E and 23G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent visibility of the display. The display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0412] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0413] Embodiment 7 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0414] An electronic component or the like to which the semiconductor device of one embodiment of the present invention is applied can be applied to the electronic devices exemplified in Embodiment 6.

[0415] [Electronic Component] FIG. 24A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 24A has semiconductor device 710 inside mold 711. FIG. 24A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0416] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0417] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0418] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0419] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0420] 24B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0421] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0422] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0423] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0424] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0425] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0426] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0427] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0428] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 24B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0429] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0430] 25A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0431] 25B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0432] Fig. 25C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Fig. 25C illustrates components other than electronic components 5626, 5627, and 5628.

[0433] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0434] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0435] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0436] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0437] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0438] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0439] In this example, a single-crystal oxide semiconductor film was formed over a single-crystal substrate, and a cross section thereof was observed.

[0440] As the single crystal substrate, a single crystal YSZ substrate was used. Two types of substrates were used: one with a (111) plane and the other with a (100) plane.

[0441] The oxide semiconductor film was an indium oxide film. Here, an indium oxide film with a thickness of approximately 5 nm was formed on a YSZ substrate by an ALD method. The film formation was performed using triethylindium as a precursor and ozone as an oxidizing agent at a substrate temperature of 200° C.

[0442] Next, cross-sections of the two types of substrates on which the indium oxide film was formed were observed using HAADF-STEM.

[0443] FIG. 26A shows a YSZ substrate having a (111) surface and an indium oxide film (In ２ O ３ The cross-sectional image shows the indium oxide film crystallized, reflecting the crystal lattice of the YSZ substrate. The crystal orientations of the YSZ substrate and the indium oxide film are shown on the right side of the image. The cross-sectional image confirms that the crystal orientations of the YSZ substrate and the indium oxide film are consistent.

[0444] Furthermore, a low-contrast layer (referred to as a buffer layer) was confirmed between the YSZ substrate and the indium oxide film.

[0445] Figure 26B shows an enlarged view of a portion of Figure 26A. It can be seen that the buffer layer is a two-atom layer. Since the HAADF-STEM method superimposes information not only on the sample surface but also on the depth direction, the observation of a dark contrast in the buffer layer suggests the presence of sites where atoms are absent. In other words, the buffer layer can be considered a region with a lower density than other regions.

[0446] Next, we focus on the interatomic distances between the YSZ substrate and the indium oxide film. Figure 26B shows the interatomic distances for the YSZ substrate and the indium oxide film as numerical values. The interatomic distances were averaged over 100 periods within the observation range. The interatomic distances in the YSZ substrate were 0.313 nm in the in-plane direction and 0.300 nm in the thickness direction, which were comparable to values ​​for an ideal YSZ single crystal. On the other hand, the interatomic distances in the indium oxide film were 0.313 nm in the in-plane direction and 0.291 nm in the thickness direction. While the thickness direction was comparable to that of an ideal indium oxide single crystal, the in-plane direction was larger than that of an ideal single crystal. Therefore, it can be seen that the crystal structure of the indium oxide film is distorted only in the in-plane direction, at least within the range observed in this example.

[0447] Figure 27A shows a cross-sectional image of a YSZ substrate with a (100) surface and an indium oxide film formed thereon. Figure 27B shows an enlarged view of the same. It can be seen that indium oxide with good crystallinity was obtained even when the substrate surface was different.

[0448] Focusing on the interatomic distance, the interatomic distance in the YSZ substrate was 0.364 nm in the in-plane direction and 0.258 nm in the thickness direction, which was comparable to that of an ideal single crystal. On the other hand, the interatomic distance in the indium oxide film was 0.364 nm in the in-plane direction and 0.252 nm in the thickness direction, which was comparable to that of an ideal indium oxide single crystal in the thickness direction, but larger than that of an ideal single crystal in the in-plane direction. In other words, similar to when the substrate surface was the (111) plane, the indium oxide film was distorted so that the interatomic distance increased in the in-plane direction compared to ideal single crystal indium oxide, but there was almost no distortion in the thickness direction.

[0449] Furthermore, focusing on the buffer layer, when the substrate surface was a (111) plane, it was two atomic layers thick, whereas when the substrate surface was a (100) plane, it was one atomic layer thick. This indicates that the magnitude of stress applied to the indium oxide film to be formed differs depending on the crystal orientation of the substrate, and this difference is related to the number of layers in the buffer layer. This result suggests that, regarding the plane orientation of the YSZ substrate, the (100) plane provides better matching of the crystal structure with the indium oxide film than the (111) plane.

[0450] According to this example, it was confirmed that a single-crystal oxide semiconductor film can be formed by epitaxially growing an oxide semiconductor film on a single-crystal substrate. It was also confirmed that a low-density buffer layer can be formed between the single-crystal substrate and the single-crystal oxide semiconductor film. It was also found that the crystal structure of the single-crystal oxide semiconductor film is distorted to the same extent as that of the substrate in the in-plane direction so as to alleviate the lattice mismatch with the substrate, but the distortion in the thickness direction is small.

[0451] 10: transistor, 11: substrate, 11a: substrate, 12: base film, 12a: layer, 15f: element, 15m: element, 15s: element, 16: intermediate layer, 21: semiconductor layer, 21f: semiconductor film, 22: insulating layer, 22f: insulating film, 23: conductive layer, 24: conductive layer, 24f: conductive film, 32: insulating layer, 33a: insulating layer, 33b: insulating layer, 33c: insulating layer, 33d: insulating layer, 50: transistor, 51: substrate, 51c: semiconductor region, 52: insulating layer, 53: conductive layer, 54: low resistance region, 61a: plug, 61b: plug, 61c: plug, 61d: plug, 71a: conductive layer, 71b : conductive layer, 71c: conductive layer, 71d: conductive layer, 81: element isolation layer, 82: insulating layer, 83a: insulating layer, 83b: insulating layer, 83c: insulating layer, 83d: insulating layer, 100: display device, 100a: display device, 100b: display device, 101: substrate, 110: light-emitting element, 110B: light-emitting element, 110G: light-emitting element, 110R: light-emitting element, 110W: light-emitting element, 111: pixel electrode, 111B: pixel electrode, 111C: connection electrode, 111G: pixel electrode, 111R: pixel electrode, 112: organic layer, 112B: organic layer, 112G: organic layer, 112R: organic layer, 112W: organic layer, 113 : common electrode, 114: common layer, 115: conductive layer, 115B: conductive layer, 115G: conductive layer, 115R: conductive layer, 116B: colored layer, 116G: colored layer, 116R: colored layer, 121: protective layer, 122: insulating layer, 123: insulating layer, 125: insulating layer, 126: resin layer, 128: layer, 140: connecting portion, 170: substrate, 171: adhesive layer, 200: transistor, 201: insulating layer, 202: insulating layer, 205: conductive layer, 230: semiconductor layer, 230f: semiconductor film, 240a: conductive layer, 240b: conductive layer, 241a: insulating layer, 241b: insulating layer, 242: conductive layer, 242a: conductive layer, 242b: conductive layer, 242f: conductive film, 250: insulating layer, 255: insulating layer, 260: conductive layer, 260a: conductive layer, 260b: conductive layer, 271a: insulating layer, 271b: insulating layer, 275: insulating layer, 280: insulating layer, 282: insulating layer, 283: insulating layer, 285: insulating layer, 301: substrate, 310: transistor, 311: conductive layer, 312: low resistance region, 313: insulating layer, 314: insulating layer, 315: element isolation layer, 320: transistor, 350: insulating layer, 351: semiconductor layer, 352: insulating layer, 353: insulating layer, 354: conductive layer, 355: conductive layer, 356: insulating layer,357: conductive layer, 358: insulating layer, 359: insulating layer, 360: insulating layer, 361: wiring layer, 362: insulating layer, 363: conductive layer, 364: conductive layer, 371: wiring layer, 372: insulating layer, 373: conductive layer, 420: layer, 422: peripheral circuit, 430[1]: element layer, 430[2]: element layer, 430[5]: element layer, 430[m]: element layer, 430[m]m: element layer, 430: element layer, 432[1,1]: memory cell, 432[i,j]: memory cell, 432[m,n]: memory cell, 432: memory cell, 437: transistor, 438: capacitor, 440: driver operation circuit, 442: row decoder, 443: row driver, 444: column decoder, 445: column driver, 446[1]: sense amplifier, 446[2]: sense amplifier, 446: sense amplifier, 447: input circuit, 448: output circuit, 470: layer, 471: PSW, 472: PSW, 473: control circuit, 474: voltage generation circuit, 480: memory device, 482: switch circuit, 482_1: transistor, 482_2: transistor, 483: precharge circuit, 483_1: transistor, 483_3: transistor, 484: precharge circuit, 484 _1: transistor, 484_3: transistor, 485: amplifier circuit, 485_1: transistor, 485_2: transistor, 485_3: transistor, 485_4: transistor, 500A: display device, 540: capacitor, 541: conductive layer, 543: insulating layer, 545: conductive layer, 554: insulating layer, 555a: insulating layer, 555b: insulating layer, 555c: insulating layer, 556: plug, 564: insulating layer, 565: insulating layer, 574: plug, 574a: conductive layer, 574b: conductive layer, 575: plug, 575a: conductive layer, 575b: conductive layer, 580: display module, 581: display unit, 582: circuit unit, 583: pixel circuit unit, 583a: pixel circuit, 584: pixel unit, 584a: pixel, 585: terminal unit, 586: wiring unit, 590: FPC, 591: substrate, 592: substrate, 700: electronic component, 700A: electronic device, 700B: electronic device, 702: printed circuit board, 704: mounting substrate, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 721: housing, 723: wearing unit, 727: earphone unit, 730: electronic component, 731: interposer,732: package substrate, 733: electrode, 735: semiconductor device, 750: earphone, 751: display panel, 753: optical member, 756: display area, 757: frame, 758: nose pad, 800A: electronic device, 800B: electronic device, 820: display unit, 821: housing, 822: communication unit, 823: wearing unit, 824: control unit, 825: imaging unit, 827: earphone unit, 832: lens, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623 : Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Electronic component, 5627: Electronic component, 5628: Electronic component, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6510: Protective member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor Sub-panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 7000: display unit, 7100: television device, 7101: housing, 7103: stand, 7111: remote control device, 7200: notebook personal computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7216: control device, 7300: digital signage, 7301: housing, 7303: speaker, 7311: information terminal device, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: Housing, 9001: Display unit, 9002: Camera, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Portable information terminal, 9102: Portable information terminal, 9103: Tablet terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

a first transistor, a second transistor, a first insulating layer, a second insulating layer, a first single crystal substrate, and a second single crystal substrate; the first transistor has a channel formed in a first single-crystal semiconductor included in the first single-crystal substrate, the second transistor is located above the first transistor and has a channel formed in a second single-crystal semiconductor in contact with the second single-crystal substrate; the second single-crystal substrate is located above the second transistor; the first insulating layer is located between the first transistor and the second transistor; the second insulating layer is located between the first insulating layer and the second transistor and has a first junction surface in contact with the first insulating layer; the first single-crystal semiconductor includes silicon; the second single crystal semiconductor includes a metal oxide; Semiconductor device. 　 In claim 1, the second single crystal substrate has a cubic crystal structure; the second single crystal semiconductor has a cubic crystal structure; Semiconductor device. 　 In claim 1, the second single crystal substrate has an oxide containing yttrium and zirconium; the second single crystal semiconductor includes indium oxide; Semiconductor device. 　 In claim 1, the second single crystal semiconductor has a lattice mismatch of −5% or more and 5% or less with respect to the second single crystal substrate; Semiconductor device. 　 In claim 1, a first conductive layer and a second conductive layer; the first conductive layer is connected to one of a source electrode and a drain electrode of the first transistor and is embedded in the first insulating layer; the second conductive layer is connected to one of a source electrode and a drain electrode of the second transistor, is embedded in the second insulating layer, and has a second junction surface in contact with the first conductive layer; Semiconductor device. 　 preparing a first single-crystal substrate including a first single-crystal semiconductor, the first single-crystal substrate including a first transistor and a first insulating layer on the first transistor; providing a second single crystal substrate; forming a semiconductor film containing a second single crystal semiconductor on the second single crystal substrate; a step of processing the semiconductor film into an island shape to form a semiconductor layer; forming a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on the semiconductor layer to fabricate a second transistor; forming a second insulating layer over the second transistor; and joining an upper surface of the first insulating layer to an upper surface of the second insulating layer. A method for manufacturing a semiconductor device. 　 In claim 6, the first single-crystal semiconductor includes silicon; the second single-crystal semiconductor includes a metal oxide; A method for manufacturing a semiconductor device. 　 In claim 6, the second single crystal substrate has a cubic crystal structure; the second single crystal semiconductor has a cubic crystal structure; A method for manufacturing a semiconductor device. 　 In claim 6, the second single crystal substrate has an oxide containing yttrium and zirconium; the second single crystal semiconductor includes indium oxide; A method for manufacturing a semiconductor device. 　 In claim 6, the second single crystal semiconductor has a lattice mismatch of −5% or more and 5% or less with respect to the second single crystal substrate; A method for manufacturing a semiconductor device.

Images