Electronic circuit and electronic apparatus

Abstract

The present technology suppresses malfunctions caused by interference inside an electronic circuit.　The electronic circuit comprises: an analog circuit formed on a semiconductor chip; a digital circuit also formed on the semiconductor chip; a current monitor circuit for monitoring, on the semiconductor chip, a current flowing through the semiconductor chip; and a timing adjustment circuit for adjusting the operation timing of at least one of the analog circuit and the digital circuit on the basis of the waveform of the current flowing through the semiconductor chip. The analog circuit may comprise an analog-to-digital (AD) conversion circuit.

Description

Electronic Circuits and Electronic Equipment

[0001] The present technology relates to an electronic circuit and an electronic device, and more particularly to an electronic circuit and an electronic device capable of controlling operation timing based on a current monitor.

[0002] In order to investigate the influence of noise on an electronic circuit, the switching current of the electronic circuit may be monitored. For example, a technique for dynamically probing power supply fluctuations in an electronic circuit has been disclosed (see, for example, Non-Patent Document 1).

[0003] ISSCC 2007 / SESSION16 POWER DISTRIBUTION AND MANAGEMENT / 16.2Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs

[0004] However, in the above-mentioned conventional technology, in a chip where analog circuits and digital circuits are integrated, there is a risk that switching noise from the digital circuits may cause the analog circuits to malfunction.

[0005] This technology was developed in light of these circumstances, and aims to suppress malfunctions caused by interference within electronic circuits.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an electronic circuit including an analog circuit formed on a semiconductor chip, a digital circuit embedded in the semiconductor chip, a current monitor circuit that monitors, on the semiconductor chip, a current flowing through the semiconductor chip, and a timing adjustment circuit that adjusts the operation timing of at least one of the analog circuit and the digital circuit based on the waveform of the current flowing through the semiconductor chip. This brings about the effect of suppressing malfunctions caused by interference within the electronic circuit based on the current flowing through the semiconductor chip monitored on the semiconductor chip.

[0007] In the first aspect, the analog circuit may include an AD (Analog to Digital) conversion circuit, which suppresses a decrease in AD conversion accuracy due to switching noise generated in a digital circuit based on a current flowing through the semiconductor chip monitored on the semiconductor chip.

[0008] In the first aspect, the timing adjustment circuit may adjust the operation timing of at least one of the analog circuit and the digital circuit so that the operation period of the analog circuit is set during a flat portion of the waveform of the current flowing through the semiconductor chip, thereby reducing the effect of switching noise generated in the digital circuit during the operation period of the analog circuit.

[0009] In addition, in the first aspect, the analog circuit may include a CDS (Correlated Double Sampling) circuit, and the timing adjustment circuit may adjust the operation timing of at least one of the analog circuit and the digital circuit so that the waveform of a current flowing through the semiconductor chip during operation of the CDS circuit is equalized between a P-phase period and a D-phase period, thereby reducing the effect of switching noise generated in the digital circuit during operation of the CDS circuit.

[0010] In addition, in the first aspect, the semiconductor chip may further include a waveform recognition circuit that recognizes the waveform of a current flowing through the semiconductor chip based on the current monitored by the current monitor circuit, and the timing adjustment circuit may adjust the operation timing of at least one of the analog circuit and the digital circuit based on the recognition result of the waveform recognition circuit, thereby providing the effect of automatically setting the operation period of the analog circuit so as to reduce the influence of switching noise generated in the digital circuit.

[0011] In addition, in the first aspect, the timing adjustment circuit may include a register that stores an adjustment value for the operation timing of at least one of the analog circuit and the digital circuit, and the adjustment value may be set in the register externally, thereby providing an effect that the operation period of the analog circuit can be manually set so as to reduce the influence of switching noise generated in the digital circuit.

[0012] In addition, in the first aspect, the semiconductor device may further include an output interface that digitizes the monitoring result of the current flowing through the semiconductor chip and outputs the digitized result to an external device, thereby suppressing a decrease in the monitoring accuracy of the current flowing through the semiconductor chip that is monitored on the semiconductor chip, and enabling the waveform of the current to be displayed.

[0013] In the first aspect, the timing adjustment circuit and the current monitor circuit may be turned off after the timing adjustment circuit adjusts the operation timing, thereby suppressing an increase in power consumption and preventing malfunctions caused by interference within the electronic circuit based on the current flowing through the semiconductor chip monitored on the semiconductor chip.

[0014] In addition, in the first aspect, the semiconductor device may further include a current consumption circuit that consumes the current flowing through the semiconductor chip based on the monitoring result of the current flowing through the semiconductor chip, thereby achieving an effect of adjusting the waveform of the current flowing through the semiconductor chip, which cannot be achieved by adjusting the timing of the operation periods of the analog circuit and the digital circuit.

[0015] In the first aspect, the current consumption circuit may consume the current flowing in the semiconductor chip so that the waveform of the current flowing in the semiconductor chip is flattened during the operation period of the analog circuit, thereby achieving flattening of the waveform of the current flowing in the semiconductor chip, which cannot be achieved by adjusting the timing of the operation periods of the analog circuit and the digital circuit.

[0016] In the first aspect, after the timing adjustment circuit adjusts the operation timing, the timing adjustment circuit, the current monitor circuit, and the current consumption circuit may be turned off, thereby suppressing an increase in power consumption and adjusting the timing of an interference period within the electronic circuit.

[0017] In addition, in the first aspect, the power supply may further include a voltage monitor circuit that monitors a voltage corresponding to a frequency component of the current based on the current monitored by the current monitor circuit, thereby achieving voltage monitoring based on the current monitor.

[0018] According to a second aspect, there is provided an electronic device including a sensor that performs sensing and an electronic circuit that processes an output from the sensor, the electronic circuit being formed on a semiconductor chip and including an AD conversion circuit that AD converts the output from the sensor, a digital circuit embedded in the semiconductor chip, a current monitoring circuit that monitors a current flowing through the semiconductor chip on the semiconductor chip, and a timing adjustment circuit that adjusts the operation timing of at least one of the AD conversion circuit and the digital circuit based on the waveform of the current flowing through the semiconductor chip. This provides the effect of suppressing a decrease in the AD conversion accuracy of sensor data due to switching noise generated in the digital circuit based on the current flowing through the semiconductor chip monitored on the semiconductor chip.

[0019] 1 is a block diagram showing a configuration example of a semiconductor chip on which an electronic circuit according to a first embodiment is formed. FIG. 2 is a diagram showing an example of a change in AD conversion timing according to the first embodiment. FIG. 3 is a block diagram showing a configuration example of a digital circuit according to the first embodiment. FIG. 4 is a diagram showing current waveforms before and after a change in the activation timing of the digital circuit according to the first embodiment. FIG. 5 is a diagram showing an example of a monitor position of a current flowing in a semiconductor chip according to the first embodiment. FIG. 6 is a diagram showing a change in monitor current due to differences in monitor position according to the first embodiment. FIG. 7 is a block diagram showing a first example of current monitor data output according to the first embodiment. FIG. 8 is a block diagram showing a second example of current monitor data output according to the first embodiment. FIG. 9 is a block diagram showing a first example of data output from an AD conversion circuit according to the first embodiment. FIG. 10 is a block diagram showing a second example of data output from an AD conversion circuit according to the first embodiment. FIG. 11 is a block diagram showing a third example of data output from an AD conversion circuit according to the first embodiment. FIG. 12 is a block diagram showing a configuration example of a semiconductor chip on which an electronic circuit according to a second embodiment is formed. FIG. 13 is a diagram showing a method of setting AD conversion timing according to the second embodiment. FIG. 14 is a block diagram showing a configuration example of a semiconductor chip on which an electronic circuit according to a third embodiment is formed. FIG. 15 is a diagram showing a first configuration example of a current consumption circuit according to the third embodiment. FIG. 16 is a diagram showing a second configuration example of a current consumption circuit according to the third embodiment. 10 is a diagram showing a method for setting AD conversion timing according to a third embodiment. FIG. 11 is a diagram showing a method for setting current consumption timing according to a third embodiment. FIG. 12 is a flowchart showing a method for changing the startup timing of a digital circuit according to a third embodiment. FIG. 13 is a diagram showing a method for setting AD conversion timing according to a fourth embodiment. FIG. 14 is a diagram showing a method for setting current consumption timing according to a fourth embodiment. FIG. 15 is a flowchart showing a method for changing the startup timing of a digital circuit according to a fourth embodiment. FIG. 16 is a diagram showing a method for monitoring the voltage of a semiconductor chip on which an electronic circuit is formed according to a fifth embodiment. FIG. 17 is a diagram showing the relationship between frequency and impedance of an electronic circuit according to a fifth embodiment. FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system. FIG. 19 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0020] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example of manually adjusting the operation timing of an analog circuit or a digital circuit based on the waveform of a current flowing through a semiconductor chip) 2. Second embodiment (an example of automatically adjusting the operation timing of an analog circuit or a digital circuit based on the waveform of a current flowing through a semiconductor chip) 3. Third embodiment (an example of adjusting the operation timing and current consumption timing of an analog circuit or a digital circuit) 4. Fourth embodiment (an example of adjusting the operation timing and current consumption timing of an analog circuit or a digital circuit during CDS operation) 5. Fifth embodiment (an example of monitoring a voltage corresponding to the frequency component of a current flowing through a semiconductor chip based on the waveform of that current) 6. Application example to a moving body

[0021] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of a semiconductor chip on which an electronic circuit according to a first embodiment is formed.

[0022] In the figure, an electronic circuit is formed on the semiconductor chip 100. A sensor for sensing can also be formed on the semiconductor chip 100. In this case, the electronic circuit can process the output from the sensor. The sensor may be an imaging element with photoelectric conversion, a MEMS (Micro Electro Mechanical Systems) sensor, or a sensor that detects cellular responses. The imaging element may be a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a CCD (Charge Coupled Device), or a distance sensor. The semiconductor material of the semiconductor chip 100 may be Si, GaAs, SiC, GaN, InGaAs, InP, InGaAsP, or the like.

[0023] The electronic circuit includes an analog circuit 110 and a digital circuit 120. In this case, the analog circuit 110 and the digital circuit 120 can be mounted together on a semiconductor chip 100.

[0024] The analog circuit 110 can, for example, AD (Analog to Digital) convert an analog signal detected by a sensor and output the converted signal. The analog circuit 110 may include an AD conversion circuit, a PLL (Phase Locked Loop) circuit, or a BGR (Band Gap Reference) that generates a reference potential. The analog circuit 110 includes an analog signal generating source 111, an AD conversion circuit 112, and an AD conversion control circuit 113.

[0025] The analog signal source 111 generates an analog signal and outputs it to the AD conversion circuit 112. The analog signal source 111 may be a sensor.

[0026] The AD conversion circuit 112 digitizes the analog signal generated by the analog signal generation source 111 and outputs it to the digital circuit 120 .

[0027] The AD conversion control circuit 113 controls the AD conversion circuit 112. For example, the AD conversion control circuit 113 can control the activation timing of the AD conversion circuit 112 based on an instruction from the digital circuit 120.

[0028] The digital circuit 120 processes the data digitized by the analog circuit 110. The digital circuit 120 may include multiple sub-circuits that can operate independently. The digital circuit 120 may include a memory, a processor, a signal processing circuit, a data processing circuit, or an interface circuit. The digital circuit 120 includes a current monitor circuit 121, a digital timing adjustment circuit 123, an AD conversion timing adjustment circuit 124, a digital processing unit 125, and an output interface 126.

[0029] The current monitor circuit 121 monitors the current flowing in the semiconductor chip 100 on the semiconductor chip 100. The current flowing in the semiconductor chip 100 may include switching noise generated when the analog circuit 110 and the digital circuit 120 are operating. In this case, the current monitor circuit 121 may monitor the current flowing in the digital circuit 120, or may monitor the current flowing in the analog circuit 110. The current monitor circuit 121 does not necessarily need to monitor all of the current flowing in the digital circuit 120, and may monitor only a portion of the current flowing in the digital circuit 120.

[0030] The digital timing adjustment circuit 123 adjusts the operation timing of the digital circuit 120 based on the waveform of the current flowing through the semiconductor chip 100. When adjusting the operation timing of the digital circuit 120, the operation timing can be adjusted for each sub-circuit included in the digital circuit 120. To adjust the operation timing of the digital circuit 120, the activation timing of the digital circuit 120 may be adjusted, or the activation timing may be adjusted for each sub-circuit included in the digital circuit 120. For example, the digital timing adjustment circuit 123 can adjust the operation timing of the digital circuit 120 and the sub-circuits included in the digital circuit 120 so that the operation period of the AD conversion circuit 112 is set during the flat portion of the waveform of the current flowing through the semiconductor chip 100. In this case, the digital timing adjustment circuit 123 can generate a flat portion even if the waveform of the current flowing through the semiconductor chip 100 does not have a flat portion. This flat portion can be longer than the operation time of the AD conversion circuit 112. In the flat portion, a current fluctuation of ±1% to ±30% of the average value of the current in the flat portion monitored by the current monitor circuit 121 can be tolerated. The digital timing adjustment circuit 123 may include a register 123A. In this case, the register 123A can store the activation timing of the digital circuit 120 and the sub-circuits included in the digital circuit 120 so that the operation period of the AD conversion circuit 112 is set to the flat portion of the waveform of the current flowing through the semiconductor chip 100.

[0031] The AD conversion timing adjustment circuit 124 adjusts the operation timing of the AD conversion circuit 112 based on the waveform of the current flowing through the semiconductor chip 100. In order to adjust the operation timing of the AD conversion circuit 112, the activation timing of the AD conversion circuit 112 may be adjusted. For example, the AD conversion timing adjustment circuit 124 can adjust the operation timing of the AD conversion circuit 112 so that the operation period of the AD conversion circuit 112 is set to the flat portion of the waveform of the current flowing through the semiconductor chip 100. The AD conversion timing adjustment circuit 124 can include a register 124A. In this case, the register 124A can store the activation timing of the AD conversion circuit 112 so that the operation period of the AD conversion circuit 112 is set to the flat portion of the waveform of the current flowing through the semiconductor chip 100.

[0032] The digital processing unit 125 digitally processes the data digitized by the analog circuit 110. The digital processing may be, for example, image processing, edge detection processing, distance measurement processing, or voice recognition processing.

[0033] The output interface 126 digitizes the monitoring result of the current flowing through the semiconductor chip 100 and outputs it to the outside. The output interface 126 may include an AD conversion circuit. At this time, based on the data output via the output interface 126, the waveform of the current flowing through the semiconductor chip 100 is displayed on a display device, and the waveform of the current flowing through the semiconductor chip 100 can be confirmed outside the semiconductor chip 100. Note that the output interface 126 may also output the monitoring result of the current flowing through the semiconductor chip 100 to the outside in analog form.

[0034] Then, the activation timing of the digital circuit 120 and the sub-circuits included in the digital circuit 120 can be stored in the register 123A so that the operation period of the AD conversion circuit 112 is set in the flat portion of the waveform of the current flowing through the semiconductor chip 100. The flat portion of the waveform of the current flowing through the semiconductor chip 100 can be confirmed and the activation timing of the digital circuit 120 and the sub-circuits included in the digital circuit 120 can be stored in the register 123A manually.

[0035] Alternatively, the activation timing of the AD conversion circuit 112 can be stored in the register 124A so that the operation period of the AD conversion circuit 112 is set to the flat portion of the waveform of the current flowing through the semiconductor chip 100. Checking the flat portion of the waveform of the current flowing through the semiconductor chip 100 and storing the activation timing of the AD conversion circuit 112 in the register 124A can be done manually.

[0036] The digital circuit 120 may turn off the current monitor circuit 121, the digital timing adjustment circuit 123, and the AD conversion timing adjustment circuit 124 after the digital timing adjustment circuit 123 or the AD conversion timing adjustment circuit 124 has adjusted the operation timing.

[0037] FIG. 2 is a diagram showing an example of a modification of the AD conversion timing according to the first embodiment.

[0038] In the figure, a current monitor circuit 121 monitors the current flowing through the semiconductor chip 100 on the semiconductor chip 100. The waveform MA of the current monitored by the current monitor circuit 121 can be displayed on a display device. At this time, for example, flat portions of the current waveform MA during periods T1, T2, and T3 can be confirmed on the display device.

[0039] On the other hand, the AD conversion period of the AD conversion circuit 112 is set based on an AD conversion start signal. For example, when the AD conversion start signal is at a low level, the AD conversion of the AD conversion circuit 112 can be set to inactive, and when the AD conversion start signal is at a high level, the AD conversion of the AD conversion circuit 112 can be set to active. The AD conversion period of the AD conversion circuit 112 can also be displayed on a display device. Here, the current waveform MA monitored by the current monitor circuit 121 and the AD conversion period T1 of the AD conversion circuit 112 can be displayed on the display device with the same time axis. At this time, it can be confirmed on the display device which portion of the current waveform MA the AD conversion period T1 of the AD conversion circuit 112 overlaps with. If the AD conversion period T1 of the AD conversion circuit 112 does not overlap with the period T2 of the flat portion of the current waveform MA, the rising timing of the AD conversion start signal is manually stored in the register 124A so that the operation period of the AD conversion circuit 112 is set to the period T2 of the flat portion of the current waveform MA. Note that the operation period of the AD conversion circuit 112 may also be set to the periods T1 and T3 of the flat portions of the current waveform MA.

[0040] As a result, as shown in b in the figure, the AD conversion of the AD conversion circuit 112 is performed during the period T2 of the flat portion of the current waveform MA. This makes it possible to make the AD conversion of the AD conversion circuit 112 less susceptible to the effects of switching noise of the digital circuit 120, and to prevent a decrease in the AD conversion accuracy in the semiconductor chip 100 on which the digital circuit 120 is embedded.

[0041] 3 is a block diagram showing an example of the configuration of a digital circuit according to the first embodiment. While the diagram shows an example in which the digital circuit 120 includes three subcircuits 120A to 120C, the number of subcircuits is not limited to three, and the digital circuit 120 may include any number of subcircuits other than the three subcircuits 120A to 120C.

[0042] In the figure, the digital circuit 120 includes multiple sub-circuits 120A to 120C. These sub-circuits 120A to 120C can be connected in parallel between a power supply potential VDD and a ground potential GND. The operation period of each of the sub-circuits 120A to 120C can be set individually. In this case, the digital timing adjustment circuit 123 can individually set the activation timing of each of the sub-circuits 120A to 120C based on the data stored in the register 123A.

[0043] FIG. 4 is a diagram showing current waveforms before and after the start-up timing of the digital circuit according to the first embodiment is changed.

[0044] In the figure, for example, assume that the current waveforms of the sub-circuits 120A to 120C during operation are WA1 to WC1, respectively. At this time, as shown in the figure, the activation timing of each of the sub-circuits 120A to 120C can be stored in the register 123A so that a flat portion TP is generated in the current waveform monitored by the current monitor circuit 121, as shown in the figure, b. The digital timing adjustment circuit 123 adjusts the activation timing of each of the sub-circuits 120A to 120C based on the data stored in the register 123A, thereby changing the current waveforms of each of the sub-circuits 120A to 120C during operation from WA2 to WC2, respectively, and generating a flat portion TP. At this time, the AD conversion timing adjustment circuit 124 can adjust the operation timing of the AD conversion circuit 112 so that the operation period of the AD conversion circuit 112 is set to this flat portion TP. This makes it possible to generate a flat portion in the waveform of the current monitored by the current monitor circuit 121 when the waveform does not have a flat portion, and to operate the AD conversion circuit 112 on that flat portion.

[0045] Fig. 5 is a diagram showing an example of a monitoring position of a current flowing in a semiconductor chip according to the first embodiment, and Fig. 6 is a diagram showing a change in the monitored current due to differences in the monitoring position according to the first embodiment. Note that Fig. 5 shows equivalent power supply systems for the digital circuit 120, the package 130, and the PCB board 140.

[0046] 5, the semiconductor chip 100 is packaged in a package 130, and the package 130 is mounted on a PCB (Printed Circuit Board) substrate 140. A current source G is connected between a power supply potential VDD and a ground potential GND of the digital circuit 120, and a capacitance C1 is connected in parallel to the current source G. The power supply potential VDD and the ground potential GND of the digital circuit 120 are connected to the package 130 via resistors R1 and R2, respectively.

[0047] An inductor L1 is connected in series to the power supply potential VDD of the package 130, and an inductor L2 is connected in series to the ground potential GND of the package 130. A capacitor C2 is connected between the power supply potential VDD and the ground potential GND of the package 130 at one end of each of the inductors L1 and L2. A capacitor C3 is connected between the power supply potential VDD and the ground potential GND of the package 130 at the other end of each of the inductors L1 and L2.

[0048] An inductor L3 is connected in series to the power supply potential VDD of the PCB board 140, and an inductor L4 is connected in series to the ground potential GND of the PCB board 140. A capacitor C4 is connected at one end of each of the inductors L3 and L4 between the power supply potential VDD and the ground potential GND of the PCB board 140. A capacitor C5 is connected at the other end of each of the inductors L3 and L4 between the power supply potential VDD and the ground potential GND of the PCB board 140. A bypass capacitor C6 is connected in parallel to the capacitor C5.

[0049] When the digital circuit 120 operates, a current In flows through the digital circuit 120. When the current In flows through the digital circuit 120, a current Io flows through the PCB board 140. As shown in FIG. 6 , the current Io has a waveform in which the high-frequency components of the current In are attenuated. At this time, the current monitor circuit 121 monitors the current In flowing through the digital circuit 120. This allows the current monitor circuit 121 to capture a waveform in which the high-frequency components of the current In are not attenuated.

[0050] FIG. 7 is a block diagram showing a first example of current monitor data output according to the first embodiment.

[0051] In the figure, the output interface 126 includes an AD conversion circuit 127. The AD conversion circuit 127 digitizes the current IA monitored by the current monitor circuit 121 and outputs a digital value ID of the current IA. At this time, the AD conversion circuit 127 can output multiple bits of the digital value ID in parallel. Here, by digitizing and outputting the current IA monitored by the current monitor circuit 121, it is possible to observe the waveform of the current IA monitored by the current monitor circuit 121 externally while suppressing distortion of the waveform.

[0052] FIG. 8 is a block diagram showing a second example of current monitor data output according to the first embodiment.

[0053] In the figure, the output interface 126 includes an AD conversion circuit 127 and a parallel-serial conversion circuit 128. The parallel-serial conversion circuit 128 serializes the multiple bits of the digital value ID output in parallel from the AD conversion circuit 127 and outputs serial data SD. By serializing and outputting the digital value ID output in parallel from the AD conversion circuit 127, the number of data output terminals can be reduced.

[0054] FIG. 9 is a block diagram showing a first example of data output from the AD conversion circuit according to the first embodiment.

[0055] In the figure, a terminal TM1 can be provided on the semiconductor chip 100. The terminal TM1 can be used to externally retrieve the digital data DAT output from the AD conversion circuit 112. The terminal TM1 can be dedicated to externally retrieving the digital data DAT.

[0056] FIG. 10 is a block diagram showing a second example of data output from the AD conversion circuit according to the first embodiment.

[0057] In the figure, a selector 129 and a terminal TM2 can be provided on the semiconductor chip 100. The selector 129 receives the output signal S0 from the semiconductor chip 100 and the digital data DAT output from the AD conversion circuit 112. At this time, the selector 129 can select and output either the output signal S0 or the digital data DAT based on a switching signal S1. The terminal TM2 can be used to extract the output from the selector 129 to the outside. Here, by providing the selector 129 on the semiconductor chip 100, the terminal TM1 dedicated to extracting the digital data DAT to the outside can be eliminated.

[0058] FIG. 11 is a block diagram showing a third example of data output from the AD conversion circuit according to the first embodiment.

[0059] In the figure, the semiconductor chip 100 is provided with a delay circuit 131 along with the output interface 126 of FIG. 8. The delay circuit 131 can delay the digital data DAT corresponding to the delays of the AD conversion circuit 127 and the parallel-serial conversion circuit 128. The delay circuit 131 may be synchronized with a clock. The delay circuit 131 may cause a delay by controlling the capacitance and resistance visible in its critical path, or may control the charging time of the capacitance within the delay circuit 131, i.e., the operating speed of the delay circuit 131, by controlling the current of the delay circuit 131. Here, by providing the delay circuit 131 on the semiconductor chip 100, the digital data DAT output data output from the AD conversion circuit 112 and the serial data SD of the monitor current by the current monitor circuit 121 can be output in synchronization with each other.

[0060] As described above, in the first embodiment, the operation timing of the analog circuit 110 or the digital circuit 120 is manually adjusted based on the waveform of the current flowing through the semiconductor chip 100. This makes it possible to improve the detection accuracy of the switching noise of the digital circuit 120 while reducing the influence of the switching noise of the digital circuit 120 on the analog circuit 110.

[0061] 2. Second Embodiment In the above-described first embodiment, the operation timing of the analog circuit 110 or the digital circuit 120 is manually adjusted based on the waveform of the current flowing through the semiconductor chip 100. In this second embodiment, the operation timing of the analog circuit or the digital circuit is automatically adjusted based on the waveform of the current flowing through the semiconductor chip.

[0062] FIG. 12 is a block diagram showing an example of the configuration of a semiconductor chip on which an electronic circuit according to the second embodiment is formed.

[0063] In the figure, this semiconductor chip 200 includes a digital circuit 220 instead of the digital circuit 120 of the first embodiment described above. Other configurations of the semiconductor chip 200 of the second embodiment are similar to the configuration of the semiconductor chip 100 of the first embodiment described above.

[0064] The digital circuit 220 is obtained by adding a current waveform recognition circuit 122 to the digital circuit 120 of the above-described first embodiment. Furthermore, this semiconductor chip 200 is obtained by removing the output interface 126 from the semiconductor chip 100 of the above-described first embodiment. Other configurations of the digital circuit 220 of the second embodiment are similar to those of the digital circuit 120 of the above-described first embodiment. Note that the semiconductor chip 200 may also include the output interface 126 of the above-described first embodiment.

[0065] The current waveform recognition circuit 122 recognizes the waveform of the current flowing through the semiconductor chip 100 based on the current monitored by the current monitor circuit 121. Here, the current waveform recognition circuit 122 may detect a flat portion of the waveform of the current flowing through the semiconductor chip 100.

[0066] At this time, the digital timing adjustment circuit 123 can adjust the operation timing of the digital circuit 120 based on the waveform of the current flowing through the semiconductor chip 100 recognized by the current waveform recognition circuit 122. The AD conversion timing adjustment circuit 124 can adjust the operation timing of the AD conversion circuit 112 based on the waveform of the current flowing through the semiconductor chip 100 recognized by the current waveform recognition circuit 122.

[0067] In addition, the digital circuit 220 may turn off the current monitor circuit 121, the current waveform recognition circuit 122, the digital timing adjustment circuit 123, and the AD conversion timing adjustment circuit 124 after the operation timing is adjusted by the digital timing adjustment circuit 123 or the AD conversion timing adjustment circuit 124.

[0068] FIG. 13 is a diagram showing a method for setting the AD conversion timing according to the second embodiment.

[0069] In the figure, a current monitor circuit 121 monitors the current flowing through a semiconductor chip 200 on the semiconductor chip 200. The monitoring result of the current monitored by the current monitor circuit 121 is input to a current waveform recognition circuit 122. At this time, the current waveform recognition circuit 122 can detect flat portions of the current waveform MB during periods T10, T12, and T13, for example.

[0070] The digital circuit 220 may include multiple sub-circuits 120A to 120C. The operation period of the digital circuit 220 is set based on a digital circuit activation signal. For example, when the digital circuit activation signal is at a low level, the digital circuit 220 is set to be inactive, and when the digital circuit activation signal is at a high level, the digital circuit 220 is set to be active. The operation period of each of the sub-circuits 120A to 120C is set based on a sub-circuit activation signal ACK. The sub-circuit activation signal ACK may be generated for each of the sub-circuits 120A to 120C during the high-level period of the digital circuit activation signal. Each time the sub-circuit activation signal ACK rises, the sub-circuit 120A to 120C corresponding to the sub-circuit activation signal ACK is activated.

[0071] At this time, the digital timing adjustment circuit 123 can adjust the rising timing of the digital circuit activation signal and the sub-circuit activation signal ACK based on the waveform of the current flowing through the semiconductor chip 100 recognized by the current waveform recognition circuit 122. At this time, the digital timing adjustment circuit 123 can generate, for example, a flat portion of the current waveform MB in the period T12 based on the result of adjusting the rising timing of the digital circuit activation signal and the sub-circuit activation signal ACK.

[0072] The AD conversion timing adjustment circuit 124 can adjust the operation timing of the AD conversion circuit 112 based on the waveform of the current flowing through the semiconductor chip 100 recognized by the current waveform recognition circuit 122. At this time, the AD conversion timing adjustment circuit 124 can adjust the rising timing of the AD conversion start signal so that the operation period of the AD conversion circuit 112 is set to the period T12 of the flat portion of the current waveform MB.

[0073] As a result, the AD conversion of the AD conversion circuit 112 is performed during the period T12 of the flat portion of the current waveform MB. This makes it possible to make the AD conversion of the AD conversion circuit 112 less susceptible to the effects of switching noise of the digital circuit 220, and to suppress a decrease in the AD conversion accuracy in the semiconductor chip 200 on which the digital circuit 220 is embedded.

[0074] In this way, in the second embodiment described above, the operation timing of the analog circuit 110 or the digital circuit 220 is automatically adjusted based on the waveform of the current flowing through the semiconductor chip 200. This makes it possible to improve the detection accuracy of the switching noise of the digital circuit 220 while reducing the influence of the switching noise of the digital circuit 220 on the analog circuit 110, and also makes it unnecessary to externally observe the current flowing through the semiconductor chip 200.

[0075] 3. Third Embodiment In the first embodiment described above, the operation timing of the analog circuit 110 or the digital circuit 220 is automatically adjusted based on the waveform of the current flowing through the semiconductor chip 200. In this third embodiment, the operation timing and current consumption timing of the analog circuit or the digital circuit are automatically adjusted based on the waveform of the current flowing through the semiconductor chip.

[0076] FIG. 14 is a block diagram showing an example of the configuration of a semiconductor chip on which an electronic circuit according to the third embodiment is formed.

[0077] In the figure, this semiconductor chip 300 includes a digital circuit 320 instead of the digital circuit 220 of the second embodiment described above. Other configurations of the semiconductor chip 300 of the third embodiment are similar to the configurations of the semiconductor chip 200 of the second embodiment described above.

[0078] The digital circuit 320 is obtained by adding a current consumption control circuit 301 and a current consumption circuit 302 to the digital circuit 220 of the second embodiment described above. The other configurations of the digital circuit 320 of the third embodiment are the same as the configurations of the digital circuit 220 of the second embodiment described above. Note that the semiconductor chip 300 may also include the output interface 126 of the first embodiment described above.

[0079] The current consumption circuit 302 supplies a consumption current to the digital circuit 320. This consumption current does not have to contribute to the operation of the digital circuit 320. In this case, this consumption current may be consumed by a resistor or may be stored in a capacitor. This consumption current is reflected in the current monitored by the current monitor circuit 121.

[0080] The current consumption control circuit 301 controls the current consumption supplied from the current consumption circuit 302. The current consumption control circuit 301 can control the current consumption consumed by the digital circuit 320 based on the current monitored by the current monitor circuit 121. For example, the current consumption control circuit 301 can control the current consumption so that the waveform of the current monitored by the current monitor circuit 121 is flattened during the operation period of the AD conversion circuit 112.

[0081] In addition, the digital circuit 320 may turn off the current monitor circuit 121, the current waveform recognition circuit 122, the digital timing adjustment circuit 123, the AD conversion timing adjustment circuit 124, and the current consumption control circuit 301 after the operation timing is adjusted by the digital timing adjustment circuit 123 or the AD conversion timing adjustment circuit 124.

[0082] FIG. 15 is a diagram illustrating a first configuration example of a current consumption circuit according to the third embodiment.

[0083] In the figure, this current consumption circuit includes multiple inverters IV and a capacitor CA. The capacitor CA is connected in parallel to the output of each inverter IV. The inverters IV are connected in multiple stages. In this case, the inverters IV and capacitor CA of each stage can form a delay circuit. An input signal SIN is input to the first stage of the inverter IV, and the capacitor CA is charged, thereby generating a consumption current. Note that the current consumption circuit may have a configuration other than an inverter chain as long as it can consume current.

[0084] FIG. 16 is a diagram illustrating a second configuration example of the current consumption circuit according to the third embodiment.

[0085] In the figure, the current consumption circuit includes multiple field-effect transistors M1 to M50. The field-effect transistors M1 to M50 may be N-channel field-effect transistors. The sizes of the field-effect transistors M1 to M50 may be different from one another. Each field-effect transistor M1 to M50 is connected between a power supply potential VDD and a ground potential GND. Control signals CT1 to CT50 are applied to the gates of the field-effect transistors M1 to M50, respectively. When the field-effect transistors M1 to M50 are turned on based on the control signals CT1 to CT50, a through current flows through each field-effect transistor M1 to M50, generating a consumption current. At this time, the current consumption amount can be set based on the number or combination of field-effect transistors M1 to M50 that are turned on based on the control signals CT1 to CT50. Note that while FIG. 16 shows an example in which only 50 field-effect transistors M1 to M50 are provided, other numbers may also be used.

[0086] FIG. 17 is a diagram showing a method for setting the AD conversion timing according to the third embodiment.

[0087] In the figure, a current monitor circuit 121 monitors the current flowing through the semiconductor chip 300 on the semiconductor chip 300. The monitoring result of the current monitored by the current monitor circuit 121 is input to a current waveform recognition circuit 122. At this time, the current waveform recognition circuit 122 can detect the flat portion of the current waveform MC for, for example, a period T12 other than a period T14.

[0088] The digital timing adjustment circuit 123 adjusts the rising timing of the digital circuit activation signal and the sub-circuit activation signal ACK based on the waveform MC of the current flowing through the semiconductor chip 300 recognized by the current waveform recognition circuit 122. Here, it is assumed that as a result of adjusting the rising timing of the digital circuit activation signal and the sub-circuit activation signal ACK, the waveform MC cannot be completely flattened throughout the entire period T12, and a non-flat portion remains in the period T14. In this case, if the operation period of the AD conversion circuit 112 is set to the period T12 of the waveform MC, there is a risk that switching noise of the digital circuit 320 will affect the AD conversion in the period T14.

[0089] FIG. 18 is a diagram showing a method for setting the current consumption timing according to the third embodiment.

[0090] 18 , the current consumption control circuit 301 detects a non-flat portion during period T14 of period T12 as a result of the timing adjustment of the digital circuit 320 by the digital timing adjustment circuit 123. At this time, the current consumption control circuit 301 controls the current consumption circuit 302 so that a current DI is consumed during period T14. At this time, the current consumption control circuit 301 recognizes whether the non-flat portion during period T14 has been eliminated based on the waveform MD of the current flowing through the semiconductor chip 300 recognized by the current waveform recognition circuit 122. The current consumption control circuit 301 can then adjust the current DI during period T14 so that the non-flat portion during period T14 is eliminated.

[0091] FIG. 19 is a flowchart showing a method for changing the activation timing of a digital circuit according to the third embodiment.

[0092] In the figure, the current monitor circuit 121 monitors the current flowing through the digital circuit 320 on the semiconductor chip 300 (S101).

[0093] Next, the current waveform recognition circuit 122 recognizes the waveform of the current flowing through the semiconductor chip 300 (S102).

[0094] Next, the digital timing adjustment circuit 123 determines whether there is a change in the current flowing through the semiconductor chip 300 during AD conversion by the AD conversion circuit 112 (S103). If there is no change in the current flowing through the semiconductor chip 300 during AD conversion by the AD conversion circuit 112, the process ends. On the other hand, if there is a change in the current flowing through the semiconductor chip 300 during AD conversion by the AD conversion circuit 112, the digital timing adjustment circuit 123 changes the activation timing of the digital circuit 320 (S104).

[0095] Next, the current consumption control circuit 301 determines whether there is a change in the current flowing through the semiconductor chip 300 during AD conversion by the AD conversion circuit 112 (S105). If there is no change in the current flowing through the semiconductor chip 300 during AD conversion by the AD conversion circuit 112, the process ends. On the other hand, if there is a change in the current flowing through the semiconductor chip 300 during AD conversion by the AD conversion circuit 112, the current consumption control circuit 301 controls the current consumption supplied from the current consumption circuit 302 (S106) and returns the process to S101.

[0096] In this way, in the third embodiment described above, the operation timing and current consumption timing of the analog circuit 110 or the digital circuit 320 are automatically adjusted based on the waveform of the current flowing through the semiconductor chip 300. As a result, even in cases where it is difficult to flatten the current flowing through the semiconductor chip 300 simply by adjusting the operation timing of the digital circuit 320, it is possible to flatten the current flowing through the semiconductor chip 300, and it becomes possible to set the operation period of the analog circuit 110 to the flat portion of the waveform of the current flowing through the semiconductor chip 300.

[0097] 4. Fourth Embodiment In the above-described third embodiment, the operation timing and current consumption timing of the analog circuit 110 or the digital circuit 320 are automatically adjusted based on the waveform of the current flowing through the semiconductor chip 300. In this fourth embodiment, the operation timing and current consumption timing of the analog circuit 110 or the digital circuit 320 during CDS operation are adjusted based on the waveform of the current flowing through the semiconductor chip 300.

[0098] FIG. 20 is a diagram showing a method for setting the AD conversion timing according to the fourth embodiment.

[0099] In the figure, an analog signal generation source 111 can generate an analog signal based on CDS and output it to an AD conversion circuit 112. At this time, the AD conversion circuit 112 can digitize the difference between the P-phase analog signal and the D-phase analog signal generated by the analog signal generation source 111 and output it to a digital circuit 120.

[0100] On the other hand, the AD conversion period of the AD conversion circuit 112 during CDS operation is set based on an AD conversion start signal. For example, when the AD conversion start signal is at a low level, the AD conversion of the P phase and D phase of the AD conversion circuit 112 can be set to inactive, and when the AD conversion start signal is at a high level, the AD conversion of the P phase and D phase of the AD conversion circuit 112 can be set to active.

[0101] The current monitor circuit 121 monitors the current flowing through the semiconductor chip 300 on the semiconductor chip 300. The monitoring result of the current monitored by the current monitor circuit 121 is input to the current waveform recognition circuit 122. At this time, the current waveform recognition circuit 122 can detect the flat portion of the current waveform ME.

[0102] The digital timing adjustment circuit 123 adjusts the rising timing of the digital circuit activation signal and the sub-circuit activation signal ACK based on the waveform ME of the current flowing through the semiconductor chip 300 recognized by the current waveform recognition circuit 122. At this time, it is assumed that the waveform ME during the P-phase AD conversion period and the D-phase AD conversion period cannot be flattened as a result of adjusting the rising timing of the digital circuit activation signal and the sub-circuit activation signal ACK. At this time, if the P-phase AD conversion period and the D-phase AD conversion period are set in the non-flat portion of the waveform ME, there is a risk that switching noise of the digital circuit 320 will affect the AD conversion.

[0103] FIG. 21 is a diagram showing a method for setting the current consumption timing according to the fourth embodiment.

[0104] In the figure, after the digital timing adjustment circuit 123 adjusts the timing of the digital circuit 320, the current consumption control circuit 301 detects the slope of the waveform MF during the P-phase AD conversion period and the D-phase AD conversion period. The current consumption control circuit 301 controls the current consumption circuit 302 so that a current FI is consumed during the P-phase AD conversion period and the D-phase AD conversion period. The current consumption control circuit 301 recognizes whether the slopes of the waveform MF during the P-phase AD conversion period and the D-phase AD conversion period match, based on the waveform MF of the current flowing through the semiconductor chip 300 recognized by the current waveform recognition circuit 122. The current consumption control circuit 301 can then adjust the current FI during the D-phase AD conversion period so that the slopes of the waveform MF during the P-phase AD conversion period and the D-phase AD conversion period match.

[0105] Here, when the slopes of the waveforms MF during the P-phase AD conversion period and the D-phase AD conversion period match, the same switching noise is superimposed on the P-phase analog signal and the D-phase analog signal generated by the analog signal generation source 111. Therefore, by digitizing the difference between the P-phase analog signal and the D-phase analog signal, the switching noise superimposed on the P-phase analog signal and the D-phase analog signal can be canceled.

[0106] FIG. 22 is a flowchart showing a method for changing the activation timing of a digital circuit according to the fourth embodiment.

[0107] In the figure, a digital circuit 320 performs the same processing as that in the third embodiment described above (S101 to S105).

[0108] Next, if there is a change in the current flowing through the semiconductor chip 300 during AD conversion by the AD conversion circuit 112, the current consumption control circuit 301 determines whether the changes in the current flowing through the semiconductor chip 300 during the P-phase AD conversion period and the D-phase AD conversion period during CDS operation are the same (S201). If the changes in the current flowing through the semiconductor chip 300 during the P-phase AD conversion period and the D-phase AD conversion period during CDS operation are the same, the process ends. On the other hand, if the changes in the current flowing through the semiconductor chip 300 during the P-phase AD conversion period and the D-phase AD conversion period during CDS operation are not the same, the current consumption control circuit 301 controls the current consumption supplied from the current consumption circuit 302 (S202) and returns the process to S101.

[0109] In this way, in the fourth embodiment described above, the operation timing and current consumption timing of the analog circuit 110 or the digital circuit 320 during CDS operation are adjusted based on the waveform of the current flowing through the semiconductor chip 300. This makes it possible to reduce the influence of switching noise generated in the digital circuit during CDS circuit operation, even when it is difficult to flatten the waveform of the current flowing through the semiconductor chip 300.

[0110] 5. Fifth Embodiment In the second embodiment described above, the operation timing of the analog circuit 110 or the digital circuit 220 is automatically adjusted based on the waveform of the current flowing through the semiconductor chip 200. In this fifth embodiment, based on the waveform of the current flowing through the semiconductor chip 200, a voltage corresponding to the frequency component of the current is monitored.

[0111] Fig. 23 is a diagram showing a voltage monitoring method for a semiconductor chip on which an electronic circuit according to the fifth embodiment is formed, and Fig. 24 is a diagram showing the relationship between frequency and impedance of the electronic circuit according to the fifth embodiment. Note that Fig. 23 shows an equivalent power supply system for a digital circuit 220.

[0112] 23, a current source G is connected between a power supply potential VDD and a ground potential GND of a digital circuit 220, and a series circuit of a capacitor C11 and a resistor R11 is connected in parallel to the current source G. The power supply potential VDD is connected to the ground potential GND via a series circuit of a resistor R12 and an inductor L11.

[0113] In this case, the voltage V(t) between the terminals generated by the frequency component of the current I(t) flowing through the digital circuit 220 can be given by the following equations: V(t)=R·I(t) V(t)=L·d / dtI(t) V(t)=1 / C·∫I(t)dt

[0114] where R is the resistance component of the loop impedance of the digital circuit 220, L is the inductance component of the loop impedance of the digital circuit 220, and C is the capacitance component of the loop impedance of the digital circuit 220. At this time, as shown in Figure 24, the voltage V(t) is determined by the frequency of the current I(t), the resistance component R, the inductance component L, and the capacitance component C. Note that the resistance component R and the inductance component L are parasitic resistance and parasitic inductance components generated by the power supply wiring and ground wiring of the package, board, etc. outside the semiconductor chip 200, and are the sum of the power supply component and the ground component. The capacitance component C is a stabilizing capacitance connected between the power supply and ground of the digital circuit 220.

[0115] In this way, in the fifth embodiment described above, a voltage corresponding to the frequency component of a current is monitored based on the waveform of the current flowing through the semiconductor chip 200. This makes it possible to improve the detection accuracy of switching noise of the digital circuit 220 while eliminating the need to detect the current flowing through the semiconductor chip 200.

[0116] 6. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0117] FIG. 25 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0118] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 25, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0119] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0120] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0121] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0122] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0123] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0124] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0125] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0126] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0127] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 25, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0128] FIG. 26 is a diagram showing an example of the installation position of the imaging unit 12031.

[0129] In FIG. 26, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0130] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0131] 26 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0132] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0133] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0134] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0135] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0136] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the drivetrain control unit 12010, the body system control unit 12020, the outside vehicle information detection unit 12030, the inside vehicle information detection unit 12040, the integrated control unit 12050, and the imaging unit 12031 among the above-described configurations. Specifically, for example, the semiconductor chips according to the first to fifth embodiments described above can be applied to the drivetrain control unit 12010, the body system control unit 12020, the outside vehicle information detection unit 12030, the inside vehicle information detection unit 12040, the integrated control unit 12050, and the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to integrate analog circuits and digital circuits on a semiconductor chip while suppressing malfunction of the analog circuits.

[0137] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0138] The present technology may also be configured as follows: (1) An electronic circuit comprising: an analog circuit formed on a semiconductor chip; a digital circuit embedded in the semiconductor chip; a current monitor circuit configured to monitor, on the semiconductor chip, a current flowing through the semiconductor chip; and a timing adjustment circuit configured to adjust operation timing of at least one of the analog circuit or the digital circuit based on the waveform of the current flowing through the semiconductor chip. (2) The electronic circuit according to (1), wherein the analog circuit comprises an AD (Analog to Digital) conversion circuit. (3) The electronic circuit according to (1) or (2), wherein the timing adjustment circuit adjusts operation timing of at least one of the analog circuit or the digital circuit so that the operation period of the analog circuit is set in a flat portion of the waveform of the current flowing through the semiconductor chip. (4) The electronic circuit according to any of (1) to (3), wherein the timing adjustment circuit adjusts operation timing of at least one of the analog circuit or the digital circuit so that the waveform of the current flowing through the semiconductor chip during a CDS (Correlated Double Sampling) operation is equal between a P-phase period and a D-phase period. (5) The electronic circuit according to any one of (1) to (4), further comprising a waveform recognition circuit that recognizes a waveform of a current flowing through the semiconductor chip based on the current monitored by the current monitor circuit, wherein the timing adjustment circuit adjusts the operation timing of at least one of the analog circuit or the digital circuit based on the recognition result of the waveform recognition circuit. (6) The electronic circuit according to any one of (1) to (5), wherein the timing adjustment circuit comprises a register that stores an adjustment value for the operation timing of at least one of the analog circuit or the digital circuit, wherein the adjustment value is set in the register from outside. (7) The electronic circuit according to any one of (1) to (6), further comprising an output interface that digitizes the monitoring result of the current flowing through the semiconductor chip and outputs the digitized result to the outside.(8) The electronic circuit according to any one of (1) to (7), which turns off the timing adjustment circuit and the current monitor circuit after the timing adjustment circuit adjusts the operation timing. (9) The electronic circuit according to any one of (1) to (8), further comprising: a current consumption circuit that consumes a current flowing in the semiconductor chip based on a monitoring result of the current flowing in the semiconductor chip. (10) The electronic circuit according to (9), wherein the current consumption circuit consumes a current flowing in the semiconductor chip so that a waveform of the current flowing in the semiconductor chip is flattened during an operation period of the analog circuit. (11) The electronic circuit according to (9) or (10), which turns off the timing adjustment circuit, the current monitor circuit, and the current consumption circuit after the timing adjustment circuit adjusts the operation timing. (12) The electronic circuit according to any one of (1) to (11), further comprising: a voltage monitor circuit that monitors a voltage corresponding to a frequency component of the current based on the current monitored by the current monitor circuit. (13) An electronic device comprising: a sensor that performs sensing; and an electronic circuit that processes an output from the sensor, wherein the electronic circuit comprises: an AD conversion circuit formed on a semiconductor chip that performs AD conversion of the output from the sensor; a digital circuit integrated on the semiconductor chip; a current monitor circuit that monitors, on the semiconductor chip, a current flowing through the semiconductor chip; and a timing adjustment circuit that adjusts the operation timing of at least one of the AD conversion circuit and the digital circuit based on the waveform of the current flowing through the semiconductor chip.

[0139] 100 Semiconductor chip 110 Analog circuit 111 Analog signal generating source 112 AD conversion circuit 113 AD conversion control circuit 120 Digital circuit 121 Current monitor circuit 122 Current waveform recognition circuit 123 Digital timing adjustment circuit 124 AD conversion timing adjustment circuit 125 Digital processing unit 126 Output interface 123A, 124A Register

Claims

1. An electronic circuit comprising: an analog circuit formed on a semiconductor chip; a digital circuit embedded in the semiconductor chip; a current monitor circuit that monitors the current flowing through the semiconductor chip on the semiconductor chip; and a timing adjustment circuit that adjusts the operation timing of at least one of the analog circuit and the digital circuit based on the waveform of the current flowing through the semiconductor chip.

2. The electronic circuit according to claim 1, wherein the analog circuit comprises an AD (Analog to Digital) conversion circuit.

3. The electronic circuit according to claim 1, wherein the timing adjustment circuit adjusts the operation timing of at least one of the analog circuit and the digital circuit so that the operation period of the analog circuit is set during the flat portion of the waveform of the current flowing through the semiconductor chip.

4. The electronic circuit according to claim 1, wherein the timing adjustment circuit adjusts the operation timing of at least one of the analog circuit and the digital circuit so that the waveform of the current flowing through the semiconductor chip during CDS (Correlated Double Sampling) operation is equal between the P-phase period and the D-phase period.

5. The electronic circuit according to claim 1, further comprising a waveform recognition circuit that recognizes the waveform of the current flowing through the semiconductor chip based on the current monitored by the current monitor circuit, and the timing adjustment circuit adjusts the operation timing of at least one of the analog circuit and the digital circuit based on the recognition result of the waveform recognition circuit.

6. The electronic circuit according to claim 1, wherein the timing adjustment circuit comprises a register that stores an adjustment value for the operation timing of at least one of the analog circuit and the digital circuit, and the adjustment value is set in the register from outside.

7. The electronic circuit according to claim 1, further comprising an output interface for digitizing the monitored results of the current flowing through said semiconductor chip and outputting the digital results to the outside.

8. The electronic circuit according to claim 1, wherein the timing adjustment circuit and the current monitor circuit are turned off after the operation timing is adjusted by the timing adjustment circuit.

9. The electronic circuit according to claim 1, further comprising a current consumption circuit that consumes the current flowing through said semiconductor chip based on the results of monitoring the current flowing through said semiconductor chip.

10. The electronic circuit according to claim 9, wherein the current consumption circuit consumes the current flowing through the semiconductor chip so that the waveform of the current flowing through the semiconductor chip is flattened during the operation of the analog circuit.

11. The electronic circuit according to claim 10, wherein after the operation timing is adjusted by the timing adjustment circuit, the timing adjustment circuit, the current monitor circuit, and the current consumption circuit are turned off.

12. The electronic circuit according to claim 1, wherein a voltage corresponding to a frequency component of the current is monitored based on the current monitored by the current monitor circuit.

13. An electronic device comprising: a sensor that performs sensing; and an electronic circuit that processes output from the sensor, wherein the electronic circuit comprises: an AD conversion circuit formed on a semiconductor chip that performs AD conversion of the output from the sensor; a digital circuit embedded in the semiconductor chip; a current monitor circuit that monitors, on the semiconductor chip, the current flowing through the semiconductor chip; and a timing adjustment circuit that adjusts the operation timing of at least one of the AD conversion circuit or the digital circuit based on the waveform of the current flowing through the semiconductor chip.

Images