A / d converter and a / d conversion method

Abstract

A control unit (CNTL) controls a plurality of switches (SW0 to SW7) to sample an analog signal to a lower-side common terminal (LCT) and an upper-side common terminal (UCT) and then performs binary search, and a comparator (CMP) outputs an A / D conversion result, whereby A / D conversion is performed. The control unit (CNTL) controls the capacitance value of a variable capacitance (CC) so that the output count of A / D conversion results of which the lower bits are all 1s and the output count of A / D conversion results of which the lower bits are all 0s are the same. When the lower bits of the A / D conversion results are all 1s or all 0s, the control unit (CNTL) applies a voltage corresponding to the least significant bit or a negative number thereof as an offset to the sampled analog signal every other time from the next A / D conversion, subtracts a digital value corresponding to the applied offset from the A / D conversion result, and outputs the result as a digital signal.

Description

A / D converter and A / D conversion method

[0001] The present disclosure relates to an A / D converter and an A / D conversion method.

[0002] In recent years, particularly in CMOS process nodes of 0.18 μm and below, short channel effects have worsened saturation region characteristics (VDS-IDS characteristics) and lowered power supply voltages. These are adverse effects for the design of analog circuits such as amplifiers. This impact is particularly significant in pipelined A / D converters that rely on amplification by amplifier circuits.

[0003] In contrast, successive approximation register analog-to-digital converters (SAR ADCs) do not require amplifiers and can be designed with comparators consisting of switches and strong-arm latches. This results in a circuit configuration that is closer to the operation of digital circuits. As a result, they can benefit from miniaturization processes, giving them an advantage in terms of power efficiency.

[0004] Charge redistribution capacitive D / A converters (hereafter referred to as CDACs) contribute to improving the power efficiency of SAR ADCs. However, because CDACs are basically composed of capacitance elements weighted by a power of 2 (2N), the area required increases exponentially as the resolution improves. To address this area issue, a bridge capacitance C Ｂ A Split-CDAC has been proposed, which combines two CDACs into one CDAC (see, for example, Non-Patent Document 1). For example, in the case of 8-bit resolution, a normal CDAC requires 256C if the capacitance value of the unit capacitance is C. On the other hand, if the Split-CDAC is configured with 4 bits on the upper side and 4 bits on the lower side, it requires 15C + 16C + C. Ｂ = 31C + C Ｂ Therefore, the unit capacity can be reduced to about 1 / 8.

[0005] In analog circuits, relative accuracy is generally obtained by the ratio of the number of identical physical patterns implemented. However, when elements with a non-integer ratio that cannot be expressed by the ratio of the number of implementation patterns at the time of element implementation are implemented, it is difficult to obtain accuracy. Also, the C corresponding to the lower bits of the A / D converter Ｂ C Ｂ The capacitance value of this C Ｂ The differential non-linearity error (DNL) occurs due to the difference between the theoretical value of the capacitance and the capacitance value including the parasitic capacitance. Ｃ It has been proposed to compensate for the error between the upper CDAC and the lower CDAC by adjusting the capacitance value of the upper CDAC and the lower CDAC (see, for example, Non-Patent Document 2).

[0006] Institute of Electronics, Information and Communication Engineers, "Knowledge Base: A / D Converters", X. Zhu et al., "A 9-bit 100MS / s SAR ADC with Digitally Assisted Background Calibration", IEICE Tran. on Electronics 2012, E95 C.

[0007] Bridge capacitance C Ｂ is connected between the upper CDAC and the lower CDAC, so when a carry occurs from the lower bit to the upper bit, C Ｂ affects the linearity of the A / D conversion. Ｂ To the extent that this affects linearity, the analog signal must be uniformly distributed and not a "DC" voltage.

[0008] However, for example, Non-Patent Document 2 employs a method called Tri-Level CDAC with 9 bits D8 to D0, which causes missing codes or wide codes at "31" to "32," "63" to "64," "95" to "96," ... "479" to "480," where a carry occurs from the lower to higher bits of the 512 gradations, impairing the linearity of the A / D conversion (see Figures 3 and 4 in Non-Patent Document 2). For example, if a "DC" voltage equivalent to "31" is continuously applied, the device will not function properly.

[0009] Specifically, the output frequency at which the A / D conversion result (output code) becomes "31" is defined as P ３１ , the output frequency that becomes "30" is P ３０ Then, C Ｂ >P in the case of optimal value ３１ <P ３０ In the method of Non-Patent Document 2, this is detected and C Ｃ Enlarge C Ｂ By making it appear smaller, P ３１ =P ３０ For example, when a DC voltage equivalent to "31" is applied, P ３１ >P ３０ This is detected as ３１ C until C = 0 Ｂ To make it look smaller, Ｃ As a result, a "chord drop" occurs where "31" is not output. Ｂ When a "DC" voltage in a range that affects linearity error is input, a corresponding digital signal is not output correctly, resulting in a problem with the linearity of the A / D conversion.

[0010] The present disclosure has been made to solve the above-mentioned problems, and its object is to provide an A / D converter and an A / D conversion method that can improve the linearity of A / D conversion.

[0011] The A / D converter according to the present disclosure includes an input terminal to which an analog signal is input, a plurality of lower-side capacitors each having a capacitance value weighted by a binary ratio and one end connected in parallel to a lower-side common terminal, a plurality of upper-side capacitors each having a capacitance value weighted by a binary ratio and one end connected in parallel to an upper-side common terminal, a bridge capacitor connected between the lower-side common terminal and the upper-side common terminal, a plurality of switches connecting the other ends of the plurality of lower-side capacitors and the other ends of the plurality of upper-side capacitors to the input terminal, a reference voltage terminal, or a ground terminal, respectively, a comparator that compares a voltage of the upper-side common terminal with a reference voltage and outputs an A / D conversion result, a variable capacitor connected between the lower-side common terminal and the ground terminal, and a control unit that controls switching of the plurality of switches and the capacitance values ​​of the variable capacitors, A control unit controls the plurality of switches to sample the analog signal to the lower common terminal and the upper common terminal, and then performs a binary search, and the comparator outputs the A / D conversion result, thereby performing A / D conversion; the control unit controls the capacitance value of the variable capacitor so that the output frequency of the A / D conversion result whose lower bits are all 1 is the same as the output frequency of the A / D conversion result whose lower bits are all 0; when the lower bits of the A / D conversion result are all 1 or all 0, the control unit applies a voltage equivalent to the least significant bit or its negative to the sampled analog signal as an offset every other A / D conversion from the next A / D conversion, and subtracts a digital value equivalent to the applied offset from the A / D conversion result to output the result as a digital signal.

[0012] The present disclosure can improve the linearity of A / D conversion.

[0013] It is a diagram showing an optical transmission system according to an embodiment. It is a circuit diagram showing an A / D converter according to an embodiment. It is a timing chart of the A / D converter according to an embodiment. It is a flowchart of the operation of the A / D converter according to an embodiment.

[0014] 1 is a diagram showing an optical transmission system according to an embodiment of the present invention, which includes a transmission signal processing circuit 1, a transmission optical module 2, a reception optical module 3, and a reception signal processing circuit 4. The transmission optical module 2 and the reception optical module 3 are connected by an optical fiber 5.

[0015] The transmission signal input to the transmission signal processing circuit 1 undergoes preliminary waveform compensation processing and error correction coding in the transmission digital signal processing circuit 6. The D / A converter 7 converts the output signal of the transmission digital signal processing circuit 6 into an analog electrical signal.

[0016] The transmitting optical module 2 converts the output signal of the D / A converter 7 into an optical signal using a laser diode and transmits it to the receiving side through the optical fiber 5. On the receiving side, the receiving optical module 3 converts the received optical signal into an analog electrical signal. The A / D converter 8 converts the output signal of the receiving optical module 3 into a digital electrical signal. The receiving digital signal processing circuit 9 performs chromatic dispersion compensation, polarization dispersion compensation, error correction, etc. on the output signal of the A / D converter 8.

[0017] 1 shows how transmission data is separated into an X-polarized signal and a Y-polarized signal and transmitted from the transmitting side to the receiving side. However, the present disclosure is not limited to the above configuration and can also be applied to transmission using only one of the polarized waves. In that case, the polarization combining and polarization splitting circuits are not required. Furthermore, the present disclosure is not limited to optical communication shown in FIG. 1 and can also be applied to wireless communication or other types of communication.

[0018] 2 is a circuit diagram showing an A / D converter according to an embodiment. This A / D converter is a successive approximation register A / D converter (SAR ADC) having a charge redistribution type capacitive D / A converter (CDAC). The CDAC connects a 4-bit upper CDAC and a 4-bit lower CDAC via bridge capacitance C Ｂ The "successive approximation type" refers to a method in which a single comparator repeatedly performs magnitude comparisons.

[0019] A plurality of lower side capacitances C ０ ~C ３One end of the lower capacitance C is connected in parallel to the lower common terminal LCT. ０ ~C ３ have capacitance values ​​1C, 2C, 4C, and 8C weighted by a binary ratio (C is a predetermined capacitance value), respectively. ４ ~C ７ One end of the upper capacitance C is connected in parallel to the upper common terminal UCT. ４ ~C ７ have capacitance values ​​1C, 2C, 4C, and 8C weighted by a binary ratio, respectively. Ｂ is connected between the lower common terminal LCT and the upper common terminal UCT. Ｂ The ideal value of is (15 / 16) C, but in reality it has a capacitance value that deviates slightly.

[0020] Multiple switches SW ０ ~SW ７ is the lower capacitance C ０ ~C ３ The other end and the upper capacitance C ４ ~C ７ The other end of each is connected to the input terminal V ｉｎ , reference voltage terminal V ｒｅｆ and the ground terminal GND. ｉｎ An analog signal is input to the reference voltage terminal V ｒｅｆ The reference voltage is applied to the ground terminal GND. The voltage V of the upper common terminal UCT is applied to the negative input of the comparator CMP. ＣＤＡＣ is input to the input terminal of the comparator CMP, and a reference voltage is input to the positive input terminal of the comparator CMP. ＣＤＡＣ is compared with a reference voltage to output the A / D conversion result.

[0021] Variable capacitance C Ｃ is connected between the lower common terminal LCT and the ground terminal GND. Ｎ One end of the offset capacitance C is connected to the lower common terminal LCT. Ｎ has a capacitance value of 1 C corresponding to the least significant bit (LSB) of binary. Ｎ is the offset capacitance CＮ The other end is connected to the reference voltage terminal V ｒｅｆ Or connect it to the ground terminal GND.

[0022] The control unit CNTL receives the control signal D ０ ~D ７ The switches SW ０ ~SW ７ and controls the switching of the control signal Φ Ｓ ' switches SW Ｓ１ , SW Ｓ２ and controls the switching of the control signal D Ｎ The offset switch SW Ｎ The control unit CNTL controls the switching of the control signal D ｃａｌ The variable capacitance C Ｃ The control unit CNTL is realized by a processing circuit such as a system LSI, but if the processing speed is low, it can also be realized by a CPU that executes a program stored in memory.

[0023] Next, the operation of the A / D converter according to the embodiment will be described. Fig. 3 is a timing chart of the A / D converter according to the embodiment. Fig. 4 is a flowchart of the operation of the A / D converter according to the embodiment.

[0024] First, the control unit CNTL receives a control signal Φ Ｓ ' to "H" and switch SW Ｓ１ , SW Ｓ２ is turned on to connect the lower common terminal LCT and the upper common terminal UCT to the reference voltage, and the control signal D Ｎ The offset switch SW Ｎ to the ground terminal GND (step S1). Next, the control unit CNTL turns on the switch SW ７ ~SW ０ to the input terminal V ｉｎ This connects the capacitance C ７ ~C ０ Next, the control unit CNTL applies an analog signal to the switch SW Ｓ１ , SW Ｓ２ When the switch SW is turned off, the analog signal is sampled at the lower common terminal LCT and the upper common terminal UCT (step S2).７ ~SW ０ is connected to the ground terminal GND, and the control signal D Ｎ The offset switch SW Ｎ Reference voltage terminal V ｒｅｆ (Step S3). Next, the control unit CNTL connects the switch SW ７ ~SW ０ In turn, the reference voltage terminal V ｒｅｆ , and performs a binary search in order from the most significant bit (step S4), and the comparator CMP outputs the A / D conversion result (output code) (step S5). ７ ~SW ０ is controlled to sample the analog signals at the lower common terminal LCT and the upper common terminal UCT, a binary search is performed, and the comparator CMP outputs the A / D conversion result, thereby performing A / D conversion.

[0025] Here, the bridge capacitance C Ｂ is connected between the fourth and fifth bits from the bottom of the CDAC. Therefore, when a carry occurs from the fourth bit from the bottom to the fifth bit, the bridge capacitance C Ｂ For example, the lower four bits of "15" are "1111" and the lower four bits of "16" are "0000", so when the analog signal is a voltage equivalent to "15" to "16", C Ｂ affects linearity.

[0026] Therefore, the control unit CNTL detects whether the A / D conversion result is "15" or "16" (step S6). If the result is not "15" or "16", the bridge capacitance C Ｂ does not affect the linearity, the control section CNTL is Ｃ The control loop of (2) is not executed, and the process returns to step S2 to sample the next analog signal.

[0027] When the control unit CNTL detects that the A / D conversion result is "15" or "16", the variable capacitance C Ｃ The control circuit CNTL starts a control loop of the output frequency P at which the A / D conversion result of the comparator CMP becomes "15". １５, the output frequency P １６ (Step S7). When the analog signal is uniformly distributed in the voltage range corresponding to "15" to "16", the bridge capacitance C Ｂ If C is the ideal value (15 / 16), then P １５ =P １６ Therefore, the control unit CNTL １５ or P １６ The A / D conversion is repeated until P is counted 511 times (step S8). １５ =P １６ The variable capacitance C Ｃ (Step S9). For example, １６ <P １５ In the case of C Ｂ < (15 / 16)C, so P １５ When the count reaches 511, the variable capacitance C Ｃ By reducing the capacitance value of Ｂ On the other hand, P １６ >P １５ In the case of C Ｂ >(15 / 16)C, so P １６ When the count reaches 511, the variable capacitance C Ｃ Increase the capacitance value of the bridge capacitance C Ｂ This makes the bridge capacitance C Ｂ The error from the ideal capacitance value (15 / 16)C is the variable capacitance C Ｃ Then, the capacitance value of P １５ and P １６ The count of the variable capacitance C is reset (step S10). Note that, since it is probabilistic whether the A / D conversion result will be "15" or "16", one determination result is not enough to reset the count of the variable capacitance C Ｃ Therefore, as described above, by collecting multiple judgment results and using a statistical method (actually majority vote), the capacitance value of the variable capacitance C Ｃ The capacitance value of the capacitor is controlled.

[0028] However, if the output frequency of "15" and "16" is not uniform and there is a bias, for example, if a DC voltage equivalent to "15" or a sine wave with an upper limit of "15" is input as an analog signal, the variable capacitance C Ｃ Adjusting the capacitance value results in a worsening of differential nonlinearity between "15" and "16." Therefore, for the control loop to function properly, the analog signal must be uniformly distributed within that range, rather than being a "DC" voltage. Therefore, in this embodiment, if the lower-order bits of the A / D conversion result are all 1s or all 0s ("15" or "16"), a voltage equivalent to the least significant bit or its negative value (+1 LSB or -1 LSB) is applied as an offset to the sampled analog signal every other A / D conversion from the next A / D conversion onwards.

[0029] Specifically, when the lower 4 bits of the A / D conversion result are "1111", the control unit CNTL detects that the least significant bit is "1" and turns on the offset switch SW Ｎ is switched to the ground terminal GND (step S11), and the next analog signal is sampled (step S12). Ｎ Reference voltage terminal V ｒｅｆ (Step S13). As a result, a voltage equivalent to the least significant bit (+1 LSB) is applied as an offset to the analog signal sampled by the CDAC. The comparator CMP A / D converts the analog signal Vin' after the offset is applied (Step S14). Therefore, the A / D conversion result becomes "16". The control unit CNTL １６ The A / D conversion result is counted up, and "1" is subtracted from the A / D conversion result to output "15" as the final digital signal (step S15). After that, the process returns to step S2, and in the next A / D conversion, an offset is not added to the analog signal.

[0030] On the other hand, if the lower 4 bits of the A / D conversion result are "0000", the control unit CNTL detects that the least significant bit is "0" and turns off the offset switch SW Ｎ Reference voltage terminal V ｒｅｆ During binary search, the offset switch SWＮ is connected to the ground terminal GND. As a result, a negative voltage (-1LSB) equivalent to the least significant bit is applied as an offset to the analog signal sampled by the CDAC. As a result, the A / D conversion result of the comparator CMP becomes "15", and the control unit CNTL １５ The process counts up, adds "1" to the A / D conversion result, and outputs "16" as the final digital signal. After that, the process returns to step S2, and in the next A / D conversion, the A / D conversion is performed without adding an offset to the analog signal.

[0031] Since the offset is applied according to the least significant bit of the A / D conversion result, the offset is applied even if the next analog signal is not a voltage corresponding to "15" or "16". However, since the A / D conversion result is not "16" or "15", the control unit CNTL １５ or P １６ Therefore, the variable capacitance C Ｃ This does not affect the adjustment of

[0032] In addition, the control unit CNTL subtracts a digital value ("+1" or "-1") corresponding to the applied offset (+1LSB or -1LSB) from the A / D conversion result of the comparator CMP to generate the final digital signal D ｏｕｔ This allows a correct A / D conversion result that does not include an offset to be obtained.

[0033] As an example, a case will be described where a voltage equivalent to "14" to "15" is input as an analog signal. If the least significant bit of the output of the comparator CMP is "0", it is determined to be "14", and if the least significant bit is "1", it is determined to be "15". If the output code of the comparator CMP is "15", +1 LSB is applied to the next analog signal. As a result, the output code of the comparator CMP becomes "16", but the control unit CNTL subtracts "1" and outputs "15" as the final digital signal.

[0034] Next, a case will be described where a voltage equivalent to "16" to "17" is input as an analog signal. If the least significant bit of the output of the comparator CMP is "0", it is determined to be "16", and if the least significant bit is "1", it is determined to be "17". If the output code of the comparator CMP is "16", -1LSB is applied to the next analog signal. As a result, the output code of the comparator CMP becomes "15", but the control unit CNTL adds "1" to it and outputs "16" as the final digital signal.

[0035] Here, an analog signal that is judged to be a "1" digital value has a voltage range equivalent to the least significant bit of "1," from the upper limit to the lower limit. For this reason, for example, if an analog signal close to the upper limit of "1" is input, subtracting the voltage equivalent to the least significant bit from it results in a voltage close to the upper limit of "0." When thermal noise is added to this, it is not necessarily judged to be a "0."

[0036] The voltage corresponding to the least significant bit is the offset capacitance C Ｎ When the conversion voltage range of an 8-bit A / D converter is 1V and the input capacitance of the CDAC is 4.1fF, the voltage corresponding to the least significant bit is 1 / (2 ８ -1) ≒ 4 mV. On the other hand, the thermal noise V ｎ is generally V ｎ ２ = kT / C, where k is the Boltzmann constant, and k = 1.380649 × 10 －２３ JK －１ For example, if C = 4.1 fF, then V ｎ = about 1 mV. Therefore, the voltage corresponding to the least significant bit has a high proportion of thermal noise, 1 / 4, which corresponds to 2σ. For this reason, even if the analog signal is at a voltage corresponding to the center of adjacent decision points, the decision of the least significant bit being "1" or "0" will be incorrect with a probability of about 5%. Therefore, even when a voltage corresponding to the least significant bit is applied, A / D conversion will be performed as if a fluctuating signal, rather than a constant voltage, was input as an offset.

[0037] As explained above, the bridge capacitance C ＢIn order to compensate for the error from the ideal capacitance value, the output frequency P of the A / D conversion result "15" in which the lower bits are all 1 is １５ and the output frequency P of the A / D conversion result "16" where the lower bits are all 0. １６ The variable capacitance C Ｃ However, when a DC voltage corresponding to "15" or "16" is input, the A / D conversion result is biased towards either "15" or "16". Ｃ Therefore, in this embodiment, when the lower bits of the A / D conversion result are all 1 or all 0 (when it is "15" or "16"), a voltage equivalent to the least significant bit or its negative value (+1LSB or -1LSB) is applied as an offset to the sampled analog signal every other A / D conversion from the next A / D conversion. This causes the sampled analog signal to vary uniformly within the voltage range equivalent to "15" to "16", and the variable capacitance C Ｃ As a result, a digital signal corresponding to an input analog signal is correctly output without generating missing codes or wide codes, and the linearity of A / D conversion can be improved.

[0038] Furthermore, if the offset has periodicity, spurious (unwanted frequency components) will occur at the corresponding frequency. To prevent this, if random numbers are generated using a random number generating circuit such as PN (Pseudo Random Noise), the circuit size will increase, resulting in higher costs. In contrast, in this embodiment, an offset capacitance C Ｎ Using this, a voltage equivalent to the least significant bit or its negative value is applied to the analog signal as an offset. Since the voltage equivalent to the least significant bit is highly dominated by thermal noise, it behaves as a non-periodic random number that follows a Gaussian distribution. This makes it possible to prevent spurious signals from occurring without using a random number generation circuit. Since a random number generation circuit is not required, costs can be reduced.

[0039] C ０ ~C ３ Lower capacitance, C ４ ~C ７Upper side capacity, C Ｂ Bridge capacitance, C Ｃ Variable capacitance, C Ｎ Offset capacitance, CMP comparator, CNTL control section, GND ground terminal, LCT lower common terminal, SW ０ ~SW ７ Switch, SW Ｎ Offset switch, UCT Upper common terminal, V ｉｎ Input terminal, V ｒｅｆ Reference Voltage Terminal

Claims

1. An analog signal input device comprising: an input terminal for inputting an analog signal; a plurality of lower side capacitors having capacitance values ​​weighted by a binary ratio and one end connected in parallel to a lower side common terminal; a plurality of upper side capacitors having capacitance values ​​weighted by a binary ratio and one end connected in parallel to an upper side common terminal; a bridge capacitor connected between the lower side common terminal and the upper side common terminal; a plurality of switches connecting the other ends of the plurality of lower side capacitors and the other ends of the plurality of upper side capacitors to the input terminal, a reference voltage terminal, or a ground terminal, respectively; a comparator comparing the voltage of the upper side common terminal with a reference voltage and outputting an A / D conversion result; a variable capacitor connected between the lower side common terminal and the ground terminal; and a control unit controlling the switching of the plurality of switches and the capacitance values ​​of the variable capacitors, wherein the control unit controls the plurality of switches to sample the analog signal to the lower side common terminal and the upper side common terminal, and then performs a binary search, and the comparator outputs the A / D conversion result, thereby performing A / D conversion. the control unit controls the capacitance value of the variable capacitor so that the output frequency of the A / D conversion result whose lower bits are all 1 is the same as the output frequency of the A / D conversion result whose lower bits are all 0; and when the lower bits of the A / D conversion result are all 1 or all 0, the control unit applies a voltage equivalent to the least significant bit or its negative to the sampled analog signal as an offset every other A / D conversion from the next A / D conversion, and subtracts a digital value equivalent to the applied offset from the A / D conversion result to output the result as a digital signal.

2. The A / D converter according to claim 1, characterized in that the control unit applies a voltage equivalent to the least significant bit to the sampled analog signal as the offset when the lower bits of the A / D conversion result are all 1, and applies a negative number of the voltage equivalent to the least significant bit to the sampled analog signal as the offset when the lower bits of the A / D conversion result are all 0.

3. The A / D converter according to claim 2, further comprising: an offset capacitor having a capacitance value corresponding to the least significant bit of binary, one end of which is connected to the lower common terminal; and an offset switch connecting the other end of the offset capacitor to the reference voltage terminal or the ground terminal, wherein the control unit applies the offset to the sampled analog signal by controlling the offset switch.

4. An A / D conversion method using an A / D converter comprising: an input terminal for inputting an analog signal; a plurality of lower-side capacitors having capacitance values ​​weighted by a binary ratio and one end connected in parallel to a lower-side common terminal; a plurality of upper-side capacitors having capacitance values ​​weighted by a binary ratio and one end connected in parallel to an upper-side common terminal; a bridge capacitor connected between the lower-side common terminal and the upper-side common terminal; a plurality of switches connecting the other ends of the plurality of lower-side capacitors and the other ends of the plurality of upper-side capacitors to the input terminal, a reference voltage terminal, or a ground terminal, respectively; a comparator that compares the voltage of the upper-side common terminal with a reference voltage and outputs an A / D conversion result; a variable capacitor connected between the lower-side common terminal and the ground terminal; and a control unit that controls the switching of the plurality of switches and the capacitance values ​​of the variable capacitor, comprising: a step of performing A / D conversion by the control unit controlling the plurality of switches to sample the analog signal to the lower-side common terminal and the upper-side common terminal, and then performing a binary search; an A / D conversion method comprising the steps of: the control unit controlling the capacitance value of the variable capacitor so that the output frequency of the A / D conversion result whose lower bits are all 1 is the same as the output frequency of the A / D conversion result whose lower bits are all 0; and the control unit, when the lower bits of the A / D conversion result are all 1 or all 0, applying a voltage equivalent to the least significant bit or its negative to the sampled analog signal as an offset every other A / D conversion from the next A / D conversion, and subtracting a digital value equivalent to the applied offset from the A / D conversion result to output the result as a digital signal.

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