Structure, quantum processor, quantum computer, and method for manufacturing structure

Abstract

A structure according to the present disclosure comprises a substrate and a first conductor layer. The substrate has a first surface, a second surface opposite to the first surface, and a through hole that penetrates the substrate from the first surface to the second surface. The substrate contains ceramic. The first conductor layer is positioned on the inner circumferential surface of the through hole. The first conductor layer is a superconductor.

Description

Structure, quantum processor, quantum computer, and method for manufacturing structure

[0001] The present disclosure relates to structures, quantum processors, quantum computers, and methods for manufacturing structures.

[0002] 2. Description of the Related Art Conventionally, a through silicon via (TSV) technology has been known as a technology for increasing the integration density of integrated circuits (see, for example, Patent Document 1).

[0003] International Publication No. 2017 / 141547

[0004] The structure of the present disclosure comprises a substrate including ceramic having a first surface, a second surface opposite the first surface, and a through hole extending from the first surface to the second surface; and a first conductor layer that is a superconductor and is located on the inner surface of the through hole.

[0005] The method for manufacturing the structure of the present disclosure includes a preparation step of preparing a ceramic-containing substrate having a through hole, and a film formation step of forming a conductive layer that is a superconductor on the inner surface of the through hole.

[0006] Objects, features, and advantages of the present disclosure will become more apparent from the following detailed description and drawings.

[0023] FIG. 1 is a plan view showing an example of a structure according to an embodiment of the present disclosure.

[0024] FIG. 2 is a cross-sectional view taken along the section line II-II of FIG. 1.

[0025] FIG. 3 is a cross-sectional view showing another example of a structure according to an embodiment of the present disclosure.

[0026] FIG. 4 is a cross-sectional view showing yet another example of a structure according to an embodiment of the present disclosure.

[0027] FIG. 5 is a cross-sectional view showing yet another example of a structure according to an embodiment of the present disclosure.

[0028] FIG. 6 is a graph schematically showing the temperature dependence of electrical resistance of a wiring in which a first conductor layer and a second conductor layer are connected in series, and a wiring consisting of the second conductor layer alone.

[0029] FIG. 7 is a schematic diagram showing a quantum processor and a quantum computer according to an embodiment of the present disclosure.

[0030] FIG. 8 is a diagram illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.

[0031] FIG. 9 is a diagram illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.

[0032] FIG. 10 is a diagram illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.

[0007] In recent years, various superconducting quantum computers (hereinafter also referred to as quantum computers) using superconducting quantum bits (hereinafter also referred to as quantum bits) have been proposed. To improve the computational power of quantum computers, high integration of quantum bits is required. From the viewpoint of high integration of quantum bits, high integration of quantum bits can be achieved by applying TSV technology, which forms through electrodes in a silicon substrate and performs three-dimensional wiring, to a structure equipped with a superconducting quantum bit circuit (hereinafter also referred to as quantum bit circuit).

[0008] In order to further improve the computational power of quantum computers, it is necessary to increase the coherence time of quantum bits.

[0009] Hereinafter, structures, quantum processors, quantum computers, and methods for manufacturing structures according to embodiments of the present disclosure will be described with reference to the drawings. The drawings referred to below are schematic, and the dimensional ratios and the like in the drawings do not necessarily correspond to the actual ones. In this specification, for convenience, a Cartesian coordinate system XYZ is defined in some of the drawings. The X-axis and Y-axis indicate mutually orthogonal planar directions, and the Z-axis indicates the thickness (height) direction. In this specification, the positive direction of the Z-axis is defined as upward, and terms such as upper end and lower end may be used.

[0010] FIG. 1 is a plan view showing an example of a structure according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along the cutting line II-II in FIG. 1. FIG. 3 is a cross-sectional view showing another example of a structure according to an embodiment of the present disclosure. FIGS. 4 and 5 are cross-sectional views showing yet another example of a structure according to an embodiment of the present disclosure. FIG. 6 is a graph schematically showing the temperature dependence of the electrical resistance of a wiring in which a first conductor layer and a second conductor layer are connected in series, and a wiring consisting of the second conductor layer alone. The cross-sectional views shown in FIGS. 3 to 5 correspond to the cross-sectional view shown in FIG. 2.

[0011] 1 and 2, the structure 1 of this embodiment includes a substrate 2 and a first conductive layer 4. The structure 1 may include a quantum bit circuit. The structure 1 may constitute a part of a superconducting quantum processor (hereinafter also referred to as a quantum processor). A quantum processor including the structure 1 may be used in an environment cooled to a low temperature of, for example, about 10 mK.

[0012] The substrate 2 has a first surface 2a and a second surface 2b opposite to the first surface 2a. The first surface 2a and the second surface 2b may be parallel or approximately parallel. In a plan view, the substrate 2 may have, for example, a polygonal, circular, elliptical, or other shape. Examples of polygonal shapes include triangular, rectangular, pentagonal, and hexagonal shapes. The substrate 2 may have a thickness T2 of 100 to 500 μm, or may have a thickness T2 of approximately 300 μm.

[0013] The substrate 2 may be a ceramic substrate containing a ceramic material. The substrate 2 may be a single crystal sapphire (Al ２ O ３ The substrate 2 is not limited to a sapphire substrate, but may be a ceramic substrate containing a ceramic material such as aluminum oxide, mullite, silicon carbide, aluminum nitride, or magnesium oxide. The ceramic material does not need to be a crystalline material, and may be glass or a mixed material of crystal and glass.

[0014] The substrate 2 has a through-hole 3 penetrating from the first surface 2a to the second surface 2b. The through-hole 3 has a first opening 3a on the first surface 2a and a second opening 3b on the second surface 2b. Hereinafter, when there is no need to distinguish between the first opening 3a and the second opening 3b, they may be referred to as openings 3a and 3b. A quantum bit circuit may be located on the first surface 2a. A conductive layer (a second conductive layer 5 described later) electrically connected to the quantum bit circuit may be located around the second opening 3b on the second surface 2b.

[0015] The openings 3a and 3b may have, for example, a circular, elliptical, or oval shape in a plan view, or other shapes. Hereinafter, it is assumed that the first opening 3a and the second opening 3b have a circular shape in a plan view. The opening diameter da of the first opening 3a and the opening diameter db of the second opening 3b may be the same or different. Note that if the first opening 3a has a shape other than a circle, the opening diameter da of the first opening 3a may be the circle-equivalent diameter of the first opening 3a. If the second opening 3b has a shape other than a circle, the opening diameter db of the second opening 3b may be the circle-equivalent diameter of the second opening 3b.

[0016] The through hole 3 may have a configuration in which the opening shape when viewed in a cross section parallel to the first surface 2 a is similar to the planar shapes of the first opening 3 a and the second opening 3 b. As shown in Fig. 2, the through hole 3 may have a shape in which the opening diameter (also referred to as the inner diameter or the diameter) d when viewed in a cross section parallel to the first surface 2 a is constant or approximately constant in the thickness direction of the substrate 2 (hereinafter also referred to as a straight shape).

[0017] The opening diameter d of the through hole 3 does not have to be constant in the thickness direction of the substrate 2. As shown in Fig. 3, the through hole 3 may have a shape in which the opening diameter d gradually increases or decreases in the thickness direction of the substrate 2 (hereinafter also referred to as a tapered shape). Fig. 3 shows an example in which the opening diameter d of the through hole 3 gradually decreases from the first opening 3a to the second opening 3b, but the opening diameter d of the through hole 3 may also gradually increase from the first opening 3a to the second opening 3b. The larger of the opening diameters da and db may be more than 1 time the smaller of the opening diameters da and db, and may be 3 times or less, 2 times or less, or 1.5 times or less.

[0018] As shown in FIG. 4 , the through hole 3 may have a narrowed portion 3d located between the first opening 3a and the second opening 3b. The narrowed portion 3d is the portion of the through hole 3 where the opening diameter d is smallest, and the opening diameter dd of the narrowed portion 3d is smaller than the opening diameters da and db. The narrowed portion 3d may be located, for example, at a depth from the first opening 3a of approximately 0.3×T2 to 0.7×T2, or may be located at a depth of approximately 0.5×T2. The opening diameter dd of the narrowed portion 3d may be approximately 0.5 to 0.9 times the opening diameter da of the first opening 3a and approximately 0.5 to 0.9 times the opening diameter db of the second opening 3b.

[0019] 5, the through hole 3 may have a shape in which the opening diameter d gradually decreases from the first opening 3a to a predetermined depth, and after the predetermined depth, the opening diameter d remains constant up to the second opening 3b. The predetermined depth may be, for example, approximately 0.3×T2 to 0.7×T2, or may be approximately 0.5×T2. The through hole 3 may have a shape in which the opening diameter d gradually decreases from the first opening 3a to a predetermined depth, and after the predetermined depth, the opening diameter d remains constant up to the second opening 3b.

[0020] The through holes 3 may have an aspect ratio of 5 or greater, or may have an aspect ratio of 7 or greater. The aspect ratio of the through holes 3 may be, for example, a value obtained by dividing the thickness T2 of the substrate 2 by the larger of the opening diameters da and db, or a value obtained by dividing the thickness T2 of the substrate 2 by the maximum value of the opening diameters d. When the aspect ratio of the through holes 3 is 5 or greater, the number of through holes 3 per unit area of ​​the first surface 2a can be increased, thereby enabling high integration of quantum bits.

[0021] The first conductor layer 4 is located on the inner circumferential surface 3c of the through hole 3. The first conductor layer 4 is located from the first opening 3a to the second opening 3b. The first conductor layer 4 can electrically connect the quantum bit circuit located on the first surface 2a to the second conductor layer 5 (described later) located on the second surface 2b. Connecting the quantum bit circuit and the second conductor layer 5 located on the second surface 2b with the first conductor layer 4 extending in the thickness direction of the substrate 2 allows for high integration of quantum bits. The first conductor layer 4 may be located so as to cover the entire inner circumferential surface 3c. In this case, the quantum bit circuit and the second conductor layer 5 located on the second surface 2b can be electrically connected well, thereby stabilizing the operation of the quantum processor. Although Figures 1 to 5 show an example in which the substrate 2 has a single through hole 3 and the first conductive layer 4 is located on the inner surface 3c of the through hole 3, the structure 1 may have a configuration in which the substrate 2 has multiple through holes 3 and the first conductive layer 4 is located on the inner surface 3c of each through hole 3.

[0022] The first conductive layer 4 is made of a superconductor. The first conductive layer 4 may be made of a superconductor containing a nitride, such as titanium nitride (TiN) or niobium nitride (NbN), or may be made of a superconductor not containing a nitride, such as aluminum (Al), tantalum (Ta), niobium (Nb), tin (Sn), indium (In), molybdenum (Mo), lead (Pb), titanium (Ti), or niobium titanium (NbTi).

[0023] When the substrate 2 is a sapphire substrate and the first conductive layer 4 is a nitride-containing superconductor (particularly titanium nitride), the dielectric loss at the interface between the substrate 2 and the first conductive layer 4 is small, thereby extending the coherence time of the quantum bit.

[0024] The first conductor layer 4 may have a thickness T4 of 0.1 μm or more and 1.5 μm or less. The thickness T4 of the first conductor layer 4 may be the thickness of the first conductor layer 4 in the plane direction of the first surface 2 a (XY plane direction). The first conductor layer 4 is a through electrode that electrically connects the quantum bit circuit located on the first surface 2 a with the second conductor layer located on the second surface 2 b, and passes a current (hereinafter also referred to as a signal current) indicating a control signal for controlling the quantum bit circuit, a readout signal from the quantum bit circuit, etc. If the thickness T4 of the first conductor layer 4 is less than 0.1 μm, the current density in the first conductor layer 4 is likely to be high, and the critical current density (the maximum value of the current density that can be passed in a superconducting state) J Ｃ When the current density in the first conductive layer 4 exceeds the critical current density J Ｃ If the thickness T4 of the first conductor layer 4 exceeds 1.5 μm, the superconducting state of the first conductor layer 4 will be destroyed, and the quantum processor will be unable to perform quantum computation. Furthermore, if the thickness T4 of the first conductor layer 4 exceeds 1.5 μm, the first conductor layer 4 will be more likely to peel off from the inner circumferential surface 3 c due to residual stress generated when forming the first conductor layer 4. If the first conductor layer 4 peels off from the inner circumferential surface 3 c, the quantum processor may be unable to perform quantum computation. By setting the thickness T4 of the first conductor layer 4 to be 0.1 μm or more and 1.5 μm or less, the risk of the quantum processor being unable to perform quantum computation can be reduced, and the operation of the quantum processor can be stabilized.

[0025] The ratio of the minimum value to the maximum value of the thickness T4 of the first conductor layer 4 may be 57% or more. In this case, fluctuations in the thickness T4 of the first conductor layer 4 in the thickness direction of the substrate 2 (the direction in which the signal current flows) can be suppressed. The current density in the first conductor layer 4 tends to be high in the portion where the thickness T4 of the first conductor layer 4 is smallest, and the critical current density J Ｃ When the current density in the first conductive layer 4 exceeds the critical current density J ＣIf the ratio of the minimum value to the maximum value of the layer thickness T4 is 57% or more, the layer thickness T4 becomes closer to uniformity, and the current density in the first conductive layer 4 reaches the critical current density J Ｃ , making it easier to maintain the superconducting state of the first conductive layer 4. As a result, the coherence time of the quantum bit can be extended, and the operation of the quantum processor can be stabilized.

[0026] The superconducting transition temperature of the first conductive layer 4 may be 4.5 K or higher. ４ When the temperature is higher than 4.2 K, which is the boiling point of liquid helium, the first conductor layer 4 can be put into a superconducting state by cooling with liquid helium. In other words, the quantum processor can be operated by cooling with liquid helium, thereby reducing the running costs of the quantum computer.

[0027] When the first conductive layer 4 is made of titanium nitride, the titanium nitride constituting the first conductive layer 4 may be columnar. In this case, stress caused by the difference in thermal expansion between the substrate 2 and the first conductive layer 4 when cooling the quantum processor can be alleviated, thereby reducing the risk of the first conductive layer 4 peeling off from the inner circumferential surface 3c. Furthermore, when the titanium nitride constituting the first conductive layer 4 is columnar, distortion of the titanium nitride constituting the first conductive layer 4 can be reduced, thereby suppressing deterioration in the crystallinity of the titanium nitride and maintaining good superconducting properties. As a result, the operation of the quantum processor can be stabilized.

[0028] Whether the titanium nitride constituting the first conductor layer 4 is columnar crystals can be determined by observing the cross section of the first conductor layer 4 using a scanning electron microscope (SEM). For example, if the proportion of the region where columnar crystals have grown is 30% or more when observing the cross section of the first conductor layer 4, the titanium nitride constituting the first conductor layer 4 may be determined to be "columnar crystals." A columnar crystal may be, for example, a crystal having an aspect ratio, calculated by dividing the major axis of the crystal by the minor axis of the crystal, of 5 or more. If the proportion of the region where columnar crystals have grown is less than 30% when observing the cross section of the first conductor layer 4, the titanium nitride constituting the first conductor layer 4 may be determined to be "film-like." The cross section to be observed may be a cross section along the plane direction of the first surface 2a of the substrate 2 or a cross section along the thickness direction of the substrate 2. Commercially available image analysis software may be used to observe the cross section of the first conductor layer 4.

[0029] When the first conductor layer 4 is made of titanium nitride, the titanium nitride constituting the first conductor layer 4 may contain oxygen (O) atoms. The titanium nitride constituting the first conductor layer 4 may contain 5 mol % or more of oxygen atoms. In this case, the processability of the first conductor layer 4 against etching such as dry etching and wet etching can be improved. Therefore, it becomes possible to successfully form a wiring pattern constituting a quantum bit circuit on the substrate 2. As a result, the coherence time of the quantum bit can be extended, and the operation of the quantum processor can be stabilized.

[0030] When the first conductor layer 4 is made of titanium nitride, the titanium nitride constituting the first conductor layer 4 may contain carbon (C) atoms. The titanium nitride constituting the first conductor layer 4 may contain 3 mol % or more of carbon atoms. In this case, the processability of the first conductor layer 4 against etching such as dry etching and wet etching can be improved. Therefore, the wiring pattern constituting the quantum bit circuit can be well formed on the substrate 2. As a result, the coherence time of the quantum bit can be extended, and the operation of the quantum processor can be stabilized.

[0031] The first conductor layer 4 can be formed by a thin film formation method such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). When the through hole 3 has a tapered shape (see FIG. 3), raw material gas or vapor containing atoms constituting the first conductor layer 4 can easily enter the through hole 3 and easily reach the center of the through hole 3 (the center in the thickness direction of the substrate 2), which is the most difficult part to form a film, and therefore the layer thickness T4 of the first conductor layer 4 can be made closer to uniform. Therefore, when the current density in the first conductor layer 4 is close to the critical current density J Ｃ , making it easier to maintain the superconducting state of the first conductive layer 4. As a result, the coherence time of the quantum bit can be extended, and the operation of the quantum processor can be stabilized.

[0032] The through hole 3 may have a diameter 30 times or less the thickness T4 of the first conductor layer 4. The diameter of the through hole 3 may be, for example, the larger of the opening diameters da and db, or the average value of the opening diameters d in the thickness direction of the substrate 2. The wiring pattern constituting the quantum bit circuit can be formed using photolithography and etching techniques used in the manufacturing process of semiconductor devices, etc. When forming the wiring pattern using photolithography and etching, it is necessary to fill the through hole 3 with a resin material and then form a resist film on the first surface 2a. When the diameter of the through hole 3 is 30 times or less the thickness T4 of the first conductor layer 4, the volume of the space within the through hole 3, whose inner surface 3c is covered by the first conductor layer 4, is reduced, making it easier to fill the through hole 3 with the resin material. Therefore, the resist film can be formed well, and the wiring pattern constituting the quantum bit circuit can be formed well. As a result, the coherence time of the quantum bit can be extended, and the operation of the quantum processor can be stabilized.

[0033] 1 to 5, the structure 1 may include a second conductive layer 5. The second conductive layer 5 is located on the first surface 2a and the second surface 2b. The second conductive layer 5 located on the first surface 2a may form part of a quantum bit circuit.

[0034] The second conductive layer 5 is made of a superconductor. The second conductive layer 5 may be made of a superconductor containing a nitride, such as titanium nitride or niobium nitride, or may be made of a superconductor not containing a nitride, such as aluminum, tantalum, niobium, tin, indium, molybdenum, lead, titanium, or niobium titanium.

[0035] When the second conductive layer 5 is made of titanium nitride, the titanium nitride constituting the second conductive layer 5 may contain oxygen (O) atoms. The titanium nitride constituting the second conductive layer 5 may contain 5 mol % or more of oxygen atoms. In this case, the processability of the second conductive layer 5 against etching such as dry etching and wet etching can be improved. Therefore, the wiring pattern constituting the quantum bit circuit can be well formed on the substrate 2. As a result, the coherence time of the quantum bit can be extended, and the operation of the quantum processor can be stabilized.

[0036] When the second conductive layer 5 is made of titanium nitride, the titanium nitride constituting the second conductive layer 5 may contain carbon (C) atoms. The titanium nitride constituting the second conductive layer 5 may contain 3 mol % or more of carbon atoms. In this case, the processability of the second conductive layer 5 against etching such as dry etching and wet etching can be improved. Therefore, the wiring pattern constituting the quantum bit circuit can be formed well on the substrate 2. As a result, the coherence time of the quantum bit can be extended, and the operation of the quantum processor can be stabilized.

[0037] The second conductive layer 5 has a thickness T5 in a direction perpendicular to the first surface 2a. The thickness T4 of the first conductive layer 4 may be larger than the thickness T5 of the second conductive layer 5. When the thickness T4 of the first conductive layer 4 is relatively large, the current density of the signal current flowing through the first conductive layer 4 becomes small, and the critical current density J Ｃ As a result, the operation of the quantum processor can be stabilized.

[0038] The second conductive layer 5 may constitute a part of a quantum bit circuit mounted on the structure 1. For example, if the quantum bit circuit mounted on the structure 1 includes a Josephson junction device, the second conductive layer 5 may constitute a part of the Josephson junction device.

[0039] When the second conductive layer 5 is made of titanium nitride, the titanium nitride constituting the second conductive layer 5 may have an orientation degree V of 0.95 or more. The orientation degree V is calculated by calculating the X-ray diffraction intensity of the 111 plane of the titanium nitride constituting the second conductive layer 5 from I １１１ The X-ray diffraction intensity of the 022 plane is I ０２２ When V=I, it is expressed by the following equation (1). １１１ / (I １１１ +I ０２２ ) … (1)

[0040] When the degree of orientation V is 0.95 or more, the titanium nitride constituting the second conductive layer 5 has good crystallinity, and therefore the superconducting transition temperature is higher than that of titanium nitride having a degree of orientation V of less than 0.95. As a result, the coherence time of the quantum bit can be extended, and the operation of the quantum processor can be stabilized.

[0041] 6 schematically shows the temperature dependence of the electrical resistance (solid line) of wiring in which the first conductive layer 4 and the second conductive layer 5 are connected in series, and the temperature dependence of the electrical resistance of the second conductive layer 5 (dashed line). The structure 1 may be configured such that the superconducting transition temperature width W4 of the first conductive layer 4 is wider than the superconducting transition temperature width W5 of the second conductive layer 5. The superconducting transition temperature width W4 of the first conductive layer 4 is the width of a temperature region in which the electrical resistance value of the first conductive layer 4 is less than the electrical resistance value in the normal conductive state and greater than the electrical resistance value in the superconducting state (i.e., "0"). The same applies to the superconducting transition temperature width W5 of the second conductive layer 5.

[0042] Because the first conductive layer 4 is a through electrode through which the signal current of the quantum bit circuit flows, the current flowing through the first conductive layer 4 is greater than the current flowing through the second conductive layer 5, and the first conductive layer 4 is more susceptible to degradation than the second conductive layer 5. If the first conductive layer 4 degrades, the superconducting state of the first conductive layer 4 may be destroyed, potentially making it impossible for the quantum processor to perform quantum computation. If the superconducting transition temperature range W4 of the first conductive layer 4 is wider than the superconducting transition temperature range W5 of the second conductive layer 5, degradation of the first conductive layer 4 can be detected from the measurement results of the electrical resistance value of the wiring in which the second conductive layer 5 and the first conductive layer 4 are connected in series. As a result, the operation of the quantum processor can be stabilized.

[0043] Next, a quantum processor and a quantum computer according to an embodiment of the present disclosure will be described. Fig. 7 is a diagram schematically illustrating a quantum processor and a quantum computer according to an embodiment of the present disclosure.

[0044] The quantum processor 30 of this embodiment is configured to include the above-described structure 1. The quantum processor 30 can extend the coherence time of the quantum bit, thereby improving the computational performance of the quantum computer.

[0045] The quantum computer 50 of the present disclosure is configured to include the quantum processor 30. According to the quantum computer 50, the coherence time of the quantum bits can be extended, thereby improving the computational performance of the quantum computer.

[0046] Next, an example of a method for manufacturing a structure according to an embodiment of the present disclosure will be described. Figures 8 to 10 are views illustrating an example of a method for manufacturing a structure according to an embodiment of the present disclosure.

[0047] The method for manufacturing a structure according to the present disclosure includes a preparation step and a film formation step.

[0048] The preparation step is a step of preparing a substrate 2 having a through hole 3. In the preparation step, first, a substrate precursor 6 (see FIG. 8) that will become the substrate 2 is prepared. The substrate precursor 6 has a first main surface 6a corresponding to the first surface 2a and a second main surface 6b corresponding to the second surface 2b. The substrate precursor 6 may be made of sapphire or a ceramic material. The ceramic material may be, for example, aluminum oxide, mullite, silicon carbide, aluminum nitride, magnesium oxide, or the like. The ceramic material does not need to be a crystalline material and may be glass or a mixed material of crystal and glass.

[0049] Next, through holes (corresponding to the through holes 3) are formed in the substrate precursor 6, penetrating from the first main surface 6a to the second main surface 6b, thereby producing a substrate 2 having the through holes 3 (see FIG. 9). The through holes can be formed by laser processing, in which the substrate precursor 6 is irradiated with laser light. Laser processing can be performed using, for example, a fiber laser, a YAG (Yttrium Aluminum Garnet) laser, an excimer laser, or the like. The power of the laser light may be 0.1 to 1000 W, or may be 1 to 10 W. The frequency of the laser light may be 1 kHz to 100 THz.

[0050] The laser light may be applied from the first main surface 6a side or the second main surface 6b side. By applying the laser light from the first main surface 6a side or the second main surface 6b side, a tapered through hole 3 (see FIG. 3) can be formed. When the thickness of the substrate precursor 6 is thin (for example, 300 μm or less), by applying the laser light from the first main surface 6a side or the second main surface 6b side, a straight through hole 3 (see FIG. 2) with a small change in opening diameter d in the thickness direction of the substrate 2 can be formed.

[0051] The laser beam may be applied from the first main surface 6a side and the second main surface 6b side. For example, the laser beam may be applied from the first main surface 6a side to form a recess on the first main surface 6a side with a depth of about half the thickness of the substrate precursor 6, and then the laser beam may be applied from the second main surface 6b side to form a hole communicating with the recess on the first main surface 6a side. This allows for the formation of a straight through hole 3 (see FIG. 2) with a small change in opening diameter d in the thickness direction of the substrate 2, even when the thickness of the substrate precursor 6 is large (for example, about 300 μm or more). When the laser beam is applied from the second main surface 6b side, the irradiation may be stopped immediately after the hole communicating with the recess on the first main surface 6a side is formed, thereby forming a through hole 3 (see FIG. 4) with a narrowed portion 3c.

[0052] When forming a plurality of through holes 3 in the substrate precursor 6, the interval between adjacent through holes 3 may be equal to or greater than the thickness of the substrate precursor 6. In this case, it becomes easy to form a plurality of through holes 3 while suppressing damage to the substrate precursor 6. Furthermore, the interval between adjacent through holes 3 may be equal to or less than the thickness of the substrate precursor 6. In this case, high integration becomes possible.

[0053] The method for forming the through-holes 3 is not limited to laser processing. The through-holes 3 may be formed by an etching technique such as reactive ion etching (RIE).

[0054] 10 , the film formation step is a step of forming a conductive layer 7 on the inner circumferential surface 3 c of the through hole 3. In the film formation step, the conductive layer 7 (i.e., the first conductive layer 4) located only on the inner circumferential surface 3 c may be formed, or the conductive layer 7 (i.e., the first conductive layer 4 and the second conductive layer 5) located from the inner circumferential surface 3 c to the first surface 2 a and the second surface 2 b may be formed.

[0055] In the film formation step, the conductor layer 7 may be formed by a thin film formation method such as CVD or PVD. The CVD method may be, for example, thermal CVD, plasma CVD, or atomic layer deposition (ALD). The conductor layer may be formed by applying a slurry prepared by adding a solvent, a dispersant, etc. to a powder of a superconductor and sintering the slurry.

[0056] In the film formation step, the conductor layer 7 may be formed by a CVD method. In this case, a high-quality conductor layer 7 can be formed by appropriately selecting the type of source gas, the type of carrier gas, the film formation temperature, the film formation time, and the like.

[0057] When the conductive layer 7 is formed by the CVD method, the substrate 2 is placed in a furnace, and a source gas and a carrier gas are introduced into the furnace to form a thin film of titanium nitride on the surface of the substrate 2. As the source gas, a mixed gas of a titanium-containing gas and a nitrogen-containing gas (hereinafter also referred to as a nitrogen source) is used. The titanium-containing gas is, for example, titanium tetrachloride (TiCl ４ The nitrogen source may be, for example, nitrogen gas (N ２ ), ammonia gas (NH ３ ) or the like. The carrier gas may be, for example, hydrogen gas (H ２ The deposition time may be, for example, about 0.5 to 5 hours, and the pressure inside the furnace may be, for example, about 1 kPa to 15 kPa.

[0058] When the conductive layer 7 is formed by the CVD method, the film formation temperature may be about 650 to 1000° C. This allows the formation of a high-quality conductive layer 7. If the substrate 2 is a silicon (Si) substrate, forming the conductive layer 7 under the same film formation conditions as above may cause a reaction between silicon and titanium nitride, nitridation of silicon, etc., which may lead to a deterioration in the characteristics of the structure.

[0059] In the film formation process, the conductive layer 7 is formed at a film formation temperature of 650° C. or higher, and then nitrogen gas (N ２ ) or hydrogen gas (H ２ By slowly cooling in a nitrogen gas atmosphere, the crystallinity of the titanium nitride constituting the conductor layer 7 can be improved and nitrogen deficiency can be reduced. As a result, a high-quality conductor layer 7 can be formed.

[0060] In the film formation process, nitrogen gas (N ２) may be used, and the film may be formed at a relatively low film formation temperature (approximately 800°C). This reduces the rate at which titanium nitride is produced, and shortens the residence time of the source gas on the first surface 2a and the second surface 2b, resulting in a thinner conductive layer 7 (second conductive layer 5) formed on the first surface 2a and the second surface 2b. Furthermore, since the residence time of the source gas is longer inside the through hole 3, the thickness of the conductive layer 7 (first conductive layer 4) formed on the inner surface 3c of the through hole 3 increases. As a result, the thickness T4 of the first conductive layer 4 can be made thicker than the thickness T5 of the second conductive layer 5.

[0061] In the film formation step, the film formation time may be set to a relatively long time, thereby increasing the thickness T4 of the first conductor layer 4. As a result, the first conductor layer 4 having the thickness T4 of 0.1 μm or more and 1.5 μm or less can be formed.

[0062] In the film formation process, nitrogen gas (N ２ ) and may be deposited at a relatively low deposition temperature (approximately 800°C). This reduces the rate at which titanium nitride is produced, so that the rate is determined not by the supply rate of the source gas but by the rate of the surface reaction on the surface (first surface 2a, second surface 2b, and inner circumferential surface 3c) of the substrate 2. As a result, the thickness of the first conductor layer 4 can be made nearly uniform, and a first conductor layer 4 can be deposited in which the ratio of the minimum value to the maximum value of the layer thickness T4 is 57% or more.

[0063] In the film formation process, nitrogen gas (N ２ ) may be used and the film may be formed at a relatively low film formation temperature (approximately 800°C). This reduces the rate at which titanium nitride is produced. As a result, a high-quality conductor layer 7 (first conductor layer 4) can be formed slowly within the through-hole 3, and the superconducting transition temperature of the first conductor layer 4 can be increased.

[0064] In the film formation process, nitrogen gas (N ２) and may be deposited at a deposition temperature of about 800 to 900° C. This can reduce the rate at which titanium nitride is produced, and can deposit a highly crystalline second conductor layer 5 having an orientation degree V represented by formula (1) of 0.95 or more.

[0065] In the film formation process, ammonia gas (NH ３ This can change the reaction path of titanium nitride formation, and the morphology of titanium nitride crystals can be made columnar.

[0066] In the film formation process, the film is formed at a film formation temperature of 650 to 1000°C, or ammonia gas (NH ３ ) may be used for film formation. This can increase the rate at which titanium nitride is produced, and can make the crystal quality of titanium nitride in the through hole 3 non-uniform. As a result, the variation in the superconducting transition temperature of the first conductor layer 4 can be increased, and the superconducting transition temperature width W4 of the first conductor layer 4 can be made larger than the superconducting transition temperature width W5 of the second conductor layer 5.

[0067] In the film formation process, an oxide substrate (e.g., single crystal sapphire, aluminum oxide sintered body, etc.) may be used as the substrate 2, and the film may be formed at a film formation temperature of approximately 650°C or higher. This allows oxygen to diffuse from the substrate 2 into the titanium nitride, doping the titanium nitride with oxygen. As a result, a first conductor layer 4 containing oxygen atoms can be formed. Furthermore, by appropriately adjusting the film formation temperature, film formation time, etc., a first conductor layer 4 containing 5 mol % or more of oxygen atoms can be formed.

[0068] In the film formation process, a jig containing graphite (C) was placed in a furnace, and hydrogen gas (H ２ ) can be used to form a film. This allows the graphite to be etched with hydrogen gas, and hydrocarbons (C ｘ H ｙ In the film formation process, ammonia gas (NH ３) may be used, and the film may be formed at a film formation temperature of 750°C. This increases the rate at which titanium nitride is produced and allows carbon to be incorporated into the titanium nitride. As a result, the first conductor layer 4 containing carbon atoms can be formed. Furthermore, by appropriately adjusting the film formation temperature, film formation time, etc., the first conductor layer 4 containing 3 mol % or more of carbon atoms can be formed.

[0069] According to the above manufacturing method, it is possible to manufacture a structure 1 that can extend the coherence time of a quantum bit.

[0070] Examples of the structure of the present disclosure will be described below. Note that the structure of the present disclosure is not limited to the examples described below. For ease of explanation, the same reference numerals as those used in the examples will be used for comparative examples.

[0071] As examples, structures 1 of Examples 1 to 5 were fabricated, each comprising a substrate 2 containing sapphire, and a first conductive layer 4 and a second conductive layer 5 containing titanium nitride. Also, as a comparative example, a structure of Comparative Example 2 was fabricated. Comparative Example 1 is a structure described in a publicly known document (J.L.Mallek et al., "Fabrication of superconducting through-silicon vias." arXiv:2103.08536 (2021)), and is a structure comprising a substrate 2 containing silicon, and a first conductive layer 4 and a second conductive layer 5 containing titanium nitride. Comparative Example 2, like Examples 1 to 5, is a structure comprising a substrate 2 containing sapphire, and a first conductive layer 4 and a second conductive layer 5 containing titanium nitride, but the superconducting transition temperature, transition temperature range, degree of orientation, oxygen content, and carbon content have not yet been measured.

[0072]

[0073] Table 1 shows the fabrication conditions for Examples 1 to 5 and Comparative Examples 1 and 2. In Table 1, "Substrate" indicates the material of the substrate 2, and "Through-hole shape" indicates the shape of the through-hole 3 (see FIGS. 2 and 3). Furthermore, "Nitrogen source" indicates the nitrogen source used when depositing the first conductive layer 4 and the second conductive layer 5 containing titanium nitride, "Film formation temperature (° C.)" indicates the film formation temperature when depositing the first conductive layer 4 and the second conductive layer 5, and "Film formation time (min)" indicates the film formation time (minutes) for the first conductive layer 4 and the second conductive layer 5.

[0074]

[0075] Table 2 shows the thicknesses of the first conductive layer 4 and the second conductive layer 5. In Table 2, the "center (μm)" of the "first conductive layer" indicates the layer thickness T4 at position T2 / 2 in the thickness direction of the substrate 2, the "minimum (μm)" indicates the minimum value of the layer thickness T4, the "maximum (μm)" indicates the maximum value of the layer thickness T4, and the "minimum / maximum ratio" indicates the value obtained by dividing the "minimum (μm)" by the "maximum (μm)." Furthermore, the "second conductive layer (μm)" indicates the layer thickness T5, and the "layer thickness ratio" indicates the value obtained by dividing the "center (μm)" of the first conductive layer 4 by the "second conductive layer (μm)." Note that the "second conductive layer (μm)" may be the average value of the layer thickness T5 in the surface direction (XY plane direction) of the first surface 2a, or may be the maximum or minimum value of the layer thickness T5.

[0076]

[0077] Table 3 shows the superconducting properties of the first conductive layer 4 and the second conductive layer 5. In Table 3, "First Conductor Layer" in "Superconducting Transition Temperature (K)" indicates the superconducting transition temperature (K) of the first conductive layer 4, "Second Conductor Layer" indicates the superconducting transition temperature (K) of the second conductive layer 5, and "Transition Temperature Difference" indicates the difference between the superconducting transition temperature (K) of the first conductive layer 4 and the superconducting transition temperature (K) of the second conductive layer 5. Furthermore, in "Transition Temperature Width (K)," "First Conductor Layer" indicates the superconducting transition temperature width W4 of the first conductive layer 4, and "Second Conductor Layer" indicates the superconducting transition temperature width W5 of the second conductive layer 5. In Table 3, "to" indicates that the values ​​are approximately equal, and a diagonal line (rising diagonally upward to the right) indicates that measurements have not yet been performed. In obtaining the results shown in Table 3, the electrical resistance of the wiring in which the first conductive layer 4 and the second conductive layer 5 are connected in series was measured, without measuring the electrical resistance of the first conductive layer 4 alone. Since the superconducting transition temperature of the wiring in which the first conductive layer 4 and the second conductive layer 5 are connected in series is lower than the superconducting transition temperature of the second conductive layer 5 alone, the superconducting transition temperature of the above wiring was used as the superconducting transition temperature of the first conductive layer 4.

[0078]

[0079] Table 4 shows the characteristics of the first conductive layer 4 and the second conductive layer 5. In Table 4, "Orientation" indicates the orientation V of the second conductive layer 5 expressed by formula (1), and "TiN shape" indicates the shape of the titanium nitride constituting the first conductive layer 4 (whether it is columnar or film-like). Furthermore, "Oxygen content (mol %)" indicates the amount of oxygen atoms contained in the titanium nitride constituting the first conductive layer 4, and "Carbon content (mol %)" indicates the amount of carbon atoms contained in the titanium nitride constituting the first conductive layer 4. Furthermore, "Layer peeling" indicates whether the first conductive layer 4 or the second conductive layer 5 peeled off from the substrate 2 when the structure 1 was cooled to a temperature below the superconducting transition temperature of the first conductive layer 4 and the second conductive layer 5. Note that the diagonal lines (rising diagonally upward to the right) in Table 4 indicate that measurements have not been performed.

[0080] In Examples 1 to 5, the substrate 2 is a sapphire substrate, which allows for an extended quantum bit coherence time compared to Comparative Example 1, in which the substrate 2 is a silicon substrate. In Examples 1 to 5, the first conductor layer 4 and the second conductor layer 5 are of high quality, which reduces layer peeling. Furthermore, in Examples 1 to 5, the through-hole 3 has a tapered shape, which allows for an extended quantum bit coherence time and stabilizes the operation of the quantum processor. Furthermore, in Examples 1 to 5, the superconducting transition temperature range W4 is wider than the superconducting transition temperature range W5, which allows for stabilization of the operation of the quantum processor by monitoring the electrical resistance value of the wiring in which the first conductor layer 4 and the second conductor layer 5 are connected in series. Furthermore, in Examples 1 to 5, the titanium nitride constituting the first conductor layer 4 contains 5 mol % or more oxygen atoms, which allows for an extended quantum bit coherence time and stabilizes the operation of the quantum processor.

[0081] In Examples 1 to 3 and 5, the ratio of the minimum value to the maximum value of the layer thickness T4 is 57% or more, so the coherence time of the quantum bit can be extended and the operation of the quantum processor can be stabilized.In Examples 1 and 2, the degree of orientation V is 0.95 or more, so the coherence time of the quantum bit can be extended and the operation of the quantum processor can be stabilized.

[0082] In Example 2, since the layer thickness T4 is 0.1 μm or more and 1.5 μm or less, the risk of the quantum processor being unable to perform quantum calculations can be reduced, and the operation of the quantum processor can be stabilized. Furthermore, in Example 2, the layer thickness T4 is greater than the layer thickness T5, and the operation of the quantum processor can be stabilized. Furthermore, in Example 2, the superconducting transition temperature of the first conductor layer 4 is 4.5 K or more, and the running costs of the quantum computer can be reduced.

[0083] In Examples 3 and 4, the titanium nitride constituting the first conductive layer 4 has columnar crystals, and therefore has better superconducting properties (higher superconducting transition temperature) than Comparative Example 1. As a result, Examples 3 and 4 can stabilize the operation of the quantum processor.

[0084] In Example 4, the titanium nitride constituting the first conductive layer 4 contains 3 mol % or more of carbon atoms, which makes it possible to extend the coherence time of the quantum bit and stabilize the operation of the quantum processor.

[0085] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-described embodiments. Various modifications, improvements, etc. are possible within the scope of the gist of the present disclosure. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included within the technical scope of the invention of the present disclosure. For example, functions contained in each component, etc., can be rearranged so as not to cause logical contradictions, and multiple components, etc., can be combined into one or separated. In other words, it should be noted that a person skilled in the art would easily be able to make various modifications or alterations based on the present disclosure. It should also be noted that these modifications, alterations, or alterations are included within the scope of the present disclosure.

[0086] According to the present disclosure, it is possible to extend the coherence time of a quantum bit.

[0087] The present disclosure can be implemented in the following aspects (1) to (21).

[0088] (1) A structure comprising: a substrate including ceramic, the substrate having a first surface, a second surface opposite the first surface, and a through hole extending from the first surface to the second surface; and a first conductive layer, which is a superconductor, located on the inner surface of the through hole.

[0089] (2) The structure according to (1) above, wherein the substrate comprises sapphire.

[0090] (3) The structure according to (1) or (2) above, wherein the first conductive layer contains titanium nitride.

[0091] (4) The structure according to any one of (1) to (3) above, wherein the thickness of the first conductive layer is 0.1 μm or more and 1.5 μm or less.

[0092] (5) The structure according to any one of (1) to (4) above, wherein the ratio of the minimum thickness to the maximum thickness of the first conductive layer is 57% or more.

[0093] (6) The structure according to any one of (1) to (5) above, wherein the first conductive layer has a superconducting transition temperature of 4.5 K or higher.

[0094] (7) The structure according to (3) above, wherein the titanium nitride of the first conductive layer has columnar crystals.

[0095] (8) The structure according to (3) or (7) above, wherein the titanium nitride of the first conductive layer contains 5 mol % or more of oxygen atoms.

[0096] (9) The structure according to (3), (7) or (8) above, wherein the titanium nitride of the first conductive layer contains 3 mol % or more of carbon atoms.

[0097] (10) The structure according to any one of (1) to (9) above, wherein the through-hole has a tapered shape.

[0098] (11) A structure described in any one of (1) to (9) above, wherein the through hole has a narrowed portion with a minimum diameter between the first opening on the first surface and the second opening on the second surface.

[0099] (12) The structure according to any one of (1) to (11) above, wherein the diameter of the through hole is 30 times or less the thickness of the first conductive layer.

[0100] (13) The structure according to any one of (1) to (12) above, wherein the through-holes have an aspect ratio of 5 or more.

[0101] (14) The structure according to any one of (1) to (13) above, further comprising a second conductive layer that is a superconductor and is located on the first surface and the second surface, wherein the thickness of the first conductive layer is greater than the thickness of the second conductive layer.

[0102] (15) The present invention further comprises a second conductive layer which is a superconductor and is located on the first surface and the second surface, the second conductive layer being made of titanium nitride, and the X-ray diffraction intensities of the 111 plane and the 022 plane of the titanium nitride of the second conductive layer are respectively I １１１ and I ０２２ When I １１１ / (I １１１ +I ０２２) is 0.95 or more.

[0103] (16) The structure according to any one of (1) to (13) above, further comprising a second conductive layer that is a superconductor and is located on the first surface and the second surface, wherein the superconducting transition temperature range of the first conductive layer is wider than the superconducting transition temperature range of the second conductive layer.

[0104] (17) A quantum processor comprising the structure according to any one of (1) to (16) above.

[0105] (18) A quantum computer comprising the quantum processor described in (17) above.

[0106] (19) A method for manufacturing a structure, comprising: a preparation step of preparing a substrate containing ceramic and having a through hole; and a film formation step of forming a conductive layer that is a superconductor on the inner surface of the through hole.

[0107] (20) The method for producing a structure according to (19) above, wherein the film forming step includes forming the conductive layer by a CVD method.

[0108] (21) The method for producing a structure according to (19) or (20) above, wherein the film-forming step includes forming the conductive layer by a CVD method under film-forming conditions of 650° C. or higher and 1000° C. or lower.

[0109] REFERENCE SIGNS LIST 1 Structure 2 Substrate 2a First surface 2b Second surface 3 Through-hole 3a First opening 3b Second opening 3c Inner peripheral surface 3d Narrowing portion 4 First conductive layer 5 Second conductive layer 6 Substrate precursor 6a First main surface 6b Second main surface 7 Conductive layer 30 Quantum processor 50 Quantum computer

Claims

1. A structure comprising: a substrate including ceramic having a first surface, a second surface opposite the first surface, and a through hole extending from the first surface to the second surface; and a first conductive layer that is a superconductor and is located on the inner surface of the through hole.

2. The structure of claim 1, wherein the substrate comprises sapphire.

3. The structure of claim 1 or 2, wherein said first conductive layer comprises titanium nitride.

4. The structure according to any one of claims 1 to 3, wherein the thickness of the first conductive layer is 0.1 µm or more and 1.5 µm or less.

5. The structure according to any one of claims 1 to 4, wherein the ratio of the minimum thickness to the maximum thickness of the first conductive layer is 57% or more.

6. The structure according to any one of claims 1 to 5, wherein the superconducting transition temperature of said first conductive layer is 4.5K or higher.

7. The structure of claim 3, wherein the titanium nitride of the first conductive layer is columnar.

8. The structure according to claim 3 or 7, wherein the titanium nitride of the first conductive layer contains 5 mol % or more of oxygen atoms.

9. The structure according to claim 3, 7 or 8, wherein the titanium nitride of the first conductive layer contains 3 mol % or more of carbon atoms.

10. The structure according to any one of claims 1 to 9, wherein the through-hole has a tapered shape.

11. A structure according to any one of claims 1 to 9, wherein the through hole has a narrowed portion, where the diameter is minimum, between the first opening on the first surface and the second opening on the second surface.

12. The structure according to any one of claims 1 to 11, wherein the diameter of the through-hole is 30 times or less the thickness of the first conductive layer.

13. The structure according to any one of claims 1 to 12, wherein the through-holes have an aspect ratio of 5 or more.

14. The structure of any one of claims 1 to 13, further comprising a second conductive layer that is a superconductor and is located on the first surface and the second surface, wherein the thickness of the first conductive layer is greater than the thickness of the second conductive layer.

15. The method further comprises providing a second conductive layer, which is a superconductor, located on the first surface and the second surface, the second conductive layer being made of titanium nitride, and measuring the X-ray diffraction intensities of the 111 plane and the 022 plane of the titanium nitride of the second conductive layer, respectively. １１１ and I ０２２ When I １１１ / (I １１１ +I ０２２ 14. The structure according to claim 1, wherein the value of (a) is 0.95 or more.

16. The structure of any one of claims 1 to 13, further comprising a second conductive layer that is a superconductor and is located on the first surface and the second surface, wherein the superconducting transition temperature range of the first conductive layer is wider than the superconducting transition temperature range of the second conductive layer.

17. A quantum processor comprising a structure according to any one of claims 1 to 16.

18. A quantum computer comprising the quantum processor of claim 17.

19. A method for manufacturing a structure, comprising: a preparation step of preparing a substrate containing ceramic and having a through hole; and a film formation step of forming a conductive layer that is a superconductor on the inner surface of the through hole.

20. The method for producing a structure according to claim 19, wherein the film forming step includes forming the conductive layer by a CVD method.

21. The method for manufacturing a structure according to claim 19 or 20, wherein the film-forming step includes forming the conductive layer by a CVD method using film-forming conditions of 650°C or higher and 1000°C or lower.

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