Memory data access method and apparatus, electronic device and readable storage medium

Abstract

The present application relates to the technical field of computers, and provides a memory data access method and apparatus, an electronic device and a readable storage medium. The method comprises: acquiring failure information of a memory component; configuring an address space mapping scheme for the failure information; in response to an initial memory access instruction sent by a processor, extracting a memory access address in the initial memory access instruction; on the basis of the memory access address and the address space mapping scheme, acquiring a plurality of target addresses corresponding to the memory access address, wherein target memory access instructions have one-to-one correspondence to the target addresses; executing the target memory access instructions by means of a memory controller so as to write split data, which is obtained after splitting write data sent by the processor, into the target addresses; and splicing read data read from the target addresses, and then returning to the processor.

Description

Memory data access method and device, electronic equipment and readable storage medium

[0001] Cross-reference to related applications

[0002] The present application claims priority from the Chinese patent application No. 202410436990.7 filed on April 11, 2024, and entitled "Memory data access method and device, electronic equipment and readable storage medium", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of computers, and in particular to a memory data access method and device, electronic equipment and readable storage medium. BACKGROUND

[0004] Memory, as a key part of computer data storage, provides data for the running of all programs. With the continuous growth of memory particle working frequency, the requirements for process manufacturing level are gradually increasing. After board testing, the entire system cannot be started due to memory unit defects, uneven PCB wiring, particle quality problems and other memory faults, or the memory cannot work at the design frequency due to stability problems, thereby affecting system performance.

[0005] In related technologies, in the case of memory unit defects, uneven PCB wiring, particle quality problems and other memory faults, the memory fault is usually solved by replacing the memory bar or memory particle, or replacing the precision power supply and other configurations to improve the memory stability. The memory frequency setting directly affects the stability of the memory and the adjustment of the memory parameters. In related technologies, the memory fault can also be solved by reducing the memory working frequency and adjusting the memory parameters, for example, the industrial level suggests that the initial value of the main frequency 1.2G and the DDR4 transmission rate 1.6G of the double data rate synchronous dynamic random access memory (DDR4) is adjusted for memory parameters, and the tuning can be improved after stabilization. The memory parameters include the performance and specifications of the memory module, such as capacity, speed, timing, etc.

[0006] However, replacing the memory bar or the memory particle cannot solve the signal integrity problem caused by uneven PCB wiring, and the on-board memory often exists in the form of particle patches, which is difficult to replace like a standard memory bar. Manual welding has the risk of causing board damage and other larger failures. Reducing the memory working frequency and adjusting the memory parameters may still have memory cell defects or uneven PCB wiring causing some data lines to work unstably, and subsequent optimization requires manual debugging of a large number of memory initialization training parameters, which is difficult to adjust the memory to stable work in a short period of time to support system startup, and even after a lot of debugging, it may still only work stably at a lower memory frequency, reducing system performance. Among them, memory initialization training is a process of continuously adjusting memory parameters to ensure that the memory module can be correctly initialized and stably run at system startup. That is, in the related art, there is a lack of a memory access method that can avoid the signal integrity problem caused by uneven PCB wiring, avoid replacing the memory particle causing the board damage, and ensure that the memory can work at the design frequency in the case of a memory component failure.

[0007] SUMMARY

[0008] The embodiments of the present application provide a memory data access method, device, electronic equipment and readable storage medium, to solve the problem that in the prior art, it is impossible to avoid the signal integrity problem caused by uneven PCB wiring, avoid replacing the memory particle causing the board damage, and ensure that the memory can work at the design frequency in the case of a memory component failure.

[0009] In a first aspect, the embodiments of the present application provide a memory data access method, comprising:

[0010] Obtain the fault information of the memory component; configure an address space mapping scheme for the fault information; in response to an initial memory access instruction sent by a processor, extract a memory access address in the initial memory access instruction; obtain a plurality of target addresses corresponding to the memory access address according to the memory access address and the address space mapping scheme; split the initial memory access instruction into a plurality of target memory access instructions according to the plurality of target addresses; the target memory access instruction and the target address correspond one by one; execute the target memory access instruction through a memory controller to write the split data obtained after splitting the write data sent by the processor into the target address; and splice the read data read from the target address and then return to the processor.

[0011] In a second aspect, an embodiment of the present application provides an apparatus for accessing memory data, the apparatus comprising: an obtaining module configured to obtain fault information of a memory component; a configuring module configured to configure an address space mapping scheme according to the fault information; an extracting module configured to extract a memory address in an initial memory access instruction in response to the initial memory access instruction being sent by a processor; a mapping processing module configured to obtain a plurality of target addresses corresponding to the memory address according to the memory address and the address space mapping scheme; an instruction splitting module configured to split the initial memory access instruction into a plurality of target memory access instructions according to the plurality of target addresses; the target memory access instructions and the target addresses correspond to each other; and a first executing module configured to execute the target memory access instructions by a memory controller to write split data obtained after splitting write data sent by the processor into the target addresses, and to splice read data read from the target addresses and then return the read data to the processor.

[0012] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a processor; a memory configured to store instructions executable by the processor; and wherein the processor is configured to execute the instructions to implement the method of the first aspect.

[0013] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to implement the method of the first aspect.

[0014] In a fifth aspect, an embodiment of the present application further provides a computer program product (stored in a non-transitory storage medium), the computer program product is executed by at least one processor to implement the method of the first aspect.

[0015] In a sixth aspect, an embodiment of the present application further provides an apparatus / device for accessing memory data, comprising the apparatus / device configured to implement the method of the first aspect.

[0016] The embodiment does not need to replace the memory component, nor does it need to solve the memory fault by reducing the memory operating frequency and adjusting the memory parameters. In the case of a fault of the memory component, the signal integrity problem caused by uneven PCB wiring can be avoided, the board damage caused by replacing the memory grain can be avoided, and the memory can work at the designed frequency. In addition, based on the method of the embodiment, in the case of a fault of the memory component, the memory controller can still provide a linear memory space for the processor core, maintain the data bit width, and ensure that the system works at the designed frequency, support the shielding of the memory fault, implement the startup of the system and the running of the program, enable the processor verification and the memory optimization to be performed in parallel, and accelerate the verification process after the board is returned.

[0017] The above description is only a summary of the technical solutions of the present application. In order to make the technical means of the present application more clear and complete, and to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0019] Fig. 1 is a schematic diagram of an application scenario of a memory data access method according to an embodiment of the present application;

[0020] Fig. 2 is a step flow chart of a memory data access method according to an embodiment of the present application;

[0021] Fig. 3 is a step flow chart of another memory data access method according to an embodiment of the present application;

[0022] Fig. 4 is a step flow chart of a splicing data processing method according to an embodiment of the present application;

[0023] Fig. 5 is a schematic diagram of a memory module address space mapping relationship of a memory particle with a fault according to an embodiment of the present application;

[0024] Fig. 6 is a framework diagram of a memory access system according to an embodiment of the present application;

[0025] Fig. 7 is a step flow chart of another memory data access method according to an embodiment of the present application;

[0026] Fig. 8 is a block diagram of a memory data access method device according to an embodiment of the present application;

[0027] Fig. 9 is a block diagram of an electronic device according to an embodiment of the present application;

[0028] Fig. 10 is a block diagram of another electronic device according to another embodiment of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0030] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class and do not limit the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the relationship between the associated objects, which means that there are three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0031] Figure 1 is a schematic diagram of an application scenario of a memory access method according to an embodiment of the present application. Referring to Figure 1, the application scenario includes at least a processor 10, a memory controller 20, a memory 30, a data line, an address line and a control line connected between the memory controller 20 and the memory 30. The memory controller 20 is provided with a memory data access device 201.

[0032] When the processor 10 performs a memory access operation on the memory 30, the processor 10 sends a memory access instruction to the memory controller 20. In the case of a read operation instruction, the memory controller 20 sends the memory access address to the memory 30 through the address line, and sends the control signal to the memory 30 through the control line, then reads the data stored in the memory 30 through the data line, and sends the read data to the processor 10. In the case of a write operation instruction, the memory controller 20 sends the memory access address and the control signal to the memory 30 through the address line, and sends the data to the memory 30 through the data line, and writes the data into the memory 30 at the memory access address.

[0033] In the present application, in response to the initial memory access instruction sent by the processor, the memory access address in the initial memory access instruction is extracted; according to the memory access address and the address space mapping scheme, a plurality of target addresses corresponding to the memory access address are obtained; according to the plurality of target addresses, the initial memory access instruction is split into a plurality of target memory access instructions; the target memory access instructions are executed by the memory controller to write the split data obtained after the write data sent by the processor is split into the target addresses; the read data read from the target addresses is spliced and then returned to the processor, so as to ensure that in the case of a memory component failure, the signal integrity problem caused by uneven PCB wiring can be avoided, the board card damage caused by replacing the memory particles can be avoided, and the memory can work at the design frequency.

[0034] The memory data access method provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] FIG. 2 is a step flowchart of a memory data access method provided by an embodiment of the present application. As shown in FIG. 2, the method can include the following steps.

[0036] In step 101, failure information of a memory component is obtained.

[0037] For example, the failure information of the memory component can include memory particle failure, data line failure, memory cell failure, or other memory component failure, and the present solution does not make specific limitations on the failed memory component. The memory particle is the basic unit of a memory device, and the mainstream memory particle types include Double Data Rate Synchronous Dynamic Random Access Memory (DDR4 SDRAM). The memory cell is the smallest storage unit in a computer, used to store binary data. The processor core runs configuration software and accesses the memory configuration interface through an on-chip bus to obtain the failure information of the memory component.

[0038] In step 102, an address space mapping scheme is configured according to the failure information.

[0039] For example, the address space mapping scheme configured according to the failure information is different for different memory components corresponding to the failure information.

[0040] For example, if the failed memory component is a part of the memory particle, the access to the failed memory particle can be mapped to an available memory particle by reserving a memory address for shielding the failure, so that the system program can run with the memory failure shielded, the system works at the design frequency through prefetching and caching, and fine memory parameter debugging can be performed in parallel with the verification of the entire system. The memory failure refers to a problem in the computer memory, which causes the computer to be unable to normally read or write data.

[0041] For another example, the failed memory component is a part of the data line, and the data line is used to transmit data between the memory particle and the memory controller. The failure of part of the memory data line will cause the effective data bit width obtained by the processor core to be less. By using different address mapping schemes such as address transformation and reserved memory space rotation access, the read-write memory of the processor core is split into multiple read-write memories, and the data bit width obtained by the processor core is filled by splicing the data, so that the system program can run with the memory data line failure shielded. By using different address mapping schemes such as address transformation and reserved memory space rotation access, the system program can run with the memory data line failure shielded.

[0042] For example, the failed memory component is a part of memory cells. By recording the address of the failed memory cell, the grain number, and the corresponding reserved memory address, grain number, and other information in the address space mapping table, the matched memory access request is split and spliced, so that the system program can run with the memory cell failure shielded.

[0043] Step 103, in response to the initial memory access instruction sent by the processor, extracting the memory access address in the initial memory access instruction.

[0044] Specifically, the memory access address is used for data access to at least part of the memory component in the memory. For example, the memory component is a memory grain in a memory bank, and there are 8 memory grains in the memory bank. The memory access address is used for data access to the 8 memory grains in the memory bank. The processor can be a central processing unit (CPU).

[0045] Step 104, according to the memory access address and the address space mapping scheme, obtaining a plurality of target addresses corresponding to the memory access address.

[0046] Specifically, the target address includes a first address and a second address. The first address is used to obtain data of all normal components in the memory component, and the second address is used to obtain data of a preset number of normal components in all normal components. The preset number is equal to the number of failed components. The normal component is a memory component in a normal operating state.

[0047] Step 105, according to the plurality of target addresses, splitting the initial memory access instruction into a plurality of target memory access instructions.

[0048] The target memory access instruction and the target address correspond to each other. For example, the initial memory access instruction is split into a plurality of target memory access instructions, and each target memory access instruction includes a target address different from each other, and the target memory access instruction and the target address correspond to each other. For example, the target address includes a first address and a second address, and the target memory access instruction includes a target memory access instruction with the first address as the memory access address, and a target memory access instruction with the second address as the memory access address.

[0049] Step 106, executing the target memory access instruction through the memory controller to write the split data obtained after writing the data sent by the processor into the target address; and splicing the read data read from the target address and returning to the processor.

[0050] In one embodiment, the target memory access instruction is a read operation instruction, the first execution result is first read data corresponding to the first address, and the second execution result is second read data corresponding to the second address; the first read data and the second read data are spliced to obtain complete read data after splicing. The complete read data is returned to the processor. The second address can be one or more, and the corresponding second read data can also be one or more.

[0051] Specifically, the plurality of read operation instructions are sent to the memory controller, the plurality of read operation instructions are received by the memory controller, and each read operation instruction is executed to obtain a plurality of read data. The read data and the read operation instruction correspond one by one, the read operation instruction and the target address correspond one by one, and therefore the read data and the target address correspond one by one.

[0052] Further, the target address is the first address or the second address, the read operation instruction includes the first address or the second address, the memory controller reads data at the first address or the second address of the memory according to the first address or the second address in the read operation instruction to obtain the read data. After executing one target memory access instruction, the memory controller stores the first read data corresponding to the first address and the second read data corresponding to the second address obtained in the data cache module, splices all first read data and all second read data after executing all target memory access instructions to obtain complete read data of the data bit width required by the processor, and then returns the complete read data to the processor.

[0053] For example, in the case where the target memory access instruction is a write operation instruction, the write data is split into write data of the same number as the number of target memory access instructions, and the split write data is provided to the corresponding write operation instruction. The write operation instruction includes the first address or the second address, and the memory controller sends the split write data and the write operation instruction to the memory to write the split write data into the first address or the second address in the memory, respectively, to obtain write data written into the first address and the second address, respectively.

[0054] In the related art, when a memory particle fault or a memory data line fault is encountered, or a memory particle is replaced or a memory operating frequency is reduced and a meticulous memory parameter is debugged, the replacement of the memory particle cannot solve the signal integrity problem caused by uneven PCB wiring and has the risk of causing greater failure of the board card, the reduction of the memory operating frequency and the meticulous memory parameter debugging cannot work at the design frequency and the memory parameter debugging greatly delays the project verification period. The related art often uses a more complex memory correction scheme or integrates a memory fault-tolerant technology in the system when a memory unit fault is encountered, which has a large resource overhead and may be over-optimized. In the embodiment, the memory fault is solved without replacing the memory component or reducing the memory operating frequency and adjusting the memory parameter, in the case of a fault of the memory component, the signal integrity problem caused by uneven PCB wiring can be avoided, the board card damage caused by the replacement of the memory particle can be avoided, and the memory can work at the design frequency. Based on the method of the embodiment, in the case of a fault of the memory component, the memory controller can still provide a linear memory space for the processor core, maintain the data bit width, and ensure that the system works at the design frequency, support the shielding of the memory fault, realize the startup of the system and the running of the program, so that the processor verification and the memory optimization can be performed in parallel, and the verification process after the board is made into a piece is accelerated.

[0055] FIG. 3 is a step flowchart of another memory data access method provided by the embodiment of the application. Referring to FIG. 3, the method can include the following steps:

[0056] Step 201: Obtain fault information of the memory component.

[0057] The method of this step has been described in the foregoing step 101, and will not be repeated here.

[0058] Step 202: Configure an address space mapping scheme for the fault information through a software program; wherein the software program runs on an embedded processor added in the memory controller or runs in firmware added in the processor core.

[0059] Further, an embedded processor can be added in the memory controller, or a memory configuration interface can be added to communicate with the processor core, and the processor core adds firmware to run the software program. The embedded processor or the processor core can obtain state information of each memory particle and each data line, and analyze the faulty memory particle, data line or memory unit. The faulty memory component is determined as a memory component that needs to be shielded, and then an address space mapping scheme corresponding to the memory component is selected, so that the address space mapping table maintained by the hardware is configured according to the determined address space mapping scheme.

[0060] Further, the acquired state information can be state information of the above memory particles, data lines, memory cells, or information of other memory components, and the address space mapping scheme is flexibly configured according to the faulty memory component through a software program.

[0061] In step 203, the address space mapping scheme is written into the address space mapping table through the memory configuration interface.

[0062] For example, the address space mapping scheme is configured through a software program, and then the address space mapping scheme is written into the address space mapping table through the memory configuration interface.

[0063] In step 204, in response to the initial memory access instruction sent by the processor, the memory access address in the initial memory access instruction is extracted.

[0064] In step 205, according to the memory access address and the address space mapping scheme recorded in the address space mapping table, a plurality of target addresses corresponding to the memory access address are acquired.

[0065] In step 206, the initial memory access instruction is split into a plurality of target memory access instructions according to the plurality of target addresses.

[0066] Specifically, the target memory access instruction and the target address are in one-to-one correspondence.

[0067] In step 207, the target memory access instruction is executed through the memory controller to write the split data obtained after the write data sent by the processor is split into the target addresses, and the read data read from the target addresses is spliced and then returned to the processor.

[0068] In this embodiment, the memory component does not need to be replaced, and the memory failure does not need to be solved by reducing the memory working frequency and adjusting the memory parameters. In the case of a faulty memory component, the signal integrity problem caused by uneven PCB wiring can be avoided, the board damage caused by replacing the memory particles can be avoided, and the memory can work at the designed frequency. In addition, based on the method of this embodiment, in the case of a faulty memory component, the memory controller can still provide a linear memory space for the processor core, maintain the data bit width, ensure the system to work at the designed frequency, support the shielding of memory failure, realize the startup of the system and the running of the program, make the processor verification and memory optimization can be carried out in parallel, and accelerate the verification process after the board is returned.

[0069] In one embodiment, referring to FIG. 4, the read data read from the target address in step 207 is spliced and then returned to the processor, which can include the following sub-steps (sub-step 2071 to sub-step 2073):

[0070] In sub-step 2071, the read data read from the target address is spliced to obtain spliced data.

[0071] For example, the read data read from the target address can be spliced by the data buffer module to obtain spliced data.

[0072] In substep 2072, error checking and correction technology is performed on the spliced data to obtain processed spliced data.

[0073] For example, the data buffer module can perform error checking and correction technology (ECC) on the spliced data to obtain processed spliced data.

[0074] In substep 2073, the processed spliced data is returned to the processor.

[0075] For example, the processor core software program acquires quality information of each memory particle and each data line, selects a corresponding address space mapping scheme according to the fault information through the software program, and writes the address space mapping scheme suitable for the quality of the current memory system into the address space mapping table maintained by the hardware. When the software program is running, the processor core splits each memory access request (i.e., an initial memory access instruction) into multiple requests (i.e., multiple target memory access instructions) according to the address space mapping table maintained by the hardware, and then sends the split multiple requests to the memory through the request prefetch module.

[0076] In one embodiment, step 205 can include the following substep (substep 2051):

[0077] In substep 2051, in the case where there is a faulty component in at least part of the memory components in the memory, the memory address is converted into the first address and the second address according to the memory address and the address space mapping scheme.

[0078] The first address is used to obtain data of all normal components in the memory component, and the second address is used to obtain data of a preset number of normal components in all normal components; the preset number is equal to the number of faulty components. The first address is one, and the second address is one or more. For example, the memory fault can be caused by at least one of a memory particle quality problem, uneven data line wiring, and a memory cell defect. The memory particle, the data line, and the memory cell are arranged in descending order of address space affected by the fault. The memory particle is a basic unit of the memory device, which can be a double data rate synchronous dynamic random access memory (DDR SDRAM), or other types of DDR SDRAM. The memory cell is the smallest memory unit in a computer, which can be used to store binary data.

[0079] The address space mapping scheme can include an address conversion method of converting the memory access address into the target address, and a corresponding relationship between the target address and the memory component. The address space mapping scheme can be a strategy pre-generated by the processor according to the fault component information. After the processor generates the address space mapping scheme, the processor can send the address space mapping scheme to the memory access device shown in FIG. 1, so that the memory access device stores the address space mapping scheme in the address space mapping table of the memory access device.

[0080] The first address is the memory access address in the initial memory access instruction, and the second address is a memory address obtained by address conversion on the first address according to the address space mapping scheme. For example, the memory address space is divided into an address space visible to the processor and an address space invisible to the processor. When the address space is visible to the processor, the memory access address in the initial memory access instruction sent by the processor can only be an address in the address space. The first address and the second address are converted addresses corresponding to the memory access address obtained according to the address space mapping scheme. The target address can include the same address as the memory access address, or can not include the same address as the memory access address.

[0081] For example, referring to FIG. 5, the memory components are memory particles in a memory bank, and there are 8 memory particles in the memory bank, among which the faulty memory particles are memory particle 3 and memory particle 6, and the normally operating memory particles are the other memory particles. The first address is the memory address in the initial memory access instruction, and the first address is an address in the memory address space between 0x00000000 and 0xbfffffff, and the first address is used to obtain data of the normal memory particles other than memory particle 3 and memory particle 6. The second address is a memory address obtained by address conversion on the first address according to the address space mapping scheme, and the second address is in the memory address space between 0xc0000000 and 0xfffffff, and the number of normal memory particles corresponding to the second address is equal to the number of faulty memory particles. In the address space mapping scheme in FIG. 5, if the memory address in the initial memory access instruction is between 0x00000000 and 0x3fffffff, the memory particles corresponding to the second address are memory particle 1 and memory particle 5, and the second address is used to obtain data of memory particle 1 and memory particle 5.

[0082] In the case where all the memory components are normal components in normal operation, the target address is not needed to be obtained according to the memory address, and the initial memory access instruction is directly sent to the memory controller, so that the memory controller performs the corresponding memory access operation according to the initial memory access instruction.

[0083] For example, the target memory access instruction is sent to the memory controller, and the memory controller performs the memory access operation on the memory according to the target address in the target memory access instruction in response to the received target memory access instruction, to obtain the memory data access result. The memory controller is a hardware intellectual property (Intellectual Property) core used to control memory access and data transmission in a computer system, including the interface between the processor and the memory, and the related processing logic.

[0084] For example, the target memory access instruction is a read operation instruction, and the first execution result and the second execution result are both read data read from the memory. The memory data access result is obtained according to the first execution result and the second execution result. For example, the first execution result and the second execution result are spliced to obtain the memory data access result. For another example, the target memory access instruction is a write operation instruction, and the first execution result and the second execution result are both write data written into the memory. The memory data access result is obtained according to the first execution result and the second execution result, including determining the write data composed of the first execution result and the second execution result as the memory data access result obtained by executing the write operation instruction.

[0085] For example, the failed memory component is a part of a memory grain, and by reserving a memory address for shielding the failure, the access to the failed memory grain is mapped to an available memory grain, so that the system program can run with the memory failure shielded. By pre-fetching and caching, the system works at the design frequency.

[0086] For example, referring to FIG. 5, each of the 8 memory grains corresponds to a data bit width of 8 bits. In the case where all the memory grains are normal memory grains, based on a memory access instruction, one memory access operation on the memory module can obtain a memory data access result with a data bit width of 8*8 bits = 64 bits. The normal memory grains corresponding to the first address are memory grain 1, memory grain 2, memory grain 4, memory grain 5, memory grain 7, and memory grain 8, respectively, and thus based on a target memory access instruction including the first address, the memory data access result obtained has a data bit width of 6*8 bits = 48 bits.

[0087] The number of normal memory grains corresponding to the second address is equal to the number of failed memory grains, which is two (memory grain 3 and memory grain 6), and thus the normal memory grains corresponding to the second address are also two, which are memory grain 1 and memory grain 5. Based on a target memory access instruction including the second address, the memory data access result obtained has a data bit width of 2*8 bits = 16 bits.

[0088] Based on a target memory access instruction including the first address, a first execution result corresponding to the first address can be obtained, and the first execution result includes the data of all the normal memory grains, and the data bit width of the data of all the normal memory grains is 48 bits. Based on a target memory access instruction including the second address, a second execution result corresponding to the second address can be obtained, and the second execution result includes the data of memory grain 1 and memory grain 5, and the data bit width of the data of the two normal memory grains is 16 bits.

[0089] According to the first execution result and the second execution result, the total data bit width of the memory access result obtained is 48 bits + 16 bits = 64 bits. That is, in the case where memory grain 3 and memory grain 6 fail, by splitting the initial memory access instruction into two target memory access instructions, based on the two target memory access instructions, the data of failed memory grain 3 and failed memory grain 6 can be shielded, and the memory access operation on the two failed memory grains is converted into a memory access operation on normal memory grain 1 and normal memory grain 5, and finally the data bit width of the memory data access result obtained is the same as the data bit width of the valid memory data access result obtainable before the failure (both are 64 bits), which ensures the data integrity of the memory data access result.

[0090] The memory data access method of the present application is further illustrated below in connection with more specific embodiments. In one embodiment, the memory component is a memory granule, and the first address is a memory access address. Step 205 can include the following sub-steps (sub-step 2052 to sub-step 2053) :

[0091] Sub-step 2052, obtaining a first address space visible to the processor and a second address space invisible to the processor in the memory address space.

[0092] The ratio of the interval size of the first address space to the interval size of the second address space is equal to the ratio of the total memory capacity of all normal memory granules to the total memory capacity of all faulty memory granules. The memory access address is an address in the first address space.

[0093] The first address space is visible to the processor, indicating that when the processor generates the initial memory access instruction, the memory access address in the initial memory access instruction can only be an address in the first address space. The second address space is invisible to the processor, indicating that when the processor generates the initial memory access instruction, the memory access address in the initial memory access instruction is not an address in the second address space. Although the second address space is invisible to the processor, the second address is visible to the memory controller. After converting the first address in the first address space to the second address in the second address space, the memory controller can still perform memory access operations based on the address in the second address space.

[0094] For example, referring to FIG. 5, the memory module includes 8 memory granules, each with a memory capacity of 4G. There are 6 normal memory granules and 2 faulty memory granules, so the effective data bit width obtained by executing each initial memory access instruction is 48 bits. The effective memory capacity of the memory module is 6x4G=24G, and the effective memory capacity is equal to the total memory capacity of all normal memory granules: 6x4G=24G. There are two faulty memory granules, so the total memory capacity of all faulty memory granules is 2x4G=8G.

[0095] The 4G memory address space is divided into a first address space and a second address space. According to the method of the present embodiment, the range of the first address space is 0x00000000 to 0xbfffffff, and the interval size of the first address space is 3G. The range of the second address space is 0xc0000000 to 0xfffffff, and the interval size of the second address space is 1G.

[0096] Sub-step 2053, converting the memory access address to a second address in the second address space according to the address space mapping scheme.

[0097] The ratio of the interval size of the first address space to the interval size of the second address space is equal to the ratio of the total capacity of all normal memory particles to the total capacity of all faulty memory particles. Further, the memory access address is an address in the first address space.

[0098] For example, the processor obtains the running state information of the memory particles. When it is determined that the memory particle 3 and the memory particle 6 are faulty memory particles that cannot stably run at the design frequency, the processor calculates that the content space visible to the processor for each memory particle is 24G / 8=3G. For each of the six normal memory particles, the remaining memory capacity is 6x(4G-3G)=6G. This part of the memory capacity is invisible to the processor. This part of the memory space is allocated to the two faulty memory particles to obtain an address space mapping scheme, and is stored in the address space mapping table in the memory access device, so as to subsequently convert the first address to the second address according to the address space mapping scheme.

[0099] For example, further, a preset offset address can be superimposed on the first address to obtain a second address in the second address space.

[0100] For example, in the embodiment shown in FIG. 5, the address conversion formula for converting the first address A to the second address can be (A%(0x40000000)+0xc0000000). Wherein, A%(0x40000000) represents obtaining the remainder of the first address A with respect to the address (0x40000000). For example, the first address A is 0x8000000f. According to the above address conversion formula, the second address is 0x0000000f+0xc0000000=0xc000000f.

[0101] In one embodiment, the faulty memory component is a memory particle, and the number of faulty memory particles is less than the number of normal memory particles. Correspondingly, step 205 can further include the following sub-steps (sub-step 2054 to sub-step 2056):

[0102] Sub-step 2054: Obtain a plurality of first sub-address spaces included in the first address space.

[0103] Specifically, the first sub-address space corresponds to a preset number of normal memory particles.

[0104] For example, the processor can divide the first address space into a preset number of first sub-address spaces, or divide the first address space into a plurality of first sub-address spaces according to random address space sizes. Each first sub-address space can be set with corresponding normal memory particles according to a random allocation method.

[0105] For example, referring to FIG. 5, a first address space with memory address range of 0x00000000 to 0xffffffff is evenly divided into three first sub-address spaces, i.e., 0x00000000 to 0x3fffffff, 0x40000000 to 0x7fffffff, and 0x80000000 to 0xbfffffff. The normal memory granules corresponding to the first sub-address space 0x00000000 to 0x3fffffff include the memory granule 1 and the memory granule 5, the normal memory granules corresponding to the first sub-address space 0x40000000 to 0x7fffffff include the memory granule 2 and the memory granule 7, and the normal memory granules corresponding to the first sub-address space 0x80000000 to 0xbfffffff include the memory granule 4 and the memory granule 8.

[0106] Sub-step 2055, determining, from the plurality of first sub-address spaces, a target first sub-address space in which the memory access address is located.

[0107] The target first sub-address space is determined by comparing the memory access address with each first sub-address space. For example, in FIG. 5, the memory access address is 0x8000000f, and the target first sub-address space in which the memory access address is located is 0x80000000 to 0xbfffffff.

[0108] Sub-step 2056, determining, as the normal component corresponding to the second address, the normal memory granule corresponding to the target first sub-address space.

[0109] For example, referring to FIG. 5, the target first sub-address space in which the memory access address is located is 0x80000000 to 0xbfffffff, and the memory granules corresponding to the first sub-address space are the memory granule 4 and the memory granule 8. Therefore, the memory granule 4 and the memory granule 8 are the normal components corresponding to the second address obtained according to the memory access address. There are six normal memory granules corresponding to the first address, and the data bit width of the memory data access result obtained based on the target memory access instruction including the first address is 48 bits. There are also two normal memory granules corresponding to the second address, and the data bit width of the memory data access result that can be obtained based on the target memory access instruction including the second address is 16 bits. The read data based on the two target memory access instructions is spliced to obtain 64-bit complete data, and the complete data is returned to the processor.

[0110] In one embodiment, the memory component is a data line, and the data line is used to transmit data between the memory granule and the memory controller. Correspondingly, the step 205 can include the following sub-steps (sub-step 2057 to sub-step 2060):

[0111] Sub-step 2057, obtain the product of the access address and the number of all data lines.

[0112] During the access operation, for one access operation, the number of data bits transmitted by one data line can be 1 bit. The first product of the access address and the number of all data lines is equal to the total sum of the number of data bits corresponding to all memory addresses before the access address, when the number of data bits obtained by performing access operation on each memory address before the access address is equal to the number of data bits before the fault.

[0113] For example, the memory bank includes 8 memory particles, and the number of data lines between each memory particle and the memory controller is 8, so the number of all data lines is: 8x8=64.

[0114] If the access address is 8, the number of memory addresses before the access address is 8. The first product of the access address and the number of all data lines is: 8x64. In the case that the number of data bits corresponding to the 8 memory addresses before the access address is equal to 64, the total sum of the number of data bits corresponding to the 8 memory addresses is: 8x64.

[0115] Sub-step 2058, obtain the ratio of the product and the number of all normal data lines.

[0116] In the case of continuous storage, the ratio of the product of the access address and the number of all data lines to the number of normal data lines is equivalent to the number of target addresses required in the case that the number of data bits obtained by performing access operation on each memory address before the access address is equal to the number of data bits before the fault.

[0117] For example, among the 8 memory particles, the data lines of 3 memory particles are faulty, and the number of faulty data lines of each memory particle is 2, so the number of all faulty data lines is 6, and the number of all normal data lines is 58. The ratio of the product to the number of all normal data lines is: (8x64)%58=8.827. In the case of ensuring that the number of data bits of the 8 memory addresses before the access address is equal to the number of data bits before the fault, the number of target addresses required is 8.827.

[0118] Sub-step 2059, determine the starting address in the plurality of target addresses and the normal data line corresponding to the starting address according to the ratio.

[0119] For example, the integer part in the ratio is determined as the start address in the target address, and the decimal part in the ratio is determined as the proportion of the number of data lines allocated to the memory address before the target address in the normal data lines corresponding to the start address. According to the proportion, the number of data lines allocated to the memory address before the target address can be obtained. The number of normal data lines corresponding to the start address is obtained by subtracting the number from the number of normal data lines, and the data line with a number equal to the number and located in the high bit is taken as the normal data line corresponding to the start address.

[0120] For example, in the foregoing embodiment, the calculated ratio is (8x64)%58=8.827, and the start address is 8. The normal data line corresponding to the start address is 58-(8x64)%58=10.

[0121] In sub-step 2060, the number of all normal data lines corresponding to all target addresses is equal to the number of all data lines in the memory as the allocation strategy. According to the start address and the number of all normal data lines corresponding to the start address, other target addresses and normal data lines corresponding to each of the other target addresses are determined.

[0122] A first difference between the number of all data lines and the number of normal data lines corresponding to the start address is obtained. In the case that the first difference is less than or equal to the number of all normal data lines, the next memory address of the start address is also taken as a target address, and the normal data lines with a number equal to the first difference are selected from the normal data lines corresponding to the target address as the normal data lines corresponding to the target address. In the case that the first difference is greater than the number of all normal data lines, the next memory address of the start address is also taken as a target address, and all normal data lines are taken as the normal data lines corresponding to the target address. The first difference and the number of all normal data lines are taken as a second difference, and the target address and the normal data lines corresponding to the target address are continuously determined until the number of all normal data lines corresponding to all target addresses is equal to the number of all data lines.

[0123] For example, in the foregoing embodiment, the calculated start address is 8, the number of data lines corresponding to the start address is 10, the number of all data lines in the memory is 64, and the number of normal data lines is 58. The first difference between the number of all data lines and the number of normal data lines corresponding to the start address is 64-10=54, and the first difference is less than the number of normal data lines 58. Therefore, the next memory address (memory address 9) is taken as the target address, and 54 normal data lines are selected from the 58 normal data lines corresponding to the target address 9 as the normal data lines corresponding to the target address 9. That is, the target addresses corresponding to the memory access address 8 are the memory address 8 and the memory address 9, the normal data lines corresponding to the memory address 8 are 10, and the normal data lines corresponding to the memory address 9 are 54. Correspondingly, when the memory access address is 8, the memory controller obtains 10 bits of data based on the memory address 8, and obtains 54 bits of data based on the memory address 9, splices the 64 bits of complete data and returns to the processor.

[0124] For another example, the memory access address is 9, the corresponding start address is 9, the number of data lines corresponding to the start address is 4, the next memory address 10 is determined as the target address, 58 data lines are selected as the normal data lines corresponding to the target address 10, and the next memory address 11 is determined as the target address. Two data lines are selected from the 58 data lines corresponding to the target address 11. That is, the target addresses corresponding to the memory access address 9 are the memory address 9, the memory address 10 and the memory address 11, the normal data lines corresponding to the memory address 9 are 4, the normal data lines corresponding to the memory address 10 are 58, and the normal data lines corresponding to the memory address 11 are 2. Correspondingly, when the memory access address is 9, the memory controller obtains 4 bits of data based on the memory address 9, 58 bits of data based on the memory address 10, and 2 bits of data based on the memory address 11, splices the 64 bits of complete data and returns to the processor.

[0125] In one embodiment, the memory component is a data line, and the data line is used to transmit data between the memory grain and the memory controller. The first address is the memory access address. Correspondingly, step 205 can further include the following sub-steps (sub-step 2061 to sub-step 2062):

[0126] Sub-step 2061: Obtain a third address space in the memory address space which is visible to the processor, and a fourth address space in the memory address space which is invisible to the processor.

[0127] The fourth address space is invisible to the processor, and thus the memory access address in the initial memory access instruction generated by the processor is not allocated to the fourth address space. However, the fourth address space is visible to the memory controller, and thus the memory controller can perform a memory access operation according to the address in the fourth address space. The ratio of the interval size of the third address space to the interval size of the fourth address space can be equal to the ratio of the number of normal data lines to the number of faulty data lines. The memory access address is in the third address space. The memory address space visible to the processor and the memory address space invisible to the processor have been described in the foregoing step 202, and thus will not be described herein.

[0128] In substep 2062, the memory access address is converted into a second address according to the address space mapping scheme.

[0129] Specifically, the second address is in the fourth address space. For example, a preset address offset can be superimposed on the first address to convert the first address into the second address in the fourth address space.

[0130] In an embodiment, the memory component is a data line, and the data line is used to transmit data between the memory cell and the memory controller. Step 205 can further include the following substeps (substep 2063 to substep 2064):

[0131] In substep 2063, a preset number of normal data lines are selected from all normal data lines.

[0132] For example, the preset number of normal data lines can be randomly selected from the normal data lines. Alternatively, the preset number of normal data lines can be determined according to a round-robin allocation manner. For example, the memory access address of a first initial memory access instruction is A, the second address obtained according to the memory access address A is B, the number of normal data lines is 58, and the number of faulty data lines is 6. The normal data lines corresponding to the second address B are determined to be the first normal data line to the sixth normal data line. The memory access address of a second initial memory access instruction is C, the second address obtained according to the memory access address C is D, and the normal data lines corresponding to the second address D are determined to be the seventh normal data line to the fourteenth normal data line. According to a next initial memory access instruction, the normal data lines corresponding to the second address are determined to be the fifteenth normal data line to the twenty-first normal data line. In this way, the round-robin allocation manner is implemented.

[0133] In substep 2064, the preset number of normal data lines are determined as the normal components corresponding to the second address.

[0134] For example, in the foregoing embodiment, the memory access address of the first initial memory access instruction is A, the second address obtained according to the memory access address A is B, and the normal data lines corresponding to the second address B are determined as the first normal data line to the sixth normal data line. In the case that the memory component has a fault component, the first normal data line to the sixth normal data line may cause the failure to obtain correct memory access data, which may cause the failure of the memory access operation, resulting in the failure of the computer system to start normally; or because of the stability problem of the memory, the memory cannot work at the design frequency, thereby affecting the performance of the computer system. The memory component fault may include a memory particle fault, and may also include a data line fault caused by uneven PCB wiring.

[0135] In one embodiment, the memory component is a memory cell, and the first address is a memory access address. Step 205 can further include the following sub-steps (sub-step 2065 to sub-step 2067):

[0136] Sub-step 2065: Obtain a fifth address space visible to the processor and a sixth address space invisible to the processor in the memory address space.

[0137] Specifically, the size of the sixth address space is equal to the preset address space size, and the memory access address is in the fifth address space. The sixth address space is invisible to the processor, so when the processor generates the initial memory access instruction, the memory access address will not be allocated to the sixth address space. However, the sixth address space is visible to the memory controller, and the memory controller can execute the corresponding memory operation according to the address allocated to the sixth address space. Compared with the memory particle fault and the data line fault, the memory cell fault affects a relatively small range of memory addresses. Although the memory address range is small, it may still cause memory read / write errors, thereby causing program running errors or dead machine phenomena.

[0138] Because the memory cell fault affects a relatively small range of memory addresses, the preset address space size can be determined according to empirical data, for example, the size of the preset address space can be set to 4MB. The address space of the preset address space size is determined as the second address space invisible to the processor, and the address space of the other part is determined as the fifth address space visible to the processor.

[0139] Among them, the address space visible to the processor and the address space invisible to the processor have been described in the foregoing step 202, and will not be repeated here.

[0140] Sub-step 2066: Obtain the fault memory address corresponding to the fault memory cell.

[0141] Each memory unit has a corresponding memory address. After determining the faulty memory unit, the corresponding memory address of the faulty memory unit is determined as a faulty memory address and stored in the address space mapping table.

[0142] Further, the address space mapping table can record the address of the faulty memory unit, the particle number of the memory particle in which the faulty memory unit is located, and the corresponding reserved memory address, and the particle number of the memory particle.

[0143] Sub-step 2067, in the case where the memory access address is equal to the faulty memory address, the memory access address is converted into a second address according to the address space mapping scheme.

[0144] The second address is in the sixth address space.

[0145] For example, the first address is superimposed with a preset address offset to obtain the second address in the sixth address space. For example, there can be multiple faulty memory units, and there can be multiple faulty memory addresses corresponding to the faulty memory units. In the case where the memory access address is equal to any of the faulty memory addresses, the memory access address is converted into a second address according to the address space mapping scheme, and the second address is in the sixth address space.

[0146] In one embodiment, the memory component is a memory unit, and the first address is a memory access address. Step 205 can include the following sub-steps (sub-step 2068 to sub-step 2069):

[0147] Sub-step 2068, from the normal memory unit corresponding to the second address, a preset number of normal memory units are selected. The preset number of normal memory units is a part of the normal memory units corresponding to the second address.

[0148] Sub-step 2069, the selected preset number of normal memory units are determined as normal components corresponding to the second address.

[0149] The preset number of normal memory units are determined as normal components corresponding to the second address, so that data of the preset number of normal memory units are used as part of data of the memory access operation when the memory access operation is performed based on the target memory access instruction including the second address. For example, the address of the faulty memory unit, the particle number of the memory particle in which the faulty memory unit is located, and the reserved memory address and the reserved particle number corresponding to the faulty memory unit are recorded in the address space mapping table. When the memory access address matches the address of the faulty memory unit, the corresponding reserved memory address and the reserved particle number are determined based on the information stored in the address space mapping table, the reserved address is determined as the second address, and the first address is determined as the memory access address. A plurality of target memory access instructions are obtained according to the two addresses, and the memory access operation is performed through the plurality of target memory access addresses. When the target memory access instruction is a write operation instruction, the write data is split and written into the memory, and when the target memory access instruction is a read operation instruction, the read data is spliced and returned to the processor. Therefore, the system program can run in the state of shielding the memory unit fault.

[0150] By dividing the memory address space into a fifth address space visible to the processor and a sixth address space invisible to the processor, the first address in the fifth address space is converted into the second address in the sixth address space when the memory access address is equal to the faulty memory address corresponding to the faulty memory unit. The memory access operation is performed based on the second address, which is equivalent to converting the memory access operation on the faulty memory unit into the memory access operation on the normal memory unit. Therefore, without replacing the faulty memory unit, the normal memory access operation is realized, and the system can work at the design frequency corresponding to the normal memory unit.

[0151] In one embodiment, before step 201, the method further includes:

[0152] In step 208, a test operation is performed on the memory component in response to the memory component test instruction sent by the processor, and a test result is obtained.

[0153] For example, the memory component test instruction can be a memory training instruction, a read-write operation instruction, or other test instructions that can test whether the memory component is in a normal working state.

[0154] In step 209, the test result is returned to the processor, so that the processor determines whether there is a faulty component in the memory component according to the test result, and obtains the fault information of the faulty component.

[0155] For example, the processor compares the test result and the expected result to obtain a comparison result, and determines whether there is a faulty component in the memory component according to the comparison result. For example, the fault information can be a component type of the faulty component and a number of the faulty components. For example, the component type can include a memory grain, a data line, a memory cell, or another memory component type.

[0156] For example, the memory component test instruction is a read operation instruction, the expected result is data written in the memory, the test result is a read value obtained from the memory, the read value is compared with the expected result, and whether there is a faulty component in the memory component is determined according to the comparison result.

[0157] Through the embodiments, the memory controller can still provide a linear memory space for the processor in the case that the memory grain is faulty, the data line is faulty, or the memory cell is faulty, to ensure that the data bit width of the memory access data is the same as the data bit width before the fault, and ensure that the system can work at the design frequency. The method of the embodiments can mask the memory fault, to realize normal startup of the operating system and normal running of the program, and can realize parallel performance of the processor verification and the memory optimization, to speed up the verification process after the board is made and the film is returned.

[0158] FIG. 6 is a framework diagram of a memory access system provided by an embodiment of the present application. Referring to FIG. 6, the system includes a processor core, a memory controller, a memory module, and an on-chip bus.

[0159] The memory controller includes a memory data access device, a control / calibration / physical layer (PHY), and an address resolution module. The memory data access device includes a memory configuration interface, an address space mapping table, a request prefetch module, and a data cache module. The memory module includes at least one memory grain. The control / calibration / physical layer and the memory module are connected with a data line, a control line, and an address line.

[0160] The memory data access device enables the memory controller to still provide a linear memory space for the processor core in the case that the memory cell is defective, or the memory grain is faulty, or the data line is faulty, to maintain the data bit width and ensure that the system works at the design frequency, support masking of the memory fault, realize startup of the operating system and running of the program, and enable the processor verification and the memory optimization to be performed in parallel, to speed up the verification process after the board is made and the film is returned.

[0161] For example, the memory data access device and its external interface are shown in the dashed box in FIG. 6. This part is integrated in the memory controller (DDRX controller IP), a memory controller hardware intellectual property (IP) core for controlling memory access and data transmission in a computer system, containing the interface between the processor and the memory and the related logic.

[0162] The memory data access device is connected to the network on chip (NoC) externally and connected to the address resolution, control / calibration / physical layer modules internally. The memory configuration interface supports the processor core to obtain the quality information of each particle and each data line of the memory through the network on chip and supports the processor core to write the address space mapping scheme that can mask the memory fault into the address space mapping table. The network on chip can be an AXI (Advanced eXtensible Interface) bus, a CHI (Coherent Hub Interface) bus, a Tilelink bus, etc.

[0163] The address space mapping table is maintained by hardware, and when the processor core sends a memory access request, it looks up the mapping table through the network on chip, splits one request into multiple requests, and sends multiple requests to the memory through the request prefetch module. The request prefetch module implements the scheduling and prefetching of multiple requests. The data cache module splices the data returned by multiple read requests and returns it to the processor core, and provides write data for the write request sent by the request prefetch module.

[0164] This embodiment selects an address space mapping scheme to mask the part of particles or data lines or memory units with poor signal quality, and only retains the memory that can work stably at the design frequency. A small memory system is constructed with these memory particles or data lines or memory units, only the memory capacity is reduced, but the entire system can work at the design frequency. By looking up the address space mapping table, the memory access request sent by the processor core is split, and the data returned by multiple read memory requests is combined, so that the data bit width of the processor core accessing the memory is guaranteed, the entire memory system can work stably without adjusting parameters, and the system can also run with memory fault masking.

[0165] The memory data access method of the present application will be further exemplified in combination with FIG. 6 and FIG. 7. Referring to FIG. 7, the method can include the following steps:

[0166] In step S1, the host software obtains the memory particle, data line or memory unit information through the memory configuration interface, and selects an address space mapping scheme corresponding to the failed memory component.

[0167] The memory configuration interface is used to obtain the information of the memory particles, data lines or memory units, so as to select different address space mapping schemes to shield the faulty memory particles, data lines or memory units. Specifically, the configuration software of the processor is used to obtain the test results returned by the memory controller when the memory component test instruction is executed on the memory component through the memory configuration interface. The test results are taken as the running information that can reflect the running state of the memory component, and whether there is a faulty component in the memory component is determined according to the test results.

[0168] In step S2, the address space mapping table is filled through the memory configuration interface by the host software or the embedded processor running program.

[0169] This step has been described in the foregoing step 203, and will not be repeated here.

[0170] In step S3, when the program runs, the host sends a memory access request, and the address space mapping table is searched through the memory interface, and the request is split into multiple requests.

[0171] The memory access request in this step is equivalent to the initial memory access instruction in the foregoing embodiment, and the multiple requests are equivalent to the multiple target memory access instructions in the foregoing embodiment. Specifically, the method of this step has been described in the foregoing steps 204 to 206, and will not be repeated here.

[0172] In step S4, when the program runs, the multiple read and write requests are scheduled and prefetched through the request prefetching module, the data returned by the multiple read requests is spliced through the data cache module, and then returned to the host, and the write data is provided for the write request sent by the request prefetching module.

[0173] For example, the faulty memory component is a memory particle, among the 8 memory particles, 2 memory particles are faulty and cannot work stably at the design frequency, so the effective memory capacity of the current memory module is 24G, and the effective data bit width of each memory access request is 48bit.

[0174] After the software obtains the above memory fault information, in order to ensure the data bit width of the processor core memory access request, the processor core visible memory space of each particle is calculated as 24G / 8=3G, the remaining memory capacity of the 6 available memory particles is (4G-3G)*6=6G, this part of the memory capacity is invisible to the processor core, and this part of the memory space is allocated to the 2 faulty memory particles respectively, the memory address mapping relationship is calculated and written into the address space mapping table.

[0175] Specifically, the processor core converts the read and write of the access address (denoted as address A) in the initial access instruction into N times of read and write after address space mapping table processing, where N is equal to the total number of particles divided by the available number of particles, and in this embodiment, the value of N is 2.

[0176] The address A of the first read and write is 6 available memory particles, and the address B of the second read and write is 2 available memory particles (the address B corresponds to the target address in the foregoing embodiment). The calculation formula of the address B is: A% (0x40000000) + 0xc0000000).

[0177] Meanwhile, in order to ensure that the write memory request is only written into 2 available memory particles, the data mask (DM_n) signals of the other 4 memory particles need to be configured as valid, so that the memory particles shield the received write operation data. For the memory particles that do not support data mask, more memory space needs to be reserved for shielding faults to meet the correctness requirement.

[0178] It should be noted that the embodiment of the present application uses a part of the memory space for shielding faults of memory access. If it is necessary to maximize the utilization of memory capacity, the memory module needs to support the data mask (DM) function, otherwise a part of the memory capacity will be wasted.

[0179] For example, the address space mapping scheme is shown in FIG. 5. Among them, the memory particles 3 and 6 cannot work at the designed frequency stably, and the processor core can see the memory address range as 0x00000000-0xbfffffff.

[0180] The processor core converts the read and write of the address A into two times of read and write after address space mapping table processing. The first read and write are performed on the memory particles 1, 2, 4, 5, 7 and 8 with the address A. If the address A belongs to the address range 0x00000000-0x3fffffff, the second read and write are performed on the memory particles 1 and 5 with the address B. If the address A belongs to the address range 0x40000000-0x7fffffff, the second read and write are performed on the memory particles 2 and 7 with the address B. If the address A belongs to the address range 0x80000000-0xbfffffff, the second read and write are performed on the memory particles 4 and 8 with the address B.

[0181] The correspondence between the memory address range and the memory particle can be arbitrarily specified and recorded in the address space mapping table. It should be noted that the mapping relationship described in this paragraph is only an example. All the data read by the data cache module is spliced and combined into the data bit width required by the processor core, and then returned to the processor core. In this embodiment, the data corresponding to a write request of the processor core is split into data of two times of write request and sent to the memory.

[0182] Compared with the memory particle failure, the corresponding memory address is inaccessible, and the memory address of the corresponding particle is still accessible when the partial data line fails, but the effective data bit width returned is reduced. Assuming that 3 of the 8 memory particles have 2 data lines failed respectively, the effective data bit width of each memory request is 58 bits.

[0183] An address mapping scheme is to regard the data bit width of a memory address as 58 bits, and store it continuously. The address of each memory access of the processor core is transformed, and the data of each memory access is split and spliced. For example, the processor core reads 64 bits of address addr=8, which is transformed into reading memory addresses 8, 9 after address mapping. The calculation formula of address mapping is: addr x 64 / 58, and the first read memory address is obtained by taking the integer part.

[0184] The calculation method of the number of memory reading is: if 64-(58-(addr x 64)%58)>58, then read 3 times, otherwise read 2 times. The data splicing rule is: select the high 58-(8x64)%58=10 bits of the read memory address 8, and the low 64-(58-(8x64)%58)=54 bits of the read memory address 9, and splice them into 64 bits to send back to the processor core. Similarly, the processor core reads 64 bits of address 9, which is transformed into reading memory addresses 9, 10, 11 after address mapping. The data cache module splices the high 4 bits of the read memory address 9, the 58 bits of the read memory address 10, and the low 2 bits of the read memory address 11 into 64 bits to send back to the processor core.

[0185] Another address mapping scheme is to reserve a memory space invisible to the processor core, similar to shielding partial memory particle failure. Each read and write memory access, the insufficient data bit width is supplemented by reading and writing this part of the reserved memory address space. In order to save memory space, the allocation of particle number and address can be in a round robin manner, that is, the same reserved memory address can be read and written for several times of read and write data bit width supplement, only the selected particle is different or the data line is different.

[0186] Compared with the memory particle failure and the data line failure, the partial memory unit failure can affect a relatively small range of memory addresses, but it can also cause memory read and write errors, thereby causing program running errors or processor core crashes.

[0187] The address space mapping scheme shielding the fault of the memory unit can reserve a smaller memory address space (for example, 4 MB per granule) invisible to the processor core, and record the fault memory unit address, the granule number, and the corresponding reserved memory address and granule number in the address space mapping table. When the processor core sends a read / write request, if a corresponding item is matched in the address space mapping table, the read / write request is split into two read / write requests to access the memory, the split data is written, and the read data is spliced. If there is no corresponding item in the address space mapping table, the shielding function of the fault memory access is closed, and the read / write request of the on-chip bus is directly transmitted to the memory controller IP, and the read / write data is directly transmitted.

[0188] Referring to FIG. 8, a memory data access device provided by an embodiment of the present application is shown, the device 30 comprising: an acquisition module 301 configured to acquire fault information of a memory component; a configuration module 302 configured to configure an address space mapping scheme according to the fault information; an extraction module 303 configured to extract a memory access address in an initial memory access instruction in response to the initial memory access instruction sent by a processor; a mapping processing module 304 configured to acquire a plurality of target addresses corresponding to the memory access address according to the memory access address and the address space mapping scheme; an instruction splitting module 305 configured to split the initial memory access instruction into a plurality of target memory access instructions according to the plurality of target addresses; the target memory access instructions and the target addresses correspond to each other; a first execution module 306 configured to execute the target memory access instructions through a memory controller to write split data obtained after splitting write data sent by the processor into the target addresses, and to splice read data read from the target addresses and then return the data to the processor.

[0189] Optionally, the configuration module 302 can comprise a first configuration sub-module configured to configure the address space mapping scheme according to the fault information through a software program; wherein the software program runs on an embedded processor added in the memory controller or runs in firmware added in the processor core.

[0190] Optionally, the device 30 further comprises a write-in module configured to write the address space mapping scheme into an address space mapping table through a memory configuration interface after configuring the address space mapping scheme according to the fault information. Correspondingly, the mapping processing module 304 can comprise a first acquisition sub-module configured to acquire the plurality of target addresses corresponding to the memory access address according to the memory access address and the address space mapping scheme recorded in the address space mapping table.

[0191] Optionally, the first execution module 306 can comprise a second acquisition sub-module configured to splice the read data read from the target addresses to obtain spliced data; a third acquisition sub-module configured to perform error checking and correction technology processing on the spliced data to obtain processed spliced data; and a return sub-module configured to return the processed spliced data to the processor.

[0192] Optionally, the mapping processing module 304 can comprise a fourth obtaining sub-module, configured to, in the case that there is a faulty component in at least part of the memory components, convert the memory access address into a first address and a second address according to the memory access address and the address space mapping scheme; wherein the first address is used to obtain data of all normal components in the memory components, and the second address is used to obtain data of a preset number of normal components among all the normal components; the preset number is equal to the number of the faulty components.

[0193] Optionally, in the case that the memory components are memory particles, the first address is the memory access address, and the mapping processing module 304 can comprise a fifth obtaining sub-module, configured to obtain a first address space visible to the processor and a second address space invisible to the processor in the memory address space; a ratio of an interval size of the first address space to an interval size of the second address space is equal to a ratio of a total memory capacity of all normal memory particles to a total memory capacity of all faulty memory particles; the memory access address is an address in the first address space; and a first conversion sub-module, configured to convert the memory access address into the second address according to the address space mapping scheme, the second address being in the second address space.

[0194] Optionally, in the case that the number of the faulty memory particles is less than the number of the normal memory particles, the mapping processing module 304 can comprise a sixth obtaining sub-module, configured to obtain a plurality of first sub-address spaces included in the first address space; a first sub-address space corresponds to a preset number of normal memory particles; a first determining sub-module, configured to determine a target first sub-address space in which the memory access address is located from the plurality of first sub-address spaces; and a second determining sub-module, configured to determine, as the normal component corresponding to the second address, the normal memory particle corresponding to the target first sub-address space.

[0195] Optionally, in the case that the memory components are data lines, the data lines being used to transmit data between the memory particles and the memory controller, the mapping processing module 304 can comprise a seventh obtaining sub-module, configured to obtain a product of the memory access address and the number of all data lines; an eighth obtaining sub-module, configured to obtain a ratio of the product to the number of all normal data lines; a third determining sub-module, configured to determine, according to the ratio, a start address in a plurality of target addresses and a normal data line corresponding to the start address; and a fourth determining sub-module, configured to determine, according to the start address and the number of all normal data lines corresponding to the start address, other target addresses and normal data lines corresponding to each of the other target addresses, with the number of all normal data lines corresponding to all the target addresses being equal to the number of all data lines in the memory as an allocation strategy.

[0196] Optionally, in the case that the memory component is a data line, the data line is used for transmitting data between the memory cell and the memory controller, and the first address is a memory access address; the mapping processing module 304 can comprise: a ninth obtaining sub-module, configured to obtain a third address space visible to the processor and a fourth address space invisible to the processor in a memory address space; a ratio of an interval size of the third address space to an interval size of the fourth address space is equal to a ratio of a number of normal data lines to a number of faulty data lines, and the memory access address is in the third address space; and a second conversion sub-module, configured to convert the memory access address into the second address according to an address space mapping scheme, and the second address is in the fourth address space.

[0197] Optionally, the mapping processing module 304 can comprise: a first selecting sub-module, configured to select a preset number of normal data lines from all normal data lines; and a fifth determining sub-module, configured to determine the preset number of normal data lines as normal components corresponding to the second address.

[0198] Optionally, in the case that the memory component is a memory cell in the memory cell, the first address is a memory access address, and the mapping processing module 304 can comprise: a tenth obtaining sub-module, configured to obtain a fifth address space visible to the processor and a sixth address space invisible to the processor in a memory address space, the sixth address space having a size equal to a preset address space size, and the memory access address being in the fifth address space; an eleventh obtaining sub-module, configured to obtain a faulty memory address corresponding to a faulty memory cell; and a third conversion sub-module, configured to convert the memory access address into the second address according to an address space mapping scheme in the case that the memory access address is equal to the faulty memory address, and the second address being in the sixth address space.

[0199] Optionally, the mapping processing module 304 can comprise: a second selecting sub-module, configured to select a preset number of normal memory cells from normal memory cells corresponding to the second address; and a sixth determining sub-module, configured to determine the selected preset number of normal memory cells as normal components corresponding to the second address.

[0200] Optionally, the apparatus 30 further comprises: a second execution module, configured to, in response to the memory component test instruction sent by the processor, perform a read-write operation on the memory component to obtain a test result before extracting the memory access address in the initial memory access instruction in response to the initial memory access instruction sent by the processor; and a return module, configured to return the test result to the processor, so that the processor determines whether there is a faulty component in the memory component according to the test result and obtains fault information of the faulty component.

[0201] The embodiment does not need to replace the memory component, and does not need to solve the memory failure by reducing the memory working frequency and adjusting the memory parameters, and can avoid the signal integrity problem caused by the uneven PCB wiring in the case of the failure of the memory component, can avoid the damage of the board caused by replacing the memory particles, and can ensure that the memory can work at the design frequency.

[0202] Fig. 9 is a block diagram of an electronic device 700 according to an exemplary embodiment. The electronic device 700 can be, for example, a computer, a tablet device, a personal digital assistant, etc. Referring to Fig. 9, the electronic device 400 can include one or more of the following components: a processing component 402, a memory 404, a power supply component 406, a multimedia component 408, an audio component 410, an input / output (I / O) interface 412, a sensor component 414, and a communication component 416.

[0203] The processing component 402 usually controls overall operations of the electronic device 400. The processing component 402 can include one or more processors 420 to execute instructions to complete all or part of steps of the above methods. In addition, the processing component 402 can include one or more modules to facilitate the interaction between the processing component 402 and other components. For example, the processing component 402 can include a multimedia module to facilitate the interaction between the multimedia component 408 and the processing component 402. The memory 404 is used to store various types of data to support operations of the electronic device 400.

[0204] The power supply component 406 supplies various components of the electronic device 400 with power. The power supply component 406 can include a power supply management system, one or more power supplies, and other components associated with generating, managing and distributing power for the electronic device 400. The multimedia component 408 includes a screen to provide an output interface between the electronic device 400 and a user. The audio component 410 is used to output and / or input audio signals. The I / O interface 412 provides an interface between the processing component 402 and peripheral interface modules. The sensor component 414 includes one or more sensors to provide various state assessments for the electronic device 400. The communication component 416 is used to facilitate wired or wireless communication between the electronic device 400 and other devices in accordance with a communication standard.

[0205] Optionally, a non-transitory computer readable storage medium including instructions, such as the memory 404 including instructions, is also provided, which can be executed by the processor 420 of the electronic device 400 to complete the above method.

[0206] FIG. 10 is a block diagram illustrating an electronic device 500 according to an exemplary embodiment. For example, the electronic device 500 can be provided as a server. Referring to FIG. 10, the electronic device 500 includes a processing component 522, further including one or more processors, and a memory resource represented by a memory 532, for storing instructions executable by the processing component 522, such as an application program. The application program stored in the memory 532 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 522 is configured to execute the instructions to perform a method for accessing memory data provided by the embodiments of the present application.

[0207] The electronic device 500 can further include a power supply component 526 configured to perform power management of the electronic device 500, a wired or wireless network interface 550 configured to connect the electronic device 500 to a network, and an input / output (I / O) interface 555. The electronic device 500 can operate based on an operating system stored in the memory 532, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

[0208] The embodiments of the present application also provide a computer program product, including a computer program, which, when executed by a processor, implements a method for accessing memory data.

[0209] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0210] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0211] In the embodiments of the present application, it should be understood that the disclosed apparatus and method can be implemented in other manners. For example, the embodiments of the apparatus described above are merely schematic; the division of the units is merely logical function division; an actual implementation can be another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0212] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0213] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can be a physically independent unit, or two or more units can be integrated into a unit.

[0214] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus necessary general hardware platforms, and of course can also be implemented by hardware, but in many cases the former is a better implementation manner. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product in essence or in the form of a part of the prior art that makes a contribution. The computer software product is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk), and includes a plurality of instructions for causing a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in the various embodiments of the present application.

[0215] It can be understood that the embodiments described in the embodiments of the present application can be realized by hardware, software, firmware, middleware, microcode or a combination thereof. For hardware implementation, the modules, units, sub-units can be implemented in one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, micro-controllers, microprocessors, other electronic units for performing the functions described in the present application, or a combination thereof.

[0216] For software implementation, the technologies described in the embodiments of the present application can be implemented by modules (for example, processes, functions, etc.) for performing the functions described in the embodiments of the present application. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0217] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the present application cover any and all variations of the application that come within the scope of the present application, along with all equivalents and alternatives falling within the scope of the present application. It is intended that the description and examples be considered exemplary only, with the true scope and spirit of the application indicated by the following claims.

[0218] It should be understood that the present application is not limited to the precise construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present application. The scope of the present application is limited only by the appended claims.

[0219] The above merely provides the preferred embodiments of the present application, and is not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. The above provides a memory data access method, device, electronic equipment and readable storage medium, and the present application applies specific examples to describe the principles and implementation manners of the present application; the above embodiment description is only used to help understand the method and core idea of the present application; meanwhile, for those skilled in the art, the specific implementation manners and application scope can be changed according to the idea of the present application; in conclusion, the content of the specification should not be understood as limiting the present application.

Claims

1. A method for accessing memory data, comprising: Get the fault information of the memory component; According to the fault information, configure an address space mapping scheme; In response to an initial memory access instruction sent by the processor, extracting a memory access address in the initial memory access instruction; According to the memory access address and the address space mapping scheme, acquiring a plurality of target addresses corresponding to the memory access address; According to the multiple target addresses, the initial memory access instruction is split into multiple target memory access instructions; the target memory access instructions correspond to the target addresses in a one-to-one manner; The target memory access instruction is executed by the memory controller to write the split data obtained after splitting the write data sent by the processor into the target address; the read data read from the target address is spliced ​​and then returned to the processor.

2. The method according to claim 1, wherein The configuring an address space mapping scheme for the fault information includes: configuring the address space mapping scheme according to the fault information through a software program; The software program runs on an embedded processor added to the memory controller, or runs in firmware added to a processor core.

3. The method according to claim 2, wherein: After configuring an address space mapping solution according to the fault information, the method further includes: Writing the address space mapping scheme into the address space mapping table through the memory configuration interface; The acquiring, according to the memory access address and the address space mapping scheme, a plurality of target addresses corresponding to the memory access address comprises: According to the memory access address and the address space mapping scheme recorded in the address space mapping table, a plurality of target addresses corresponding to the memory access address are acquired.

4. The method according to claim 1, wherein The step of splicing the read data read from the target address and then returning the spliced ​​data to the processor includes: splicing the read data read from the target address to obtain spliced ​​data; performing error checking and correction technology processing on the spliced ​​data to obtain processed spliced ​​data; The processed spliced ​​data is returned to the processor.

5. The method according to claim 1, wherein The acquiring, according to the memory access address and the address space mapping scheme, a plurality of target addresses corresponding to the memory access address comprises: In a case where a faulty component exists in at least some of the memory components in the memory, converting the memory access address into a first address and a second address according to the memory access address and the address space mapping scheme; The first address is used to obtain data of all normal components in the memory component, and the second address is used to obtain data of a preset number of normal components in all the normal components; the preset number and the faulty component The number of pieces is equal.

6. The method according to claim 5, wherein: In a case where the memory component is a memory chip, the first address is the memory access address, and acquiring a plurality of target addresses corresponding to the memory access address according to the memory access address and the address space mapping scheme includes: Obtaining a first address space visible to the processor and a second address space invisible to the processor in the memory address space; a ratio of an interval size of the first address space to an interval size of the second address space is equal to a ratio of a total memory capacity of all normal memory cells to a total memory capacity of all faulty memory cells; the memory access address is an address within the first address space; According to the address space mapping scheme, the memory access address is converted into the second address, and the second address is in the second address space.

7. The method according to claim 6, wherein: In a case where the number of the faulty memory cells is less than the number of the normal memory cells, acquiring a plurality of target addresses corresponding to the memory access address according to the memory access address and the address space mapping scheme includes: Acquire a plurality of first sub-address spaces included in the first address space; the first sub-address spaces correspond to the preset number of normal memory particles; Determining a target first sub-address space where the memory access address is located from the plurality of first sub-address spaces; The normal memory particles corresponding to the target first sub-address space are determined as normal components corresponding to the second address.

8. The method according to claim 5, wherein In a case where the memory component is a data line and the data line is used to transmit data between a memory chip and the memory controller, acquiring a plurality of target addresses corresponding to the memory access address according to the memory access address and the address space mapping scheme includes: Obtaining the product of the memory access address and the number of all the data lines; Obtaining a ratio of the product to the number of all normal data lines; determining a start address among the plurality of target addresses and a normal data line corresponding to the start address according to the ratio; The allocation strategy is that the number of all normal data lines corresponding to all target addresses is equal to the number of all data lines in the memory. According to the starting address and the number of all normal data lines corresponding to the starting address, the other target addresses and the normal data lines corresponding to each other target address are determined.

9. The method according to claim 5, wherein: In a case where the memory component is a data line used for transmitting data between a memory chip and the memory controller, the first address is the memory access address; The acquiring, according to the memory access address and the address space mapping scheme, a plurality of target addresses corresponding to the memory access address comprises: Obtain a third address space visible to the processor and a fourth address space invisible to the processor in the memory address space; the ratio of the interval size of the third address space to the interval size of the fourth address space is equal to the ratio of the number of normal data lines to the number of faulty data lines, and the memory access address is in the third address space. between; According to the address space mapping scheme, the memory access address is converted into the second address, and the second address is in the fourth address space.

10. The method according to claim 9, wherein: The acquiring, according to the memory access address and the address space mapping scheme, a plurality of target addresses corresponding to the memory access address comprises: Selecting the preset number of normal data lines from all normal data lines; The preset number of normal data lines are determined as normal components corresponding to the second address.

11. The method according to claim 5, wherein: In a case where the memory component is a memory unit in a memory chip, the first address is the memory access address, and acquiring a plurality of target addresses corresponding to the memory access address according to the memory access address and the address space mapping scheme includes: Acquire, in the memory address space, a fifth address space visible to the processor and a sixth address space invisible to the processor, wherein a size of the sixth address space is equal to a preset address space size, and the memory access address is in the fifth address space; Obtain the faulty memory address corresponding to the faulty memory unit; In a case where the memory access address is equal to the faulty memory address, the memory access address is converted into the second address according to the address space mapping scheme, and the second address is in the sixth address space.

12. The method according to claim 11, wherein The acquiring, according to the memory access address and the address space mapping scheme, a plurality of target addresses corresponding to the memory access address comprises: Selecting the preset number of normal memory cells from the normal memory cells corresponding to the second address; The selected preset number of normal memory cells are determined as normal components corresponding to the second address.

13. The method according to claim 1, wherein Before extracting the memory access address in the initial memory access instruction sent by the processor in response to the initial memory access instruction, the method further includes: In response to the memory component test instruction sent by the processor, performing a read and write operation on the memory component to obtain a test result; The test result is returned to the processor, so that the processor can determine whether there is a faulty component in the memory component according to the test result, and obtain the fault information of the faulty component.

14. A device for accessing memory data, the device comprising: An acquisition module, used to obtain fault information of a memory component; A configuration module, configured to configure an address space mapping scheme according to the fault information; an extraction module, configured to extract a memory access address in the initial memory access instruction in response to the initial memory access instruction sent by the processor; A mapping processing module, configured to obtain a plurality of target addresses corresponding to the memory access address according to the memory access address and the address space mapping scheme; an instruction splitting module, configured to split the initial memory access instruction into a plurality of target memory access instructions according to the plurality of target addresses; the target memory access instructions and the target addresses having a one-to-one correspondence; The first execution module is used to execute the target memory access instruction through the memory controller to write the split data obtained after splitting the write data sent by the processor into the target address; and splice the read data read from the target address and then return it to the processor.

15. The device according to claim 14, wherein The configuration module includes: The first configuration submodule is used to configure an address space mapping scheme for fault information through a software program; wherein the software program runs on an embedded processor added to the memory controller, or runs in firmware added to the processor core.

16. The device according to claim 15, wherein The device further comprises: A writing module is used to write the address space mapping scheme into the address space mapping table through the memory configuration interface after configuring the address space mapping scheme according to the fault information; The mapping processing module includes: a first acquisition submodule, which is used to acquire multiple target addresses corresponding to the memory access address according to the memory access address and the address space mapping scheme recorded in the address space mapping table.

17. An electronic device, wherein: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method according to any one of claims 1 to 13.

18. A computer-readable storage medium, wherein: When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method according to any one of claims 1 to 13.

19. A computer program product, the computer program product being stored in a non-transitory storage medium, the computer program product being executed by at least one processor to implement the method according to any one of claims 1 to 13.

20. An apparatus / device for accessing memory data, comprising the apparatus / device (configured to) be used in the method according to any one of claims 1 to 13.

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