Laser chip fabrication method, laser chip and optical module

Abstract

Provided in the present disclosure are a laser chip fabrication method, a laser chip and an optical module. The laser chip fabrication method comprises: growing a laser epitaxial layer on a substrate; etching an initial modulation region on the laser epitaxial layer so as to form an initial light-emitting region on a side edge of the initial modulation region; growing a modulator epitaxial layer in the initial modulation region, and forming an initial butt joint region at a butt joint position of the modulator epitaxial layer and the initial light-emitting region; growing a waveguide layer at the top of the modulator epitaxial layer and the top of the initial light-emitting region; forming a butt joint opening, the butt joint opening spanning across the initial butt joint region, and in a light field transmission direction of the laser chip, forming a light emitting region on one side of the butt joint opening, and forming a modulation region on the other side of the butt joint opening; and growing a but joint waveguide in the butt joint opening, the butt-joint waveguide connecting the light-emitting region and the modulation region, the butt-joint waveguide comprising a wrapping layer and a butt-joint waveguide layer, the wrapping layer wrapping the butt-joint waveguide layer, and the refractive index of the butt-joint waveguide layer being greater than that of the wrapping layer.

Description

Laser chip preparation method, laser chip and optical module

[0001] This application claims priority to application number 202410442333.3 filed on April 12, 2024 with the China Patent Office; and priority to application number 202410444334.1 filed on April 12, 2024 with the China Patent Office; all contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of optical communication technology, and in particular to a laser chip manufacturing method, a laser chip, and an optical module. Background Art

[0003] With the rapid development of application markets such as big data, cloud computing, and artificial intelligence, the demand for data communication optical modules is also increasing rapidly. The optical device industry continues to develop towards higher speeds and lower power consumption. As key optical devices in optical communications, semiconductor laser chips face higher challenges. The demand for electro-absorption moduled laser chips (EML) is gradually shifting from 10G to 56G and 100G.

[0004] EML laser chips include distributed feedback lasers (DFBs) and electro-absorption modulators (EAMs). EML laser chips should have higher modulation rates, higher modulation efficiency, and wide operating temperature capabilities to meet the high-speed requirements of optical modules.

[0005] Summary of the Invention

[0006] In a first aspect, the present disclosure provides a method for preparing a laser chip, which is configured to prepare a laser chip configured to generate an optical signal; the method comprises:

[0007] growing a laser epitaxial layer on a substrate, wherein the laser epitaxial layer comprises a first lower confinement layer, a first active layer, a first upper confinement layer and a grating layer;

[0008] Etching an initial modulation area on the laser epitaxial layer to form an initial light-emitting area on the side of the initial modulation area;

[0009] Growing a modulator epitaxial layer in the initial modulation region, where the modulation epitaxial layer and the initial light-emitting region are joined to form an initial joint region, the modulator epitaxial layer comprising a second lower confinement layer, a second active layer and a second upper confinement layer;

[0010] A waveguide layer is grown on top of the modulator epitaxial layer and on top of the initial light emitting region, the waveguide layer includes a first waveguide layer and a second waveguide layer, the first waveguide layer is above the grating layer, and the second waveguide layer is above the second upper confinement layer;

[0011] An abutment opening is opened, the abutment opening crosses the initial abutment region, and the bottom of the abutment opening extends below the first active layer and the second active layer, one side of the abutment opening forms a light emitting region in the light field transmission direction of the laser chip, and the other side of the abutment opening forms a modulation region; the light emitting region generates light, and the modulation region modulates the light generated by the light emitting region;

[0012] An abutment waveguide is grown in the abutment opening, the abutment waveguide abuts the light emitting region and the modulation region, the abutment waveguide includes a cladding layer and an abutment waveguide layer, the cladding layer wraps the abutment waveguide layer, and the refractive index of the abutment waveguide layer is greater than the refractive index of the cladding layer;

[0013] In the light field transmission direction, the light emitting region and the modulation region are shallowly etched to form a shallow etching part of the first ridge waveguide in the light emitting region and a shallow etching part of the second ridge waveguide in the modulation region, and the first ridge waveguide is connected to the shallow etching part; wherein one side of the first ridge waveguide forms a first groove, the other side of the first ridge waveguide forms a second groove, one side of the shallow etching part forms a third initial groove, and the other side of the shallow etching part forms a fourth initial groove;

[0014] A dielectric film is deposited, the dielectric film covers the surfaces of the first groove, the second groove, the third initial groove and the fourth initial groove, and the top surfaces of the first ridge waveguide and the shallow etching part;

[0015] The dielectric film on the bottom surfaces of the third initial groove and the fourth initial groove is etched;

[0016] The bottom surface of the third initial groove is etched to form a third groove, and the bottom surface of the fourth initial groove is etched to form a fourth groove, to form a deep etching part below the shallow etching part, and the width of the deep etching part is greater than the width of the shallow etching part;

[0017] The residual dielectric film is removed, and a step surface is formed at the connection between the shallow etching part and the deep etching part.

[0018] In a second aspect, the disclosure provides a laser chip configured to generate an optical signal; comprising:

[0019] A light emitting region configured to generate light, the light emitting region includes a first substrate layer, a first lower confinement layer, a first active layer, a first upper confinement layer, a grating layer and a first waveguide layer from bottom to top; the light emitting region is provided with a first ridge waveguide, one side of the first ridge waveguide is provided with a first groove, and the other side of the first ridge waveguide is provided with a second groove;

[0020] The modulation region is configured to modulate the light generated by the light-emitting region. The modulation region comprises, from bottom to top, a second substrate layer, a second lower confinement layer, a second active layer, a second upper confinement layer, and a second waveguide layer. The second substrate layer is connected to the first substrate layer. The modulation region is provided with a second ridge waveguide. One side of the second ridge waveguide is provided with a third groove, and the other side of the second ridge waveguide is provided with a fourth groove. The second ridge waveguide comprises a shallow etching part and a deep etching part. The shallow etching part is located above the deep etching part. The width of the deep etching part is greater than the width of the shallow etching part. A step surface is formed at the connection between the shallow etching part and the deep etching part. The shallow etching part is connected to the first ridge waveguide.

[0021] The butt joint region is connected to the light-emitting region at one end and connected to the modulation region at the other end. The butt joint region comprises a butt joint waveguide. The butt joint waveguide is connected to the light-emitting region and the modulation region. The butt joint waveguide comprises a cladding layer and a butt joint waveguide layer. The cladding layer wraps the butt joint waveguide layer. The refractive index of the butt joint waveguide layer is greater than the refractive index of the cladding layer.

[0022] In a third aspect, the present disclosure provides an optical module, comprising: a circuit board;

[0023] A light-emitting component is electrically connected to the circuit board.

[0024] The light-emitting component comprises:

[0025] A socket is provided with a pin to electrically connect the circuit board through the pin.

[0026] A cap is arranged on the top of the socket to form a containing cavity with the socket.

[0027] A laser chip is arranged in the containing cavity and configured to generate an optical signal. The laser chip is prepared by the laser chip preparation method of the first aspect or the laser chip of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings used in some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure. Those skilled in the art can also obtain other drawings from these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0029] FIG. 1 is a partial architecture diagram of an optical communication system according to some embodiments of the present disclosure;

[0030] FIG. 2 is a partial structure diagram of an upper computer according to some embodiments of the present disclosure;

[0031] FIG. 3 is a structure diagram of an optical module according to some embodiments of the present disclosure;

[0032] FIG. 4 is an exploded view of a light module according to some embodiments of the present disclosure;

[0033] FIG. 5 is a structural diagram of a light emitting component according to some embodiments of the present disclosure;

[0034] FIG. 6 is an exploded view of a light emitting component according to some embodiments of the present disclosure;

[0035] FIG. 7 is a structural diagram of a laser chip according to some embodiments of the present disclosure;

[0036] FIG. 8 is an exploded structural diagram of a laser chip according to some embodiments of the present disclosure;

[0037] FIG. 9 is a partial enlarged view of A in FIG. 8;

[0038] FIG. 10 is a partial enlarged view of B in FIG. 8;

[0039] FIG. 11 is a partial enlarged view of C in FIG. 8;

[0040] FIG. 12 is a cross-sectional structural diagram of a light emitting region according to some embodiments of the present disclosure;

[0041] FIG. 13 is a cross-sectional structural diagram of a modulation region according to some embodiments of the present disclosure;

[0042] FIG. 14 is a cross-sectional structural diagram of a light emitting region and a modulation region directly abutting according to some embodiments of the present disclosure;

[0043] FIG. 15 is a use state diagram of an abutting region according to some embodiments of the present disclosure;

[0044] FIG. 16 is a diagram of the relationship between the thickness of an abutting waveguide layer and the transmittance of an abutting region according to some embodiments of the present disclosure;

[0045] FIG. 17 is a flowchart of a laser chip preparation method according to some embodiments of the present disclosure;

[0046] FIG. 18 is a flowchart of a laser chip preparation method according to some embodiments of the present disclosure;

[0047] FIG. 19 is a flowchart of another laser chip preparation method according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0048] Some embodiments of the present disclosure will be described in detail below with reference to the drawings. However, the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0049] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is to be interpreted as open, inclusive language that means "including, but not limited to"; the terms "first", "second", etc. are not intended to imply or indicate relative importance or indicate the upper limit of the number; the term "multiple" means two or more; the term "connected" should be interpreted broadly, for example, "connected" can be fixed connection, or detachable connection, or integrated, can be directly connected, or indirectly connected through an intermediate medium; the use of the terms "adapted to" or "configured to" means open and inclusive language, which does not exclude devices adapted to or configured to perform additional tasks or steps; the terms "parallel", "vertical", "same", "consistent", "flush" and the like are not limited to absolute mathematical relationships, but also include acceptable error ranges generated in practice, and also include differences based on the same design concept but due to manufacturing reasons.

[0050] In optical communication technology, in order to establish information transmission between information processing devices, information needs to be loaded onto light, and the transmission of information is realized by the propagation of light. Here, the light loaded with information is an optical signal. The optical signal can reduce the loss of optical power when transmitted in the information transmission device, so as to realize high-speed, long-distance and low-cost information transmission. The signal that can be recognized and processed by the information processing device is an electrical signal. The information processing device usually includes an optical network terminal (Optical Network Unit, ONU), a gateway, a router, a switch, a mobile phone, a computer, a server, a tablet computer, a television, etc., and the information transmission device usually includes an optical fiber and an optical waveguide, etc.

[0051] The optical module can realize mutual conversion between optical signals and electrical signals between the information processing device and the information transmission device. For example, at least one of the optical signal input end or the optical signal output end of the optical module is connected with an optical fiber, and at least one of the electrical signal input end or the electrical signal output end of the optical module is connected with an optical network terminal; a first optical signal from the optical fiber is transmitted to the optical module, the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the optical network terminal; a second electrical signal from the optical network terminal is transmitted to the optical module, the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber. Since information transmission can be performed between multiple information processing devices through electrical signals, at least one of the multiple information processing devices needs to be directly connected with the optical module, without the need for all the information processing devices to be directly connected with the optical module. Here, the information processing device directly connected with the optical module is referred to as a host computer of the optical module. In addition, the optical signal input end or the optical signal output end of the optical module can be referred to as an optical port, and the electrical signal input end or the electrical signal output end of the optical module can be referred to as an electrical port.

[0052] FIG. 1 is a partial structure diagram of an optical communication system according to some embodiments of the present disclosure. As shown in FIG. 1, the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, a host computer 100, an optical module 200, an optical fiber 101, and a network cable 103.

[0053] One end of the optical fiber 101 extends to the direction of the remote information processing device 1000, and the other end of the optical fiber 101 is connected with the optical module 200 through the optical port of the optical module 200. The optical signal can be totally reflected in the optical fiber 101, and the propagation of the optical signal in the totally reflected direction can almost maintain the original optical power. The optical signal is totally reflected multiple times in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or to transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby realizing long-distance and low-power-loss information transmission.

[0054] The optical communication system can include one or more optical fibers 101, and the optical fiber 101 can be detachably connected with the optical module 200 or fixedly connected. The host computer 100 is configured to provide a data signal to the optical module 200, or receive a data signal from the optical module 200, or monitor or control the working state of the optical module 200.

[0055] The host computer 100 includes a housing substantially in the shape of a rectangular cuboid, and an optical module interface 102 disposed on the housing. The optical module interface 102 is configured to access the optical module 200, so as to establish a one-way or two-way electrical signal connection between the host computer 100 and the optical module 200.

[0056] The host computer 100 further comprises an external electrical interface configured to access an electrical signal network. For example, the external electrical interface comprises a Universal Serial Bus (USB) interface or a network cable interface 104 configured to access a network cable 103 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the network cable 103. One end of the network cable 103 is connected to the local information processing device 2000, and the other end of the network cable 103 is connected to the host computer 100 to establish an electrical signal connection between the local information processing device 2000 and the host computer 100 through the network cable 103. For example, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103, and the host computer 100 generates a second electrical signal according to the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200, and the optical module 200 converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber 101. The second optical signal is transmitted in the optical fiber 101 to the remote information processing device 1000. For example, the first optical signal from the remote information processing device 1000 is transmitted through the optical fiber 101, the first optical signal from the optical fiber 101 is transmitted to the optical module 200, the optical module 200 converts the first optical signal into a first electrical signal, the optical module 200 transmits the first electrical signal to the host computer 100, the host computer 100 generates a fourth electrical signal according to the first electrical signal, and the fourth electrical signal is transmitted to the local information processing device 2000. It should be noted that the optical module is a tool for converting optical signals and electrical signals, and the information does not change in the conversion process of the optical signals and the electrical signals, and the encoding and decoding mode of the information can change.

[0057] In addition to the optical network terminal, the host computer 100 further comprises an optical line terminal (OLT), an optical network terminal (ONT), or a data center server, etc.

[0058] FIG. 2 is a partial structure diagram of a host computer according to some embodiments of the present disclosure. In order to clearly show the connection relationship between the optical module 200 and the host computer 100, FIG. 2 only shows the structure of the host computer 100 related to the optical module 200. As shown in FIG. 2, the host computer 100 further comprises a PCB circuit board 105 arranged in the shell, a cage 106 arranged on the surface of the PCB circuit board 105, a heat sink 107 arranged on the cage 106, and an electrical connector arranged inside the cage 106. The electrical connector is configured to access the electrical port of the optical module 200; the heat sink 107 has a protruding structure such as fins to increase the heat dissipation area.

[0059] The optical module 200 is inserted into the cage 106 of the host computer 100, and the optical module 200 is fixed by the cage 106. The heat generated by the optical module 200 is conducted to the cage 106, and then diffused through the heat sink 107. After the optical module 200 is inserted into the cage 106, the electrical port of the optical module 200 is connected with the electrical connector inside the cage 106, so that the optical module 200 and the host computer 100 establish a bidirectional electrical signal connection. In addition, the optical port of the optical module 200 is connected with the optical fiber 101, so that the optical module 200 and the optical fiber 101 establish a bidirectional optical signal connection.

[0060] FIG. 3 is a structural diagram of an optical module according to some embodiments of the present disclosure, and FIG. 4 is an exploded view of an optical module according to some embodiments of the present disclosure. As shown in FIGS. 3 and 4, the optical module 200 includes a shell, a circuit board 300 arranged in the shell, an optical transmitting component 400, and an optical receiving component 500. However, the present disclosure is not limited thereto, and in some embodiments, the optical module 200 includes one of the optical transmitting component 400 and the optical receiving component 500.

[0061] The shell includes an upper shell 201 and a lower shell 202. The upper shell 201 is covered on the lower shell 202 to form the above-mentioned shell having two openings 203 and 204. The outer contour of the shell generally presents a square body.

[0062] In some embodiments, the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 arranged perpendicularly to the bottom plate 2021 on both sides of the bottom plate 2021. The upper shell 201 includes a cover plate 2011, and the cover plate 2011 is covered on the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.

[0063] In some embodiments, the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 arranged perpendicularly to the bottom plate 2021 on both sides of the bottom plate 2021. The upper shell 201 includes a cover plate 2011 and two upper side plates 2012 arranged perpendicularly to the cover plate 2011 on both sides of the cover plate 2011. The two upper side plates 2012 and the two lower side plates 2022 are combined to realize that the upper shell 201 is covered on the lower shell 202.

[0064] The direction of the line connecting the two openings 203 and 204 can be consistent with the length direction of the optical module 200, or can be inconsistent with the length direction of the optical module 200. For example, the opening 203 is located at the end of the optical module 200 (the right end of FIG. 3), and the opening 204 is also located at the end of the optical module 200 (the left end of FIG. 3). Alternatively, the opening 203 is located at the end of the optical module 200, and the opening 204 is located at the side of the optical module 200. The opening 203 is an electrical port, and the gold fingers 301 of the circuit board 300 extend from the opening 203 and are inserted into the electrical connector of the host computer 100. The opening 204 is an optical port configured to access the external optical fiber 101, so that the optical fiber 101 connects the optical transmitting component 400 and the optical receiving component 500 in the optical module 200.

[0065] The assembly of the upper shell 201 and the lower shell 202 facilitates the installation of the circuit board 300, the optical transmitting component 400, the optical receiving component 500, etc. in the shells, and the shells can protect the above-mentioned devices. In addition, when assembling the circuit board 300, the optical transmitting component 400, and the optical receiving component 500, etc., the positioning components, heat dissipation components, and electromagnetic shielding components of these devices can be easily deployed, which facilitates automated production.

[0066] In some embodiments, the upper shell 201 and the lower shell 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0067] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside the shell of the optical module 200. The unlocking component 600 is configured to achieve fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0068] For example, the unlocking component 600 is located outside the two lower side plates 2022 of the lower shell 202 and includes a clamping component matched with the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the clamping component of the unlocking component 600 fixes the optical module 200 in the cage 106. When the unlocking component 600 is pulled, the clamping component of the unlocking component 600 moves, thereby changing the connection relationship between the clamping component and the host computer, to release the fixation between the optical module 200 and the host computer, so that the optical module 200 can be pulled out of the cage 106.

[0069] The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to circuit design through the circuit traces to realize power supply, electrical signal transmission, and grounding, etc. The electronic components may, for example, include capacitors, resistors, transistors, and Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). The chips may, for example, include Microcontroller Units (MCUs), laser drive chips, Transimpedance Amplifiers (TIAs), Limiting Amplifiers (LAs), Clock and Data Recovery (CDR) chips, power management chips, and Digital Signal Processing (DSP) chips.

[0070] The circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize a bearing function, such as stably bearing the above-mentioned electronic components and chips. The rigid circuit board can also be inserted into the electrical connector in the cage 106 of the host computer 100.

[0071] The circuit board 300 also includes a gold finger 301 formed on the surface of the end thereof. The gold finger 301 is composed of a plurality of pins independent of each other. The circuit board 300 is inserted into the cage 106, and the gold finger 301 is in conduction with the electrical connector in the cage 106. The gold finger 301 can be provided only on the surface (e.g., the upper surface shown in FIG. 4) of one side of the circuit board 300, or can be provided on the surfaces of both upper and lower sides of the circuit board 300 to provide a larger number of pins, thereby adapting to occasions requiring a large number of pins. The gold finger 301 is configured to establish electrical connection with the host computer to realize power supply, grounding, Inter-Integrated Circuit (I2C) signal transmission, data signal transmission, etc. Of course, flexible circuit boards are also used in some optical modules. The flexible circuit board is generally used in cooperation with the rigid circuit board to supplement the rigid circuit board.

[0072] At least one of the optical transmitting component 400 or the optical receiving component 500 is located on the side of the circuit board 300 away from the gold finger 301.

[0073] In some embodiments, the optical transmitting component 400 and the optical receiving component 500 are physically separated from the circuit board 300, and then are electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors, respectively.

[0074] In some embodiments, at least one of the light emitting component or the light receiving component can be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component can be disposed on a surface of the circuit board 300 or a side of the circuit board 300.

[0075] As shown in FIG. 4, in the optical module provided by the embodiment, the light emitting component 400 and the light receiving component 500 are disposed on a round square tube body. The light emitting component 400 is configured to generate and output signal light, and the light receiving component 500 is configured to receive signal light from outside the optical module. A fiber adapter is disposed on the round square tube body, and the fiber adapter is configured to realize the connection between the optical module and an external optical fiber. A lens assembly is usually disposed in the round square tube body, and the lens assembly is configured to change the propagation direction of the signal light output by the light emitting component 400 or the signal light input by the external optical fiber.

[0076] The light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, so it is difficult for the light emitting component 400 and the light receiving component 500 to be directly connected to the circuit board 300. Therefore, in the embodiment, the light emitting component 400 and the light receiving component 500 are electrically connected through flexible circuit boards. However, in the embodiment, the assembly structure of the light emitting component 400 and the light receiving component 500 is not limited to the structures shown in FIGS. 3 and 4, and other assembly structures can also be used. For example, the light emitting component 400 and the light receiving component 500 can be disposed on different tube bodies. The embodiment is only used as an example of the structures shown in FIGS. 3 and 4.

[0077] FIG. 5 is a structural diagram of a light emitting component according to some embodiments of the present disclosure. As shown in FIG. 5, the light emitting component 400 provided by some embodiments of the present disclosure includes a tube base 410 and a tube cap 420, and the tube cap 420 covers the top of the tube base 410. The tube base 410 and the tube cap 420 form a containing cavity, and other devices such as a laser assembly, a lens, and a TEC can be disposed in the containing cavity. The tube base 410 includes a plurality of pins, and the pins are configured to electrically connect the flexible circuit board to other electrical devices in the light emitting component 400, thereby realizing the electrical connection between the light emitting component 400 and the circuit board 300. The form of the light emitting component in the embodiment is not limited to the form shown in FIG. 5, and the structure shown in FIG. 5 is only used as an example for illustration.

[0078] FIG. 6 is an exploded view of a light emitting component according to some embodiments of the present disclosure. As shown in FIG. 6, the light emitting component 400 can include a laser assembly 430, and the laser assembly 430 can be configured to generate signal light. The signal light generated by the laser assembly 430 can pass through the tube cap 420.

[0079] In some embodiments, the laser assembly 430 can include a laser chip 700 and a substrate, the upper surface of the substrate is paved with circuits, and the laser chip 700 is connected to the corresponding circuits on the substrate by wire bonding. For example, the laser chip 700 can be an EML laser chip, which can be obtained by monolithic integration of a DFB laser and an EAM modulator. By using the external modulation technology, the EML laser chip avoids the interaction between photons and electrons in the laser at high modulation speed, reduces the large chirp caused by direct modulation, and can achieve a higher transmission rate.

[0080] The key performance indicators of the laser chip 700 include low power consumption, modulation rate, and modulation efficiency. When the modulation rate is higher, the bandwidth performance of the laser is improved.

[0081] FIG. 7 is a structural diagram of a laser chip according to some embodiments of the present disclosure, in which the X direction is the light field transmission direction. As shown in FIG. 7, the laser chip 700 can include a light emitting region 710, a modulation region 720, and a butt joint region 730; one end of the light emitting region 710 is away from the modulation region 720, and the other end is close to the modulation region 720; one end of the modulation region 720 is close to the light emitting region 710, and the other end is away from the light emitting region 710; one end of the butt joint region 730 is connected to the other end of the light emitting region 710, and the other end of the butt joint region 730 is connected to one end of the modulation region 720.

[0082] The light emitting region 710 can be formed with a first active layer, and the light emitting region 710 can emit light without carrying a signal. The modulation region 720 can be formed with a second active layer, and the modulation region 720 can modulate the light emitted by the light emitting region 710 to generate an optical signal. The butt joint region 730 is configured to couple and transmit the light generated by the light emitting region 710 to the modulation region 720 to ensure the coupling efficiency of the light generated by the light emitting region 710 to the modulation region 720.

[0083] In some embodiments, a light emitting electrode 711 is arranged on the top of the light emitting region 710, and the light emitting electrode 711 is configured to be electrically connected to the pin on the socket 410 to load a bias current, thereby providing carriers to the first active layer of the light emitting region 710 to make the light emitting region 710 generate light.

[0084] In some embodiments, a modulation electrode 721 is arranged on the top of the modulation region 720, and the modulation electrode 721 is configured to be electrically connected to the pin on the socket 410 to load a modulation signal, thereby providing a modulation current to the second active layer of the modulation region 720 to modulate the light generated by the light emitting region 710.

[0085] FIG. 8 is an exploded schematic diagram of a laser chip according to some embodiments of the present disclosure, in which the X direction is the light field transmission direction, FIG. 9 is a partial enlarged view of A in FIG. 8, FIG. 10 is a partial enlarged view of B in FIG. 8, and FIG. 11 is a partial enlarged view of C in FIG. 8.

[0086] As shown in FIG. 9, the light emitting region 710 can include a first ridge waveguide 712, which can extend from one end of the light emitting region 710 to one end of the butt joint region 730 along the X direction. One side of the first ridge waveguide 712 can be provided with a first groove 713, and the other side of the first ridge waveguide 712 can be provided with a second groove 714.

[0087] In some embodiments, the first groove 713 and the second groove 714 can extend above the first active layer, i.e., the bottom of the first ridge waveguide 712 is located above the first active layer, and the first ridge waveguide 712 can be a shallow ridge waveguide.

[0088] In some embodiments, the first groove 713 and the second groove 714 can respectively extend from one end of the light emitting region 710 to one end of the butt joint region 730 along the X direction.

[0089] As shown in FIG. 10, the modulation region 720 can include a second ridge waveguide 722, which can extend from the other end of the butt joint region 730 to the other end of the modulation region 720 along the X direction. One side of the second ridge waveguide 722 can be provided with a third groove 723, and the other side of the second ridge waveguide 722 can be provided with a fourth groove 724.

[0090] In some embodiments, the third groove 723 and the fourth groove 724 can respectively extend below the second active layer, and the bottom of the second ridge waveguide 722 can be located below the second active layer, and the second ridge waveguide 722 can be a deep ridge waveguide.

[0091] In some embodiments, the third groove 723 and the fourth groove 724 can respectively extend from the other end of the butt joint region 730 to the other end of the modulation region 720 along the X direction.

[0092] In some embodiments, the depth of the first groove 713 can be less than the depth of the third groove 723, and the depth of the second groove 714 can be less than the fourth groove 724, so that the height of the first ridge waveguide 712 is less than the height of the second ridge waveguide 722.

[0093] As shown in FIG. 11, the butt joint region 730 includes a butt joint ridge waveguide 731, one end of the butt joint ridge waveguide 731 is connected to the first ridge waveguide 712, and the other end of the butt joint ridge waveguide 731 is connected to the second ridge waveguide 722. The butt joint ridge waveguide 731 is provided with a first butt joint groove 732 on one side and a second butt joint groove 733 on the other side. One end of the first butt joint groove 732 is communicated with the first groove 713, and the other end of the first butt joint groove 732 is communicated with the third groove 723; one end of the second butt joint groove 733 is communicated with the second groove 714, and the other end of the second butt joint groove 733 is communicated with the fourth groove 724. The butt joint ridge waveguide 731 connects the first ridge waveguide 712 and the second ridge waveguide 722 to reduce the technical difficulty of directly butt jointing the first ridge waveguide 712 and the second ridge waveguide 722.

[0094] FIG. 12 is a schematic diagram of a cross-sectional structure of a light emitting region according to some embodiments of the present disclosure, the cross-section being perpendicular to the light field transmission direction of the laser chip 700. As shown in FIG. 12, the light emitting region 710 includes, from bottom to top, a first substrate layer 7101, a first lower confinement layer 7102, a first active layer 7103, a first upper confinement layer 7104, a grating layer 7105, and a first waveguide layer 7106. The light emitting electrode 711 is located on top of the first waveguide layer 7106; the first waveguide layer 7106 is formed with a first ridge waveguide 712, a first groove 713, and a second groove 714, the bottom of the first groove 713 and the bottom of the second groove 714 extending above the grating layer 7105. The lower confinement layer 7102 and the upper confinement layer 7104 can confine electrons and holes in the quantum hydride of the first active layer 7103.

[0095] In some embodiments, the first active layer 7103 is a multi-quantum hydride active layer formed by stacking quantum hydrides with quantum barriers. For example, the first active layer 7103 includes quantum barriers, quantum hydrides, and quantum barriers stacked in sequence.

[0096] In some embodiments, the first substrate layer 7101 can be InP, and the first active layer 7103 can be any one of AlInGaAs or InGaAsP.

[0097] FIG. 13 is a schematic diagram of a cross-sectional structure of a modulation region according to some embodiments of the present disclosure, the cross-section being perpendicular to the light field transmission direction of the laser chip 700. As shown in FIG. 13, the modulation region 720 includes, from bottom to top, a second substrate layer 7201, a second lower confinement layer 7202, a second active layer 7203, a second upper confinement layer 7204, and a second waveguide layer 7205. The modulation electrode 721 is located on top of the second waveguide layer 7205; the second waveguide layer 7205 is formed with a second ridge waveguide 722, a third groove 723, and a fourth groove 724, the bottom of the third groove 723 and the bottom of the fourth groove 724 extending to the second lower confinement layer 7202.

[0098] In some embodiments, the second active layer 7203 can include a multi-quantum-hydride active layer formed by stacking quantum-hydrides and quantum-barriers. For example, the second active layer 7203 can include quantum-barriers, quantum-hydrides, quantum-barriers, quantum-hydrides, and quantum-barriers stacked in sequence. The second active layer 7203 has a thickness greater than that of the first active layer 7103, and the center of the second active layer 7203 is aligned with the center of the first active layer 7103.

[0099] In some examples, it can be understood that the center of the second active layer 7203 is not absolutely aligned with the center of the first active layer 7103. In some examples, the center of the second active layer 7203 can have a preset distance deviation from the center of the first active layer 7103; the preset distance can be less than or equal to a preset threshold. For example, the center of the second active layer 7203 can have a deviation from the center of the first active layer 7103 due to processing errors, tolerances, etc.; this part of the deviation can be negligible.

[0100] In some embodiments, the second substrate layer 7201 can be made of InP, and the second active layer 7203 can be made of any one of AlInGaAs or InGaAsP. In some examples, the second substrate layer 7201 and the first substrate layer 7101 are in an integrated structure.

[0101] As shown in FIG. 13, the second ridge waveguide 722 can include a shallow etching part 7221 and a deep etching part 7222, the shallow etching part 7221 is located above the deep etching part 7222, the width of the deep etching part 7222 is greater than that of the shallow etching part 7221, and the connection between the shallow etching part 7221 and the deep etching part 7222 forms a step surface 7223.

[0102] In some embodiments, the shallow etching part 7221 and the deep etching part 7222 are formed by two etching processes, i.e., the shallow etching part 7221 is formed by a first etching process, and the deep etching part 7222 is formed by a second etching process.

[0103] FIG. 14 is a schematic diagram of a cross-sectional structure of a light emitting region directly connected to a modulation region according to some embodiments of the present disclosure, in which the X direction is the light field transmission direction. As shown in FIG. 14, after the modulation region 720 is epitaxially grown, the contact position between the modulation region 720 and the light emitting region 710 forms an initial connection region D. In the initial connection region D, the second active layer 7203 of the modulation region 720 is curved, the growth defects of the quantum-hydrides in the curved part of the second active layer 7203 are more, which causes the composition of the quantum-hydrides in the second active layer 7203 to deviate, the band gap to decrease, the light absorption rate of the initial connection region D to increase, and the growth defects of the quantum-hydrides in the initial connection region D to reduce the service life of the laser chip.

[0104] FIG. 15 is a diagram illustrating a use state of a butt joint region according to some embodiments of the present disclosure. As shown in FIG. 15, the butt joint region 730 can include a first cladding layer 7301, a butt joint waveguide layer 7302, and a second cladding layer 7303, and the butt joint waveguide layer 7302 is located between the first cladding layer 7301 and the second cladding layer 7303.

[0105] In some examples, one end of the butt joint waveguide layer 7302 can be located at a side of the other end of the first active layer 7103, and the other end of the butt joint waveguide layer 7302 can be located at a side of the one end of the second active layer 7203.

[0106] In some examples, the refractive index of the butt joint waveguide layer 7302 can be greater than the refractive index of the first cladding layer 7301, and the refractive index of the butt joint waveguide layer 7302 can be greater than the refractive index of the second cladding layer 7303, so as to form a waveguide structure, thereby enabling the butt joint waveguide layer 7302 to achieve optical coupling connection between the first active layer 7103 and the second active layer 7203, reducing optical loss in the butt joint region 730, and ensuring optical coupling between the first active layer 7103 and the second active layer 7203.

[0107] In some embodiments, the first cladding layer 7301 can be made of InP material.

[0108] In some examples, the second cladding layer 7303 can be made of InP material.

[0109] In some examples, the butt joint waveguide layer 7302 is made of InGaAsP material.

[0110] In some embodiments, the first cladding layer 7301 can be located below the butt joint waveguide layer 7302. The second cladding layer 7303 can be located above the butt joint waveguide layer 7302.

[0111] In some examples, the first cladding layer 7301 can be located above the butt joint waveguide layer 7302. The second cladding layer 7303 can be located below the butt joint waveguide layer 7302.

[0112] In some embodiments, the first cladding layer 7301 and the second cladding layer 7303 can form an integrated cladding layer and wrap around the sides of the butt joint waveguide layer 7302.

[0113] In some embodiments, the butt joint waveguide layer 7302 can include a first curved portion 7302a, a flat portion 7302b, and a second curved portion 7302c. One end of the flat portion 7302b is connected to the first curved portion 7302a, and the other end of the flat portion 7302b is connected to the second curved portion 7302c. The first curved portion 7302a is close to an end of the first active layer 7103, the second curved portion 7302c is close to an end of the second active layer 7203, and the flat portion 7302b extends along the light field transmission direction. The first curved portion 7302a is curved from one end of the flat portion 7302b to the direction of the second cladding layer 7303, and the second curved portion 7302c is curved from the other end of the flat portion 7302b to the direction of the second cladding layer 7303.

[0114] In some embodiments, the thickness of the flat portion 7302b can be greater than the thickness of the first curved portion 7302a.

[0115] In some examples, the thickness of the flat portion 7302b can be greater than the thickness of the second curved portion 7302c.

[0116] In some embodiments, the thickness of the flat portion 7302b is greater than the thickness of the first active layer 7103, and the thickness of the flat portion 7302b is less than the thickness of the second active layer 7203. The center of the flat portion 7302b is aligned with the center of the first active layer 7103, and the center of the second active layer 7203 is aligned with the center of the flat portion 7302b. Here, the center of the flat portion 7302b and the center of the first active layer 7103 can be aligned within a predetermined range; the center of the second active layer 7203 and the center of the flat portion 7302b can be aligned within a predetermined range.

[0117] FIG. 16 is a graph showing the relationship between the thickness of the butt joint waveguide layer and the transmittance of the butt joint region according to some embodiments of the present disclosure; wherein the thickness of the butt joint waveguide layer 7302 mainly refers to the thickness of the flat portion 7302b. As shown in FIG. 16, the transmittance of the butt joint region 730 first increases and then decreases as the thickness of the butt joint waveguide layer 7302 increases. The thickness of the butt joint waveguide layer 7302 is selected in combination with the thickness of the first active layer 7103 and the thickness of the second active layer 7203, so that the butt joint region 730 has good light transmittance.

[0118] In some embodiments, the thickness of the butt joint waveguide layer 7302 is 180nm-260nm; such as 200nm-240nm, 200nm-230nm, 200nm-210nm, or 210nm-240nm, etc.

[0119] In some embodiments, the flat portion 7302b has a thickness of 180-260 nm; the cladding waveguide layer 7302 has a thickness of 200-240 nm, 200-230 nm, 200-210 nm, or 210-240 nm, etc.

[0120] Based on the laser chip provided in the above embodiments, the embodiments of the present disclosure further provide a preparation method of a laser chip for preparing the laser chip. FIG. 17 is a flowchart I of a preparation method of a laser chip according to some embodiments of the present disclosure, and FIG. 18 is a flowchart II of a preparation method of a laser chip according to some embodiments of the present disclosure. FIGS. 17 and 18 show the cross-sectional structure corresponding to each step in the preparation of the laser chip.

[0121] The embodiments of the present disclosure further provide a preparation method of a laser chip, comprising:

[0122] S110: growing a laser epitaxial layer on a substrate, the laser epitaxial layer comprising a first lower confinement layer, a first active layer, a first upper confinement layer, and a grating layer.

[0123] The first lower confinement layer 7102, the first active layer 7103, and the first upper confinement layer 7104 are epitaxially grown on the substrate in sequence. An InP layer 7107 is grown on the first upper confinement layer 7104, and the InP layer 7107 is photoetched to form the grating layer 7105. The substrate comprises a first substrate layer 7101 and a second substrate layer 7201, and the first substrate layer 7101 and the second substrate layer 7201 are in an integrated structure. In some embodiments, the initial light-emitting area is above the first substrate layer 7101.

[0124] In some embodiments, the grating layer 7105 can be formed by photoetching the InP layer through electron beam lithography or holographic lithography technology.

[0125] In some embodiments, the first active layer 7103 comprises a quantum well, a quantum well, and a quantum well stacked in sequence.

[0126] S120: etching an initial modulation region on the laser epitaxial layer to form an initial light-emitting area on the side of the initial modulation region.

[0127] The medium film 7108 covers the initial light-emitting area above the grating layer 7105, the area outside the initial light-emitting area is etched, and the laser epitaxial layer not covered by the medium film is etched to form an initial modulation region 720a. The initial modulation region 720a is located at the light-emitting end of the initial light-emitting area.

[0128] In some embodiments, the depth of the initial modulation region 720a extends to the second substrate layer 7201, so that the original top of the second substrate layer 7201 is etched.

[0129] S130: growing a modulator epitaxial layer on the initial modulation region, the modulator epitaxial layer forms an initial butt joint with the butt joint of the initial light emitting region, the modulator epitaxial layer comprises a second lower confinement layer, a second active layer and a second upper confinement layer.

[0130] The second lower confinement layer 7202, the second active layer 7203 and the second upper confinement layer 7204 are sequentially grown on the initial modulation region 720a, the second lower confinement layer 7202 is located above the second substrate layer 7201, and the second lower confinement layer 7202, the second active layer 7203 and the second upper confinement layer 7204 form a modulator epitaxial layer, one end of the modulator epitaxial layer is butt jointed with the initial light emitting region to form an initial butt joint.

[0131] In some embodiments, the side edge of the second lower confinement layer 7202 is connected to the end surface of the initial light emitting region.

[0132] In some embodiments, the bottom surface of the second active layer 7203 is lower than the bottom surface of the first active layer 7103, and the top surface of the second active layer 7203 is higher than the top surface of the first active layer 7103, so that the thickness of the second active layer 7203 is greater than the thickness of the first active layer 7103.

[0133] In some embodiments, the thickness of the second active layer 7203 is greater than the thickness of the first active layer 7103, and the center of the second active layer 7203 is aligned with the center of the first active layer 7103.

[0134] In some embodiments, the top surface of the second upper confinement layer 7204 is higher than the top surface of the first upper confinement layer 7104. For example, the top surface of the second upper confinement layer 7204 is flush with the top surface of the grating layer 7105.

[0135] In some embodiments, the second active layer 7203 comprises a quantum barrier, a quantum well, a quantum barrier, a quantum well and a quantum barrier which are sequentially stacked.

[0136] S140: growing a waveguide layer on the top of the modulator epitaxial layer and the top of the initial light emitting region, the waveguide layer comprises a first waveguide layer and a second waveguide layer, the first waveguide layer is located above the grating layer, and the second waveguide layer is located above the second upper confinement layer.

[0137] The medium film covering the initial light emitting region is etched away, and the waveguide layer is grown on the top of the modulator epitaxial layer and the top of the initial light emitting region. For example, the waveguide layer comprises a first waveguide layer 7106 and a second waveguide layer 7205, the first waveguide layer 7106 is located above the grating layer 7105, the second waveguide layer 7205 is located above the second upper confinement layer 7204, and the first waveguide layer 7106 is connected to the second waveguide layer 7205 to form the waveguide layer of the laser chip 700.

[0138] In some embodiments, the medium film can be SiO2 or Si3N4, etc.

[0139] S150: opening an abutment opening, the abutment opening crossing the initial abutment region and a bottom of the abutment opening extending below the first active layer and the second active layer, one side of the abutment opening forming a light emitting region and the other side of the abutment opening forming a modulation region.

[0140] The abutment opening 730a is etched in the waveguide layer to form the abutment opening 730a, one side edge of the abutment opening 730a penetrating through the first waveguide layer 7105 and the other side edge of the abutment opening 730a penetrating through the second waveguide layer 7205, so as to open the abutment opening 730a in the initial abutment region, the abutment opening 730a crossing the initial abutment region. The bottom of the abutment opening 730a extends below the first active layer 7103 and the second active layer 7203, so that the laser epitaxial layer and the modulator epitaxial layer in the initial abutment region are etched away to form the light emitting region 710 on one side of the abutment opening 730a and the modulation region 720 on the other side of the abutment opening 730a.

[0141] In some embodiments, the bottom of the abutment opening 730a extends to the substrate.

[0142] S160: growing an abutment waveguide in the abutment opening, the abutment waveguide abutting the light emitting region and the modulation region, the abutment waveguide comprising a cladding layer and an abutment waveguide layer, the cladding layer cladding the abutment waveguide layer, the abutment waveguide layer having a refractive index greater than that of the cladding layer.

[0143] The abutment waveguide is grown in the abutment opening 730a to form the abutment region 730 in the abutment opening 730a, so that the abutment waveguide abuts the light emitting region 710 and the modulation region 720. The abutment waveguide comprises a cladding layer and an abutment waveguide layer 7302, the cladding layer cladding the abutment waveguide layer 7302, the abutment waveguide layer having a refractive index greater than that of the cladding layer, so that the cladding layer and the abutment waveguide layer 7302 form a waveguide structure.

[0144] In some embodiments, the cladding layer comprises a first cladding layer 7301 and a second cladding layer 7303. The first cladding layer 7301, the abutment waveguide layer 7302 and the second cladding layer 7303 are sequentially grown in the abutment opening 730a, the first cladding layer 7301 being below the abutment waveguide layer 7302 and the second cladding layer 7303 being above the abutment waveguide layer 7302. The first cladding layer 7301, the abutment waveguide layer 7302 and the second cladding layer 7303 respectively cross the abutment opening 730a, so that one end of the abutment waveguide layer 7302 is close to the end of the light emitting region 710 and the other end of the abutment waveguide layer 7302 is close to the end of the modulation region 720.

[0145] In some embodiments, the first cladding layer 7301 and the second cladding layer 7303 are made of InP material or the like, and the butt joint waveguide layer 7302 is made of InGaAsP material or the like.

[0146] In some embodiments, the first cladding layer 7301 and the second cladding layer 7303 form an integrated cladding layer to wrap the butt joint waveguide layer 7302 in the cladding layer, one end of the cladding layer contacts the end of the light emitting region 710, and the other end of the cladding layer contacts the end of the modulation region 720.

[0147] In some embodiments, the middle part of the first cladding layer 7301 is flat, and the two ends are curved, so that the middle part of the butt joint waveguide layer 7302 is flat, and the two ends are curved. For example, the butt joint waveguide layer 7302 includes a first curved portion 7302a, a flat portion 7302b, and a second curved portion 7302c. One end of the flat portion 7302b is connected to the first curved portion 7302a, and the other end of the flat portion 7302b is connected to the second curved portion 7302c. The first curved portion 7302a is close to the end of the first active layer 7103, the second curved portion 7302c is close to the end of the second active layer 7203, and the flat portion 7302b extends along the light field transmission direction.

[0148] In some embodiments, the first curved portion 7302a is curved from one end of the flat portion 7302b to the direction where the second cladding layer 7303 is located, and the second curved portion 7302c is curved from the other end of the flat portion 7302b to the direction where the second cladding layer 7303 is located.

[0149] In some embodiments, the thickness of the flat portion 7302b is greater than the thickness of the first curved portion 7302a and greater than the thickness of the second curved portion 7302c.

[0150] In some embodiments, the thickness of the flat portion 7302b is greater than the thickness of the first active layer 7103, and the thickness of the flat portion 7302b is less than the thickness of the second active layer 7203. The center of the flat portion 7302b is aligned with the center of the first active layer 7103, and the center of the second active layer 7203 is aligned with the center of the flat portion 7302b.

[0151] In some embodiments, the thickness of the flat portion 7302b is 180nm-260nm; for example, the thickness of the butt joint waveguide layer 7302 is 200nm-240nm, 200nm-230nm, 200nm-210nm, or 210nm-240nm, or the like.

[0152] The laser chip preparation method provided in the embodiments of the present disclosure includes the following steps.

[0153] Based on the laser chip provided in the above embodiments, the embodiments of the present disclosure further provide another laser chip preparation method for preparing a laser chip. FIG. 19 is a flowchart of another laser chip preparation method according to some embodiments of the present disclosure, and FIG. 19 shows the cross-sectional structure corresponding to each step in the preparation of a laser chip, in which (a) is a light emitting region, and (b) is a modulation region.

[0154] The another laser chip preparation method provided in the embodiments of the present disclosure includes the following steps.

[0155] S210: forming a light emitting region and a modulation region along the light field transmission direction of the laser chip, the light emitting region generating light, and the modulation region modulating the light generated by the light emitting region.

[0156] The laser chip preparation method provided in the embodiments of the present disclosure includes the following steps.

[0157] In some embodiments, the bottom surface of the second active layer 7203 is lower than the bottom surface of the first active layer 7103, and the top surface of the second active layer 7203 is higher than the top surface of the first active layer 7103, so that the thickness of the second active layer 7203 is greater than the thickness of the first active layer 7103.

[0158] In some embodiments, the thickness of the second active layer 7203 is greater than the thickness of the first active layer 7103, and the center of the second active layer 7203 is aligned with the center of the first active layer 7103.

[0159] In some embodiments, the first active layer 7103 comprises a quantum barrier, a quantum well and a quantum barrier stacked in sequence, and the second active layer 7203 comprises a quantum barrier, a quantum well, a quantum barrier, a quantum well and a quantum barrier stacked in sequence.

[0160] In the embodiment, the specific steps of forming the light-emitting region 710 and the modulation region 720 along the light field transmission direction of the laser chip can also refer to the steps of forming the light-emitting region 710 and the modulation region 720 described in the above embodiment S110-S140.

[0161] In some embodiments, a butt joint region 730 is arranged between the light-emitting region 710 and the modulation region 720. The structure of the butt joint region 730 can refer to the above embodiment, and the preparation process of the butt joint region 730 can refer to the preparation process described in the above embodiment S150-S160.

[0162] S220: shallow etching the light-emitting region and the modulation region along the light field transmission direction to form a shallow etching part of a first ridge waveguide in the light-emitting region and a shallow etching part of a second ridge waveguide in the modulation region, the first ridge waveguide connecting the shallow etching parts; wherein one side of the first ridge waveguide forms a first groove, the other side of the first ridge waveguide forms a second groove, one side of the shallow etching part forms a third initial groove, and the other side of the shallow etching part forms a fourth initial groove.

[0163] In the light-emitting region 710, the first groove 713 and the second groove 714 are shallow etched, and the first ridge waveguide 712 is formed between the first groove 713 and the second groove 714. In the modulation region 720, the third initial groove 723a and the fourth initial groove 724a are shallow etched, and the shallow etching part 7221 is formed between the third initial groove 723a and the fourth initial groove 724a. The first ridge waveguide 712 connects the shallow etching part 7221.

[0164] In some embodiments, before shallow etching, a dielectric film is covered on the top of the light-emitting region 710 and the modulation region 720 to form an etching pattern in the light-emitting region 710 and the modulation region 720 by using the dielectric film, and the top surface of the first ridge waveguide 712 and the top surface of the shallow etching part 7221 are covered with the dielectric film.

[0165] In some embodiments, in the light-emitting region 710, shallow etching is performed to the upper side of the grating layer 7105.

[0166] In some embodiments, a corrosion stop layer is arranged above the grating layer 7105, and the corrosion stop layer is located between the grating layer 7105 and the first waveguide layer 7106; the bottom of the first groove 713 extends to the corrosion stop layer, and the bottom of the second groove 714 extends to the corrosion stop layer.

[0167] In some embodiments, in the modulation region 720, a shallow etching is performed to the top of the second active layer 7203. For example, the bottom of the third initial trench 723a extends to the second upper confinement layer 7204, and the bottom of the fourth initial trench 724a extends to the second upper confinement layer 7204.

[0168] In some embodiments, a shallow etching is performed through the butt joint region 730, and a first butt joint trench 732 and a second butt joint trench 733 are etched in the butt joint region 730, and a butt joint ridge waveguide 731 is formed between the first butt joint trench 732 and the second butt joint trench 733. One end of the first butt joint trench 732 is connected to the first trench 713, and the other end of the first butt joint trench 732 is connected to the third initial trench 723a; one end of the second butt joint trench 733 is connected to the second trench 714, and the other end of the second butt joint trench 733 is connected to the fourth initial trench 724a.

[0169] S230: Depositing a dielectric film covering the surfaces of the first trench, the second trench, the third initial trench, and the fourth initial trench, and the top surface of the first ridge waveguide and the top surface of the shallow etching part.

[0170] After the shallow etching, a dielectric film 01 is deposited on the surface of the laser chip after the shallow etching. For example, the dielectric film 01 covers the surface of the first trench 713, the surface of the second trench 714, the surface of the third initial trench 723a, the surface of the fourth initial trench 724a, the top of the first ridge waveguide 712, and the top of the shallow etching part 7221, etc.

[0171] In some embodiments, the dielectric film 01 also covers the surface of the first butt joint trench 732, the surface of the second butt joint trench 733, and the top of the butt joint ridge waveguide 731, etc.

[0172] In some embodiments, after the shallow etching, the dielectric film on the top surface of the first ridge waveguide 712 and the top surface of the shallow etching part 7221 is left, and a dielectric film 01 is again deposited on the top of the dielectric film, so that the dielectric film 01 again deposited covers the dielectric film.

[0173] In some embodiments, after the shallow etching, the dielectric film on the top surface of the butt joint ridge waveguide 731 is left, and a dielectric film 01 is again deposited on the top of the dielectric film, so that the dielectric film 01 again deposited covers the dielectric film.

[0174] S240: Etching the dielectric film on the bottom surface of the third initial trench and the bottom surface of the fourth initial trench.

[0175] The dielectric film 01 on the bottom surface of the third initial trench 723a and the bottom surface of the fourth initial trench 724a is etched away, so that the area except the edge of the bottom surface of the third initial trench 723a and the edge of the bottom surface of the fourth initial trench 724a is exposed.

[0176] In some embodiments, when etching the dielectric film 01 on the bottom surface of the third initial trench 723a, the etching is extended to the dielectric film 01 on the bottom surface of the first butt joint trench 732.

[0177] In some embodiments, when etching the dielectric film 01 on the bottom surface of the fourth initial trench 724a, the etching is extended to the dielectric film 01 on the bottom surface of the second butt joint trench 733.

[0178] S250: etching the bottom surface of the third initial trench to form a third trench and the bottom surface of the fourth initial trench to form a fourth trench, so as to form a deep etching part below the shallow etching part, the width of the deep etching part being greater than the width of the shallow etching part.

[0179] The bottom surface exposed area of the third initial trench 723a is etched to below the second active layer 7203 to form a third trench 723. The third trench 723 is narrower than the third initial trench 723a at the bottom of the third initial trench 723a, and the third trench 723 is in communication with the third initial trench 723a. The bottom surface exposed area of the fourth initial trench 724a is etched to below the second active layer 7203 to form a fourth trench 724. The fourth trench 724 is narrower than the fourth initial trench 724a at the bottom of the fourth initial trench 724a, and the fourth trench 724 is in communication with the fourth initial trench 724a.

[0180] After etching the bottom surface exposed area of the third initial trench 723a and the bottom surface exposed area of the fourth initial trench 724a, a deep etching part 7222 is formed below the shallow etching part 7221, and the deep etching part 7222 supports the connection of the shallow etching part 7221 to form a second ridge waveguide 722.

[0181] In some embodiments, the materials and equipment required for etching in this step can use the materials and equipment used for shallow etching.

[0182] In some embodiments, etching the bottom surface exposed area of the third initial trench 723a and the bottom surface exposed area of the fourth initial trench 724a uses dry etching.

[0183] In some embodiments, etching the bottom surface exposed area of the first butt joint trench 732 and the bottom surface exposed area of the second butt joint trench 733 deepens the first butt joint trench 732 and the second butt joint trench 733.

[0184] S260: removing the residual dielectric film, and forming a stepped surface at the connection of the shallow etching part and the deep etching part.

[0185] After etching the bottom exposed area of the third initial groove 723a and the bottom exposed area of the fourth initial groove 724a, the residual dielectric film on the laser chip 700 is removed. After removing the residual dielectric film, a step surface 7223 is formed at the connection between the shallow etching part 7221 and the deep etching part 7222.

[0186] The laser chip preparation method provided by the embodiments of the present disclosure includes: performing shallow etching first, and then further etching during the preparation of the first ridge waveguide 712 and the second ridge waveguide 722; the shallow etching forms a part of the first ridge waveguide 712 and a part of the second ridge waveguide 722, and the further etching forms another part of the second ridge waveguide 722, so as to form the second ridge waveguide 722 through twice etching. The laser chip preparation method provided by the embodiments of the present disclosure integrates the deep ridge waveguide processing process in the shallow ridge waveguide processing process, which makes the deep ridge waveguide processing more convenient on the basis of ensuring the shape of the shallow ridge waveguide.

[0187] The above merely provides a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for preparing a laser chip, configured to prepare a laser chip, wherein the laser chip is configured to generate an optical signal; the method comprising: growing a laser epitaxial layer on a substrate, wherein the laser epitaxial layer comprises a first lower confinement layer, a first active layer, a first upper confinement layer and a grating layer; Etching an initial modulation area on the laser epitaxial layer to form an initial light-emitting area on the side of the initial modulation area; Growing a modulator epitaxial layer in the initial modulation region, wherein the junction between the modulation epitaxial layer and the initial light-emitting region forms an initial junction region, and the modulator epitaxial layer includes a second lower confinement layer, a second active layer, and a second upper confinement layer; growing a waveguide layer on top of the modulator epitaxial layer and the initial light emitting region, wherein the waveguide layer includes a first waveguide layer and a second waveguide layer, wherein the first waveguide layer is located above the grating layer, and the second waveguide layer is located above the second upper confinement layer; A docking opening is formed, the docking opening spanning the initial docking area and having a bottom extending below the first active layer and the second active layer, wherein a light-emitting area is formed on one side of the docking opening and a modulation area is formed on the other side of the docking opening along the light field transmission direction of the laser chip; the light-emitting area generates light, and the modulation area modulates the light generated by the light-emitting area; Growing a butt-joint waveguide in the butt-joint opening, the butt-joint waveguide butt-jointly connecting the light-emitting region and the modulation region, the butt-joint waveguide comprising a wrapping layer and a butt-joint waveguide layer, the wrapping layer wrapping the butt-joint waveguide layer, the butt-joint waveguide layer having a refractive index greater than that of the wrapping layer; shallowly etching the light-emitting area and the modulation area along the light field transmission direction to form a first ridge waveguide in the light-emitting area and a shallowly etched portion forming a second ridge waveguide in the modulation area, wherein the first ridge waveguide is connected to the shallowly etched portion; wherein a first groove is formed on one side of the first ridge waveguide, a second groove is formed on the other side of the first ridge waveguide, a third initial groove is formed on one side of the shallowly etched portion, and a fourth initial groove is formed on the other side of the shallowly etched portion; depositing a dielectric film, wherein the dielectric film covers surfaces of the first trench, the second trench, the third initial trench, and the fourth initial trench, as well as a top surface of the first ridge waveguide and a top surface of the shallow etched portion; Etching the dielectric film on the bottom surface of the third initial trench and the bottom surface of the fourth initial trench; Etching the bottom surface of the third preliminary trench to form a third trench and the bottom surface of the fourth preliminary trench to form a fourth trench, so as to form a deep etched portion below the shallow etched portion, wherein the width of the deep etched portion is greater than the width of the shallow etched portion; The residual dielectric film is removed, and a step surface is formed at the connection between the shallow etching portion and the deep etching portion.

2. The preparation method according to claim 1, wherein Growing a butt-jointed waveguide within the butt-jointed opening comprises: Growing a first wrapping layer, a butt-joint waveguide layer, and a second wrapping layer in sequence in the butt-joint opening, wherein the first wrapping layer is located below the butt-joint waveguide layer, and the second wrapping layer is located above the butt-joint waveguide layer; The butted waveguide layer includes a first curved portion, a straight portion, and a second curved portion, wherein one end of the straight portion is connected to the first curved portion, and the other end of the straight portion is connected to the second curved portion, the first curved portion is close to the light emitting area, and the second curved portion is close to the modulation area; The thickness of the straight portion is greater than that of the first active layer, and the thickness of the straight portion is less than that of the second active layer. The center of the straight portion is aligned with the center of the first active layer and the center of the second active layer respectively.

3. The preparation method according to claim 2, wherein The first cladding layer and the second cladding layer are made of InP material, and the butting waveguide layer is made of InGaAsP material; The thickness of the straight portion is 180nm-260nm.

4. The preparation method according to claim 1, wherein Growing a laser epitaxial layer on a substrate, including: A first lower confinement layer, a first active layer, a first upper confinement layer and an InP layer are sequentially grown on an InP substrate, wherein the first active layer comprises a quantum barrier, a quantum hydrazine and a quantum barrier that are sequentially stacked; Photolithography the InP layer to form the grating layer; Growing a modulator epitaxial layer in the initial modulation region, comprising: A second lower confinement layer, a second active layer and a second upper confinement layer are sequentially grown on the InP substrate in the initial modulation region, wherein the second active layer comprises a quantum barrier, a quantum hydrazine, a quantum barrier, a quantum hydrazine and a quantum barrier that are sequentially stacked.

5. The preparation method according to claim 1, wherein Along the light field transmission direction of the laser chip, a light emitting area and a modulation area are formed, including: The bottom of the first trench and the bottom of the second trench extend above the grating layer; The bottom of the third preliminary trench and the fourth preliminary trench extend to above the second active layer, the bottom of the third preliminary trench extends to the second lower confinement layer, and the bottom of the fourth preliminary trench extends to the second lower confinement layer.

6. A laser chip configured to generate an optical signal; comprising: a light-emitting region configured to generate light, the light-emitting region comprising, from bottom to top, a first substrate layer, a first lower confinement layer, a first active layer, a first upper confinement layer, a grating layer, and a first waveguide layer; the light-emitting region being provided with a first ridge waveguide, a first groove being provided on one side of the first ridge waveguide, and a second groove being provided on the other side of the first ridge waveguide; a modulation area configured to modulate the light generated by the light emitting area; The modulation region includes, from bottom to top, a second substrate layer, a second lower confinement layer, a second active layer, a second upper confinement layer and a second waveguide layer, wherein the second substrate layer is connected to the first substrate layer; The modulation area is provided with a second ridge waveguide, a third groove is provided on one side of the second ridge waveguide, and a fourth groove is provided on the other side of the second ridge waveguide; wherein the second ridge waveguide includes a shallow etching portion and a deep etching portion, the shallow etching portion is located above the deep etching portion, the width of the deep etching portion is greater than the width of the shallow etching portion, a step surface is formed at the connection between the shallow etching portion and the deep etching portion, and the shallow etching portion is connected to the first ridge waveguide; A docking area, one end of which is connected to the light-emitting area and the other end of which is connected to the modulation area; the docking area includes a docking waveguide, and the docking waveguide docks and connects the light-emitting area and the modulation area; wherein the docking waveguide includes a wrapping layer and a docking waveguide layer, the wrapping layer wraps the docking waveguide layer, and the refractive index of the docking waveguide layer is greater than the refractive index of the wrapping layer.

7. The laser chip according to claim 6, wherein: The wrapping layer includes a first wrapping layer and a second wrapping layer, and the bottom of the first wrapping layer is connected to the first substrate layer and the second substrate layer; The butted waveguide layer is located above the first wrapping layer, and the second wrapping layer is located above the butted waveguide layer; The first cladding layer and the second cladding layer are made of InP material, and the butting waveguide layer is made of InGaAsP material.

8. The laser chip according to claim 6, wherein: The butted waveguide layer includes a first curved portion, a straight portion, and a second curved portion, wherein one end of the straight portion is connected to the first curved portion, and the other end of the straight portion is connected to the second curved portion, the first curved portion is close to the light emitting area, and the second curved portion is close to the modulation area; The thickness of the straight portion is greater than that of the first active layer, and the thickness of the straight portion is less than that of the second active layer. The center of the straight portion is aligned with the center of the first active layer and the center of the second active layer respectively.

9. The laser chip according to claim 6, wherein: The docking area is provided with a docking ridge waveguide, one side of the docking ridge waveguide is provided with a first docking groove, and the other side of the docking ridge waveguide is provided with a second docking groove; One end of the butted ridge waveguide is connected to the first ridge waveguide, and the other end of the butted ridge waveguide is connected to the second ridge waveguide; One end of the first butting groove is connected to the first groove, and the other end of the first butting groove is connected to the third groove; One end of the second docking groove is connected to the second groove, and the other end of the second docking groove is connected to the fourth groove.

10. The laser chip according to claim 9, characterized in that The wrapping includes a first wrapping layer and a second wrapping layer; the first wrapping layer is located below the butt-jointed waveguide layer, the second wrapping layer is located above the butt-jointed waveguide layer, and the butt-jointed waveguide layer butt-jointly connects the first active layer and the second active layer.

11. An optical module, comprising: circuit boards; a light emitting component electrically connected to the circuit board; Wherein, the light emitting component includes: A tube socket, provided with tube pins, so as to be electrically connected to the circuit board through the tube pins; A pipe cap is mounted on the top of the pipe base, and the pipe cap and the pipe base form a receiving cavity; A laser chip is disposed in the accommodating cavity and is configured to generate an optical signal; the laser chip is a laser chip prepared by the laser chip preparation method according to any one of claims 1 to 5 or a laser chip according to any one of claims 6 to 10.

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