Data processing method and related apparatus

Abstract

A data processing method. In the method, in a scenario in which a plurality of buffers are optimized, when compiling a source code, a compiler can directly assign to a first variable in a compiling template (i.e., a target template in the embodiments of the present application) a numerical value equal to the number of buffers for which optimization is to be enabled, that is, the target template may be a template adapted to different numbers of buffers; and after said value is assigned to the first variable, an intermediate representation (IR) of the source code can be obtained, and a machine code is obtained on the basis of the IR. Therefore, storage overheads during deployment can be reduced, thereby improving the deployment efficiency.

Description

Data processing method and related apparatus

[0001] The present application claims priority to the Chinese patent application No. 202410430400.X, filed on April 10, 2024, and entitled "A data processing method and related apparatus", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of artificial intelligence (AI), and in particular to a data processing method and related apparatus. BACKGROUND

[0003] With the rapid development of artificial intelligence technology, the traditional processor architecture has been unable to meet the growing performance requirements. The industry accelerates key operators on specific hardware chips based on AI compilation frameworks such as Tvm and Halide, which can realize the construction of high-performance neural network models.

[0004] The multi-buffer technology (also known as n-buffer technology) is widely used to improve the pipeline efficiency of the entire data stream. The multi-buffer technology can reduce the memory access latency of data transfer and calculation, thereby accelerating data execution. The multi-buffer technology needs to expand the original cache size. When optimizing the performance of a single operator, the developer will selectively use n-buffer optimization according to the use case scenario or resource consumption. In this way, optimization for different buffer quantities will derive a series of different templates. Through combination, as shown in FIG. 1, it will cause the problem of template expansion. In the binary release process, each template needs to correspond to a bin file, resulting in a large release package file, a large deployment storage, and thus affecting the efficiency of customer-side deployment. SUMMARY

[0005] The present application provides a data processing method and related apparatus, which can reduce the storage overhead during deployment and improve the deployment efficiency.

[0006] The first aspect of the present application provides a data processing method. In the scenario of optimizing a plurality of cache areas buffer, when the source code is compiled, the compiler can directly assign the first variable in the compilation template (that is, the target template in the embodiment of the present application) to the value of the buffer quantity that needs to be optimized. That is, the target template can be a template adapted to different buffer quantities. After assigning the first variable, the intermediate representation (IR) of the source code can be obtained, and the machine code can be obtained according to the IR.

[0007] In the prior art, different buffer quantity multi-buffer optimization corresponds to different templates, which causes excessive storage overhead and reduces deployment efficiency. In the embodiment of the present application, the buffer optimization of different buffer quantities can share the same template. The template (that is, the target template in the embodiment of the present application) can be adapted to multi-buffer optimization of different buffer quantities. Specifically, the template can include a variable (that is, the first variable in the embodiment of the present application) related to the buffer quantity of the enabled multi-buffer optimization. During compilation, for the same template, only the variable in the template needs to be assigned based on the buffer quantity of the enabled multi-buffer optimization, so that the corresponding intermediate representation (IR) can be obtained. Since the buffer optimization of different buffer quantities can share the same template, the storage overhead during deployment can be reduced. During the binary release process, a single template only needs to correspond to one bin file. Compared with multiple templates, the single template has a smaller release package file, which can improve the efficiency of customer-side deployment. In addition, the multi-template form is time-consuming during compilation, which is not conducive to online compilation of the model. The single template of the embodiment of the present application can reduce the compilation time.

[0008] During compilation, the compiler can compile the source code based on the preset template to obtain machine code. The template can include the execution relationship of the operations in the source code, such as whether they can be parallel, the sequence constraint, and the like. Specifically, the template can include the relationship between the use of each buffer, such as the storage space of each buffer, the sequence constraint, waiting relationship, and whether they can be parallel between different buffers.

[0009] In a possible implementation, the first variable is a variable related to the buffer quantity in the target template.

[0010] In a possible implementation, the target template includes: a first cache space used by a first operation, the first cache space being represented by a start address and an address offset; the first operation is an operation within a loop count in a loop operation; the start address is represented by first information, and the first information is a relationship between the loop count in which the first operation is located and the first variable.

[0011] In a possible implementation, the target template further includes a plurality of candidate start addresses; the first information is specifically a remainder result of the loop count in which the first operation is located and the first variable, and different candidate start addresses correspond to different remainder results.

[0012] For example, when the loop count is 0, 2, 4, 6, 8, etc., the operation uses the buffer A0, and when the loop count is 1, 3, 5, 7, 9, etc., the operation uses the buffer A1. Thus, when the loop count is even, the starting address of the buffer used by the operation is the starting address of A0, and when the loop count is odd, the starting address of the buffer used by the operation is the starting address of A1. For another example, when the loop count is 0, 2, 4, 6, 8, etc., the operation uses the buffer B0, and when the loop count is 1, 3, 5, 7, 9, etc., the operation uses the buffer B1. Thus, when the loop count is even, the starting address of the buffer used by the operation is the starting address of B0, and when the loop count is odd, the starting address of the buffer used by the operation is the starting address of B1.

[0013] In a possible implementation, the target template includes: a first execution constraint between the second operation and the third operation; the first execution constraint indicates whether to execute in parallel, the second operation and the third operation belong to operations of different loop counts in a loop operation, and the execution order constraint is represented by a relationship between second information and third information, the second information is a relationship between a loop count where the second operation is located and the first variable, and the third information is a relationship between a loop count where the third operation is located and the first variable.

[0014] In a possible implementation, the second information is specifically a remainder result of the loop count where the second operation is located and a quantity, and the third information is specifically a remainder result of the loop count where the third operation is located and the quantity; when the second information and the third information are the same, the first execution constraint indicates that the second operation and the third operation are not executed in parallel.

[0015] In addition to the multi-buffer optimization, a preload technique (a preloading technique, that is, a technique of performing reading and moving of data of a subsequent loop count in advance) is also applied to improve the pipeline efficiency of the entire data flow, and the proload technique can load associated data in advance.

[0016] In addition to being compatible with buffer optimization of different buffer quantities, the target template in the embodiment of the present application can also be compatible with enabling or not enabling preload optimization. Similarly to the above, a variable (that is, the second variable in the embodiment of the present application) related to whether to enable the preload optimization can also be set in the target template. Based on the assignment to the variable, the IR obtained based on the template can be IR of enabling the proload optimization or IR of not enabling the proload optimization.

[0017] In a possible implementation, the second indication information can be acquired, and the second indication information is used to indicate whether to start a preload optimization; the target template is further adapted to start or not to start the preload optimization, the target template includes a second variable related to whether to start the preload optimization, and the compiler is further configured to assign the second variable in the target template based on whether to start the preload optimization, to obtain the intermediate representation IR of the source code.

[0018] In the above manner, one template can represent the functions of n buffers and preload at the same time, so that a common template is realized at the operator side, and storage overhead and coding time overhead are further reduced.

[0019] In a possible implementation, when the second indication information indicates that the preload is started, the second variable in the target template is assigned a first preset value, and when the second variable is the first preset value, the IR indicates that the first code and the second code are executed, the first code indicates data required by an operation with a loop count of 0, and the second code indicates data required by an operation with a loop count of j+1, where j is a current loop count.

[0020] In a possible implementation, when the second indication information indicates that the preload is not started, the second variable in the target template is assigned a second preset value, and when the second variable is the second preset value, the IR indicates that the third code is executed, the third code indicates data required by an operation with a loop count of j, where j is a current loop count.

[0021] In a second aspect, the present application provides a data processing apparatus, applied to a scenario of optimizing a plurality of buffer areas, and the apparatus comprises:

[0022] The obtaining module is configured to obtain a source code and first indication information, and the first indication information is used to indicate a number of buffers to be started for optimization.

[0023] The processing module is configured to assign a first variable in a target template based on the source code and the first indication information, to obtain an intermediate representation IR of the source code by using a compiler, and to obtain machine code based on the IR.

[0024] In a possible implementation, the target template is a template adapted to different numbers of buffers.

[0025] In a possible implementation, the first variable is a variable in the target template related to the number of buffers.

[0026] In a possible implementation, the target template comprises:

[0027] The first cache space used by the first operation is represented by a start address and an address offset; the first operation is an operation in a loop count in a loop operation; the start address is represented by the first information; and the first information is a relationship between the loop count in which the first operation is located and the first variable.

[0028] In a possible implementation, the target template further includes a plurality of candidate start addresses; and the first information is specifically a remainder result of the loop count in which the first operation is located and the first variable; and different candidate start addresses correspond to different remainder results.

[0029] In a possible implementation, the target template includes:

[0030] A first execution constraint between the second operation and the third operation; the first execution constraint indicates whether the second operation and the third operation are executed in parallel; the second operation and the third operation belong to operations in different loop counts in a loop operation; and the execution order constraint is represented by a relationship between the second information and the third information; the second information is a relationship between the loop count in which the second operation is located and the first variable; and the third information is a relationship between the loop count in which the third operation is located and the first variable.

[0031] In a possible implementation, the second information is specifically a remainder result of the loop count in which the second operation is located and the number;

[0032] The third information is specifically a remainder result of the loop count in which the third operation is located and the number;

[0033] When the second information and the third information are the same, the first execution constraint indicates that the second operation and the third operation are not executed in parallel.

[0034] In a possible implementation, the obtaining module is further configured to:

[0035] obtain second indication information, the second indication information being used to indicate whether to start a preload optimization; and

[0036] The target template is further adapted to start or not start the preload optimization; the target template includes a second variable related to whether to start the preload optimization; and the compiler is further configured to assign the second variable in the target template based on whether to start the preload optimization, to obtain the intermediate representation IR of the source code.

[0037] In a possible implementation, when the second indication information indicates that the preloading is enabled, the second variable in the target template is assigned a first preset value, and when the second variable is the first preset value, the IR indicates execution of a first code and a second code, the first code indicates data required for an operation with a loop count of 0, and the second code indicates data required for an operation with a loop count of j+1, where j is a current loop count.

[0038] In a possible implementation, when the second indication information indicates that the preloading is not enabled, the second variable in the target template is assigned a second preset value, and when the second variable is the second preset value, the IR indicates execution of a third code, the third code indicates data required for an operation with a loop count of j, where j is a current loop count.

[0039] The third aspect of the present application provides a data processing apparatus, which can include a processor, the processor and a memory are coupled, and the memory stores program instructions, when the program instructions stored in the memory are executed by the processor, the method of the first aspect or any implementation manner of the first aspect is implemented. For the processor to execute the steps in each possible implementation manner of the first aspect, specific details can be referred to the first aspect, which will not be repeated here.

[0040] The fourth aspect of the present application provides a computer readable storage medium, the computer readable storage medium stores a computer program, when the computer program is run on a computer, the computer executes the method of any implementation manner of the first aspect.

[0041] The fifth aspect of the present application provides a circuit system, the circuit system includes a processing circuit, the processing circuit is configured to execute the method of any implementation manner of the first aspect.

[0042] The sixth aspect of the present application provides a computer program product, when the computer program product is run on a computer, the computer executes the method of any implementation manner of the first aspect.

[0043] The seventh aspect of the present application provides a chip system, the chip system includes a processor, and is used for supporting a server or a threshold value obtaining apparatus to implement functions involved in any implementation manner of the first aspect, for example, sending or processing data and / or information involved in the method. In a possible design, the chip system further includes a memory, the memory is used for storing necessary program instructions and data of the server or the communication device. The chip system can be composed of a chip, or can include the chip and other discrete devices.

[0044] The beneficial effects of the second aspect to the seventh aspect can be referred to the introduction of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 is a schematic diagram of a multi-buffer optimization provided by an embodiment of the present application;

[0046] Figure 2 is a schematic diagram of a system architecture provided by an embodiment of the present application;

[0047] Figure 3 is a schematic diagram of a data processing method provided by an embodiment of the present application;

[0048] Figures 4 and 5 are schematic diagrams of data execution synchronization provided by an embodiment of the present application;

[0049] Figures 6 and 7 are schematic diagrams of a storage space provided by an embodiment of the present application;

[0050] Figure 8 is a schematic diagram of a data processing apparatus provided by an embodiment of the present application;

[0051] Figure 9 is a schematic diagram of an execution device provided by an embodiment of the present application;

[0052] Figure 10 is a schematic diagram of a chip provided by an embodiment of the present application;

[0053] Figure 11 is a schematic diagram of a computer-readable storage medium provided by an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the present application clearer, embodiments of the present application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Those skilled in the art can know that, as new application scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0055] The terms "first", "second", and the like in the description and in the claims of the present application and above drawings are used for distinguishing between similar objects and not necessarily for describing a specific sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the application are capable of functioning in other sequences than those explicitly described or illustrated herein. Furthermore, the terms "comprise", "include", "contain" and "have" and any variations thereof used in the present application are intended to cover a non-exclusive inclusion, such that e.g. a process, method, article or apparatus that comprises, includes or contains one step or unit A also comprises, includes or contains another step or unit B, unless there are limitations in the point of the present application. The naming or numbering of steps appearing in the present application does not mean that the steps in the method flow must be executed in the time / logical order indicated by the naming or numbering, and the named or numbered flow steps can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved. The division of units appearing in the present application is a logical division, and in actual application, there can be another division manner, for example, multiple units can be combined or integrated into another system, or some features can be ignored or not executed, in addition, the coupling or direct coupling or communication connection between the units shown or discussed can be through some interface, the indirect coupling or communication connection between the units can be electrical or other similar forms, which are not limited in the present application. And the units or sub-units described as separate components can or can not be physically separated, can or can not be physical units, or can be distributed into multiple circuit units, and part or all of the units can be selected according to actual needs to achieve the purpose of the present application.

[0056] With the rapid development of artificial intelligence technology, the traditional processor architecture has been unable to meet the growing performance demand. The industry accelerates key operators on specific hardware chips based on AI compilation frameworks such as Tvm and Halide, which can realize the construction of high-performance neural network models.

[0057] The multi-buffer technology (also referred to as n-buffer technology) is widely used to improve the pipeline efficiency of the entire data stream. The multi-buffer technology can reduce the memory access latency of data transfer and calculation, thereby accelerating data execution. The multi-buffer technology needs to expand the original cache size. When optimizing the performance of a single operator, the developer will selectively use n-buffer optimization according to the use case scenario or resource consumption. In this way, optimization for different buffer quantities will derive a series of different templates. Through combination, as shown in FIG. 1, the problem of template expansion will be caused. In the binary release process, each template needs to correspond to a bin file, which leads to a large release package file and large deployment storage, thereby affecting the efficiency of customer-side deployment.

[0058] The system architecture and application scenario of the embodiments of the present application will be introduced below. Please refer to FIG. 2, which is a schematic diagram of a system architecture in the embodiments of the present application.

[0059] As shown in FIG. 2, the compiling device 320 compiles the source program 350 to obtain the program compilation result 301. The source program 350 is the program (first program or second program) in the embodiments of the present application, which can be a program for multi-dimensional data operation in different scenarios, including image processing, speech recognition, scientific calculation, or physical modeling, etc. The compiling device 320 can be any device containing a compiler (such as GCC or LLVM compiler, etc.).

[0060] The compiling process of the compiling device 320 on the source program 350 will be described in detail below based on the embodiment shown in FIG. 2.

[0061] The program compilation result 301 obtained by compiling with the compiling device 320 can be applied to different systems or devices, such as the execution device 310 shown in FIG. 2. The execution device 310 can be a terminal, such as a mobile phone terminal, a tablet computer, a notebook computer, an augmented reality (AR) / virtual reality (VR), a vehicle-mounted terminal, etc., and can also be a server or a cloud, etc. In FIG. 2, the execution device 310 is configured with an input / output (I / O) interface 312 for data interaction with external devices.

[0062] The execution device 310 can receive data in the database 330 or input by the client device 340, and use the computing module 311 to execute the related calculation process in the program compilation result 301 to obtain the corresponding processing result.

[0063] Finally, the I / O interface 312 returns the processing result (e.g., image processing result or speech recognition result, etc.) to the client device 340 for providing to the user.

[0064] It is worth noting that the compiling device 320 can compile source programs for different targets or different tasks to obtain corresponding program compilation results 301, and then the execution device 310 executes the related computing process in the program compilation results 301 to obtain the processing results required for different targets or different tasks.

[0065] In the case shown in FIG. 2, the user can manually give the input data, which can be operated through the interface provided by the I / O interface 312. In another case, the client device 340 can automatically send the input data to the I / O interface 312, and if the authorization of the user is required for the client device 340 to automatically send the input data, the user can set the corresponding permission in the client device 340. The user can view the result output by the execution device 310 in the client device 340, and the specific presentation form can be a specific way such as display, sound, action, etc.

[0066] It is worth noting that FIG. 2 is only a schematic diagram of a system architecture provided by an embodiment of the present application, and the positional relationship between the devices, components, modules, etc. shown in the figure does not constitute any limitation. For example, in FIG. 2, the compiling device 320 is an external device relative to the execution device 310, and in other cases, the compiling device 320 can be placed in the execution device 310. The execution device 310 is an external device relative to the client device 340, and in other cases, the execution device 310 and the client device 340 can be the same device.

[0067] It should be understood that the compiling method in the embodiments of the present application can be applied to scenarios requiring multi-dimensional data operation in the fields of artificial intelligence (such as image processing or speech recognition, etc.), scientific computing, physical modeling, etc. First, the image data to be processed is obtained, and the image data to be processed is defined in a high-level language (e.g., C, C++, or Python programming language, etc.) to obtain a multi-dimensional data program representation 420 corresponding to the image data to be processed (i.e., the source program in FIG. 2).

[0068] The compiling method in the embodiments of the present application is executed by the compiling device 320 to obtain a program compilation result (i.e., the program compilation result 301 in FIG. 2). The program compilation result is optimized and instruction mapping, etc. to obtain a hardware machine language executable on hardware (e.g., CPU or GPU, etc.).

[0069] The hardware machine language is run by the execution device 310 to perform corresponding multi-dimensional data operation to obtain an image processing result.

[0070] It should be understood that in FIG. 2, the compiling device 320 is an external device relative to the execution device 310, and in other cases, the compiling device 320 can also be placed in the execution device 310.

[0071] The system architecture to which the method provided in the embodiment is applied is introduced above, and the specific execution process of the method provided in the embodiment will be introduced in detail below with reference to the drawings.

[0072] Please refer to FIG. 3, which is a flowchart of a data processing method provided in an embodiment of the present application. As shown in FIG. 3, the data processing method includes the following steps 301-302.

[0073] In step 301, source code and first indication information are obtained, and the first indication information is used to indicate the number of buffers to be opened for optimization.

[0074] In the embodiment of the present application, source code to be compiled can be obtained, and the source code can be code written by using an application editing interface of a high-level editing language. For example, the high-level programming language can be a domain specific language (DSL), and the DSL language can be Halide, GraphIt, Spatial, or other customized domain specific language. Halide is suitable for vector and tensor operations, GraphIt is suitable for the field of graph computing, Spatial is suitable for the field of programmable hardware, and the customized domain specific language is suitable for the corresponding customized field.

[0075] Referring to FIG. 1, buffers (indicated as shared_mem in the figure) of different colors represent different caches to be used in different operations, for example, shared_memA is a cache to be used when reading and carrying data to be operated, shared_memB is a cache to be used when performing operations on the read data, and shared_memC is a cache to be used when carrying the results of the operations. When double buffer optimization is not opened, shared_memA, shared_memB and shared_memC need to be used in sequence to perform data reading and carrying, operations and result carrying in sequence. When double buffer optimization is opened and shared_memA, shared_memB and shared_memC are all split, shared_memA includes two parts, and when shared_memA is used for reading and carrying, shared_memB can be used in parallel for data operations, and so on, so that the overall operation process is accelerated.

[0076] When compiling the source code, whether to enable multi-buffer optimization and the number of buffers of the enabled multi-buffer optimization can be selected. When compiling, the compiler can compile the source code based on a preset template to obtain machine code. The template can include execution relationships of operations in the source code, such as whether to be parallel, a sequence constraint, and the like. Specifically, the template can include relationships between the buffers, such as storage spaces of the buffers, a sequence constraint, a waiting relationship, and whether to be parallel between different buffers. In the prior art, different templates correspond to multi-buffer optimization of different numbers of buffers, which can cause excessive storage overhead and reduce deployment efficiency. In an embodiment of the present application, the multi-buffer optimization of different numbers of buffers can share the same template. The template (that is, the target template in the embodiment of the present application) can be adapted to multi-buffer optimization of different numbers of buffers. Specifically, the template can include a variable (that is, the first variable in the embodiment of the present application) related to the number of buffers of the enabled multi-buffer optimization. When compiling, the variable in the template needs to be assigned based on the number of buffers of the enabled multi-buffer optimization, so as to obtain the corresponding intermediate representation (IR). Since the multi-buffer optimization of different numbers of buffers can share the same template, the storage overhead during deployment can be reduced. In the binary publishing process, a single template only needs to correspond to one bin file. Compared with multiple templates, the publishing package file of the single template is smaller, which can improve the efficiency of customer-side deployment. In addition, the multi-template form causes a long time during compiling, which is not conducive to online compiling of the model. The single template in the embodiment of the present application can reduce the compiling time.

[0077] It should be understood that the number of buffers of the enabled multi-buffer optimization in the embodiment of the present application can be the split number of the cache used for each operation. For example, the split number for shared_memA can be 2, the split number for shared_memB can be 1 (that is, not split), and the split number for shared_memC can be 2.

[0078] In a possible implementation, the number of buffers of the enabled multi-buffer optimization indicated in the first indication information can be specified by a user (or a provider of the source code, which can be a user or a device) or determined by the compiling system itself, for example, based on the current running environment. The embodiment of the present application does not limit this.

[0079] At step 302, the first variable in the target template is assigned a value by the compiler according to the source code and the first indication information to obtain an intermediate representation IR of the source code, and machine code is obtained according to the IR.

[0080] In a possible implementation, the source code can be compiled by a compiler calling a target template according to the source code and the first indication information to obtain machine code. The target template is a template for multi-buffer optimization adapted to different buffer numbers, and the target template includes a first variable related to the buffer number of the multi-buffer optimization. The compiler is configured to assign a value to the first variable in the target template based on the buffer number, to obtain an intermediate representation IR of the source code, and to obtain machine code according to the IR.

[0081] Next, the first variable and how the template adapts to multi-buffer optimization of different buffer numbers through the first variable are introduced.

[0082] In multi-buffer optimization of different buffer numbers, the buffer space allocated to each operation can be different. For example, referring to FIG. 6, multi-buffer optimization is not enabled in FIG. 6, and the starting address of the buffer B is the starting address of the buffer A plus the address offset of the buffer A. Referring to FIG. 7, double buffer optimization is enabled in FIG. 7, and the starting address of the buffer A1 is the starting address of the buffer A0 plus the address offset of the buffer A0, and the starting address of the buffer B is the starting address of the buffer A1 plus the address offset of the buffer A1.

[0083] Therefore, the starting address of each buffer can be specified in the template, and the starting address of the buffer is related to the buffer number. For example, the allocation of the storage space of different buffers on the shared memory is essentially affected by each other. For example, whether the double buffer of the buffer A is enabled determines the starting address of the buffer B, as shown in FIG. 7. Therefore, when the n value of the nbuffer defined by the actual operator compute is not perceived, the memory size also needs to be dynamically allocated. Random n buffers:

[0084] shared_mem A = ALL_LOOP % N == 0? A[0] : (ALL_LOOP % N == 1? A[1] :...);

[0085] shared_mem B = A + (ALL_LOOP % N == 0? B[0] : (ALL_LOOP % N == 1? B[1] :...));

[0086] Taking the first operation as an example, in a possible implementation, the target template includes: a first cache space used by the first operation, the first cache space is represented by a starting address and an address offset; the first operation is an operation within a loop count in a loop operation, the starting address is represented by first information, and the first information is the relationship between the loop count in which the first operation is located and the first variable.

[0087] In a possible implementation, the target template further includes multiple candidate start addresses; the first information is specifically a modulo result of a loop count of the first operation and the first variable, and different candidate start addresses correspond to different modulo results.

[0088] The operation is often a loop operation. For example, as shown in FIG7 , when the loop count is an even number such as 0, 2, 4, 6, or 8, the cache used by the operation is A0. When the loop count is an odd number such as 1, 3, 5, 7, or 9, the cache used by the operation is A1. Therefore, when the loop count is an even number, the starting address of the cache used by the operation is the starting address of A0. When the loop count is an odd number, the starting address of the cache used by the operation is the starting address of A1. For another example, as shown in FIG7 , when the loop count is an even number such as 0, 2, 4, 6, or 8, the cache used by the operation is B0. When the loop count is an odd number such as 1, 3, 5, 7, or 9, the cache used by the operation is B1. Therefore, when the loop count is an even number, the starting address of the cache used by the operation is the starting address of B0. When the loop count is an odd number, the starting address of the cache used by the operation is the starting address of B1.

[0089] For example, the target template may be:

[0090] #nbuffer

[0091] for jm

[0092] wait(comsumer_pipe,mode=j%N)

[0093] producer_instr(shared_mem A[j%N]+address offset)

[0094] set(producer_pipe,mode=j%N)

[0095] wait(producer_pipe,mode=j%N)

[0096] comsumer_instr(shared_mem A[j%N]+address offset)

[0097] set(comsumer_pipe, mode = j % N)

[0098] wherein the producer can be a process of an operation of reading and carrying data, the operation using an address of shared_mem A[j % N] + offset, wherein % represents remainder, j is a current loop count, N is a number of buffers of the multi-buffer optimization enabled, when j is even, a cache start address used by the operation is shared_mem A[0], and when j is odd, the cache start address used by the operation is shared_mem A[1].

[0099] In a possible implementation, the target template comprises: a first execution constraint between the second operation and the third operation; the first execution constraint indicates whether to perform the second operation and the third operation in parallel, the second operation and the third operation belong to operations of different loop counts in a loop operation, and the execution order constraint is represented by a relationship between second information and third information, the second information is a relationship between a loop count in which the second operation is located and the first variable, and the third information is a relationship between a loop count in which the third operation is located and the first variable.

[0100] In a possible implementation, the second information specifically is a remainder result of a number and a loop count in which the second operation is located; the third information specifically is a remainder result of the number and a loop count in which the third operation is located; and when the second information and the third information are the same, the first execution constraint indicates that the second operation and the third operation are not performed in parallel.

[0101] The multi-buffer optimization can accelerate the data processing process mainly because some operations are performed in parallel. The concept of inter-instruction synchronization and "lock" of the operations is similar, controls the execution logic between data, and determines the actual data flow arrangement. As shown in FIG. 4 and FIG. 5, FIG. 4 is a data execution order of a single buffer, and FIG. 5 is a data execution order of a double buffer. Mode represents a synchronization mode, and the synchronization instructions of set and wait are matched and associated through the mode value. Here, in order to better enable the nbuffer to be parallel, it is necessary to dynamically allocate and generate a synchronization mode: mode = (ALL_LOOP % N)

[0102] wherein the synchronization mode of the single buffer is mode = 0, and the synchronization mode of the double buffer is mode = loop_count % 2, wherein loop_count represents a current loop count.

[0103] For example, the target template can be:

[0104] #nbuffer

[0105] for jm

[0106] wait(comsumer_pipe,mode=j%N)

[0107] producer_instr(shared_mem A[j%N]+bias)

[0108] set(producer_pipe,mode=j%N)

[0109] wait(producer_pipe,mode=j%N)

[0110] comsumer_instr(shared_mem A[j%N]+address offset)

[0111] set(comsumer_pipe,mode=j%N)

[0112] The order of the codes indicates the order of execution, and the wait instruction requires the completion of the previous set of the same mode before execution, without having to wait for the completion of the previous set of different modes, that is, parallel execution.

[0113] In addition to multi-buffer optimization, preload technology (pre-loading technology, that is, reading and moving data after loop counting in advance) is also used to improve the efficiency of the entire data flow. Proload technology can load related data in advance.

[0114] In addition to being compatible with buffer optimization for different buffer numbers, the target template in the embodiment of the present application can also be compatible with enabling or disabling preload optimization. Similar to the above, a variable related to whether preload optimization is enabled can also be set in the target template (that is, the second variable in the embodiment of the present application). Based on the assignment of this variable, the IR obtained based on the template can be an IR with or without preload optimization enabled.

[0115] In one possible implementation, second indication information can be obtained, and the second indication information is used to indicate whether to enable preload optimization; wherein, the target template is also adapted to enable or not enable preload optimization, and the target template includes a second variable related to whether to enable preload optimization, and the compiler is further used to assign a value to the second variable in the target template based on whether to enable preload optimization, to obtain an intermediate representation IR of the source code.

[0116] Through the above method, a template can be used to represent both nbuffer and preload, thereby implementing a common template on the operator side, further reducing storage overhead and encoding time overhead.

[0117] In one possible implementation, when the second indication information indicates to turn on preload, the second variable in the target template is assigned a first preset value, and when the second variable is the first preset value, the IR indicates to execute the first code and the second code, the first code indicates to load the data required for the operation with a loop count of 0, and the second code indicates to preload the data required for the operation with a loop count of j+1, where j is the current loop count.

[0118] In one possible implementation, when the second indication information indicates that preload is not enabled, the second variable in the target template is assigned a second preset value, and when the second variable is the second preset value, the IR indicates the execution of a third code, and the third code indicates the loading of data required for an operation with a loop count of j, where j is the current loop count.

[0119] Among them, when preload optimization is turned on, the data reading and moving operation with a loop count of 0 can be executed first, and then the data reading and moving operation with a loop count of 1 can be executed. That is, the data calculation operation with a loop count of 0 is not executed, but the data loading of the next loop count is performed in advance (when it is not turned on, the data calculation operation with a loop count of 0 is executed here).

[0120] For example, the target template may be:

[0121] #preload

[0122] for jm

[0123] if(j==0):

[0124] wait(consumer_pipe,mode=0)

[0125] producer_instr(shared_mem A[0]+address offset)

[0126] set(producer_pipe,mode=0)

[0127] if(j<m-1):

[0128] wait(comsumer_pipe,mode=(j+1)%N)

[0129] producer_instr(shared_mem A[j+1 % N] + address offset)

[0130] set(producer_pipe, mode = (j+1) % N)

[0131] wait(producer_pipe, mode = j % N)

[0132] comsumer_instr(shared_mem A[j % N] + address offset)

[0133] set(comsumer_pipe, mode = j % N)

[0134] where, when the preload optimization is enabled, the data transfer operation with the loop count of 0 is executed first, and when the loop count is not the last one (j < m-1), the data transfer operation with the loop count of j+1 is executed first, and then the data operation with the loop count of j is executed, for example, the data transfer operation with the loop count of 1 is executed first, and then the data operation with the loop count of 0 is executed, thereby playing the function of data preloading.

[0135] Exemplarily, the target template can be:

[0136] shared_mem A = ALL_LOOP % N == 0? A[0] : (ALL_LOOP % N == 1? A[1] :...) # dynamic memory

[0137] shared_mem B = A[0] + (ALL_LOOP % N == 0? B[0] : (ALL_LOOP % N == 1? B[1] :...)) # dynamic memory

[0138] for j m

[0139] if (j == 0 && ~pre_ctrl_var): # built-in preload

[0140] wait(comsumer_pipe, mode = 0)

[0141] producer_instr(shared_mem A[0] + address offset)

[0142] set(producer_pipe, mode = 0)

[0143] if (j < m-1 || ~pre_ctrl_var):

[0144] wait(comsumer_pipe,mode=(j+pre_ctrl_var) % N) # dynamic mode

[0145] producer_instr(shared_mem A[(j+pre_ctrl_var) % N] + offset)

[0146] set(producer_pipe,mode=(j+pre_ctrl_var) % N) # dynamic mode

[0147] wait(producer_pipe,mode=j % N)

[0148] comsumer_instr(shared_mem A[j % N] + offset)

[0149] set(comsumer_pipe,mode=j % N)

[0150] This target template shows the case of combining multi-buffer optimization and preload optimization into the same template, where pre_ctrl_var is the second variable.

[0151] When preload optimization is on, pre_ctrl_var is 1, and when preload optimization is off, pre_ctrl_var is 0. When pre_ctrl_var is 1, j == 0 && 0, so the following is executed:

[0152] wait(comsumer_pipe,mode=0)

[0153] producer_instr(shared_mem A[0] + offset)

[0154] set(producer_pipe,mode=0)

[0155] When pre_ctrl_var is 1, j < m-1 || 0, so the following is executed:

[0156] wait(comsumer_pipe,mode=(j+1) % N) # dynamic mode

[0157] producer_instr(shared_mem A[(j+1) % N] + offset)

[0158] set(producer_pipe,mode=(j+1) % N) # dynamic mode

[0159] wait(producer_pipe,mode=j % N)

[0160] comsumer_instr(shared_mem A[j % N]+offset)

[0161] set(comsumer_pipe,mode=j % N)

[0162] if pre_ctrl_var is 0, j==0&&1, so not executed:

[0163] wait(comsumer_pipe,mode=0)

[0164] producer_instr(shared_mem A[0]+offset)

[0165] set(producer_pipe,mode=0)

[0166] if pre_ctrl_var is 0, j

[0167] wait(comsumer_pipe,mode=(j) % N)#dynamic mode

[0168] producer_instr(shared_mem A[(j) % N]+offset)

[0169] set(producer_pipe,mode=(j) % N)#dynamic mode

[0170] wait(producer_pipe,mode=j % N)

[0171] comsumer_instr(shared_mem A[j % N]+offset)

[0172] set(comsumer_pipe,mode=j % N)

[0173] Next, the data processing method of the embodiments of the present application is introduced in combination with several specific examples.

[0174] For example, the current input specification has 10*10, 100*100, 1000*1000 image matrix, the small matrix 10*10 can meet the use of hardware resources, and the single_buffer performance can achieve the best. The 100*100 image matrix needs double_buffer performance to achieve the best. The 1000*1000 image matrix has larger data volume, and needs preload optimization to obtain the best performance. Therefore, for the above scenarios, the operator front end Compute is expressed as follows:

[0175] (I) 10*10 specification single_buffer:

[0176] The generated IR is as follows:

[0177] (II) 100*100 specification double_buffer:

[0178] The generated IR is as follows:

[0179] (III) 1000*1000 specification double_buffer and preload:

[0180] The generated IR is as follows:

[0181] Due to different scenarios, multiple templates may appear in the pursuit of extreme performance.

[0182] The application utilizes dynamic synchronization and memory code generation to realize the functions of single, double, etc. nbuffer and preload with one code, and realizes common templates on the operator side.

[0183] The operator front end Compute is as follows:

[0184] The finally generated IR is as follows:

[0185] The above describes the method provided by the embodiments of the application in detail, and next, the device for executing the above method provided by the embodiments of the application will be introduced.

[0186] Please refer to FIG. 8, which is a structural schematic diagram of a data processing apparatus provided by an embodiment of the application. As shown in FIG. 8, the data processing apparatus comprises an acquisition module 1001 configured to acquire source code and first indication information, wherein the first indication information is used to indicate the number of buffers to be opened for optimization.

[0187] The processing module 1002 is configured to assign a value to the first variable in the target template according to the source code and the first indication information, to obtain an intermediate representation (IR) of the source code by using a compiler, and to obtain machine code according to the IR.

[0188] In a possible implementation, the target template is a template adapted to different buffer quantities.

[0189] In a possible implementation, the first variable is a variable in the target template that is related to the buffer quantity.

[0190] In a possible implementation, the target template includes:

[0191] The first cache space used by the first operation, the first cache space being represented by a start address and an address offset; the first operation is an operation within a loop count in a loop operation, the start address being represented by the first information, and the first information being a relationship between the loop count in which the first operation is located and the first variable.

[0192] In a possible implementation, the target template further includes a plurality of candidate start addresses; the first information specifically is a remainder result of the loop count in which the first operation is located and the first variable, and different candidate start addresses correspond to different remainder results.

[0193] In a possible implementation, the target template includes:

[0194] The first execution constraint between the second operation and the third operation; the first execution constraint indicates whether the second operation and the third operation are executed in parallel, the second operation and the third operation belong to operations in different loop counts in a loop operation, and the execution order constraint is represented by a relationship between the second information and the third information, the second information being a relationship between the loop count in which the second operation is located and the first variable, and the third information being a relationship between the loop count in which the third operation is located and the first variable.

[0195] In a possible implementation, the second information specifically is a remainder result of the loop count in which the second operation is located and the quantity;

[0196] The third information specifically is a remainder result of the loop count in which the third operation is located and the quantity;

[0197] When the second information and the third information are the same, the first execution constraint indicates that the second operation and the third operation are not executed in parallel.

[0198] In a possible implementation, the obtaining module 1001 is further configured to:

[0199] obtain second indication information, the second indication information being used to indicate whether to enable a preload optimization; and

[0200] The target template is also adapted to turn on or not turn on the preload optimization, the target template includes a second variable related to whether to turn on the preload optimization, and the compiler is further configured to assign a value to the second variable in the target template based on whether to turn on the preload optimization, to obtain the intermediate representation IR of the source code.

[0201] In a possible implementation, when the second indication information indicates that the preload is turned on, the second variable in the target template is assigned a first preset value, and when the second variable is the first preset value, the IR indicates execution of first code and second code, the first code indicates data required for an operation with a loop count of 0, and the second code indicates data required for an operation with a loop count of j+1, where j is a current loop count.

[0202] In a possible implementation, when the second indication information indicates that the preload is not turned on, the second variable in the target template is assigned a second preset value, and when the second variable is the second preset value, the IR indicates execution of third code, the third code indicates data required for an operation with a loop count of j, where j is a current loop count.

[0203] Referring to FIG. 9, FIG. 9 is a structural schematic diagram of an execution device provided by an embodiment of the present application. The execution device 1100 can be embodied as a server, a personal computer, a smart phone, or the like, which is not limited herein. Specifically, the execution device 1100 includes a receiver 1101, a transmitter 1102, a processor 1103, and a memory 1104 (wherein the number of processors 1103 in the execution device 1100 can be one or more, and one processor is taken as an example in FIG. 9). The processor 1103 can include an application processor 11031 and a communication processor 11032. In some embodiments of the present application, the receiver 1101, the transmitter 1102, the processor 1103, and the memory 1104 can be connected through a bus or other manners.

[0204] The memory 1104 can include a read-only memory and a random access memory, and provide instructions and data for the processor 1103. A part of the memory 1104 can also include a non-volatile random access memory (NVRAM). The memory 1104 stores processor and operation instructions, executable modules or data structures, or subsets thereof, or expanded sets thereof, wherein the operation instructions can include various operation instructions for implementing various operations.

[0205] The processor 1103 controls the operation of the execution device. In a specific application, various components of the execution device are coupled together by a bus system, which can include a data bus, a power bus, a control bus, and a state signal bus, etc. However, for the sake of clarity, various buses are referred to as a bus system in the figure.

[0206] The method disclosed in the embodiments of the present application can be applied to the processor 1103 or implemented by the processor 1103. The processor 1103 can be an integrated circuit chip having a signal processing capability. In the implementation process, the steps of the above method can be completed by hardware integrated logic circuits in the processor 1103 or by instructions in the form of software. The processor 1103 described above can be a general processor, a digital signal processor (DSP), a microprocessor or a microcontroller, and can further include an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0207] The processor 1103 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium in the art. The storage medium is located in the memory 1104, and the processor 1103 reads the information in the memory 1104 and combines the hardware to complete the steps of the above method.

[0208] The receiver 1101 can be used to receive input digital or character information, and generate signal input related to the relevant settings and function control of the execution device. The transmitter 1102 can be used to output digital or character information through the first interface; the transmitter 1102 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; the transmitter 1102 can also include a display device such as a display screen.

[0209] The electronic device provided in the embodiments of the present application can be a chip, which includes a processing unit, for example, a processor, and a communication unit, for example, an input / output interface, a pin, or a circuit, etc. The processing unit can execute computer execution instructions stored in a storage unit, so as to enable the chip in the execution device to execute the model structure determination method described in the above embodiments, or so as to enable the chip in the training device to execute the model structure determination method described in the above embodiments. Alternatively, the storage unit is a storage unit in the chip, such as a register, a cache, etc., and the storage unit can also be a storage unit outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0210] Specifically, refer to FIG. 10, which is a structural schematic diagram of a chip provided in the embodiments of the present application. The chip can be a neural network processor NPU 1200, which is mounted on a host CPU (Host CPU) as a coprocessor and is assigned tasks by the Host CPU. The core part of the NPU is an operation circuit 1203, which extracts matrix data in a memory and performs multiplication operation under the control of a controller 1204.

[0211] In some implementations, the operation circuit 1203 internally includes a plurality of processing units (PEs). In some implementations, the operation circuit 1203 is a two-dimensional systolic array. The operation circuit 1203 can also be a one-dimensional systolic array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the operation circuit 1203 is a general-purpose matrix processor.

[0212] For example, it is assumed that there are an input matrix A, a weight matrix B, and an output matrix C. The operation circuit takes corresponding data of the matrix B from the weight memory 1202 and buffers them on each PE in the operation circuit. The operation circuit takes the matrix A data from the input memory 1201 and performs matrix operation with the matrix B, and the partial result or final result of the obtained matrix is saved in an accumulator 1208.

[0213] The unified memory 1206 is used to store input data and output data. The weight data is transferred to the weight memory 1202 through a direct memory access controller (DMAC) 1205. The input data is also transferred to the unified memory 1206 through the DMAC.

[0214] BIU for Bus Interface Unit, 1210, is used for the interaction between AXI bus and DMAC and instruction fetch buffer (IFB) 1209.

[0215] Bus Interface Unit (BIU) 1210 is used for instruction fetch buffer 1209 to fetch instructions from external memory, and also used for input matrix A or weight matrix B data fetch from external memory by memory access controller 1205.

[0216] DMAC is mainly used to move input data in external memory DDR to unified memory 1206, or to move weight data to weight memory 1202, or to move input data to input memory 1201.

[0217] Vector computation unit 1207 includes multiple operation processing units, which further process the output of operation circuit 1203 as needed, such as vector multiplication, vector addition, exponential operation, logarithmic operation, size comparison, etc. It is mainly used for non-convolution / full connection layer network computation in neural network, such as batch normalization, pixel-level summation, upsampling of feature plane, etc.

[0218] In some implementations, vector computation unit 1207 can store the processed output vector to unified memory 1206. For example, vector computation unit 1207 can apply a linear function; or, a non-linear function to the output of operation circuit 1203, such as linear interpolation on the feature plane extracted by convolution layer, and further, for example, a vector of accumulated values to generate activation values. In some implementations, vector computation unit 1207 generates normalized values, pixel-level summation values, or both. In some implementations, the processed output vector can be used as activation input to operation circuit 1203, for example, for use in subsequent layers in neural network.

[0219] Controller 1204 is connected to instruction fetch buffer 1209, which is used to store instructions used by controller 1204;

[0220] Unified memory 1206, input memory 1201, weight memory 1202, and instruction fetch buffer 1209 are all on-chip memories. External memory is private to the NPU hardware architecture.

[0221] Any of the above-mentioned processors can be a general central processing unit, microprocessor, ASIC, or one or more integrated circuits for controlling the execution of the above-mentioned programs.

[0222] Referring to FIG. 11, there is shown a structural diagram of a computer readable storage medium according to an embodiment of the present application. The present application also provides a computer readable storage medium, in some embodiments, the method disclosed in FIG. 3 above can be implemented as computer program instructions encoded in a computer readable storage medium or other non-transitory medium or article in a machine readable format.

[0223] FIG. 11 schematically illustrates a conceptual partial view of an example computer readable storage medium arranged in accordance with at least some embodiments presented herein, the example computer readable storage medium including a computer program for executing a computer process on a computing device.

[0224] In one embodiment, the computer readable storage medium 1300 is provided using a signal bearing medium 1301. The signal bearing medium 1301 can include one or more program instructions 1302 which, when executed by one or more processors, can provide the functionality or some portion of the functionality described above with respect to FIG. 3.

[0225] In some examples, the signal bearing medium 1301 can embody a computer readable medium 1303, such as, but not limited to, a hard disk drive, a compact disk (CD), a digital video disk (DVD), a digital tape, memory, ROM, RAM, or the like.

[0226] In some implementations, the signal bearing medium 1301 can embody a computer recordable medium 1304, such as, but not limited to, memory, a read / write (R / W) CD, a R / W DVD, or the like. In some implementations, the signal bearing medium 1301 can embody a communication medium 1305, such as, but not limited to, a digital and / or an analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communication link, a wireless communication link, and / or the like). Thus, for example, the signal bearing medium 1301 can be conveyed by a wireless form of the communication medium 1305 (e.g., a wireless communication medium complying with the IEEE 802.11 standard or other transmission protocol).

[0227] The one or more program instructions 1302 can be, for example, computer executable instructions or logic-implementing instructions. In some examples, a computing device of a computing device can be configured to provide various operations, functions, or actions in response to the program instructions 1302 being conveyed to the computing device by one or more of the computer readable medium 1303, the computer recordable medium 1304, and / or the communication medium 1305.

[0228] It should be noted that the apparatus embodiments described above are merely illustrative, and units described as separate components can or can not be physically separate, and components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the connection relationship between the modules in the apparatus embodiment provided in the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines.

[0229] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software and the necessary general hardware, and of course can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure for implementing the same function can also be various, such as analog circuit, digital circuit or special circuit, etc. However, for the present application, software program implementation is a better embodiment. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., including a plurality of instructions to make a computer device (which can be a personal computer, training device, or network device, etc.) execute the methods of various embodiments of the present application.

[0230] In the above embodiments, all or part can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in the form of a computer program product in whole or in part.

[0231] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website site, computer, training device or data center to another website site, computer, training device or data center through wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can store or be integrated into a training device, data center, etc. data storage device including one or more available media sets. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

Claims

1. A data processing method, applied to a scenario of optimizing multiple buffers, is characterized in that: The method comprises: Obtain source code and first indication information, where the first indication information is used to indicate the number of buffers to enable optimization; According to the source code and the first indication information, a compiler assigns a value to a first variable in a target template to obtain an intermediate representation IR of the source code, and obtains a machine code according to the IR.

2. The method according to claim 1, characterized in that The target template is a template adapted to different buffer quantities.

3. The method according to claim 1 or 2, characterized in that The first variable is a variable in the target template that is related to the buffer quantity.

4. The method according to claim 1, wherein The method is applied to a scenario where multiple buffers are optimized.

5. The method according to any one of claims 1 to 4, characterized in that: The target template includes: A first cache space used by a first operation, the first cache space being represented by a starting address and an address offset; the first operation being an operation within a loop count in a loop operation, the starting address being represented by first information, and the first information being a relationship between the loop count in which the first operation is located and the first variable.

6. The method according to claim 5, characterized in that The target template further includes a plurality of candidate starting addresses; the first information is specifically a modulo result of a loop count where the first operation is located and the first variable, and different candidate starting addresses correspond to different modulo results.

7. The method according to any one of claims 1 to 6, characterized in that: The target template includes: A first execution constraint between a second operation and a third operation; the first execution constraint indicates whether to execute in parallel, the second operation and the third operation belong to operations with different loop counts in a loop operation, and the execution order constraint is represented by a relationship between second information and third information, the second information being a relationship between the loop count where the second operation is located and the first variable, and the third information being a relationship between the loop count where the third operation is located and the first variable.

8. The method according to claim 7, characterized in that The second information is specifically a modulo result of a loop count of the second operation and the quantity; The third information is specifically a modulo result of the loop count of the third operation and the quantity; When the second information and the third information are the same, the first execution constraint indicates that the second operation and the third operation are not executed in parallel.

9. The method according to any one of claims 1 to 8, characterized in that: The method further comprises: Obtain second indication information, where the second indication information is used to indicate whether to enable preload optimization; wherein, The target template is also adapted to enable or disable preload optimization, and the target template includes a second variable related to whether preload optimization is enabled. The compiler is also used to assign a value to the second variable in the target template based on whether preload optimization is enabled to obtain an intermediate representation IR of the source code.

10. The method according to claim 9, characterized in that When the second indication information indicates to turn on preload, the second variable in the target template is assigned a first preset value, and when the second variable is the first preset value, the IR indicates the execution of a first code and a second code, the first code indicates loading data required for an operation with a loop count of 0, and the second code indicates preloading data required for an operation with a loop count of j+1, where j is the current loop count.

11. The method according to claim 10, characterized in that When the second indication information indicates that preload is not enabled, the second variable in the target template is assigned a second preset value, and when the second variable is the second preset value, the IR indicates the execution of a third code, and the third code indicates the loading of data required for an operation with a loop count of j, where j is the current loop count.

12. A data processing device, used in a scenario of optimizing multiple buffers, characterized in that: The device comprises: An acquisition module, configured to acquire source code and first indication information, wherein the first indication information is used to indicate the number of buffers for which optimization is enabled; A processing module is configured to assign a value to a first variable in a target template through a compiler according to the source code and the first indication information to obtain an intermediate representation IR of the source code, and obtain a machine code according to the IR.

13. The device according to claim 12, characterized in that The target template is a template adapted to different buffer quantities.

14. The device according to claim 12 or 13, characterized in that The first variable is a variable in the target template that is related to the buffer quantity.

15. The device according to any one of claims 12 to 14, characterized in that The target template includes: A first cache space used by a first operation, the first cache space being represented by a starting address and an address offset; the first operation being an operation within a loop count in a loop operation, the starting address being represented by first information, and the first information being a relationship between the loop count in which the first operation is located and the first variable.

16. The device according to claim 15, characterized in that The target template further includes a plurality of candidate starting addresses; the first information is specifically a modulo result of a loop count where the first operation is located and the first variable, and different candidate starting addresses correspond to different modulo results.

17. The device according to any one of claims 12 to 16, characterized in that The target template includes: A first execution constraint between a second operation and a third operation; the first execution constraint indicates whether to execute in parallel, the second operation and the third operation belong to operations with different loop counts in a loop operation, and the execution order constraint is represented by a relationship between second information and third information, the second information being a relationship between the loop count where the second operation is located and the first variable, and the third information being a relationship between the loop count where the third operation is located and the first variable.

18. The device according to claim 17, characterized in that The second information is specifically a modulo result of a loop count of the second operation and the quantity; The third information is specifically a modulo result of the loop count of the third operation and the quantity; When the second information and the third information are the same, the first execution constraint indicates that the second operation and the third operation are not executed in parallel.

19. The device according to any one of claims 12 to 18, characterized in that The acquisition module is further used to: Obtain second indication information, where the second indication information is used to indicate whether to enable preload optimization; wherein, The target template is also adapted to enable or disable preload optimization, and the target template includes a second variable related to whether preload optimization is enabled. The compiler is also used to assign a value to the second variable in the target template based on whether preload optimization is enabled to obtain an intermediate representation IR of the source code.

20. The device according to claim 19, characterized in that When the second indication information indicates to turn on preload, the second variable in the target template is assigned a first preset value, and when the second variable is the first preset value, the IR indicates the execution of a first code and a second code, the first code indicates loading data required for an operation with a loop count of 0, and the second code indicates preloading data required for an operation with a loop count of j+1, where j is the current loop count.

21. The device according to claim 20, characterized in that When the second indication information indicates that preload is not enabled, the second variable in the target template is assigned a second preset value, and when the second variable is the second preset value, the IR indicates the execution of a third code, and the third code indicates the loading of data required for an operation with a loop count of j, where j is the current loop count.

22. A data processing device, characterized in that: The device comprises a memory and a processor; the memory stores codes, the processor is configured to execute the codes, and when the codes are executed, the device executes the method according to any one of claims 1 to 11.

23. A computer storage medium, characterized in that The computer storage medium stores instructions, which, when executed by a computer, cause the computer to implement the method according to any one of claims 1 to 11.

24. A computer program product, characterized in that The computer program product stores instructions, which, when executed by a computer, cause the computer to implement the method according to any one of claims 1 to 11.

Images