Logarithmic detector capable of calibrating intercept, calibration method of logarithmic detector, and chip

Abstract

Disclosed in the embodiments of the present disclosure are a logarithmic detector capable of calibrating an intercept, a calibration method of the logarithmic detector, and a chip. The logarithmic detector comprises: a logarithmic amplifier, which receives a radio frequency signal, performs logarithmic transformation on the radio frequency signal, and outputs a first current; a plurality of editable units, which receive a plurality of control signals, and output a plurality of enable signals, wherein the control signals are used for controlling logical states of the editable units, and the editable units output the enable signals on the basis of the logical states; a plurality of current paths, which are connected to the editable units, wherein the current paths receive the enable signals, the enable signals are used for controlling the turning-on and turning-off of the current paths, and a turned-on current path is used for outputting a compensation current; and an arithmetic unit, which is connected to the logarithmic amplifier and the plurality of current paths, wherein the arithmetic unit receives the first current and the compensation current, and outputs a second current.

Description

Logarithmic detector with calibratable intercept, calibration method and chip thereof

[0001] Cross-reference to Related Applications

[0002] The present disclosure is based on and claims priority to Chinese Patent Application No. 202410413996.2, filed on April 8, 2024, entitled “Logarithmic detector with calibratable intercept, calibration method and chip thereof”, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the field of electronic devices, and more particularly, but not exclusively, to a logarithmic detector with calibratable intercept, a calibration method and a chip thereof. BACKGROUND

[0004] Logarithmic detectors are commonly used for measuring and detecting the amplitude of signals, which have the characteristic of converting input signals into output voltages or currents proportional to the logarithm of input signals. Logarithmic detectors are mainly used in radar, satellite communication, microwave point-to-point communication, test instruments, radio spectrum monitoring equipment, and are suitable for signal strength indication, wideband spectrum detection, fault detection, automatic gain control and other application scenarios. Logarithmic detectors have good application prospects and research significance.

[0005] Different logarithmic detectors are affected by full process angle mismatch and process deviation, which affects the performance of the logarithmic detector, so that the logarithmic curves of different logarithmic detectors are different, thereby causing the intercept of the logarithmic curve to have deviation, wherein the logarithmic curve is the curve of output voltage and input power. For logarithmic detectors, the intercept of the logarithmic curve is a critical parameter, so it is necessary to calibrate the intercept of the logarithmic curve. SUMMARY

[0006] Therefore, embodiments of the present disclosure provide a logarithmic detector with calibratable intercept, a calibration method and a chip thereof.

[0007] In a first aspect, embodiments of the present disclosure provide a logarithmic detector with calibratable intercept, comprising:

[0008] The log amplifier receives a radio frequency signal, converts the radio frequency signal into a logarithm, and outputs a first current; a plurality of editable units, which receive a plurality of control signals and output a plurality of enable signals, the control signals being used to control logic states of the editable units, the editable units outputting the enable signals according to the logic states; a plurality of current paths connected to the editable units, which receive the enable signals, the enable signals being used to control whether the current paths are turned on, the current paths that are turned on being used to output compensation currents; and an operation unit connected to the log amplifier and the plurality of current paths, which receives the first current and the compensation currents and outputs a second current.

[0009] In some embodiments, further comprising: a first transistor and a current source connected in series; the current path comprises: a first switch and a second transistor, wherein a first end of the first switch is connected to a control end of the first transistor, a second end of the first switch is connected to a control end of the second transistor, and a control end of the first switch receives the enable signal; and a first end of the second transistor is connected to a power supply voltage, and a second end of the second transistor outputs the compensation current.

[0010] In some embodiments, the editable unit is a fuse unit, the control signal is used to control a fuse state of the fuse unit, and the fuse unit outputs the enable signal according to the fuse state.

[0011] In some embodiments, the fuse unit comprises: the fuse unit comprises: a first unit and a second unit, a first end of the first unit is connected to a voltage receiving end and a working voltage end, and a second end of the first unit is connected to the second unit; a second end of the second unit is grounded; wherein the voltage receiving end is used to receive the control signal, and a second end of the first unit outputs the enable signal, wherein the first unit or the second unit is a fuse circuit or a fuse short circuit.

[0012] In some embodiments, the first unit is a fuse capacitor, and when the fuse capacitor is broken down by the control signal, a short circuit of the first unit is formed; and the second unit is a first resistor.

[0013] In some embodiments, the first unit is a second resistor; and the second unit is a fuse resistor, and when the fuse resistor is fused by the control signal, an open circuit of the second unit is formed.

[0014] In some embodiments, the editable unit is a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).

[0015] In some embodiments, the compensation current comprises a first compensation current and a second compensation current, and the first compensation current and the second compensation current are opposite in current direction.

[0016] In some embodiments, the operation unit comprises an adder and a subtractor, the first compensation current is sent to the adder, and the second compensation current is sent to the subtractor.

[0017] The adder and the subtractor are connected in series, or the operation unit further comprises a selection unit configured to switch the adder or the subtractor.

[0018] In some embodiments, the logarithmic detector further comprises:

[0019] an output unit connected to the operation unit and configured to receive the second current converted into an output voltage;

[0020] a feedback unit connected to the operation unit and connected to an output end of the output unit, and configured to provide a feedback current to the operation unit based on the output voltage;

[0021] The operation unit is specifically configured to obtain the second current based on the first current, one or more compensation currents, and the feedback current, and output the second current to the output unit.

[0022] In a second aspect, the embodiments of the present disclosure provide a calibration method of a logarithmic detector, the method being applied to any logarithmic detector described above, and the method comprising:

[0023] inputting the radio frequency signal into the logarithmic amplifier, and detecting an output voltage of the logarithmic amplifier;

[0024] obtaining an initial logarithmic curve of the logarithmic detector based on the output voltage and input power of the radio frequency signal;

[0025] obtaining an offset of the initial logarithmic curve relative to a standard logarithmic curve based on the initial logarithmic curve of the logarithmic detector and the standard logarithmic curve, and determining the control signal;

[0026] sending the control signal to the editable unit.

[0027] In a third aspect, the embodiments of the present disclosure further provide a chip, comprising:

[0028] at least one radio frequency channel;

[0029] Any one of the above logarithmic detectors is connected with the radio frequency channel and used for detecting the radio frequency signal provided by the radio frequency channel.

[0030] The logarithmic detector provided by the embodiment of the present disclosure includes a logarithmic amplifier, a plurality of editable units, a plurality of current paths and an operation unit. The logic state of the editable unit is controlled by using a control signal, and the editable unit with different logic states outputs a corresponding enable signal, so that the enable signal can control whether the corresponding current path outputs a compensation current. For the same logarithmic detector, when the input radio frequency signal is fixed, the first current is fixed, and the logarithmic curve is related to the size of the second current. If the size of the second current is to be changed, the size of the second current can be changed by adjusting the number of compensation currents, so as to adjust the output offset of the logarithmic detector, thereby adjusting the intercept of the logarithmic curve.

[0031] In this way, the initial logarithmic curve of a logarithmic detector can be measured when the current path does not output a compensation current. When the intercept in the initial logarithmic curve of the logarithmic amplifier is different from a target intercept, the number of editable units can be controlled by using a control signal, so as to control the number of compensation currents input to the operation unit, thereby achieving compensation of the second current. Therefore, the size of the second current can be adjusted by using different control signals, so as to adjust the output offset of the logarithmic detector, thereby adjusting the intercept of the logarithmic curve of the logarithmic detector, so that different logarithmic detector products have the same intercept of the logarithmic curve, thereby improving the yield of the products. BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1 is a structural schematic diagram of a logarithmic detector according to an embodiment of the present disclosure;

[0033] FIG. 2 is a structural schematic diagram of a logarithmic detector according to an embodiment of the present disclosure;

[0034] FIG. 3 is a circuit structural schematic diagram of a fuse unit and a current path in a logarithmic detector according to an embodiment of the present disclosure;

[0035] FIG. 4 is a circuit structural schematic diagram of a fuse unit and a current path in a logarithmic detector according to an embodiment of the present disclosure;

[0036] FIG. 5 is a circuit structural schematic diagram of a fuse unit and a current path in a logarithmic detector according to an embodiment of the present disclosure;

[0037] FIG. 6 is a structural schematic diagram of a logarithmic detector according to an embodiment of the present disclosure;

[0038] FIG. 7 is a flowchart of a calibration method of a logarithmic detector according to an embodiment of the present disclosure;

[0039] Fig. 8 is a schematic diagram of log curve intercept compensation of a log detector in the embodiment of the present disclosure;

[0040] Fig. 9 is a schematic diagram of a log curve before calibration of a log detector in the embodiment of the present disclosure;

[0041] Fig. 10 is a schematic diagram of a log curve after calibration of a log detector in the embodiment of the present disclosure;

[0042] Fig. 11 is a schematic diagram of a structure of a chip provided in the embodiment of the present disclosure.

[0043] Legend: 100-detector; 110-radio frequency logarithmic amplifier; 120-current operation module; 130-output module; 140-feedback module; 200-log detector; 210-logarithmic amplifier; 220-editable unit; 221-fuse unit; 230-current path; 240-operation unit; 250-output unit; 260-feedback unit; 300-chip; 301-radio frequency channel. DETAILED DESCRIPTION

[0044] In order to facilitate the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terminology used in the specification of the present disclosure is only for the purpose of achieving the description of the specific embodiments and is not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items. In the embodiments of the present application, the terms "first", "second", "third", "fourth" are only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", "third", "fourth" can be explicitly or implicitly included one or more of the features.

[0046] It should be understood that in the description of the embodiments of the present application, it is necessary to explain that, unless otherwise explicitly specified and limited, the terms "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be directly connected, or indirectly connected through an intermediate medium, or the communication inside two elements.

[0047] The terms involved in the embodiments of the present disclosure are explained as follows:

[0048] Log detector: A device used to measure and detect the amplitude of a signal, which has the characteristic of converting the input RF signal into a DC voltage proportional to the logarithm of the input signal.

[0049] Log curve: The curve of the output DC voltage signal of a log detector changing with the input signal. The horizontal coordinate of the log curve is the signal power of the input RF signal, and the unit of the RF signal power is exemplarily dBm (decibel-milliwatt). The vertical coordinate of the log curve is the output signal of the DC voltage, and the unit can be V (volt) or mV (millivolt).

[0050] Intercept of log curve: The voltage value corresponding to the intersection of the log curve and the vertical coordinate axis. The intercept of the log curve can also be understood as the output offset of the log detector.

[0051] Log amplifier: An amplifier with a logarithmic input-output relationship, for example, Vout = Vylog(Vin / Vx).

[0052] Transconductance: A property of an electronic component, which refers to the ratio of the change in output current to the change in input voltage. Transconductance devices are devices that convert voltage to current.

[0053] Efuse programming: Efuse is a fuse-like device, which belongs to one-time programmable memory. Usually, the one-time change of the circuit is realized by burning out or shortening a certain device through a large current.

[0054] Process corner: Refers to different process variations and parameter variations considered during chip design and manufacturing. On a wafer, it is impossible for the average drift velocity of carriers in each chip to be the same, and the characteristics of different chips will also be different with different voltages and temperatures. Different process characteristics are classified as PVT (Process, Voltage, Temperature) characteristics. Process characteristics are further divided into different process limits, which are called process corners. The log characteristic performance of the detector chip under different process corners will have certain dispersion.

[0055] As shown in FIG. 1, a circuit structure block diagram of a detector for implementing logarithmic detection. As shown in FIG. 1, the detector 100 is composed of multiple modules, including a radio frequency logarithmic amplifier 110, a current operation module 120, an output module 130, and a feedback module 140, etc. After the radio frequency signal RF to be detected is input, it is amplified by the radio frequency logarithmic amplifier 110 and an output current I corresponding to the amplitude is output. The current operation module 120 can be considered as a current version operational amplifier, which implements the addition operation or subtraction operation of the input current and outputs the current. The output module 130 is to convert the current into a direct current voltage (DC) output. At the same time, the direct current output is converted into a current (acting like a transconductance) by the feedback module 140 and output to the current operation module. Through the feedback loop in the dashed box, a stable direct current voltage output is achieved.

[0056] Generally, the slope of the logarithmic curve can be realized by the feedback module 140. Exemplarily, the feedback module can not be connected in the loop, that is, the output end of the output module 130 is not connected to the input end of the feedback module, but a controllable voltage is provided to the feedback module 140 alone, so that a specified current is output to realize the slope calibration of the logarithmic curve. However, the above method cannot realize the calibration of the intercept of the logarithmic curve. If the intercept of the logarithmic curve is not calibrated, the logarithmic curve of the logarithmic detector will have a certain degree of dispersion in different batches of wafers or different wafer regions, thereby affecting the screening of good products.

[0057] It can be understood that the logarithmic detector amplifies the input radio frequency signal through the logarithmic amplifier and outputs a current corresponding to the amplitude. The size of the output current corresponds to the amplitude of the signal to be detected (i.e. the amplitude of the input radio frequency signal) one by one. Taking a logarithmic detector with a negative slope logarithmic curve as an example: assuming that the slope of the logarithmic curve of the logarithmic detector is 20 mV / dBm, the power of the signal to be detected is -20 dBm, and the current flowing into the current operation module after the logarithmic amplifier is 0.6 mA. After the feedback loop is locked, the direct current voltage output through the output module is 0.8 V. Due to the process dispersion, the output voltage of different batches of chips is 0.7 V-0.9 V. This may be due to the deviation of the logarithmic amplifier caused by the process, so that the output current I of the logarithmic amplifier exists deviation, thereby the current I flowing into the current operation module 120 exists deviation, for example, the current I flowing into the current operation module 120 of different batches of chips is between 0.5 mA and 0.7 mA. Thus, for the same radio frequency input signal, the detected value will have a difference of 0.2 V / (20 mV / dBm) = 10 dBm, so that the intercept error of the logarithmic curve detected by different batches of detectors is large.

[0058] Therefore, the present disclosure provides a logarithmic detector with a calibratable intercept. As shown in FIG. 2, the logarithmic detector 200 provided by the present disclosure includes:

[0059] The logarithmic amplifier 210 receives the radio frequency signal RF, logarithmically converts the radio frequency signal RF, and outputs a first current I1;

[0060] The plurality of editable units 220 receive a plurality of control signals V, and output a plurality of enable signals EN. The control signals V are used to control the logic state of each editable unit, and the editable units 220 output the enable signals EN according to the logic state. In FIG. 2, there are x control signals, which are shown as a plurality of control signals xV.

[0061] The plurality of current paths 230 are connected to the editable units 220. The current paths 230 receive the enable signals EN, which are used to control whether the current paths 230 are turned on. The turned-on current paths 230 are used to output a compensation current I0, which is used to compensate the first current I1;

[0062] The operation unit 240 is connected to the logarithmic amplifier 210 and the plurality of current paths 230. The operation unit 240 receives the first current I1 and the compensation current I0, and outputs a second current I2. The operation unit 240 can perform addition or subtraction. In the embodiment shown in FIG. 2, the operation unit 240 can receive x compensation currents I0, which are shown as xI0. The value of x can be 0 or an integer greater than or equal to 1. When x is 0, the intercept of the logarithmic detector is not compensated.

[0063] The logarithmic amplifier 210 receives the radio frequency signal RF, logarithmically converts the radio frequency signal RF, and outputs a first current I1. The first current I1 is a current signal proportional to the logarithm of the power of the radio frequency signal RF. Correspondingly, the converted direct current voltage signal should also be a voltage signal proportional to the logarithm of the radio frequency signal RF. During the chip manufacturing process, there may be process deviations, resulting in a deviation between the actual logarithmic curve and the theoretical value. Since the logarithmic curve of the logarithmic detector is proportional to the output current signal, when the output current deviates, the intercept of the logarithmic curve and the intercept of the ideal logarithmic curve will have a positive or negative difference.

[0064] In order to compensate for the deviation of the intercept, a plurality of editable units 220 and a plurality of current paths 230 are used to jointly compensate for the deviation of the intercept, the state of the editable unit 220 is edited by using a control signal xV, and the editable unit outputs an enable signal EN with different logic states, so that the enable signal EN can control whether the current path 230 outputs the compensation current I0. By controlling the enable signal EN, the size of the second current I2 can be changed by adjusting the amount of the compensation current I0, so as to adjust the output offset of the logarithmic detector, thereby adjusting the intercept of the logarithmic curve. In this way, by compensating for the output current of the logarithmic detector, the intercept of the logarithmic curve of the logarithmic detector can be directly compensated, and the difference between the intercept of the logarithmic curve and the preset logarithmic curve can be reduced.

[0065] The preset logarithmic curve is an ideal logarithmic curve of the logarithmic detector, that is, a logarithmic curve expected by the logarithmic detector. When the logarithmic curve of the logarithmic detector is the preset logarithmic curve, the detection result and accuracy of the logarithmic detector meet the expectation.

[0066] In addition, if the logarithmic detector uses a direct current voltage as an output signal, the second current I2 after compensation can be further converted into a current voltage to output a corresponding direct current voltage. In this way, the process deviation of the logarithmic detector is compensated, and the intercept of the logarithmic curve is closer to the theoretical setting.

[0067] The editable unit is a logic device that can store and modify data. When the stored data is different, the editable unit presents different logic states. The logic state refers to the circuit structure state or the circuit logic state of the editable unit. For example, the editable unit can be a fuse unit. The fuse unit is a one-time programmable memory. The control signal can control the fuse state of the fuse unit. The fuse unit outputs the enable signal according to the fuse state. When the editable unit can be a fuse unit, the logic state refers to the circuit structure state of the editable unit, that is, the fuse state. The editable unit can also be a FPGA or a CPLD. The FPGA and the CPLD are programmable logic devices. The logic function is determined according to the user programming of the device. The FPGA and the CPLD can be edited multiple times. The control signal can be used for editing the FPGA and the CPLD, so as to change the logic state of the FPGA and the CPLD. The FPGA and the CPLD output the enable signal according to the logic state. When the editable unit can be a FPGA and a CPLD, the logic state refers to the circuit logic state of the editable unit, that is, the logic function.

[0068] The editable unit 220 is edited once in the embodiment of the present disclosure, the control of different current paths 230 is realized, one or more current paths that need to output the compensation current I0 are enabled, and the compensation of the first current I1 is realized. In this way, the dispersion of the logarithmic detector performance under different process angles can be compensated in a targeted manner, so as to improve the yield and consistency of the product.

[0069] In the embodiment shown in FIG. 2, the editable units 220 and the current paths 230 are in one-to-one correspondence, one editable unit 220 is used to control whether one current path 230 outputs the compensation current I0, the logarithmic detector 200 in FIG. 2 shows five editable units 220 and five current paths 230, the number of compensation currents I0 can be adjusted by controlling the number of valid control signals V, by editing the number of units in the editable units 220 that can be used to output valid enable signals. For example, when three control signals V are valid, three editable units 220 can be used to output valid enable signals, i.e. three enable signals EN are valid, so that three current paths 230 output three compensation currents I0 to compensate the first current I1.

[0070] In some embodiments, the control signal is configured to be determined based on an initial logarithmic curve of the logarithmic detector 200 and a preset standard logarithmic curve, the initial logarithmic curve being a logarithmic curve of the logarithmic detector 200 when all the current paths 230 do not output the compensation current I0.

[0071] The initial logarithmic curve is an uncalibrated logarithmic curve, which reflects the relationship between the current output by the logarithmic amplifier processing the radio frequency signal and the radio frequency signal. Due to process deviation, the initial logarithm of different products has a certain dispersion. The standard logarithmic curve is a theoretical curve calculated based on the parameters of the logarithmic detector device. That is, the intercept that needs to be compensated, i.e. the difference between the initial logarithmic curve of each logarithmic detector and the intercept of the standard logarithmic curve. According to the difference, the current value that needs to be compensated can be calculated, and then how many compensation currents are needed to compensate. Based on this, the corresponding control signal can be set.

[0072] In some embodiments, when the slope of the logarithmic curve is negative and the intercept of the initial logarithmic curve is greater than the intercept of the standard logarithmic curve, the control signal outputs the corresponding compensation current by editing the state of each editable unit, and then reduces the second current to shift the initial logarithmic curve downward, thereby achieving the purpose of calibrating the intercept; and / or, when the intercept of the initial logarithmic curve is less than the intercept of the standard logarithmic curve, the control signal outputs the corresponding compensation current by editing the state of each editable unit, and then increases the number of compensation current outputs to shift the initial logarithmic curve upward, thereby achieving the purpose of calibrating the intercept. In different embodiments, the positivity or negativity of the slope of the logarithmic curve is inconsistent, and the compensation current can be increased or decreased when the intercept of the initial logarithmic curve is greater than the intercept of the standard logarithmic curve according to the positivity or negativity of the slope. Similarly, the compensation current can be decreased or increased when the intercept of the initial logarithmic curve is less than the intercept of the standard logarithmic curve according to the positivity or negativity of the slope.

[0073] The operation unit 240 can be implemented by an adder, which sums the received current signals to obtain the output current signal. The summed current signal can have different positive and negative cases, i.e., the current direction output from the adder can determine the positive and negative of the summed current. The operation unit 240 can also be implemented by a subtractor, which subtracts one or more compensation currents I0 from the first current II. Of course, the compensation current can also have different positive and negative cases, i.e., the current direction can determine the positive and negative of the compensation current. For example, the compensation current I0 can be a positive current, and when the operation unit 240 is an adder, the number of compensation currents I0 is increased to increase the current value of the second current I2 compared to the first current II. In addition, the compensation current I0 can be a negative current, and when the operation unit 240 is an adder, the number of compensation currents I0 is increased to decrease the current value of the second current I2 compared to the first current II. In some embodiments, a first part of the compensation current I0 can have a different direction from a second part of the compensation current I0 to achieve a bidirectional compensation effect. For example, the first part of the compensation current I0 is a positive current, and the second part of the compensation current I0 is a positive current, so that the current value of the second current I2 can be compensated in both the large direction and the small direction. It can be understood that whether it is an adder or a subtractor, bidirectional compensation of the first current II can be achieved, i.e., bidirectional compensation of the intercept of the logarithmic curve of the logarithmic detector can be achieved.

[0074] It can be understood that in order to achieve bidirectional compensation of positive and negative currents, the output current direction of the current path can be variable.

[0075] In some embodiments, the operation unit 240 includes both an adder and a subtractor, and the adder and the subtractor can be connected in series. A first part of the compensation current I0 is input to the adder to increase the current value of the first part of the compensation current I0, so that the current value of the second current I2 is compensated in the large direction. A second part of the compensation current I0 is input to the subtractor to increase the current value of the second part of the compensation current I0, so that the current value of the second current I2 is compensated in the small direction, thereby achieving bidirectional compensation.

[0076] In some embodiments, the operation unit 240 includes an adder, a subtractor, and a selection unit. The selection unit is used to switch the adder or the subtractor to output the second current from the adder or the subtractor.

[0077] Here, the multiple current paths can be the same paths outputting the same direction compensation current. In actual application, the selection of the adder or the subtracter can be set according to the output current direction of the current path and the current direction to be compensated. Exemplarily, when the first current I0 needs to be positively compensated, the selection unit can select to use the adder, and at least part of the compensation current I0 is input to the adder; when the first current I0 needs to be negatively compensated, the selection unit can select to use the subtracter, and at least part of the compensation current I0 is input to the subtracter. In addition, the above-mentioned process deviation of the logarithmic detector can be tested and calibrated before leaving the factory, and there is no need to reserve an editable pin for the compensation operation of the above-mentioned circuit on the chip. Therefore, the above-mentioned editable unit can use a one-time programming device, such as a fuse unit or an anti-fuse unit, to reduce the external pins.

[0078] In some embodiments, as shown in FIG. 3, the logarithmic detector 200 further comprises:

[0079] The first transistor M0 is connected in series with the current source A1; wherein the first end of the first transistor M0 is connected to the power supply voltage VDD, and the second end of the first transistor M0 is connected to the current source A1;

[0080] The current path 230 comprises a first switch Ki and a second transistor Mi, wherein the first end of the first switch Ki is connected to the control end of the first transistor M0, the second end of the first switch Ki is connected to the control end of the second transistor Mi, and the control end of the first switch Ki receives an enable signal EN; the first end of the second transistor Mi is connected to the power supply voltage VDD, and the second end of the second transistor Mi is used to output the compensation current I0.

[0081] The current source A1 can output a reference current Iref, and when the first switch Ki on one current path is turned on, the control end of the first transistor M0 is connected to the control end of the first transistor Mi on the current path, so that the two form a current mirror. In this way, the compensation current I0 output by the current path 230 has a current size proportional to the reference current Iref, and the proportion is determined by the sizes of the second transistor Mi and the first transistor M0. In some embodiments, the compensation current I0 is the same as the reference current Iref. A plurality of same current paths can be pre-set in the circuit, and each current path can output a compensation current I0 of the same size when turned on. The compensation current I0 determines the accuracy of the logarithmic curve intercept calibration of the logarithmic detector. Therefore, if the required calibration accuracy is high, a smaller reference current can be set, and more current paths can be set; if the required calibration accuracy is low, a larger reference current can be set, and fewer current paths can be set.

[0082] Exemplarily, the first switch Ki can be implemented by an NMOS device, and the second transistor Mi and the first transistor M0 can be implemented by PMOS devices. Of course, the above-mentioned switches can also be implemented by other three-terminal devices, which will not be listed one by one here.

[0083] In some embodiments, FIG. 3 shows an implementation of the related circuit in the logarithmic detector when the editable unit is a fuse unit. As shown in FIG. 3, each fuse unit 221 includes:

[0084] A first unit S1 and a second unit S2, a first end of the first unit S1 is connected with a voltage receiving end Vi and a working voltage end, and a second end is connected with a first end of the second unit S2; a second end of the second unit S2 is grounded; wherein the voltage receiving end Vi is used to receive a control signal corresponding to the fuse unit 221, and a second end of the first unit S1 outputs an enable signal EN. The first unit S1 or the second unit S2 can be a fuse circuit or a fuse short circuit, wherein the fuse circuit means that the unit forms an open circuit when it is broken down, and the fuse short circuit means that the unit forms a short circuit when it is broken down.

[0085] The above-mentioned i can represent the i-th fuse unit 221 and the corresponding i-th current path 230, and Vi represents the voltage receiving end connected with the i-th fuse unit 221. Exemplarily, the logarithmic detector has n current paths, corresponding to n fuse units, so i is a positive integer greater than or equal to 1 and less than or equal to n. Wherein, the value of n is greater than or equal to 1, for example, 2, 3, 4, 5, 10 or more, and the number of n represents the maximum number of compensation currents I0 that can be output.

[0086] In some embodiments, as shown in FIG. 4, the first unit S1 is a fuse capacitor Ci, and the second unit S2 is a first resistor R1i. When the control signal received by the voltage receiving end Vi is valid, the fuse capacitor Ci is broken down by the corresponding control signal, forming a short circuit of the first unit S1, the voltage of the first switch Ki is high, the first switch Ki is turned on, and the current path 230 where the first switch Ki is located outputs the compensation current I0.

[0087] In some embodiments, as shown in FIG. 5, the first unit S1 is a second resistor R2i; and the second unit S2 is a fuse resistor R3i. When the control signal received by the voltage receiving end Vi is valid, the fuse resistor R3i is fused by the control signal, forming an open circuit of the second unit S2, the voltage of the first switch Ki is high, the first switch Ki is turned on, and the current path 230 where the first switch Ki is located outputs the compensation current I0.

[0088] Here, the fuse resistor R3i can be a resistor with a very small width, so it is easier to be burned out. The control signal can be a voltage much higher than the working voltage VDD, so it can break the fuse capacitor or burn out the fuse resistor instantly, realizing the one-time programming operation.

[0089] In some embodiments, as shown in FIG. 6, the logarithmic detector 200 further comprises:

[0090] The output unit 250 is connected to the operation unit 240 and receives the second current converted into an output voltage, and the output of the output unit 250 is a DC output;

[0091] The feedback unit 260 is connected to the operation unit 240 and connected to the output end of the output unit 250; the feedback unit 260 is used to provide a feedback current Ir to the operation unit 240 based on the output voltage Vout of the output unit 250;

[0092] The operation unit 240 specifically obtains the second current based on the first current I1, one or more compensation currents I0, and the feedback current Ir, and outputs the second current I2 to the output unit 250.

[0093] The feedback unit 260 can be realized by a voltage-to-current conversion circuit, which is used to convert the output DC voltage into a current and feedback to the operation unit 240, so that the logarithmic detector has a more stable output, and the feedback unit 260 realizes the locking of the DC output, which can calibrate the slope of the logarithmic curve. Therefore, the logarithmic detector 200 shown in FIG. 6 can not only calibrate the intercept of the logarithmic curve, but also calibrate the slope of the logarithmic curve.

[0094] As shown in FIG. 7, the present disclosure further provides a calibration method of a logarithmic detector, the method is applied to the logarithmic detector in any of the above embodiments; the method comprises:

[0095] S101, inputting a radio frequency signal to a logarithmic amplifier and detecting an output voltage of the logarithmic amplifier;

[0096] S102, obtaining an initial logarithmic curve of the logarithmic detector based on the output voltage and the input power of the radio frequency signal, at this time, the current path 230 does not output the compensation current I0;

[0097] S103, based on the initial logarithmic curve of the logarithmic detector and a preset standard logarithmic curve, the offset of the initial logarithmic curve relative to the standard logarithmic curve can be obtained, and the control signal is determined according to the offset, for example, the number of control signals is determined, so as to control the number of compensation currents;

[0098] S104, a control signal is sent to the editable unit, in some embodiments, the control signal can edit the corresponding editable unit 220, so that the editable unit 220 sends an enable signal EN to the corresponding current path 230, and the corresponding current path 230 outputs a compensation current I0, thereby adjusting the second current I2, calibrating the intercept of the logarithmic curve, so that the intercept of the calibrated logarithmic curve is the same or substantially the same as the intercept of the standard logarithmic curve.

[0099] The above-mentioned standard logarithmic curve can be an ideal input-output curve of a logarithmic detector, which can be obtained by operating the parameters of the logarithmic detector. For an actual logarithmic detector product, its actual logarithmic curve can be obtained by testing. Exemplarily, by measuring two input power points of the logarithmic detector within a specified range, the slope and intercept of the logarithmic curve can be obtained. By comparing the intercept of the actual initial logarithmic curve with the intercept of the standard logarithmic curve, the offset of the initial logarithmic curve relative to the standard logarithmic curve is obtained, and the difference between the two intercepts, i.e., the intercept to be compensated, is obtained. As shown in FIG. 8, the initial logarithmic curve is downwardly offset relative to the standard logarithmic curve, and therefore the initial logarithmic curve needs to be moved upward to be closer to the standard logarithmic curve. The dashed straight line in FIG. 8 is the slope of the logarithmic curve. Then the required compensation current can be determined according to the difference, and the required control signal can be calculated.

[0100] In this way, by applying the control signal to the editable unit of the above-mentioned logarithmic detector, the corresponding current path can output the required compensation current, and then the operation unit can compensate the first current output by the logarithmic amplifier, and then the output unit can perform current-voltage conversion to obtain an output result closer to the ideal logarithmic curve.

[0101] Exemplarily, for an uncalibrated product, as shown in FIG. 9, the logarithmic curve intercepts of logarithmic detectors of different wafer batches have a large dispersion (about 0.13V of dispersion of Vout scaled by pin=-30dBm, corresponding to a floating of input signal power ±3.25dB).

[0102] After the intercept calibration by the above-mentioned scheme in the embodiments of the present disclosure, as shown in FIG. 10, the dispersion is optimized by 70% (about 0.04V of dispersion of Vout scaled by pin=-30dBm, corresponding to a floating of input signal power ±1dB).

[0103] As shown in FIG. 11, the embodiments of the present disclosure provide a chip 300, which comprises at least one radio frequency channel 301; and a logarithmic detector 200 according to any of the above-mentioned embodiments, connected with the radio frequency channel 301, for detecting a radio frequency signal RF provided by the radio frequency channel 301. Generally, the chip 300 further comprises a radio frequency amplifier, a mixer, a filter, etc.

[0104] It should be understood that any reference to an "embodiment" or "one embodiment" or "an embodiment" of the application herein means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of steps in the above-described processes is not meant to be limiting, and that the sequence of steps should be determined in accordance with the function and the internal logic of the processes, and should not constitute any limitation on the implementation of the embodiments of the application. The sequence of the above-described embodiments of the application is only for the purpose of description, and does not represent the advantages or disadvantages of the embodiments.

[0105] It should be noted that, as used in this document, the terms "includes," "including," "has," "having," "contains," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements, but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0106] The above merely describes the embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A logarithmic detector with calibrated intercept, characterized in that: include: a logarithmic amplifier, receiving a radio frequency signal, performing logarithmic conversion on the radio frequency signal, and outputting a first current; A plurality of editable units, each of which receives a plurality of control signals and outputs a plurality of enable signals, wherein the control signals are used to control the logic states of the editable units, and the editable units output the enable signals according to the logic states; a plurality of current paths connected to the editable unit, wherein the current paths receive the enable signal, the enable signal is used to control whether the current paths are turned on, and the turned-on current paths are used to output compensation currents; An operation unit is connected to the logarithmic amplifier and the multiple current paths, and receives the first current and the compensation current, and outputs a second current.

2. The logarithmic detector according to claim 1, wherein Also includes: A first transistor and a current source connected in series; The current path includes: a first switch and a second transistor, wherein the first end of the first switch is connected to the control end of the first transistor, the second end of the first switch is connected to the control end of the second transistor, and the control end of the first switch receives the enable signal; the first end of the second transistor is connected to the power supply voltage, and the second end of the second transistor outputs the compensation current.

3. The logarithmic detector according to claim 1, wherein The editable unit is a fuse unit, the control signal is used to control the blowing state of the fuse unit, and the fuse unit outputs the enable signal according to the blowing state.

4. The logarithmic detector according to claim 3, wherein The fuse unit comprises: The fuse unit includes: a first unit and a second unit, wherein the first end of the first unit is connected to the voltage receiving end and the working voltage end, and the second end is connected to the second unit; the second end of the second unit is grounded; wherein the voltage receiving end is used to receive the control signal, and the second end of the first unit outputs the enable signal, wherein the first unit or the second unit can be fused to open or fused to short.

5. The logarithmic detector according to claim 4, characterized in that The first unit is a fuse capacitor, which forms a short circuit when broken down by the control signal; the second unit is a first resistor.

6. The logarithmic detector according to claim 4, wherein The first unit is a second resistor; the second unit is a fuse resistor. When the fuse resistor is blown by the control signal, the second unit is disconnected.

7. The logarithmic detector according to claim 1, wherein The editable unit is a field programmable gate array FPGA or a complex programmable logic device CPLD.

8. The logarithmic detector according to any one of claims 1 to 7, characterized in that: The compensation current includes a first portion of compensation current and a second portion of compensation current, and the current directions of the first portion of compensation current and the second portion of compensation current are opposite.

9. The logarithmic detector according to claim 8, characterized in that The operation unit includes an adder and a subtractor, the first part of the compensation current is sent to the adder, and the second part of the compensation current is sent to the subtractor; The adder and the subtractor are connected in series; or, the operation unit further includes a selection unit, and the selection unit is used to switch the adder or the subtractor.

10. The logarithmic detector according to any one of claims 1 to 7, characterized in that: Also includes: an output unit, connected to the computing unit, receiving the second current and converting it into an output voltage; a feedback unit connected to the operation unit and to the output end of the output unit; the feedback unit is configured to provide a feedback current to the operation unit based on the output voltage; The operation unit specifically obtains the second current according to the first current, one or more compensation currents and the feedback current, and outputs the second current to the output unit.

11. A method for calibrating a logarithmic detector, characterized in that: The method is applied to the logarithmic detector according to any one of claims 1 to 10, and the method comprises: inputting the radio frequency signal into the logarithmic amplifier and detecting an output voltage of the logarithmic amplifier; obtaining an initial logarithmic curve of the logarithmic detector based on the output voltage and the input power of the radio frequency signal; Based on an initial logarithmic curve of the logarithmic detector and a preset standard logarithmic curve, obtaining an offset of the initial logarithmic curve relative to the standard logarithmic curve, and determining the control signal; The control signal is sent to the editable unit.

12. A chip, characterized in that: include: at least one radio frequency channel; The logarithmic detector according to any one of claims 1 to 10, connected to the radio frequency channel, and configured to detect the radio frequency signal provided by the radio frequency channel.

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