Driver circuit and chip

Abstract

The present disclosure provides a driver circuit and a chip. The driver circuit comprises a gate driving circuit, a power transistor, a drain-source voltage detection circuit, an adaptive timing and control circuit and a current limiting circuit. When an on control signal is at an effective level, the gate driving circuit provides a driving current for a control electrode of the power transistor to reach a target driving voltage. The drain-source voltage detection circuit detects a voltage difference between a first electrode of the power transistor and a second electrode of the power transistor. The adaptive timing and control circuit uses the voltage difference to carry out segmented timing and enables each time period to correspond to one current limiting value among a plurality of current limiting values. Within each time period and on the basis of the current limiting value corresponding to the time period, the current limiting circuit limits the maximum current flowing through the power transistor. Therefore, the power transistor can be kept working in a safe working area, and the maximum power transfer capability is improved.

Description

Driver circuit and chip

[0001] Cross Reference to Related Applications

[0002] The present disclosure claims priority to the Chinese patent application No. 202410424478.0, filed on April 9, 2024, and entitled “Driver circuit and chip”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of integrated circuits, and in particular, to a driver circuit and chip. BACKGROUND

[0004] A driver circuit can include a high-side driver and a low-side driver. The high-side driver is mainly used to control the switch or load located on the positive side of the power supply, and the low-side driver is mainly used to control the switch or load located on the ground side. The working principle of the high-side driver and the low-side driver is mainly based on power electronic switching technology, which realizes the control of the load through internal metal-oxide semiconductor field effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT) switching devices. When such a driver circuit receives a turn-on control signal, it controls the on-off of the switching device and limits the output current according to the high and low levels of the turn-on control signal, thereby realizing the driving and control of the load.

[0005] When the load of such a driver circuit is a capacitive load, the voltage difference across the switching device and the current flowing through the switching device will change with different turn-on times. There is usually a safe operating area defined for the voltage difference and the current for different turn-on times. During the charging of the capacitive load, the switching device may work in a non-safe operating area, which needs to be avoided. SUMMARY

[0006] The embodiments described in the present disclosure provide a driver circuit and chip.

[0007] According to a first aspect of the present disclosure, a driver circuit is provided, which includes a gate drive circuit, a power tube, a drain-source voltage detection circuit, an adaptive timing and control circuit, and a current limiting circuit. The gate drive circuit is configured to provide a drive current to a control electrode of the power tube to reach a target drive voltage during a period when an on-off control signal is at an active level. A first electrode of the power tube is coupled to a first voltage terminal, and a second electrode of the power tube is coupled to an output terminal. The drain-source voltage detection circuit is configured to detect a voltage difference between the first electrode and the second electrode of the power tube. The adaptive timing and control circuit is configured to segment timing based on the voltage difference and make each time segment correspond to one of a plurality of preset current limiting values. The current limiting circuit is configured to limit a maximum current flowing through the power tube according to the current limiting value corresponding to each time segment.

[0008] In some embodiments of the present disclosure, the current limiting values are positively correlated with the voltage difference.

[0009] In some embodiments of the present disclosure, the adaptive timing and control circuit includes a logic control circuit configured to take a maximum value of the plurality of current limiting values as an initial value of the current limiting value provided to the current limiting circuit, and update the current limiting value provided to the current limiting circuit according to a voltage inversion at an input terminal of the logic control circuit, wherein the current limiting value provided to the current limiting circuit is updated in the following manner: the current limiting values other than the maximum value in the plurality of current limiting values are sequentially taken as the current limiting value provided to the current limiting circuit in descending order.

[0010] In some embodiments of the present disclosure, the logic control circuit is further configured to update the current limiting value provided to the current limiting circuit when the voltage at the input terminal of the logic control circuit inverts to an active level.

[0011] In some embodiments of the present disclosure, the logic control circuit is further configured to calculate a number of times that the voltage at the input terminal of the logic control circuit inverts to an active level, and update the current limiting value provided to the current limiting circuit and reset the number of times when the number of times reaches a target value.

[0012] In some embodiments of the present disclosure, a capacitor and a voltage-controlled current source are provided in the adaptive timing and control circuit, and a first terminal of the capacitor is a second node. The voltage-controlled current source is configured to generate a charging current according to the voltage difference and provide the charging current to the first terminal of the capacitor, and the charging current is positively correlated with the voltage difference. When a current limiting enable signal inverts from an inactive level to an active level, the capacitor starts charging based on the charging current, and the voltage at the second node starts rising. When the voltage at the second node rises to a reference voltage, the voltage at the input terminal of the logic control circuit inverts from the inactive level to the active level, and the capacitor stops charging, so that the energy generated by the power tube is independent of the voltage difference.

[0013] In some embodiments of the present disclosure, the adaptive timing and control circuit further comprises a voltage comparator, a NAND gate and a voltage-controlled switch. The second end of the capacitor is coupled to the second voltage terminal, the first input terminal of the voltage comparator is coupled to the reference voltage terminal, the second input terminal of the voltage comparator is coupled to the first end of the capacitor, and the output terminal of the voltage comparator is coupled to the first input terminal of the NAND gate and the input terminal of the logic control circuit via the first node. The second input terminal of the NAND gate is provided with a current limit enable signal, the output terminal of the NAND gate is coupled to the controlled terminal of the voltage-controlled switch, the first terminal of the voltage-controlled switch is coupled to the second voltage terminal, and the second terminal of the voltage-controlled switch is coupled to the first end of the capacitor.

[0014] In some embodiments of the present disclosure, the adaptive timing and control circuit further comprises an inverter coupled between the first node and the output terminal of the voltage comparator.

[0015] In some embodiments of the present disclosure, each of the plurality of current limit values is associated with a target value. The target values associated with the plurality of current limit values are the same or different.

[0016] In some embodiments of the present disclosure, the adaptive timing and control circuit further comprises a unidirectional delay circuit. The unidirectional delay circuit is coupled between the input terminal of the logic control circuit and the first input terminal of the NAND gate. The unidirectional delay circuit is configured to output an invalid level when the time for the voltage at the input terminal of the logic control circuit to flip to the invalid level reaches a target time period.

[0017] In some embodiments of the present disclosure, the first input terminal of the voltage comparator is an inverting input terminal, and the second input terminal of the voltage comparator is a non-inverting input terminal.

[0018] In some embodiments of the present disclosure, the average of the current limit values corresponding to the time periods is higher than the lower limit of the current corresponding to the length of the on time, and the length of the on time is the length of time during which the on control signal is at the valid level.

[0019] In some embodiments of the present disclosure, the current limit circuit limits the maximum current flowing through the power tube by detecting the current flowing through the power tube, and in the case that the current flowing through the power tube exceeds the current limit value corresponding to the current time period, controlling the gate drive circuit to adjust the drive current so that the current flowing through the power tube is limited to the current limit value.

[0020] In some embodiments of the present disclosure, the driver circuit is coupled to a capacitive load.

[0021] According to a second aspect of the present disclosure, a chip is provided. The chip comprises the driver circuit according to the first aspect of the present disclosure.

[0022] According to a third aspect of the present disclosure, an electronic device is provided. The electronic device comprises the chip according to the third aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present disclosure, rather than limitations of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] FIG1 is an exemplary circuit diagram of a high-side driver;

[0025] FIG2 is a schematic diagram of the safe operating area of ​​the high-side driver shown in FIG1 under different on-time scenarios;

[0026] FIG3 is a schematic block diagram of a driver circuit provided in an embodiment of the present disclosure;

[0027] FIG4 is an exemplary circuit diagram of a driver circuit provided by an embodiment of the present disclosure;

[0028] FIG5 is an exemplary circuit diagram of another driver circuit provided by an embodiment of the present disclosure;

[0029] FIG6 is a diagram showing the relationship between multiple current limit values ​​and safe operating areas of a driver circuit provided by an embodiment of the present disclosure;

[0030] FIG. 7 is a waveform diagram of some signals of a driver circuit provided by an embodiment of the present disclosure.

[0031] In the drawings, reference numerals having the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts or components are "connected" or "coupled" together shall mean that the parts or components are joined or operate together either directly or through one or more intermediate parts or components.

[0034] In all embodiments of the present disclosure, the controlled middle terminal of a MOS transistor is referred to as a control terminal, and the remaining two terminals of the MOS transistor are referred to as a first terminal and a second terminal, respectively. In addition, for the sake of uniform expression, in the context, the base of a bipolar junction transistor (BJT) is referred to as a control terminal, the emitter of the BJT is referred to as a first terminal, and the collector of the BJT is referred to as a second terminal. In addition, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0035] As described above, a driver circuit can include a high-side driver and a low-side driver. The high-side driver and the low-side driver have similar structures, and hereinafter and in the accompanying drawings, the high-side driver is taken as an example for introduction. Those skilled in the art should understand that the technical solutions proposed by the present disclosure can be applied to both the high-side driver and the low-side driver.

[0036] FIG. 1 shows an exemplary circuit diagram of a high-side driver, as shown in FIG. 1, the high-side driver 100 includes a gate drive circuit GD and a power tube M0, the power supply voltage VCP of the gate drive circuit GD is higher than the voltage VCC at the first terminal of the power tube M0. During the on control signal ON is at a high level (hereinafter referred to as the on time length Pw), the gate drive circuit GD provides a drive current to the control terminal of the power tube M0 to reach a target drive voltage. The second terminal of the power tube M0 is coupled to the output terminal OUT of the high-side driver 100, and the output terminal OUT of the high-side driver 100 is coupled to the load capacitor Cload, and the current flowing through the power tube M0 is denoted as Id.

[0037] FIG. 2 shows a diagram of the safe operating area of the high-side driver 100 of FIG. 1 under different on-time scenarios, in which the horizontal axis represents the voltage difference VDS between the first and second poles of the power transistor M0, and the vertical axis represents the current Id flowing through the power transistor M0. It should be noted that the values of the horizontal and vertical axes are marked in logarithmic scale. FIG. 2 shows the ranges of the safe operating area of VDS and Id under different on-time lengths Pw, i.e., 10 μs, 50 μs, 100 μs, 1 ms, 10 ms, 100 ms, and constant on-time. The safe operating area is within the range defined by the solid line and the horizontal and vertical axes. When the power transistor M0 operates in the safe operating area, the total energy generated by the power transistor M0 during operation can be within a safe range.

[0038] Under different on-time lengths, the maximum current of Id can be limited to ensure that the high-side driver 100 operates in the safe operating area regardless of the value of VDS. However, the maximum power transfer capability of the high-side driver 100 can be limited by the maximum current of Id, resulting in waste of energy resources.

[0039] Therefore, embodiments of the present disclosure propose a driver circuit that operates in a safe operating area and improves the maximum power transfer capability. FIG. 3 is a schematic block diagram of a driver circuit according to an embodiment of the present disclosure. As shown in FIG. 3, the driver circuit 300 includes a gate drive circuit GD, a power transistor M0, a drain-source voltage detection circuit 320, an adaptive timing and control circuit 330, and a current limiting circuit 310.

[0040] In the example of FIG. 3, the driver circuit 300 is a high-side driver, and the power transistor M0 is an N-type transistor. The control pole of the power transistor M0 is coupled to the output of the gate drive circuit GD, and the first pole (drain) of the power transistor M0 is coupled to a first voltage terminal. A high voltage signal is input from the first voltage terminal, and the power supply voltage VCP of the gate drive circuit GD is higher than the voltage VCC at the first pole of the power transistor M0.

[0041] The gate drive circuit GD is provided with an on control signal ON, and the length of time during which the on control signal ON is at a high level is referred to as the on-time length Pw in the context. The gate drive circuit GD is further coupled to the current limiting circuit 310 and the power transistor M0. The gate drive circuit GD is configured to provide a drive current to the control pole of the power transistor M0 to reach a target drive voltage during the period when the on control signal ON is at a valid level, where the target drive voltage can be determined according to specific applications.

[0042] The drain-source voltage detection circuit 320 is coupled to the first voltage terminal, the output terminal OUT of the driver circuit 300, and the adaptive timing and control circuit 330. The drain-source voltage detection circuit 320 is configured to detect a voltage difference VDS between the first electrode and the second electrode of the power tube M0. The drain-source voltage detection circuit 320 can obtain the voltage difference VDS by subtracting the voltage at the second electrode of the power tube M0 (e.g., the voltage at the output terminal OUT of the driver circuit 300) from the voltage at the first electrode of the power tube M0 (e.g., the first voltage VCC). The drain-source voltage detection circuit 320 is further configured to provide the voltage difference VDS to the adaptive timing and control circuit 330.

[0043] The adaptive timing and control circuit 330 is coupled to the drain-source voltage detection circuit 320 to receive the voltage difference VDS between the first electrode and the second electrode of the power tube M0 from the drain-source voltage detection circuit 320. The adaptive timing and control circuit 330 is configured to segment timing using the voltage difference VDS and to cause each time segment to correspond to one of a plurality of preset current limit values ILM1, …, ILMn. In some embodiments of the present disclosure, the current limit values are positively correlated with the voltage difference VDS, i.e., the smaller the voltage difference VDS, the smaller the current limit value. The plurality of current limit values ILM1, …, ILMn can be preset according to the safe operating area shown in FIG. 2.

[0044] The current limit circuit 310 is coupled to the adaptive timing and control circuit 330, the gate drive circuit GD, and the power tube M0. The current limit circuit 310 is configured to limit the maximum current flowing through the power tube M0 according to the current limit value corresponding to each time segment in each time segment.

[0045] The relationship between the current limit values ILM1, ILM2, ILM3 and ILM4 and the safe operating area is described below in connection with FIG. 6. As shown in FIG. 6, the voltage difference VDS between the first electrode and the second electrode of the power transistor M0 gradually decreases over time, assuming that the value of Pw is 100 μs in practical applications. At the beginning, the duration of the large current flowing through the power transistor M0 is still short, and the time during which the on control signal ON is at the high level is less than 10 μs. At this time, the current limit value can be set to the lower limit value ILM1 corresponding to Pw = 10 μs (which is higher than the lower limit value ILM3 corresponding to Pw = 100 μs), and the duration of ILM1 can be controlled by means of VDS (corresponding to the range of VDS between Vf1 and Vf2), so that the energy generated by the power transistor M0 does not reach the maximum energy threshold. Then, the current limit value can be decreased to ILM2, and the duration of ILM2 can be controlled by means of VDS (corresponding to the range of VDS between Vf2 and Vf3), so that the energy generated by the power transistor M0 still does not reach the maximum energy threshold. In this way, the current limit value gradually decreases, and finally the current limit value is equal to ILM4. ILM4 < ILM3 < ILM2 < ILM1. In this way, the energy generated by the power transistor M0 does not reach the maximum energy threshold in each time period, and the power transistor M0 operates in the safe operating area, and the average current limit value can be higher than the lower limit value corresponding to Pw = 100 μs, so that the maximum power transfer capability of the driver circuit 300 can be improved.

[0046] When the load of the driver circuit 300 is a capacitive load, the voltage difference VDS between the first electrode and the second electrode of the power transistor M0 and the current Id flowing through the power transistor M0 change with the on time of the power transistor M0. The driver circuit 300 according to the embodiments of the present disclosure can keep the power transistor M0 operating in the safe operating area by segmenting the timing by means of the voltage difference VDS and limiting the maximum current flowing through the power transistor M0 according to the current limit value corresponding to each time period in each time period, and therefore the driver circuit 300 according to the embodiments of the present disclosure is suitable for coupling a capacitive load.

[0047] FIG. 4 is an exemplary circuit diagram of a driver circuit according to an embodiment of the present disclosure. In the example of FIG. 4, the adaptive timing and control circuit 330 includes a voltage-controlled current source I1, a capacitor Cr, a voltage comparator COMP, a NAND gate NAND, an inverter NG, a voltage-controlled switch S1, and a logic control circuit 350.

[0048] The voltage-controlled current source I1 is coupled to the drain-source voltage detection circuit 320 and receives the voltage difference VDS between the first electrode and the second electrode of the power tube M0 from the drain-source voltage detection circuit 320. The voltage-controlled current source I1 is configured to generate a charging current I1 according to the voltage difference VDS and provide the charging current I1 to the first end (the second node N2) of the capacitor Cr, the charging current I1 being proportional to the voltage difference VDS, the smaller the voltage difference VDS, the smaller the charging current I1, in other words, the charging current I1 decreases as the voltage difference VDS decreases.

[0049] The second end of the capacitor Cr is coupled to the second voltage terminal, the first input terminal of the voltage comparator COMP is coupled to the reference voltage terminal, the second input terminal of the voltage comparator COMP is coupled to the first end of the capacitor Cr, and the output terminal of the voltage comparator COMP is coupled to the input terminal of the inverter NG. In the example of FIG. 4, the first input terminal of the voltage comparator COMP is the inverting input terminal, and the second input terminal of the voltage comparator COMP is the non-inverting input terminal.

[0050] The output terminal of the inverter NG is directly coupled to the first input terminal of the NAND gate NAND and the input terminal of the logic control circuit 350 via the first node N1, the second input terminal of the NAND gate NAND is provided with the current-limiting enable signal ilmhit. The current-limiting enable signal ilmhit is used to indicate whether to perform the operation on the power tube M0, when the current-limiting enable signal ilmhit is at the effective level, the operation on the power tube M0 is allowed to be performed, and when the current-limiting enable signal ilmhit is at the ineffective level, the operation on the power tube M0 is not allowed to be performed. The output terminal of the NAND gate NAND is coupled to the controlled terminal of the voltage-controlled switch S1.

[0051] The first end of the voltage-controlled switch S1 is coupled to the second voltage terminal, and the second end of the voltage-controlled switch S1 is coupled to the first end (the second node N2) of the capacitor Cr.

[0052] The logic control circuit 350 is configured to take the maximum value of the plurality of current-limiting values as the initial value of the current-limiting value provided to the current-limiting circuit 310, and update the current-limiting value provided to the current-limiting circuit 310 when the voltage of the first node N1 flips to the effective level. Among them, the current-limiting value provided to the current-limiting circuit 310 is updated in the following manner: in order from large to small, the current-limiting values other than the maximum value in the plurality of current-limiting values are sequentially taken as the current-limiting value provided to the current-limiting circuit 310.

[0053] In some embodiments of the present disclosure, the logic control circuit 350 can be provided with the current-limiting enable signal ilmhit, and the logic control circuit 350 controls the current-limiting circuit 310 to work during the period when the current-limiting enable signal ilmhit is at the effective level, and controls the current-limiting circuit 310 not to work during the period when the current-limiting enable signal ilmhit is at the ineffective level.

[0054] In the example of FIG. 4, a high voltage signal is input from the first voltage terminal, the second voltage terminal is grounded, and the power transistor M0 is an NMOS transistor. The driver circuit 300 can further include a charge pump 340 that raises the first voltage VCC to VCP as a power supply voltage for the gate drive circuit GD. Those skilled in the art should understand that variations of the circuit shown in FIG. 4 based on the above inventive concept should also fall within the protection scope of the present disclosure. In the variations, the above-mentioned transistors and voltage terminals can also have different settings from the example shown in FIG. 4.

[0055] During the period when the current limit enable signal ilmhit is at an inactive level (low level), the NAND output is at an active level (high level), and thus the voltage-controlled switch S1 remains closed, and the voltage at the second node N2 is equal to the second voltage V2, and the first node N1 is at an inactive level (high level).

[0056] When the current limit enable signal ilmhit flips to an active level (high level), since the first node N1 is at an inactive level (high level), the voltage-controlled switch S1 is opened, and the charging current I1 charges the capacitor Cr. The logic control circuit 350 takes the maximum value among the plurality of current limit values as the initial value of the current limit value provided to the current limit circuit 310.

[0057] When the voltage Vca at the second node rises to the reference voltage Vr, the voltage at the first node N1 flips to an active level (low level), and the NAND output is at an active level (high level), and thus the voltage-controlled switch S1 is closed, causing the capacitor Cr to discharge. Here, the internal delay time of the inverter NG and the NAND can be utilized to provide the discharge time of the capacitor Cr. In this way, the voltage Vca at the second node will return to the second voltage V2 again.

[0058] Whenever the voltage at the first node N1 flips to an active level, the logic control circuit 350 updates the current limit value provided to the current limit circuit 310, and the plurality of current limit values ILM1, …, ILMn gradually decrease. Thus, the initial current limit value is ILM1, when the voltage at the first node N1 flips to an active level for the first time, the current limit value is updated to ILM2, and so on, and finally the current limit value stabilizes at ILMn. The specific value of n can be set according to actual application, and in the example of FIG. 6, n = 4. In this way, the segmented current limiting shown in FIG. 6 can be achieved.

[0059] The energy E generated by the power transistor M0 can be calculated as: E = Id x VDS x T (1)

[0060] where Id represents the current flowing through the power transistor M0, VDS represents the voltage difference between the first and second poles of the power transistor M0, and T represents the time of energy generation.

[0061] Assuming that the charging current I1 = K x VDS, in the case of charging the capacitor Cr using I1, I1 can be expressed as: I1 = C r x V r / Tm (2)

[0062] where Tm represents the time required for the capacitor Cr to be fully charged, C r represents the capacitance value of the capacitor Cr, V r represents the voltage value of the reference voltage Vr, and K is the voltage current conversion coefficient. According to equation (2), Tm = (C r x V r ) / (K x VDS) can be obtained.

[0063] Therefore, equation (2) is brought into equation (1) to obtain E = Id x VDS x T = ILM x VDS x Tm = ILM x VDS x (C r x V r ) / (K x VDS) = ILM x C r x V r / K. In this way, in fact, the energy generated by the power tube M0 in each time period is not related to the value of VDS, and can be set by setting ILM, C r , V r and K. Therefore, the energy generated by the power tube M0 is pre-controllable.

[0064] In practical applications, the capacitance value of the capacitor Cr can be large, which can occupy a large chip area. In some embodiments of the present disclosure, in order to reduce the size of the capacitor Cr, the timing can be performed by cumulative counting. In this case, the logic control circuit 350 can be configured to take the maximum value of the plurality of current limiting values as the initial value of the current limiting value provided to the current limiting circuit 310, calculate the number of times the voltage of the first node N1 flips to the effective level, and update the current limiting value provided to the current limiting circuit 310 and clear the number of times when the number of times reaches the target value. Wherein the current limiting value provided to the current limiting circuit 310 is updated in the following manner: in the order from large to small, the current limiting values other than the maximum value in the plurality of current limiting values are sequentially taken as the current limiting value provided to the current limiting circuit 310.

[0065] In some embodiments of the present disclosure, each of the plurality of current limiting values is associated with a target value, and the target values associated with the plurality of current limiting values are the same or different. Referring to FIG. 7, each time Vca rises to Vr, Vca is cleared (as shown by the solid line in the uppermost coordinate system in FIG. 7), and when the number of times Vca rises to Vr reaches a target value (for example, 5 times) from the time origin, a time length Tm1 is counted, during which Tm1, VDS gradually decreases (as shown by the solid line in the middle coordinate system in FIG. 7), and the current limiting value is ILM1 (as shown by the solid line in the lowermost coordinate system in FIG. 7). Starting from the end of Tm1 (at time t1), when the number of times Vca rises to Vr reaches a target value (for example, 4 times), a time length Tm2 is counted, during which Tm2, the slope of the decrease of VDS decreases, and the current limiting value is ILM2. Starting from the end of Tm2 (at time t2), when the number of times Vca rises to Vr reaches a target value (for example, 5 times) (at time t3), a time length Tm3 is counted, during which Tm3, the slope of the decrease of VDS decreases again, and the current limiting value is ILM3. After time t3, the current limiting value is maintained as ILM4. Through the cumulative counting manner, the size of the capacitor Cr can be significantly reduced.

[0066] In some embodiments of the present disclosure, the current limiting circuit 310 limits the maximum current flowing through the power tube M0 by: detecting the current Id flowing through the power tube M0, and in the case that the current Id flowing through the power tube M0 exceeds the current limiting value corresponding to the current time period, controlling the gate drive circuit GD to adjust the drive current so that the current Id flowing through the power tube M0 is limited to the current limiting value.

[0067] In an alternative example of FIG. 4, the first input terminal of the voltage comparator COMP can be the non-inverting input terminal, the second input terminal of the voltage comparator COMP can be the inverting input terminal, the inverter NG can be removed, and the output terminal of the voltage comparator COMP can be directly coupled to the first input terminal of the NAND gate NAND and the input terminal of the logic control circuit 350 via the first node N1.

[0068] In another alternative example of FIG. 4, referring to FIG. 5, the adaptive timing and control circuit 330 can further include a one-way delay circuit 360, wherein the one-way delay circuit 360 is coupled between the first node N1 and the first input terminal of the NAND gate NAND. The one-way delay circuit 360 is configured to output an invalid level when the time for the voltage of the first node N1 to flip to the invalid level reaches a target time period. In this way, the discharging time of the capacitor Cr can be more accurately controlled, ensuring that the capacitor Cr can be fully discharged.

[0069] In yet another alternative example of FIG. 4, the driver circuit 300 can be a low-side driver. FIG. 5 shows an example in which the driver circuit 300 is a low-side driver, in which the first pole (source) of the power tube M0 is coupled to the first voltage terminal, and the second pole (drain) of the power tube M0 is coupled to the output terminal OUT. A low voltage signal is input from the first voltage terminal, and the power supply voltage VCP of the gate drive circuit GD is equal to the power supply voltage VCP of the load.

[0070] Referring to FIGS. 6 and 7, when VDS is between Vf1 and Vf2 (i.e., between time 0 and time t1), the maximum energy of the power tube M0 can be calculated as follows:

[0071] When VDS is between Vf2 and Vf3 (i.e., between time t1 and time t2), the maximum energy of the power tube M0 can be calculated as follows:

[0072] When VDS is between Vf3 and Vf4 (i.e., between time t2 and time t3), the maximum energy of the power tube M0 can be calculated as follows:

[0073] When VDS is between Vf4 and 0V (i.e., between time t3 and time t4), the maximum energy of the power tube M0 can be calculated as follows:

[0074] It should be noted that in FIG. 6, the values of the horizontal and vertical axes are marked in logarithmic scale. Therefore, in practice, the maximum power transfer capability of the power tube M0 is better exploited.

[0075] In addition, referring to FIG. 7, the dashed line Org represents the falling curve of VDS when the high-side driver 100 shown in FIG. 1 is used. It can be seen that when the driver circuit 300 of the embodiment of the present disclosure is used, the time required for VDS to fall to 0V is shorter, and thus the capacitor-type load can be better served.

[0076] The embodiment of the present disclosure also provides a chip. The chip includes the driver circuit according to the embodiment of the present disclosure. The chip is, for example, a driving chip that needs to accurately control or protect a load.

[0077] The embodiment of the present disclosure also provides an electronic device. The electronic device includes the chip according to the embodiment of the present disclosure. The electronic device is, for example, an industrial control device, a motor driving device, etc.

[0078] In summary, the driver circuit according to the embodiments of the present disclosure utilizes the voltage difference between the two poles of the power tube to segment timing, and limits the maximum current flowing through the power tube according to different current limiting values in each time period, so that the power tube can be kept working in the safe working area and the maximum power transfer capability is improved. Further, the energy generated by the power tube can also be pre-controlled regardless of the voltage difference between the two poles of the power tube, so that the energy is pre-controllable in actual application, thereby being suitable for actual application scenarios.

[0079] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular form "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Accordingly, the use of "a" or "an" herein and in the following claims is intended to be interpreted to include the plural, unless the context clearly indicates otherwise. Similarly, the words "comprise," "comprises," and "comprising," and the like, are to be construed in an inclusive sense as opposed to an exclusive sense, so that any "comprising" language is to be construed as "comprising, but also including." Also, the use of "or" is to be construed as inclusive and exclusive, unless the context clearly indicates otherwise. Where the term "example" is used in the following description and not followed by the term "of the invention," the term "example" is used to introduce an example of a non-claimed aspect of the disclosure, and is not to be construed as limiting the scope of the invention.

[0080] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that the various aspects of the present disclosure can be practiced alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended to be for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0081] The foregoing detailed description of several embodiments of the present disclosure has been presented for purposes of illustration and description. It is apparent to those skilled in the art, however, that various modifications and changes can be made without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A driver circuit comprising: Gate drive circuit, power tube, drain-source voltage detection circuit, adaptive timing and control circuit, and current limiting circuit, The gate drive circuit is configured to: provide a drive current to the control electrode of the power tube to achieve a target drive voltage during a period when the conduction control signal is at an effective level; The first electrode of the power tube is coupled to the first voltage terminal, and the second electrode of the power tube is coupled to the output terminal; The drain-source voltage detection circuit is configured to: detect a voltage difference between a first electrode and a second electrode of the power tube; The adaptive timing and control circuit is configured to: utilize the voltage difference to perform segmented timing and make each time period correspond to one of a plurality of preset current limit values; The current limiting circuit is configured to limit the maximum current flowing through the power tube in each time period according to the current limiting value corresponding to the time period.

2. The driver circuit according to claim 1, wherein The current limit value is positively correlated with the voltage difference.

3. The driver circuit according to claim 1, wherein The adaptive timing and control circuit includes a logic control circuit, which is configured to: use the maximum value of the multiple current limit values ​​as the initial value of the current limit value provided to the current limit circuit, and update the current limit value provided to the current limit circuit according to the voltage reversal of the input terminal of the logic control circuit, wherein the current limit value provided to the current limit circuit is updated in the following manner: the other current limit values ​​of the multiple current limit values ​​except the maximum value are sequentially used as the current limit value provided to the current limit circuit in descending order.

4. The driver circuit according to claim 3, wherein: The logic control circuit is further configured to update the current limiting value provided to the current limiting circuit when the voltage at the input terminal of the logic control circuit flips to the valid level.

5. The driver circuit according to claim 3, wherein The logic control circuit is further configured to: count the number of times the voltage at the input terminal of the logic control circuit flips to the valid level, and when the number reaches a target value, update the current limiting value provided to the current limiting circuit and clear the number.

6. The driver circuit according to claim 3, wherein The adaptive timing and control circuit is provided with a capacitor and a voltage-controlled current source, wherein the first end of the capacitor is the second node; The voltage-controlled current source is configured to: generate a charging current according to the voltage difference and provide the charging current to the first end of the capacitor, wherein the charging current is proportional to the voltage difference; When the current limiting enable signal flips from the invalid level to the valid level, the capacitor starts to charge based on the charging current, and the voltage of the second node starts to increase. When the voltage of the second node increases to the reference voltage, the voltage of the input terminal of the logic control circuit flips from the invalid level to the valid level, and the capacitor stops charging, so that the energy generated by the power tube is independent of the voltage difference.

7. The driver circuit according to claim 6, wherein: The adaptive timing and control circuit further includes: a voltage comparator, a NAND gate and a voltage-controlled switch, The second terminal of the capacitor is coupled to the second voltage terminal, the first input terminal of the voltage comparator is coupled to the reference voltage terminal, the second input terminal of the voltage comparator is coupled to the first terminal of the capacitor, and the output terminal of the voltage comparator is coupled to the first input terminal of the NAND gate and the input terminal of the logic control circuit via a first node; The second input terminal of the NAND gate is provided with the current limiting enable signal, the output terminal of the NAND gate is coupled to the controlled terminal of the voltage-controlled switch, the first terminal of the voltage-controlled switch is coupled to the second voltage terminal, and the second terminal of the voltage-controlled switch is coupled to the first terminal of the capacitor.

8. The driver circuit according to claim 7, wherein: The adaptive timing and control circuit further includes an inverter coupled between the first node and an output terminal of the voltage comparator.

9. The driver circuit according to claim 5, wherein: Each current limit value among the multiple current limit values ​​is associated with a target value, and the target values ​​associated with the multiple current limit values ​​are the same or different.

10. The driver circuit according to claim 7 or 8, wherein: The adaptive timing and control circuit further comprises: a one-way delay circuit, Wherein, the unidirectional delay circuit is coupled between the input terminal of the logic control circuit and the first input terminal of the NAND gate, and is configured to: output the invalid level when the time when the voltage at the input terminal of the logic control circuit flips to the invalid level reaches the target time period.

11. The driver circuit according to claim 7 or 8, wherein: The first input terminal of the voltage comparator is an inverting input terminal, and the second input terminal of the voltage comparator is a non-inverting input terminal.

12. The driver circuit according to any one of claims 1 to 9, wherein: The average value of the current limit values ​​corresponding to each time period is higher than the lower current limit value corresponding to the on-time length, where the on-time length is the length of time the on-control signal is at the valid level.

13. The driver circuit according to any one of claims 1 to 9, wherein: The current limiting circuit limits the maximum current flowing through the power tube by the following operations: detecting the current flowing through the power tube, and when the current flowing through the power tube exceeds the current limiting value corresponding to the current time period, controlling the gate drive circuit to adjust the drive current so that the current flowing through the power tube is limited to the current limiting value.

14. The driver circuit according to any one of claims 1 to 9, wherein: The driver circuit is coupled to a capacitive load.

15. A chip, characterized in that: The chip includes the driver circuit according to any one of claims 1 to 14.

16. An electronic device, characterized in that: The electronic device comprises the chip according to claim 15.

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