Photon counting frontend circuit

Abstract

The present disclosure relates to a frontend circuit (200) for a photon counting component, the frontend circuit (200) including: a shaper circuit (202) configured to receive an input current (206) and convert the input current (206) into an output voltage (208); and a capacitance cancellation circuit (204) coupled with an output terminal (214) of the shaper circuit (202), wherein the capacitance cancellation circuit (204) is configured to receive the output voltage (208) from the shaper circuit (202), and provide a capacitance cancellation current (220) at the output terminal (214) of the shaper circuit (202) based on the received output voltage (208), wherein the capacitance cancellation current (220) matches a load current drawn by a load capacitance (216) of the shaper circuit (202).

Description

PHOTON COUNTING FRONTEND CIRCUITTechnical Field

[0001] The present disclosure relates generally to a frontend circuit for a photon counting component, wherein the frontend circuit includes a shaper circuit and a capacitance cancellation circuit configured to compensate a load capacitance of the shaper circuit.Background

[0002] In general, photon counting is a detection technique in which individual photons are transformed into electrical signals. Compared to other detection approaches that rely on the accumulation of signal over an integration time, photon counting exploits the capabilities of a photodetector to detect individual photons. Furthermore, the energy level of a photon may be determined based on the corresponding electrical signal, thus enabling a detection with intrinsic spectral sensitivity. Photon counting for single-photon detection has various applications, for example for light-based communication, distance measurements (e.g., light detection and ranging, LIDAR), material science, and medical imaging. In particular, for medical imaging the so-called “Photon-counting computed tomography” (PCCT) has emerged as a powerful technique for X-ray computer tomography (CT), and allows imaging an area of interest in a patient with enhanced resolution. Improvements in photon counting components may thus be of particular interest for the advancement of several technologies.Brief Description of the Drawings

[0003] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various aspects of the invention are described with reference to the following drawings, in which:FIG.1A shows a frontend topology for a photon counting component in a schematic representation, according to various aspects;FIG. IB and FIG.1C show graphs related to the operation of the frontend topology of FIG.1A, according to various aspects;FIG.2A shows a frontend circuit for a photon counting component in a schematic representation, according to various aspects;FIG.2B shows a photon counting component including the frontend circuit in a schematic representation, according to various aspects;FIG.3A shows a shaper circuit for a frontend circuit in a schematic representation, according to various aspects;FIG.3B and FI.3C show a capacitance cancellation circuit for a frontend circuit in a schematic representation, according to various aspects;FIG.4A and FIG.4B show exemplary configurations of a frontend circuit for a photon counting component in a schematic representation, according to various aspects;FIG.5 shows an exemplary configuration of a frontend circuit for a photon counting component in a schematic representation, according to various aspects; andFIG.6A and FIG.6B show exemplary configurations of a frontend circuit for a photon counting component in a schematic representation, according to various aspects.Description

[0004] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and aspects in which the invention may be practiced. These aspects are described in sufficient detail to enable those skilled in the art to practice the invention. Other aspects may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects are not necessarily mutually exclusive, as some aspects may be combined with one or more other aspects to form new aspects. Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures. Throughout the drawings, it should be noted that proportions are not necessary to scale and that the size of features may be emphasized for ease of illustration.

[0005] In general, in a photon counting component single photon events are detected and counted in order to obtain intensity and spectral information. In contrast to a classical image sensor or X-ray sensor in which only the total input intensity is measured, a photon counting component allows extracting the photon energy by detecting the photons individually. The detection of single photons is enabled by a special sensor material, which converts quants into current pulses. The sensor material may be selected depending on the wavelength range of interest, for example the sensor material may include cadmium telluride (CdTe) or cadmium zinc telluride (CdZnTe) for X-ray conversion. The current pulses from the sensor are converted to voltage pulses by a frontend circuit (e.g., a CMOS frontend circuit, where CMOS stands for Complementary Metal-Oxide-Semiconductor). The height of the output voltage peak isproportional to the photon energy, thus containing spectral information. Digitization of the spectral information (output pulse height) may be performed using a discriminator, which consists of several comparators with different thresholds. The outputs of the comparators (e.g., part of a flash analog-to-digital converter chip) are then individually counted to obtain a spectral distribution.

[0006] As photon counting detectors are usually deployed in laboratories and hospitals, ultra-low power consumption is typically not a requirement. However, photon counting components may deploy a large number of channels to achieve sufficient spatial resolution. Thus, the total power consumption might still produce a considerable amount of heat, requiring sophisticated cooling. Consequently, maximum power consumption per channel should be limited to allow for cost efficient air cooling.

[0007] As a further consideration, the sensor (illustratively, the photodetector) is usually not integrated in the frontend circuit (e.g., in the CMOS frontend chip), so that a complex assembly process is required to connect sensor and frontend. As a result, a photon counting component may include external routing traces from sensor to frontend input which introduce considerable amount of parasitic capacitance. As parasitic input capacitance directly impacts noise and speed of the frontend this can considerably increase the power consumption budget of the integrated circuit.

[0008] In the context of photon counting components there are two widely spread topologies for photon counting front ends. For example, in a first topology a photon counting component may be a two-stage circuit that includes a charge sensitive amplifier (CSA) circuit followed by a shaper circuit. As another example, in a second topology a photon counting component may be a single-stage circuit, in which basically the CSA is omitted, and sensor current pulses are directly converted into sharp output voltage pulses via a shaper circuit.

[0009] FIG.1 A shows a generalized version of a single stage topology 100 for a frontend circuit including a shaper circuit 102, in which high pulse gain is implemented by an operational amplifier 104 with a feedback network consisting of a small feedback capacitance 106 and a parallel transconductance element 108. The current feedback element 108 may be a resistor or a transconductor.

[0010] Assuming a feedback resistor RFB as transconductance element 108, and omitting the parasitic input capacitance 110, CIN, and parasitic output capacitance 112, CL, the current transfer function of the topology 100 may be expressed as:

[0011] A typical response for a rectangular current pulse is shown in the graph 120b in FIG. IB. As it may be inferred from the graph 120b, with increasing input capacitance 110 CIN the shaper response slows down, so that the output pulse peaking time increases while the pulse peak decreases.

[0012] Taking the parasitic input capacitance 110, CIN, and parasitic output capacitance 112, CL, into account, the current transfer function of the topology 100 may be approximated as:

[0013] Consequently, CIN and CL introduce a high order term that may only be attenuated by increasing the transconductance gm of the amplifier 104, which means higher power consumption, and / or by reducing CL which means a scaled and more expensive technology node, or by reducing RFB. AS shown in the graph 120c in FIG.1C reduction of the resistance RFB leads to undershoot or even oscillations in the pulse response, which are undesirable.

[0014] Outside photon counting there have been bandwidth enhancement or capacitance cancellation techniques reported. These typically involve positive feedback in differential stages to create an active inductor for cancelling parasitic capacitance. For example, an active circuit may be added at the output of a source follower buffer to cancel at least some of the parasitic capacitance introduced by sharing the source follower output node between many pixels in an image sensor.

[0015] Aspects of the present disclosure are directed to a single-stage topology for a frontend circuit for use in a photon counting component, which is adapted to operate with large input and output load capacitance(s), e.g. up to several hundred femtofarad (fF). The topology proposed herein is thus adapted to provide the capability to operate with large capacitances without significant increase in power consumption.

[0016] The present disclosure may be based on the realization that a capacitance cancellation circuit may be introduced in a single-stage topology to compensate for the parasitic output capacitance of the shaper circuit, thus enhancing the capabilities of the arrangement and expanding its operating range. Illustratively, the present disclosure may be based on the realization that the output load capacitance of the shaper circuit may be cancelled by suitably dimensioning a capacitance cancellation circuit. The capacitance cancellation circuit may be configured to receive the output voltage pulse of the shaper circuit, and to provide an amplified version of the output voltage pulse back to the output terminal of the shaper circuit. By suitably dimensioning the amplification of the output voltage, a cancellation of a load current drawn by the load capacitance is obtained, thus making the topology insensitive to the load capacitance.

[0017] As a result, the frontend topology proposed herein may achieve lower power and / or lower noise compared to conventional double stage or single stage topologies. In conventional topologies, a single stage configuration was implemented for very low input capacitance of about 100 fF. Besides, the single stage topology proposed herein results in area savings, which is crucial to minimize the total die size. This results in cost reduction and helps to accommodate a variety of photon counting module dimensions.

[0018] According to various aspects, a frontend circuit for a photon counting component may include: a shaper circuit configured to receive an input current and convert the input current into an output voltage; and a capacitance cancellation circuit coupled with an output terminal of the shaper circuit. The capacitance cancellation circuit may be configured to receive the output voltage from the shaper circuit, and provide a capacitance cancellation current at the output terminal of the shaper circuit based on the received output voltage, wherein the capacitance cancellation current matches a load current drawn by a load capacitance of the shaper circuit.

[0019] The capacitance cancellation circuit may illustratively be configured to define a capacitance that cancels out the load capacitance of the shaper circuit. Such configuration may be based on the realization that the load capacitance at the shaper output draws a current given by, _ out_shaper‘out_shaper i w / sCL

[0020] Thus, by dimensioning the capacitance cancellation circuit to provide a current matching the current drawn by the load capacitance, then the load capacitance is effectively not seen by the shaper circuit and thus cancelled. In order to enable fast pulse response without sacrificing power efficiency or stability a suitably dimensioned capacitance cancellation circuit is added at the shaper output.

[0021] Various configurations may be provided for the frontend circuit proposed herein, e.g. for the shaper circuit and capacitance cancellation circuit, as discussed in further detail below in relation to FIG.2A to FIG.6B. It is understood that the aspects discussed in relation to a certain configuration (e.g., in terms of values, parameters, etc.) may apply in a corresponding manner also to the other configurations, unless explicitly stated otherwise.

[0022] In the following, certain components of the circuit(s) may be shown or described as single components, e.g. a capacitor, a resistor, etc. It is however understood that a circuit component may also be realized via a combination of a plurality of components that together provide the same functionality as the single component.

[0023] FIG.2A shows a frontend circuit 200 for use in a photon counting component (see FIG.2B) in a schematic representation, according to various aspects. According to the topology proposed herein, the frontend circuit 200 may include a shaper circuit 202, and a capacitance cancellation circuit 204 coupled with the output of the shaper circuit 202. In relation to FIG.2A the general principles of the operation of the frontend circuit 200 are described. Possible configurations of the shaper circuit 202 and capacitance cancellation circuit 204 will be discussed in detail in relation to FIG.3A to FIG.6B.

[0024] The shaper circuit 202 may be configured to receive an input current 206 and to convert the input current 206 into an output voltage 208. In particular considering photon counting applications the shaper circuit 202 may be configured to receive an input current pulse, and to convert the input current pulse into an output voltage pulse. Illustratively, the input current 206 may be or include a current pulse, and the output voltage 208 may be or include a voltage pulse. The shaper circuit 202 may have any suitable configuration to implement the pulse shaping functionality, e.g. the shaper circuit 202 may include an amplifier with a feedback network as discussed in further detail in relation to FIG.3A.

[0025] As shown in FIG.2 A, the frontend circuit 200 may include an input terminal 207 at which the frontend circuit 200 may receive the input current 206. The input terminal 207 may be configured to be coupled with a photodetector (see also FIG.2B) to receive a current resulting from detection of a (single) photon. The input terminal 207 may be coupled with the shaper circuit 202, e.g. the shaper circuit 202 may include a shaper input 210 coupled with the input terminal 207 to receive the input current 206. In an exemplary configuration the shaper input 210 may coincide with the input terminal 207 of the frontend circuit 200.

[0026] Furthermore, the frontend circuit 200 may include an output terminal 212 at which the frontend circuit 200 may deliver the output voltage 208. The output terminal 212 may be configured to be coupled with a discriminator (see FIG.2B) to enable the photon counting functionality. The output terminal 212 may be coupled with the shaper circuit 202, e.g. the shaper circuit 202 may include a shaper output 214 coupled with the output terminal 212 to deliver the output voltage 208 from the shaper circuit 202 externally of the frontend circuit 200. In an exemplary configuration the shaper output 214 may coincide with the output terminal 212 of the frontend circuit 200.

[0027] The shaper circuit 202 may have a load capacitance 216, CL, associated therewith. In general, the load capacitance 216 may be known, e.g. the capacitance value of the load capacitance 216 may be determined based on measurements, simulations, and the like. For example, the load capacitance 216 may be identified by simulations and parasitic extractionfrom a chip layout. For example, the load capacitance 216 may be or include a parasitic output capacitance, e.g. the parasitic output capacitance defined by electrical wiring to couple the shaper circuit 202 with a load (e.g., with a discriminator). The load capacitance 216 may include, additionally or alternatively, other contributions from other circuit components and / or load components. The load capacitance 216 draws a load current 218 at the shaper output 214. Although not shown, the shaper circuit 202 may further have an input capacitance associated therewith.

[0028] According to proposed topology, the frontend circuit 200 may further include a capacitance cancellation circuit 204 configured to cause an effective cancellation of the load capacitance 216 for the shaper circuit 202. Illustratively, the capacitance cancellation circuit 204 may be configured to provide a compensation of the load capacitance 216 such that the shaper circuit 202 has a substantially null capacitance at its output. The frontend circuit 200 may thus be understood as an analog single-stage frontend circuit with cancellation of the load capacitance 216 of the shaper circuit 202. The presence of the capacitance cancellation circuit 204 allows the frontend circuit 200 to accommodate large input and output capacitance.

[0029] As shown, the capacitance cancellation circuit 204 may be coupled with the shaper output 214 (and with the output terminal 212), and may be configured to receive the output voltage 208 of the shaper circuit 202 (e.g., the output voltage pulse). The capacitance cancellation circuit 204 may be configured to provide a current 220 at the output terminal 214 of the shaper circuit based on the received output voltage 208. Illustratively, the capacitance cancellation circuit 204 may be configured to deliver a capacitance cancellation current 220 at the output terminal 214, and the capacitance cancellation circuit 204 may be configured (e.g., dimensioned) such that the capacitance cancellation current 220 cancels out the current drawn by the load capacitance 216.

[0030] According to various aspects, the capacitance cancellation circuit 204 may be configured to provide an amplification of the output voltage 208 by an amplification factor to provide (e.g., generate) an amplified voltage. The amplification factor may be a function of the load capacitance 216 (illustratively, of the capacitance value of the load capacitance). The amplification factor may be configured to define a current 220 proportional to the difference between the amplified voltage and the output voltage 208 that matches the load current 218.

[0031] Stated in a different fashion, the capacitance cancellation circuit 204 may be configured to transfer the output voltage 208 back to the output terminal 214 of the shaper circuit 202 (as a current 220), and the transfer function of the capacitance cancellation circuit 204 may be a function of the load capacitance 216. Illustratively, the transfer function of the capacitancecancellation circuit 204 may be configured to cause a cancellation of the load capacitance 216 at the output of the shaper circuit 202. The dimensioning of the capacitance cancellation circuit 204 to obtain the effective capacitance cancellation will be discussed in further detail in relation to FIG.3B and FIG.3C.

[0032] The capacitance cancellation circuit 204 may thus render the shaper circuit 202 unaffected by the load capacitance 216, thus enhancing the capabilities of the frontend circuit 200 without increasing the overall complexity and area occupancy as in a two-stage topology.

[0033] According to various aspects, the shaper circuit 202 and the capacitance cancellation circuit 204 may be integrated on the same substrate, thus forming a single integrated circuit defining the frontend topology. In other aspects, the shaper circuit 202 and the capacitance cancellation circuit 204 may be formed on different substrates. According to various aspects, the shaper circuit 202 and the capacitance cancellation circuit 204 may be configured / formed according to CMOS-technology, e.g. in this scenario the frontend circuit 200 may be referred to as CMOS frontend or CMOS frontend circuit.

[0034] FIG.2B shows a photon counting component 250 including the frontend circuit 200 with the adapted topology for cancellation of the load capacitance 216. The photon counting component 250 may also be referred to herein as photon counting circuit, photon counting system, or photon counting device. The general principles of operation of a photon counting component are known in the art. A brief description is provided herein to discuss aspects relevant for the present disclosure. The photon counting component 250 may be for use in any suitable application. For example, a medical imaging device may include the photon counting component 250, e.g. to carry out a photon-counting computed tomography. As another example, a spectroscopy device may include the photon counting component 250. As a further example, a security scanner may include the photon counting component 250.

[0035] The photon counting component 250 may in general be configured to allow detecting / counting single photons, and may include a photodetector 252 configured to detect single photons. In particular, the photodetector 252 may be configured to generate a detection signal (the current 206 input to the frontend circuit 200) upon photons 254 impinging onto a sensing area of the photodetector 252. A sensing area may be an active area of the photodetector 252 configured to convert photon energy in electrical energy (illustratively, in the photo current 206, e.g. in current pulses each corresponding to a respective photon). For example, for X-ray detection the sensing area may include or consists of CdTe or CdZnTe for X-ray conversion.

[0036] In the photon counting component 250 single photon events may thus be detected and counted in order to obtain intensity and spectral information, and photon energy may also beextracted because photons are detected individually. Detection of single photons may be enabled by the sensor material of the photodetector 252, which converts photon quants into current pulses 206. As discussed in relation to FIG.2A, the frontend circuit 200 may convert the input current 206 from the photodetector 252 into a corresponding output voltage 208, e.g. the frontend circuit 200 (shaper circuit 202) may convert input current pulses into corresponding output voltage pulses.

[0037] The frontend circuit 200 may deliver the output voltage 208 to a photon counting stage 256 of the photon counting component 250. The photon counting stage 256 may in general be configured to determine a count of photons received / detected at the photodetector 252 based on the output voltage 208 of the frontend circuit 200. As shown, the photon counting stage 256 may include a discriminator stage 258 (also referred to simply as discriminator) and a counter stage 260. In some aspects, the frontend circuit 200, discriminator stage 258, and counter stage 260 may be referred together as CMOS integrated circuit (CMOS IC).

[0038] The discriminator stage 258 may include a plurality of comparators 262, and each comparator 262 may be configured with a respective threshold voltage specific for that comparator 262. A first comparator 262 may have a first threshold voltage Vth-i, a second comparator 262 may have a second threshold voltage Vth-2,..., an N-th comparator 262 may have an N-th threshold voltage Vth-N. The discriminator stage 258 may include any suitable number of comparators 262 depending on the desired granularity for the detection. The discriminator stage 258 may thus allow to determine the voltage amplitude of the output voltage 208 (the pulse) received at the discriminator stage 258 from the frontend circuit 200.

[0039] Illustratively, from an input terminal of the discriminator stage 258, the voltage signal 208 is delivered to each comparator 262 (each disposed in a respective branch). Each comparator 262 may provide a respective output signal (e.g., a low voltage or high voltage, e.g. a 0 or a 1) depending on whether the voltage signal 208 is lower or greater than the respective threshold voltage for that comparator 262. For example, a comparator 262 may include an amplifier configured to receive the voltage signal 208 at the non-inverting terminal and the respective threshold voltage at the inverting terminal.

[0040] The counter stage 260 may include a plurality of counters 264, each coupled to the output of a respective comparator 262. Illustratively, the plurality of counters 264 may be coupled in a one-to-one fashion with the plurality of comparators 262. The counters 264 having the threshold voltage of their preceding comparator 262 exceeded register a count by the pulse amplitude. This can be converted into a single count and the corresponding energy bin by a post processing procedure.

[0041] As shown in FIG.2B, the photodetector 252 generates a current pulse IPULSE corresponding to incident photons 254. The frontend circuit 200 converts the pulse signal 206 into a voltage pulse signal, VPULSE, and delivers the voltage pulse signal to the discriminator 258 for determining the energy of the pulse (and accordingly of the detected photon 258), and for counting the detected photon 258. The counter 264 that counts a photon is the counter 264 coupled with the comparator 262 having a threshold voltage matching the voltage amplitude of the voltage pulse generated upon detection of the photon.

[0042] The pulse length, e.g. full width half-maximum (FWHM), of the voltage pulse signal corresponds to a number of detected photons at the same time or within an overlapping time window. The amplitude of the pulse of the voltage pulse signal corresponds to the energy of the detected photon. Ideally, pulses of photons do not overlap in time allowing single photon detection. Thus, the energy determined using a comparator 262 - counter 264 pair allows to determine the energy of detected photons.

[0043] In the frontend circuit 200 (e.g., in the shaper circuit 202), the height of the output voltage peak is proportional to the photon energy, thus containing spectral information. Digitization of the spectral information, e.g. output pulse height, may be performed by the discriminator 258. The discriminator outputs are individually counted by the counters 260 to obtain the spectral distribution.

[0044] FIG.3A, FIG.3B, and FIG.3C show in further detail a shaper circuit (FIG.3A), and a capacitance cancellation circuit (FIG.3B). The shaper circuit 300 may be an exemplary realization of the shaper circuit 202 of the feedback circuit 200. The capacitance cancellation circuit 350 may be an exemplary realization of the capacitance cancellation circuit 204 of the feedback circuit 200.

[0045] The configurations described in FIG.3A to FIG.3C (and further in FIG.4A to FIG.6B) have been found to provide an efficient implementation of the proposed topology with capacitance cancellation. It is however understood that in principle the shaper circuit and / or capacitance cancellation circuit may be realized in other configurations (e.g., with more, fewer, or alternative components) to implement the pulse shaping functionality and the capacitance cancellation functionality. It is also understood that the various configurations for the shaper circuit may be combined with any of the configurations of the capacitance cancellation circuit, as appropriate.

[0046] FIG.3A shows a shaper circuit 300 in a schematic representation, according to various aspects. In general, the shaper circuit 300 may be configured to receive a current 310 (e.g., a current pulse) and deliver, as output, a voltage 312 (e.g., a voltage pulse). In this regard, theshaper circuit 300 may include an amplifier 302. The amplifier 302 may include a first input terminal 304, a second input terminal 306, and an output terminal 308. The amplifier 302 may receive the input current 310 at one input terminal, e.g. at the second input terminal 306, and may provide a corresponding output voltage 312 at the output terminal 308. The amplifier 302 may further receive a reference voltage 314 at the other input terminal, e.g. at the first input terminal 304.

[0047] For example, the first input terminal 304 may be configured to be coupled with a reference voltage source for the shaper circuit, e.g. with a reference potential. In some aspects, the shaper circuit 300 may include a reference voltage source coupled to the first input terminal 304. The second input terminal 306 may be configured to be coupled with a photodetector that generates the input current 310 (upon detection of a photon), as discussed in relation to FIG.2B. As an example, the first input terminal 304 may be the non-inverting terminal (the positive terminal, +) of the amplifier 302, and the second input terminal 306 may be the inverting terminal (the negative terminal, -) of the amplifier 302.

[0048] The shaper circuit 300 may further include a feedback network 320 coupled with the amplifier 302. The feedback network 320 may be coupled between the output terminal 308 and the input terminal at which the amplifier 302 receives the input current 310, e.g. the second input terminal 306 (e.g., the inverting terminal). The feedback network 320 may have any suitable configuration to couple the output of the amplifier 302 with the input 302, thus bringing a fraction of the output voltage 308 back at the input terminal. The feedback network 320 may enhance the stability of the amplifier 302, e.g. damping oscillations at the output of the amplifier 302. The feedback network 320 may be an active feedback or a passive feedback. Exemplary configurations will be discussed in relation to FIG.4A to FIG.6B. In general, the feedback network 320 may include one or more feedback components 322 (e.g., resistors, capacitors, transconductor elements, and the like) disposed on one or more feedback branches.

[0049] FIG.3B shows a first configuration of a capacitance cancellation circuit 350a, and FIG.3C shows a second configuration of a capacitance cancellation circuit 350b in a schematic representation, according to various aspects. In general, the capacitance cancellation circuit 350a, 350b may be configured to be coupled with a shaper circuit (e.g., the shaper circuit 300) and may be configured to cause a cancellation of a load capacitance of the shaper circuit. In particular, the capacitance cancellation circuit 350a, 350b may be configured to cause a flow of a current 360 that matches (and cancels out) a current drawn by the load capacitance of the shaper circuit.

[0050] The capacitance cancellation circuit 350a, 350b may include a first terminal 352 and a second terminal 354. The first terminal 352 and the second terminal 354 may both be configured to be coupled with the output terminal of the shaper circuit, so that the first terminal 352 and the second terminal 354 may be at the output voltage of the shaper circuit. The capacitance cancellation circuit 350a, 350b may be configured to generate / deliver the capacitance cancellation current 360 at one of the terminals, e.g. at the second terminal 354.

[0051] As discussed in relation to FIG.2A, the capacitance cancellation circuit 350a, 350b may be configured to cause an amplification of the output voltage of the shaper circuit by an amplification factor that defines a suitable current value for the capacitance cancellation current 360 to cancel the load current indicated in Equation 3 above.

[0052] In a simple configuration, the capacitance cancellation circuit 350a may include an amplifier 356 configured to receive as input the output voltage of the shaper circuit and provide, as output, an amplified version of the output voltage as amplified voltage. The capacitance cancellation circuit 350a may further include a capacitor element 358 coupled at the output of the amplifier 356. The capacitor element 358 may be coupled between the output of the amplifier and the terminal 354 at which the capacitance cancellation circuit 350a delivers the capacitance cancellation current 360.

[0053] According to various aspects, the amplifier 356 may be configured to amplify the voltage by an amplification factor that, in combination with the capacitance of the capacitor element 358, causes cancellation of the load capacitance of the shaper circuit. The amplification factor of the amplifier 356 and the capacitance value of the capacitor element 358 may thus be configured to define a capacitance cancellation current 360 matching the load current drawn by the load capacitance of the shaper circuit.

[0054] As a possible configuration, the amplification factor of the amplifier 356 may be two, so that the amplifier 356 provides an amplified voltage having a voltage value two-times greater than the output voltage of the shaper circuit. Thus, the capacitor element 358 has a voltage drop corresponding to the output voltage of the shaper circuit, by seeing the output voltage at one side and twice the output voltage at the other side of the capacitor element 358. By dimensioning the capacitor element 358 such that the capacitance value is equal to the load capacitance of the shaper circuit, the matching of the capacitance cancellation current 360 with the load current is obtained.

[0055] Illustratively, in the configuration 350a the shaper output voltage is amplified by factor 2 and injected into the shaper output node via the capacitor 358. Denoting with Cc the capacitance of the capacitor element 358 the following relation is obtained,

[0056] Hence, load current cancellation is achieved for Cc = CL.

[0057] Turning to the configuration 350b in FIG.3C, the capacitance cancellation circuit 350b may include a high pass filter stage 362 and a transconductance stage 364. The high pass filter stage 362 may be coupled with the first terminal 352 and may be configured to perform a high pass filter operation on the output voltage of the shaper circuit to deliver a filtered version of the voltage at the output of the high pass filter stage 362. The transconductance stage 364 may be coupled with the output of the high pass filter stage 362 and may receive the filtered voltage. The transconductance stage 364 may be configured to generate the capacitance cancellation current 360 based on the received filtered voltage. In some aspects, the capacitance cancellation circuit 350b may further include an optional buffer stage (e.g., including a unity amplifier 366) between the first terminal 352 and the high pass filter stage 362.

[0058] As an example, the high pass filter stage 362 may include a capacitor element 368 and a resistor element 372 coupled with one another to define a high pass filter configuration. As generally known, the high pass filter stage 362 may be configured such that at high frequencies of the voltage input to the high pass filter stage 362 (the output voltage of the shaper circuit) the voltage at the output of the high pass filter stage 362 appears virtually without attenuation. On the other hand, as the frequency of the input decreases, the voltage at the output of the high pass filter stage 362 is increasingly attenuated.

[0059] The output of the high pass filter stage 362 may be coupled with the input of the transconductance stage 364. The transconductance stage 364 may include, for example, a transconductance amplifier 370 (with gain gm), which generates the capacitance cancellation current from the filtered voltage received from the high pass filter stage 362.

[0060] In the configuration in FIG.3C, the shaper output voltage is applied to a high pass filter and then applied to a transconductance stage, which generates the desired cancellation current 360. Denoting with Rc the resistance value of the resistor element 372 and with Cc the capacitance value of the capacitor element 368, the effective shaper load current may be expressed as

[0061] Hence, at high frequencies where the load capacitance becomes a limitation this circuit may effectively cancel the load current seen by the shaper by setting gm*Rc*Cc equal to CL.Illustratively, in the configuration 350b, the capacitor element 368, resistor element 372, and amplifier 370 may be configured (e.g., dimensioned) to define an effective capacitance matching the load capacitance of the shaper circuit.

[0062] FIG.4A to FIG.6B show possible realizations of a frontend circuit as proposed herein, including a shaper circuit and a capacitance cancellation circuit. Illustratively, FIG.4A to FIG.6B show possible implementations of the frontend circuit 200, shaper circuit 300, and capacitance cancellation circuit 350a, 350b. It is understood that the aspects discussed in relation to FIG.4A to FIG.6B may be combined with one another, as appropriate, e.g. the shaper circuit discussed in relation to a certain configuration may be combined with a capacitance cancellation circuit discussed in relation to another configuration, and vice versa.

[0063] FIG.4A and FIG.4B show a frontend circuit 400a, 400b including a shaper circuit 402 and a capacitance cancellation circuit 404a, 404b. The shaper circuit 402 may in general be configured as the shaper circuit 300 of FIG.3, and may include an amplifier 406 and a feedback network 408. The capacitance cancellation circuit 404a of FIG.4A may be configured as the capacitance cancellation circuit 350a of FIG.3B, and may include an amplifier 410 and a capacitor element 412 to deliver a capacitance cancellation current at the output of the shaper circuit 402 to compensate for a load capacitance 416. The capacitance cancellation circuit 404b of FIG.4B may be configured as the capacitance cancellation circuit 350b of FIG.3C, and may include a unity amplifier 426, a capacitor element 428, a resistor element 430, and a further amplifier 432 with gain gmto deliver the capacitance cancellation current at the output of the shaper circuit 402. As discussed in relation to FIG.2A, the shaper circuit 402 may further have a parasitic capacitance 414 at its input (also referred to as input capacitance).

[0064] In general, the frontend circuit 400a, 400b may receive an input current 418, e.g. an input current pulse, and deliver an output voltage 424 (an output voltage pulse), as discussed above. The presence of the capacitance cancellation circuit 404a, 404b enables operation in a wider capacitance range compared to conventional configurations, while maintaining an overall reduced area consumption.

[0065] In brief, the shaper circuit 402 may receive the input current 418, and deliver / generate the corresponding output voltage 424. For example, the shaper circuit 402 may include an amplifier 406 receiving the input current 418 at its inverting terminal, and a reference voltage at the non-inverting terminal. The shaper circuit 402 may further include the feedback network 408 coupled between the output of the amplifier 406 and the inverting terminal of the amplifier. As an exemplary configuration, the feedback network 408 may include a plurality of branchesin parallel to one another, e.g. a first branch including a transconductance element 420 (e.g., a resistor, a transconductor) and a second branch including a capacitor element 422.

[0066] The capacitance cancellation circuit 404a, 404b may be coupled at the output of the shaper circuit 402, e.g. between the output terminal of the shaper circuit 402 and the output terminal of the frontend circuit 400a, 400b. As discussed in relation to FIG.3B and FIG.3C, the capacitance cancellation circuit 404a, 404b may be configured to define an effective capacitance matching the load capacitance 416 to provide a capacitance cancellation current canceling the load current.

[0067] In the configuration 404a of FIG.4A, the capacitance cancellation circuit 404a may include an amplifier 410 having an amplification factor of 2 to provide a voltage at one side of the capacitor element 412 twice the output voltage of the shaper circuit 402. In this scenario, the capacitor element 412 sees the output voltage of the shaper circuit 402 at one side and twice the output voltage of the shaper circuit 402 at the opposite side, thus having a voltage drop that defines a capacitance cancellation current matching the load current for a capacitance value of the capacitor element 412 being equal to the load capacitance 416.

[0068] In the configuration 404b of FIG.4B, the capacitance cancellation circuit 404b may include a high pass filter stage that filters the output voltage of the shaper circuit 402, and a transconductance stage that generates the capacitance cancellation current. As shown, the high pass filter stage may include a unity amplifier 426 and a capacitor element 428 in series with one another, and the transconductance stage may include a resistor element 430 and an amplifier 432. The capacitance value of the capacitor element 428, resistance value of the resistor element 430, and gain of the amplifier 432 may define a capacitance matching the load capacitance 416 to provide a suitable cancellation current.

[0069] FIG.5 shows a frontend circuit 500 including a shaper circuit 402 and a capacitance cancellation circuit 502. For ease of reference, the same reference signs are maintained in relation to the same elements as the frontend circuit 400a, 400b. The capacitance cancellation circuit 502 may be a practical implementation of the capacitance cancellation circuit 404b of FIG.4B. As discussed in relation to FIG.3C, the capacitance cancellation circuit 502 may include a buffer stage 504 (a buffer circuit) disposed between the high pass filter stage and the terminal at which the capacitance cancellation circuit 502 receives the output voltage of the shaper circuit 402.

[0070] The buffer stage 504 may in general be configured to copy the voltage from the output of the shaper circuit 402 to the input of the high pass filter stage, and may provide a more ideal source for the processing of the voltage and the generation of the capacitance cancellationcurrent. In general, the buffer stage 504 may be configured as a buffer amplifier with a unitary gain. For example, the buffer amplifier may be realized as a pair of transistors 506, 508. For example, the buffer stage 504 may include a first transistor 506, e.g. first PMOS, and a second transistor 508, e.g. a second PMOS. The source of the first transistor 506 may be coupled with the drain of the second transistor 508 at a common node, and the voltage at the common node may be delivered to the high pass filter stage. Thus, in the simplest form the buffer stage 504 may be realized as a source follower. More advanced implementations of the buffer may include for example a super source follower. In some aspects, the buffer stage may be omitted at the expense of adding additional load capacitance Cc to the output.

[0071] In the configuration in FIG.5, the shaper output may thus be buffered and injected via a capacitor 510 into a cascode node 514 which forms a common gate amplifier configuration for the injection path. The proposed topology does not require a complex swing inversion circuitry. The input impedance at the cascode node 514 represents the resistor element (Rc) of the high pass filter stage, and the transconductance Ml of a further transistor element 512 represents the gain gmof the transconductance stage. As shown in FIG.5, the capacitance cancellation circuit 502 may include bias sources to provide a bias to the various components / stages of the circuit. For example, the capacitance cancellation circuit 502 may include a first bias source 516 to generate a bias current for the buffer stage 504, e.g. the drain node of the first transistor 506 may be coupled with the first bias source 516. For example, the capacitance cancellation circuit 502 may include a second bias source 518 and third bias source 520 to generate bias current for the transconductance stage. The source node of the transistor element 512 may be coupled with the second bias source 518, and the drain node of the transistor element 512 may be coupled with the third bias source 520.

[0072] According to various aspects, a more complex configuration may be provided in which a node of the amplifier of the shaper circuit is used for capacitive coupling. This configuration may be provided, for example, in case the shaper circuit includes an operational transconductance amplifier (OTA) that allows sharing a branch of the shaper circuit with the capacitance cancellation circuit. Thus, in some aspects, the shaper circuit and the capacitance cancellation circuit may have a shared branch, thus allowing an efficient utilization of space and resources. Such configuration is shown in FIG.6A (for a shaper circuit including a folded cascode amplifier) and in FIG.6B (for a shaper circuit including a telescopic cascode amplifier).

[0073] Illustratively, instead of a dedicated common gate amplifier a cascode node of a telescopic cascode OTA or the folding node of a folded cascode OTA may be used for capacitive coupling, thus providing a further power reduction. In such configuration, the currentof the shaper OTA is reused for generating the capacitance cancellation current, as shown in the frontend circuits 600a, 600b in FIG.6A and FIG.6B. For example, a branch / cascode node may be shared between the shaper circuit and the capacitance cancellation circuit to be part of both the operational amplifier of the shaper circuit and of the transconductance stage of the capacitance cancellation circuit (considering the configuration of FIG.3C, FIG.4B, and FIG.5).

[0074] With reference to FIG.6 A, the frontend circuit 600a may include a shaper circuit and a capacitance cancellation circuit, and may in general be configured to receive an input current 601 (an input pulse), and deliver an output voltage 603 (a voltage pulse). The shaper circuit may include an amplifier circuit 602a configured as a folded cascode amplifier, and a feedback network 604. For example, the feedback network 604 may include a capacitor element 606 on a first branch and a transconductance element 608 (e.g., a resistor, a transconductor) on a second branch, or may have any other suitable configuration.

[0075] The folded cascode amplifier 602a may include a plurality of branches, e.g. a first branch 610 (the main branch) and a second branch 612 (the folding branch), and one of the branches may be shared with the capacitance cancellation circuit. In the folded cascode configuration, the first branch 610 may include a bias source 614 to bias a first transistor element 616 (e.g., a NMOS) coupled in series with a second transistor element 618 (e.g., a NMOS). The second transistor element 618 may receive the input current 601 at its gate node. The drain node of the first transistor element 616 may be coupled with the bias source 614. The source node of the first transistor element 616 may be coupled with the drain node of the second transistor element 618, and the source node of the second transistor element 618 may be coupled with a reference potential, e.g. ground.

[0076] At the second branch 612, the folded cascode amplifier 602a may include a second bias source 620 to provide bias current to a third transistor element 622 (e.g., PMOS). The cascode node 624 of the second branch 612 (e.g., the source node of the third transistor element 622) may be shared with the capacitance cancellation circuit. Illustratively, the capacitor element 632 of the capacitance cancellation circuit (defining the high pass filter stage) may be coupled with the cascode node 624 of the second branch 612, thus using the second branch 612 of the folded cascode amplifier 602a as transconductance stage, e.g. using the third transistor element 622 as transconductance element and the input impedance at the at the cascode node as resistor element.

[0077] In this regard, the capacitance cancellation circuit may include a buffer stage, e.g. implemented via a transistor pair 626, 628 (source follower) and including a bias source 630. In other aspects the buffer stage may be omitted. At the high pass filter stage the capacitancecancellation circuit may include the capacitor element 632, and one side of the capacitor element 632 may be coupled with the cascode node 624 of the second branch 612 of the folded cascode amplifier 602a, as discussed above. The folding branch may thus be shared with the capacitance cancellation circuit. In this configuration, the cancellation of the load capacitance 636 may be provided with reduced power. As shown, an input capacitance 634 may also be present in the arrangement.

[0078] In the configuration of the frontend circuit 600b in FIG.6B, the shaper circuit may include an amplifier 602b configured as a telescopic cascode amplifier. In this scenario, the telescopic cascode amplifier 602b may include a main branch shared with the capacitance cancellation circuit.

[0079] The main branch of the telescopic cascode amplifier 602b may include a first transistor element 638 (e.g., a NMOS) coupled in series with a second transistor element 640 (e.g., a NMOS). The second transistor element 640 may receive the input current 601 at its gate node. The source node of the first transistor element 638 may be coupled with the drain node of the second transistor element 640, and the source node of the second transistor element 640 may be coupled with a reference potential, e.g. ground. The main branch may further include a bias source 642 coupled at the source node of a third transistor element 644 (e.g., PMOS). The drain node of the third transistor element 644 and the drain node of the first transistor element 638 may be coupled to a common cascode node 646 shared with the capacitance cancellation circuit. Illustratively, the capacitor element 632 of the capacitance cancellation circuit may be coupled with the common cascode node 646. The shaper OTA 602b may thus be implemented as a telescopic cascode amplifier allowing to share the main branch with the capacitance cancellation circuit.

[0080] As an optional component, the telescopic cascode amplifier 602b may include a capacitor element 648 coupled at a node between the third transistor element 644 and the bias source 642, and further coupled at the node between the pair of transistors 626, 628 of the buffer stage of the capacitance cancellation circuit.

[0081] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0082] The phrase “at least one” and “one or more” may be understood to include a numerical quantity greater than or equal to one (e.g., one, two, three, four, [...], etc.). The phrase “at least one of’ with regard to a group of elements may be used herein to mean at least one element from the group consisting of the elements. For example, the phrase “at least one of’ with regardto a group of elements may be used herein to mean a selection of: one of the listed elements, a plurality of one of the listed elements, a plurality of individual listed elements, or a plurality of a multiple of individual listed elements.

[0083] All acronyms defined in the above description additionally hold in all claims included herein.

[0084] While the invention has been particularly shown and described with reference to specific aspects, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes, which come within the meaning and range of equivalency of the claims, are therefore intended to be embraced.List of reference signs 308 Output terminal310 Input current100 Frontend circuit 312 Output voltage102 Shaper circuit 314 Reference voltage104 Amplifier 320 Feedback network106 Capacitor 322 Feedback component108 Transconductance element 350a Capacitance cancellation circuit110 Parasitic input capacitance 350b Capacitance cancellation circuit112 Parasitic output capacitance 352 First terminal120b Graph 354 Second terminal120c Graph 356 Amplifier200 Frontend circuit 358 Capacitor element202 Shaper circuit 360 Capacitance cancellation current204 Capacitance cancellation circuit 362 High pass filter stage206 Input current 364 Transconductance stage208 Input terminal 366 Unity amplifier210 Shaper input 368 Capacitor element212 Output terminal 370 Amplifier214 Shaper output 372 Resistor element216 Load capacitance 400a Frontend circuit218 Load current 400b Frontend circuit220 Capacitance cancellation current 402 Shaper circuit250 Photon counting component 404a Capacitance cancellation circuit252 Photodetector 404b Capacitance cancellation circuit254 Incident photons 406 Amplifier256 Photon counting stage 408 Feedback network258 Discriminator stage 410 Amplifier260 Counter stage 412 Capacitor element262 Comparator 416 Load capacitance264 Counter 418 Input current pul se300 Shaper circuit 420 Transconductance element302 Amplifier 422 Capacitor element304 First input terminal 424 Output voltage pulse306 Second input terminal 426 Unity amplifierCapacitor element 634 Input capacitanceResistor element 636 Load capacitanceAmplifier 638 First transistor elementFrontend circuit 640 Second transistor elementCapacitance cancellation circuit 642 Bias sourceBuffer stage 644 Third transistor elementTransistor element 646 Cascode nodeTransistor element 648 Capacitor elementCapacitor elementTransistor elementCascode nodeFirst bias sourceSecond bias sourceThird bias source a Frontend circuit b Frontend circuitInput current a Amplifier circuitOutput voltageFeedback networkCapacitor elementTransconductance elementFirst branchSecond branchBias sourceFirst transistor elementSecond transistor elementBias sourceThird transistor elementCascode nodeTransistor elementTransistor elementBias sourceCapacitor element

Claims

Claims1. A frontend circuit (200) for a photon counting component, the frontend circuit (200) comprising: a shaper circuit (202) configured to receive an input current (206) and convert the input current (206) into an output voltage (208); and a capacitance cancellation circuit (204) coupled with an output terminal (214) of the shaper circuit (202), wherein the capacitance cancellation circuit (204) is configured to receive the output voltage (208) from the shaper circuit (202), and provide a capacitance cancellation current (220) at the output terminal (214) of the shaper circuit (202) based on the received output voltage (208), wherein the capacitance cancellation current (220) matches a load current drawn by a load capacitance (216) of the shaper circuit (202).

2. The frontend circuit (200) according to claim 1, wherein the capacitance cancellation circuit (204, 350a) comprises: an amplifier (356) configured to receive as input the output voltage (208) of the shaper circuit (202) and provide, as output, an amplified version of the output voltage (208) as amplified voltage; and a capacitor element (358) coupled between the output of the amplifier (356) and the output terminal (214) of the shaper circuit (202), wherein voltage drop across the capacitor element (358) is defined by the output voltage (208) of the shaper circuit (202) and by the amplified voltage from the amplifier (356), such that the capacitor element (358) causes a flow of the capacitance cancellation current (220, 360) to the output terminal (214) of the shaper circuit (202).3 The frontend circuit (200) according to claim 2,wherein the amplifier (356) is configured to provide an amplified voltage being two times greater than the output voltage (208) of the shaper circuit (202), and wherein a capacitance value of the capacitor element (358) matches a capacitance value of the load capacitance (216).

4. The frontend circuit (200) according to claim 1, wherein the capacitance cancellation circuit (204, 350b) comprises: a high pass filter stage (362) configured to receive the output voltage (208) of the shaper circuit (202) and provide a high pass filtered version of the output voltage (208) as filtered voltage; and a transconductance stage (364) coupled with the high pass filter stage (362), wherein the transconductance stage (364) is configured to receive the filtered voltage from the high pass filter stage (362) and convert the filtered voltage into the capacitance cancellation current (220, 360) delivered to the output terminal (214) of the shaper circuit (202)5. The frontend circuit (200) according to claim 4, wherein the high pass filter stage (362) comprises a capacitor element (368) and a resistor element (372) coupled in series with one another, and wherein the transconductance stage (364) comprises an amplifier coupled between the high pass filter stage (362) and the output terminal (214) of the shaper circuit (202).

6. The frontend circuit (200) according to claim 5, wherein a capacitance value of the capacitor element (368), a resistance value of the resistor element (372), and a gain of the amplifier (370) are configured to define an effective capacitance matching the load capacitance (216) of the shaper circuit (202).

7. The frontend circuit (200, 500) according to claim 5 or 6,wherein the amplifier (370) comprises a transistor element (512), wherein the capacitor element (368, 510) is coupled to a cascode node of the amplifier (370), wherein an input impedance at the cascode node (514) defines the resistor element (372), and wherein a transconductance of the transistor element (512) defines the gain of the amplifier (370). The frontend circuit (200) according to any one of claims 4 to 7, further comprising: a buffer stage configured to copy the output voltage (208) from the shaper circuit (202) to the input of the high pass filter stage (362). The frontend circuit (200) according to claim 8, wherein the buffer stage comprises a unity amplifier (366) configured to transfer the output voltage (208) from the shaper circuit (202) to the input of the high pass filter stage (362) with a unitary gain. The frontend circuit (200, 600a, 600b) according to any one of claims 4 to 9, wherein the shaper circuit (202) and the capacitance cancellation circuit (204) share a common cascode node. The frontend circuit (200, 600a) according to claim 10, wherein the shaper circuit (202) comprises a folded cascode amplifier (602a), wherein the folded cascode amplifier (602a) comprises a main branch (610) and a folding branch (612), and wherein the high pass filter stage (362) of the shaper circuit (202) is coupled with the folding branch (612) to use the folding branch (612) as transconductance stage (364) of the capacitance cancellation circuit (204).

12. The frontend circuit (200, 600b) according to claim 10, wherein the shaper circuit (202) telescopic a folded cascode amplifier (602b), wherein the telescopic cascode amplifier (602a) comprises a main branch, and wherein the high pass filter stage (362) of the shaper circuit (202) is coupled with the main branch to use the main branch as transconductance stage (364) of the capacitance cancellation circuit (204).

13. A photon counting component (250) comprising: the frontend circuit (200) according to any one of claims 1 to 12; a photodetector (252) coupled with an input terminal (208) of the frontend circuit (200), wherein the photodetector (252) is configured to generate a current pulse upon detecting a photon and deliver the current pulse as input current (206) to the frontend circuit (200); and a photon counting stage (256) coupled with an output terminal (212) of the frontend circuit (200), wherein the frontend circuit (200) is configured to deliver the output voltage (208) of the shaper circuit (202) to the photon counting stage (256).

14. The photon counting component (250) according to claim 13, wherein the photodetector (252) is configured to be sensitive for X-ray photons.

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