Method for producing a substrate for a plurality of electronic semiconductor chips and substrates for a plurality of electronic semiconductor chips

Abstract

The invention relates to a method for producing a substrate for a plurality of electronic semiconductor chips, comprising the following steps: - providing a flexible carrier (1) to which a polymer layer (3) is applied, - introducing cavities (4) into the polymer layer (3) such that a structured main surface (5) of the polymer layer (3) is produced, - applying a seed layer (6) to the structured main surface (5) of the polymer layer (3), - depositing a metal layer (7) on the seed layer (6), - depositing a solder layer (9) on or over the metal layer (7), - partially removing the solder layer (9) and the metal layer (7) such that a planar surface (11) is produced on which regions (12) having the solder (13) of the solder layer (7) and / or having an intermetallic phase (14) of the solder (13) of the solder layer (9) are exposed. The invention relates to a further method for producing a substrate for a plurality of electronic semiconductor chips, and to substrates for a plurality of electronic semiconductor chips.

Description

[0001] 2023PF01692 12 March 2025P2024,0137 WO N - 1 –Description METHOD FOR PRODUCING A SUBSTRATE FOR A PLURALITY OF ELECTRONIC SEMICONDUCTOR CHIPS AND SUBSTRATES FOR A PLURALITY OF ELECTRONIC SEMICONDUCTOR CHIPS Methods for producing a substrate for a plurality of electronic semiconductor chips and substrates for a plurality of electronic semiconductor chips are specified. The invention also aims to provide an improved method for producing a substrate for a plurality of electronic semiconductor chips. Furthermore, an improved substrate for a plurality of electronic semiconductor chips is to be specified. These objects are achieved by the methods comprising the steps of patent claim 1, patent claim 13, and patent claim 17. Furthermore, these objects are achieved by a substrate having the features of patent claim 11 and by a substrate having the feature of patent claim 18.Advantageous embodiments and further developments of the methods and substrates are specified in the dependent claims. According to one embodiment of the method for producing a substrate for a plurality of electronic semiconductor chips, a flexible carrier is provided to which a polymer layer is applied.2023PF01692 March 12, 2025P2024,0137 WO N -. 2 –In particular, the carrier has a main extension plane to which a vertical direction is perpendicular. A lateral direction also runs within the main extension plane of the carrier and is perpendicular to the vertical direction. In particular, the carrier is transparent to electromagnetic radiation from the visible spectral range and / or the infrared spectral range. In this context, the term "transparent" means in particular that the carrier transmits at least 50%, at least 85%, or at least 90%, or at least 95% of the electromagnetic radiation from the respective spectral range. For example, the carrier is a plastic film. The carrier comprises, for example, one of the following materials or is formed from one of the following materials: PET (polyethylene terephthalate), PI (polyimide), PC (polycarbonate), PMMA (polymethyl methacrylate), polyethylene naphthalate (PEN).For example, the carrier has a thickness of between 20 micrometers and 200 micrometers, in particular between 50 micrometers and 100 micrometers. In particular, the polymer layer is applied to the carrier in liquid form, preferably over the entire surface. For example, the liquid polymer layer is applied to the carrier by spin coating or with the aid of a slot die, by doctor blade coating, or by printing. The liquid polymer layer is in particular not fully cured and comprises uncrosslinked monomers. For example, the 2023PF01692 March 12, 2025P2024,0137 WO N -. 3 –The polymer layer comprises an acrylate or an epoxy or is formed from one of these materials. For example, the polymer layer has a thickness of between 2 micrometers and 10 micrometers inclusive, in particular of approximately 4 micrometers. According to a further embodiment of the method, cavities are introduced into the polymer layer, so that a structured main surface of the polymer layer is created. In particular, the cavities are introduced into the polymer layer when the polymer layer is in liquid, at least partially uncured form. After the cavities have been introduced, the polymer layer is in particular cured, for example with ultraviolet radiation or with heat. A printing process, in particular a nanoimprint process, is used, for example, to introduce the cavities.Here, a stamp with the appropriate structure is introduced into the liquid polymer layer, and the liquid polymer layer is cured, for example, with electromagnetic radiation from the ultraviolet spectral range. For example, the electromagnetic radiation is radiated through the stamp onto the polymer layer, so that the monomers of the liquid polymer layer are crosslinked with one another. According to a further embodiment of the method, a seed layer is applied to the structured main surface of the polymer layer, preferably over the entire surface. The seed layer is, in particular, designed to be at least partially absorbent for electromagnetic radiation, in particular for electromagnetic radiation from the visible spectral range and / or from the ultraviolet spectral range and / or from the infrared spectral range. 2023PF01692 March 12, 2025P2024,0137 WO N -. 4 –In other words, the seed layer is preferably dark. The seed layer, for example, comprises a metal or is formed from a metal. For example, the seed layer is applied to the structured main surface of the polymer layer by sputtering, PVD (short for physical vapor deposition), PECVD (short for plasma-enhanced chemical vapor deposition), CVD (short for chemical vapor deposition), or ALD (short for atomic layer deposition). The seed layer is comparatively thin and has, for example, a thickness between 50 and 500 nanometers. The seed layer generally follows the structuring of the underlying material. In other words, one main surface of the seed layer has the same structuring as the main surface of the structured polymer layer.In particular, the seed layer is configured to deposit a metal layer thereon, for example, galvanically or electrolessly. According to a further embodiment of the method, a metal layer is deposited on the seed layer, in particular in a vertical direction. In particular, the metal layer comprises copper or is formed from copper. Furthermore, it is also possible for the metal layer to comprise one of the following materials or to be formed from one of the following materials: nickel, palladium, gold, tin, indium, silver, bismuth, zinc, aluminum. In particular, the metal layer is deposited over the entire surface of the seed layer and thus over the structured main surface of the polymer layer. In this case, the metal layer follows the structure of the underlying structured main surface of the polymer layer. In other words, the metal layer is deposited conformally over the structured main surface of the polymer layer. 2023PF01692 March 12, 2025P2024,0137 WO N -.5 –In particular, a main surface of the metal layer has the same structure as the structured main surface of the polymer layer. For example, the metal layer has a thickness of between 0.5 micrometers and 5 micrometers inclusive. In particular, the metal layer is electroplated onto the seed layer under current flow. In other words, a current flows during the electroplating of the metal layer. For example, during electroplating, metal ions are deposited from a liquid electrolyte onto the surface to be coated by applying an external voltage, whereby an electric current develops in the liquid electrolyte. The deposition of the metal layer can also be carried out electrolessly in a liquid electrolyte, for example, autocatalytically. Electroless deposition generally involves a precipitation reaction of metal ions from the liquid electrolyte onto the surface to be coated.If the deposition is carried out autocatalytically or by substitution, the material to be deposited acts in particular as a catalyst for the precipitation reaction. According to a further embodiment of the method, a solder layer is deposited on or above the metal layer, in particular over the entire surface and in a vertical direction. The electroplating of the solder layer on or above the metal layer can be carried out galvanically under current flow or also electrolessly (eless), for example autocatalytically. The deposition of the solder layer is also particularly preferably carried out conformally, i.e., the solder layer conforms to the 2023PF01692 March 12, 2025P2024,0137 WO N -. 6 –Structuring of the metal layer follows. In other words, a main surface of the solder layer preferably has the same structure as the structured main surface of the polymer layer and the structured main surface of the metal layer. The solder layer preferably has a thickness of at least 1 micrometer. For example, the solder layer has a thickness between 3 micrometers and 5 micrometers inclusive. In particular, the solder layer comprises a solderable material or consists of a solderable material, such as a solderable metal. For example, the solder layer comprises at least one of the following materials or is formed from one of the following materials: tin, indium, tin-bismuth.According to a further embodiment of the method, the solder layer and the metal layer are at least partially removed, creating a flat surface on which regions containing the solder of the solder layer and / or an intermetallic phase of the solder of the solder layer are exposed. In particular, the partial removal occurs uniformly along the vertical direction. In other words, material of the solder layer and the metal layer is removed uniformly in the vertical direction. This can be achieved, for example, by grinding and / or polishing. The intermetallic phase of the solder of the solder layer can form, in particular, with a directly underlying material, for example, the material of the metal layer. According to one embodiment of the method for producing a substrate for a plurality of electronic semiconductor chips, the following steps are performed: 2023PF01692 March 12, 2025P2024,0137 WO N -. 7 –- Providing the flexible carrier to which the polymer layer is applied, - Introducing the cavities into the polymer layer so that a structured main surface of the polymer layer is created, - Applying the seed layer to the structured main surface of the polymer layer, - Depositing the metal layer on the seed layer, - Depositing the solder layer on or above the metal layer, - Partially removing the solder layer and the metal layer so that the flat surface is created, on which areas with the solder of the solder layer and / or with the intermetallic phase of the solder of the solder layer are exposed. With the present method, it is particularly possible to provide very small electrically conductive structures with a solderable surface in a flexible carrier, such as a plastic film, which serve, for example, as electrical connection points for small-sized electronic semiconductor chips.The shape of the cavities determines the shape of the subsequent electrical connection points. The cavities can have the shape not only of electrical connection points, but also of electrical conductor tracks that, for example, electrically connect the electrical connection points externally. According to a further embodiment of the method, the regions with the solder of the solder layer and / or with the intermetallic phase of the solder of the solder layer are part of electrical connection points. It is particularly possible for the regions with the solder of the solder layer and / or with the intermetallic phase of the solder of the solder layer to form a surface of the electrical connection points. 2023PF01692 March 12, 2025P2024,0137 WO N -. 8 –In particular, the surfaces of the electrical connection points are designed to be solderable. According to a further embodiment of the method, areas of the substrate that are not to be provided with electrical connection points are covered with a protective layer before the solder layer is applied. In other words, after the cavities have been created and the metal layer has been applied, but before the solder layer is deposited, a protective layer is applied to the polymer layer in places. For example, the protective layer comprises a resist, in particular a photoresist, or is formed from a resist, in particular a photoresist. For example, the protective layer has a thickness of between 10 micrometers and 100 micrometers inclusive.According to a further embodiment of the method, in particular after the removal of the metal layer and the solder layer, metallic base bodies made of the material of the metal layer are arranged in the cavities, and the metallic base bodies are covered with the solder of the solder layer and / or the intermetallic phase of the solder of the solder layer. The intermetallic phase of the solder of the solder layer is formed in particular with the metal of the base bodies. In particular, the cavities are at least partially filled with the metallic base bodies made of the metal layer. The metallic base body and the solder of the solder layer and / or the intermetallic phase of the solder of the solder layer are in this case encompassed in particular by the electrical connection points.2023PF01692 March 12, 2025P2024,0137 WO N -. 9 –According to a further embodiment of the method, the partial removal of the solder layer and the metal layer takes place in the vertical direction, so that the polymer layer is partially exposed and separates the regions containing the solder of the solder layer and / or the intermetallic phase of the solder of the solder layer from one another in a lateral direction. In other words, after the partial removal of the solder layer and the metal layer, the regions containing the solder of the solder layer are separated from one another in the lateral direction by regions of the polymer layer. For example, the material of the polymer layer surrounds the material of the solder layer and / or the intermetallic phase of the solder of the solder layer in a plan view of the polymer layer. The material of the polymer layer electrically insulates the material of the solder layer and / or the intermetallic phase of the solder of the solder layer from one another.According to a further embodiment of the method, the solder layer is applied directly to the metal layer, and the exposed regions at least partially comprise an intermetallic phase of the solder of the solder layer with the metal of the metal layer. The formation of the intermetallic phase of the solder of the solder layer with the metal of the metal layer occurs, for example, when the solder of the solder layer is soluble in the metal of the metal layer, or vice versa. The exposed regions do not necessarily have to be completely formed by the intermetallic phase. Rather, it is also possible for the exposed regions to be formed partially by the intermetallic phase and partially by the solder of the solder layer. For example, the intermetallic phase comprises or consists of an intermetallic phase of copper and tin.2023PF01692 March 12, 2025P2024,0137 WO N -. 10 –According to a further embodiment of the method, a darkening layer is deposited on the metal layer. In particular, the darkening layer is deposited before the solder layer is deposited. In other words, the darkening layer is preferably deposited directly on the metal layer, and the solder layer directly on the darkening layer. The darkening layer separates the metal layer and the solder layer, in particular from one another. If the darkening layer is deposited densely on the metal layer, in particular no intermetallic phase is formed from the metal of the metal layer and the solder of the solder layer, since the solder of the solder layer does not dissolve in the metal layer. For example, the darkening layer is deposited on the metal layer using an electroless process, such as autocatalytically. For example, the darkening layer has a thickness of between 20 nanometers and 40 nanometers.Particularly preferably, the darkening layer is designed to absorb electromagnetic radiation from the visible spectral range and / or the ultraviolet spectral range and / or the infrared spectral range. The darkening layer serves, in particular, to at least reduce reflection of electromagnetic radiation, in particular from the visible spectral range and / or the ultraviolet spectral range and / or the infrared spectral range, at the metal layer. For example, the darkening layer comprises palladium or is formed from palladium. However, it is also possible, 2023PF01692 March 12, 2025P2024,0137 WO N -. 11 –that the darkening layer comprises another metal, for example platinum, nickel, gold, tin, indium, bismuth and / or zinc, or consists of one of these materials. Furthermore, a metal nitride or a metal oxide, such as copper nitride, copper oxide or palladium oxide, is also suitable for the darkening layer. The darkening layer can also comprise carbon or silicon or consist of one of these materials. According to a further embodiment of the method, a further solder is deposited on or over the exposed areas with the solder of the solder layer and / or with the intermetallic phase of the solder of the solder layer, for example galvanically or electrolessly, for example autocatalytically. For example, the further solder comprises one of the following materials or is formed from one of the following materials: tin, indium, tin-bismuth.Furthermore, all features and configurations disclosed herein in connection with the solder of the solder layer can also be implemented in the additional solder, and vice versa. According to a further embodiment of the method, the additional solder completely covers the exposed regions with the solder of the solder layer and / or with the intermetallic phase of the solder of the solder layer. In other words, a surface of the electrical connection point is formed by the additional solder. Such a surface is also designed to be solderable. In particular, the additional solder does not form a closed layer over the structured polymer surface. Rather, the additional solders are preferably separated from each other by electrically insulating regions of the polymer layer. 2023PF01692 March 12, 2025P2024,0137 WO N -. 12 –According to a further embodiment of the method, the additional solder is melted. After melting, in particular, a surface of the additional solder protrudes vertically beyond the polymer layer. In particular, the solder forms an outwardly curved surface after melting. The method is particularly suitable for producing a substrate for a plurality of electronic semiconductor chips. Consequently, all features and embodiments described in connection with the method can also be implemented in the substrate, and vice versa. According to one embodiment, the substrate comprises a flexible carrier with a polymer layer into which cavities are introduced. In particular, the carrier is transparent. The substrate, like the carrier, is particularly flexible. The polymer layer is cured in this case.In particular, the cavities extend vertically from a main surface of the polymer layer into the polymer layer. Particularly preferably, however, the cavities do not completely penetrate the polymer layer, but rather have bottom surfaces arranged within the polymer layer. For example, a seed layer is applied to the bottom surfaces and side surfaces of the cavities, preferably over the entire surface. According to a further embodiment, the substrate comprises electrical connection points with metallic base bodies that are introduced into the cavities. Particularly preferably, 2023PF01692 March 12, 2025P2024,0137 WO N -. 13 –The metallic base bodies completely fill the cavities, at least in the lateral direction. According to a further embodiment of the substrate, the metallic base bodies are covered with a solder and / or an intermetallic phase of a solder. In particular, the intermetallic phase of the solder is formed with the metal of the base bodies. For example, the solder and / or the intermetallic phase of the solder completely fill the cavities, at least in the lateral direction. For example, the solder is applied in direct contact to the metallic base body. In this case, the substrate in particular has an intermetallic phase of the solder with the metal of the base body. Furthermore, it is also possible for a darkening layer to be applied to the metallic base bodies, as already described. In this case, especially if the darkening layer is dense, the cavities are preferably free of an intermetallic phase of the solder.According to a further embodiment of the substrate, an additional solder is applied on or over the metallic base bodies. It is also possible for the solder to completely cover the metallic base bodies. For example, the additional solder is applied to the solder and / or the intermetallic phase of the solder, which is formed in particular with the metal of the base body. According to a further embodiment, the electrical connection points have, in plan view, an inner region with the solder and / or the intermetallic phase of the solder, which2023PF01692 March 12, 2025P2024,0137 WO N -. 14 –from an outer region with the metal of the base body. This geometry is achieved in particular by depositing the metal layer and the solder layer conformally over the structured main surface of the polymer layer and then removing it. A further method for producing a substrate for a plurality of electronic semiconductor chips is described below. All features already described in connection with the other method and the substrate can also be implemented in this method, and vice versa. According to one embodiment of the method, a plurality of metallic base bodies of electrical connection points are provided, which are arranged on or above a flexible carrier. The carrier is preferably transparent. In particular, the metallic base bodies are arranged separately from one another on or above the flexible carrier.For example, the metallic base bodies are identical or different from one another. In particular, the metallic base bodies comprise the same metal, such as copper, or are formed from the same metal, such as copper. It is also possible for the metallic base bodies to comprise one of the following materials or to consist of one of the following materials: nickel, palladium, gold, tin, indium, silver, bismuth, zinc, aluminum. According to a further embodiment of the method, a solder is deposited on or over the metallic base bodies of the electrical connection points. Preferably, the solder is galvanically deposited on or over the metallic base bodies. 15 –deposited under current flow or without current, for example autocatalytically. The method for producing the substrate for a plurality of electronic semiconductor chips comprises, in particular, the following steps: - providing the plurality of metallic base bodies of the electrical connection points, which are arranged above or on the flexible carrier, and - depositing the solder on or above the metallic base bodies of the electrical connection points. The method is based, in particular, on the idea of ​​applying the solder to the metallic base bodies of the electrical connection points and thus providing a substrate having solderable electrical connection points. In particular, with this substrate, it is possible to dispense with the need to apply solder in a separate step before placing electronic semiconductor chips on the substrate or on the electronic semiconductor chips. This simplifies the method.According to a further embodiment of the method, a polymer layer is applied to the carrier, and the base bodies of the electrical connection points are introduced into cavities in the polymer layer. According to a further embodiment of the method, in order to arrange the metallic base bodies on the carrier, a metal layer is first applied over the entire surface of the carrier. The metal layer is then structured such that the metallic base bodies are created on the carrier. For example, the metal layer is galvanically deposited under 2023PF01692 March 12, 2025P2024,0137 WO N -. 16 –Current flow or electrolessly deposited on the carrier. For this purpose, a seed layer is generally first applied over the entire surface of the carrier, onto which the metal layer is then deposited. Furthermore, it is also possible for the metal layer to be a metal foil laminated to the carrier. In this case, the structuring of the metal layer, so that the metallic base bodies are created on the carrier, is carried out, for example, by etching the metal layer. According to a further embodiment of the method, a darkening layer is arranged between the metallic base bodies and the solder, as already described. In particular, the darkening layer comprises nickel or is formed from nickel. In this case, the darkening layer has a thickness of between 0.3 micrometers and 1 micrometer, inclusive. A further method for producing a substrate for a plurality of electronic semiconductor chips is specified.All features already described in connection with the other method and substrates can also be implemented in this method, and vice versa. According to one embodiment of the method, a metal layer is deposited on a carrier. In particular, the carrier is flexible. According to one embodiment of the method, a solder layer is deposited on or above the metal layer. 2023PF01692 March 12, 2025P2024,0137 WO N -. 17 –According to a further embodiment of the method, the metal layer and the solder layer are structured so that metallic base bodies are formed on the carrier, which are covered with the solder of the solder layer, with side surfaces of the base bodies being free of the solder of the solder layer. In this method, the metal layer and the solder layer are preferably deposited galvanically under current flow. Electroless deposition can advantageously be omitted. A further substrate is specified. All features and embodiments that have already been described in connection with the other substrate or with the two methods can also be implemented with this substrate, and vice versa. According to one embodiment, the substrate comprises a flexible carrier, on or above which electrical connection points with metallic base bodies are arranged. In this case, the metallic base bodies are in particular covered by a solder.The carrier is preferably transparent. Particularly preferably, the substrates described here are an electrical connection carrier to which electronic semiconductor chips can be applied to form an electronic component. In other words, the substrates described here are particularly suitable for being part of an electronic component. Therefore, all features and 2023PF01692 March 12, 2025P2024,0137 WO N -. 18 –Embodiments disclosed herein in connection with the substrates or the methods for producing the substrates can also be implemented in the electronic component described below and in the method for producing the same, and vice versa. According to one embodiment of the method for producing an electronic component, one of the substrates already described is provided. According to one embodiment of the method, a capture layer is applied to electrical connection points of the substrate. The capture layer can, for example, comprise a flux, in particular for soldering. The flux is particularly designed to remove oxides on the electrical connection points and / or electrical contacts of the electronic semiconductor chips. For this purpose, the flux comprises, in particular, an acid, for example, an organic acid.The capture layer may additionally or alternatively also comprise volatile hydrocarbons or a solder paste, or may consist of one of these materials. The capture layer can be applied to the electrical connection points of the substrate, for example, by screen printing, spraying, or dispensing. According to one embodiment of the method, electronic semiconductor chips are applied to the electrical connection points. For example, the electronic semiconductor chips are applied to the substrate using a LIFT method (short for "Laser Induced Forward Transfer method"). In the LIFT method, the semiconductor chips to be transferred are applied to a main surface of an auxiliary carrier. An interface between a 2023PF01692 March 12, 2025P2024,0137 WO N -. 19 –The semiconductor chip and the auxiliary carrier are irradiated with a laser beam, so that the semiconductor chip is transferred to the substrate. The electronic component comprises, in particular, one of the substrates described here and an electronic semiconductor chip. The semiconductor chip is preferably a µLED chip. However, it is also possible for the semiconductor chip to be a mini-LED chip, an IC chip (IC stands for "integrated circuit"), a µIC chip, or a µcomponent. A µcomponent, such as a µIC chip or a µLED chip, is in particular free of a growth substrate for an epitaxial semiconductor layer sequence. The thickness of a µcomponent is in particular not greater than 30 micrometers. In contrast to the µLED chip, the mini-LED chip in particular comprises a growth substrate for an epitaxial semiconductor layer comprising an active radiation-generating zone. The mini-LED chip is therefore particularly thicker than the µLED chip.A µLED chip, for example, is any light-emitting diode (LED) chip with particularly small dimensions. Generally, a µLED chip is not a laser chip that generates electromagnetic laser radiation through stimulated emission. Typically—this is a very important criterion alongside size—the growth substrate is removed from µLED chips, so typical thicknesses of such µLED chips range from 1.5 micrometers to 10 micrometers, for example. 2023PF01692 March 12, 2025P2024,0137 WO N -. 20 –In principle, a µLED chip does not necessarily have to have a rectangular radiation exit surface. For example, a µLED chip has a radiation exit surface where, in a plan view of the active zone, each lateral extension of the radiation exit surface is less than or equal to 100 micrometers or less than or equal to 70 micrometers. For example, for rectangular µLED chips, an edge length of less than or equal to 70 micrometers or less than or equal to 50 micrometers is often cited as a criterion – especially in a plan view of the active zone. Such µLED chips are usually provided on wafers with holding structures that can be removed non-destructively for the µLED chip. Displays are currently the most common application for µLED chips. The µLED chips form pixels or subpixels and emit light of a defined color.Due to their small pixel size and high density with close spacing, the µLED chips are suitable for small monolithic displays for AR applications, especially data glasses. Further applications are also being developed, particularly in data communications or pixelated lighting applications. Various notations for "µLED" can be found in the literature, e.g., micro-LED, µ-LED, uLED, u-LED, or micro light-emitting diode. 2023PF01692 March 12, 2025P2024,0137 WO N -. 21 –The electronic component and the two substrates can be used in particular in the automotive sector, the industrial sector, and the consumer sector. For example, the electronic component and the two substrates can be incorporated into headlights, taillights, brake lights, or indicators. The substrates and the electronic component are also suitable for the interior lighting of a motor vehicle. Furthermore, the substrates and the electronic component can be used in video walls. Further advantageous embodiments and developments of the methods for producing the substrates and the substrates emerge from the exemplary embodiments described below in conjunction with the figures. Figures 1 to 4 show schematic sectional views of stages of a method for producing a substrate for a plurality of electronic semiconductor chips according to a further exemplary embodiment.Figures 5 and 6 show sections of Figures 1 to 4 for a more detailed illustration of the process stages. Figures 7 and 8 show schematic sectional views of stages of a method for producing an electronic component according to a further embodiment. Figures 9 and 10 show schematic representations of an electronic component according to an embodiment.2023PF01692 March 12, 2025P2024,0137 WO N -. 22 –Figure 11 shows a schematic sectional view of an electronic component according to a further exemplary embodiment. Figures 12 and 13 show schematic sectional views of stages of a method for producing a substrate for a plurality of electronic semiconductor chips according to a further exemplary embodiment. Figures 14 to 17 show schematic sectional views of stages of a method for producing an electronic component according to a further exemplary embodiment. Figure 18 shows a schematic sectional view of an electronic component according to a further exemplary embodiment. Figures 19 to 22 show schematic sectional views of stages of a method for producing a substrate for a plurality of electronic semiconductor chips according to a further exemplary embodiment. Figures 23 and 24 show schematic sectional views of electronic components according to further exemplary embodiments.Identical, similar, or functionally identical elements are provided with the same reference numerals in the figures. The figures and the relative sizes of the elements depicted in the figures are not to be considered to scale. Rather, individual elements, in particular 2023PF01692 March 12, 2025P2024,0137 WO N -. 23 –Layer thicknesses may be exaggerated for clarity and / or clarity. In the method according to the exemplary embodiment of Figures 1 to 4, a plastic film 2 is first provided as a flexible, transparent carrier 1. A liquid polymer layer 3 is then applied to the plastic film 2, into which a plurality of cavities 4 are introduced, for example using a nanoimprint process using a stamp. The cavities 4 are partially formed differently from one another. The liquid polymer layer 3 is then cured, so that a solid, structured main surface 5 of the polymer layer 3 is created (Figure 1). A seed layer 6 is applied to the solid, structured main surface 5 of the polymer layer 3, for example by sputtering. The seed layer 6 has, for example, a thickness of approximately 10 nanometers. The seed layer 6 comprises a metal, for example titanium.A metal layer 7 is deposited on the seed layer 6, for example, galvanically under current flow. The deposition of the metal layer 7 is conformal, i.e., a main surface 8 of the metal layer 7 has the same structure as the main surface 5 of the polymer layer 3. In this case, the metal layer 7 comprises copper. A solder layer 9 is deposited on the metal layer 7, in particular autocatalytically without current. This deposition of the solder layer 9 is also conformal, i.e., the solder layer 9 has a main surface 10 with the same structure as 2023PF01692 March 12, 2025P2024,0137 WO N -. 24 –the underlying material (Figure 2). The solder layer 9 comprises tin in this case. Then, the solder layer 9 and the metal layer 7 are evenly removed, for example by grinding, along a vertical direction RV, which is perpendicular to a main extension plane of the carrier 1. In Figure 2, the surface to be achieved is schematically represented by a dashed line. The solder layer 9 and the metal layer 7 are thus removed in the vertical direction R Vremoved so that a flat surface 11 is created, on which areas 12 with the solder 13 of the solder layer 9 and / or with an intermetallic phase 14 of the solder 13 of the solder layer 9 are exposed. In particular, areas 15 of the polymer layer 3 between the cavities 4 are exposed. After grinding off the metal layer 7 and the solder layer 9, the solder layer 9 is partially exposed, so that an intermetallic phase 14 forms between the copper of the metal layer 7 and the tin of the solder layer 9. Between the areas 12 with the intermetallic phase 14, the polymer layer 3 is exposed and separates the areas 14 in a lateral direction R L from each other, with the lateral direction R L on the vertical direction R Vis perpendicular. Furthermore, the exposed areas 14 partially comprise solder 13 of the solder layer 9, which does not form an intermetallic phase 14 (Figure 3). In a further step, another solder is deposited on the exposed areas, for example, also galvanically or electrolessly. The additional solder covers the intermetallic phase of the solder and the underlying 2023PF01692 March 12, 2025P2024,0137 WO N - 25 –Metal layer completely (Figure 4). For example, the additional solder contains tin or is made of tin. Figure 4 shows the finished substrate 16 produced using the process. The substrate 16 has a flexible, transparent film 2 as carrier 1, onto which a polymer layer 3 is applied. Metallic base bodies 17 made of copper, which are covered by an intermetallic phase 14 of tin and copper, are introduced into the cavities 4 in the polymer layer 3. A further solder 18 is applied to the intermetallic phase 14 of tin and copper. The metallic base bodies 17, the intermetallic phase 14 of tin and copper, and the additional solder 18 form electrical connection points 19 and conductor tracks 20. The electrical connection points 19 are designed to have electronic semiconductor chips 25 soldered thereto. In the process, additional metallic layers (not shown) can also be arranged between the metal layer 7 and the solder layer 9.For example, a nickel layer can be applied directly to the copper metal layer 7, and another copper layer can be applied to the nickel layer. If further layers are arranged between the metal layer 7 and the solder layer 9, these are preferably also deposited conformally, so that their surfaces follow the structuring of the main surface 5 of the polymer layer 3. During ablation in the vertical direction RV, these layers are also partially removed, so that the polymer layer 5 is exposed in places. The polymer layer 3 is generally no thicker than 5 micrometers (thickness of the polymer layer d1). A lateral dimension dL of the cavities 4 in the lateral direction RL lies 2023PF01692 March 12, 2025P2024,0137 WO N -. 26 –for example, between 2 micrometers and 10 micrometers inclusive. A distance d2 between the cavities 4 is in particular not less than 4 micrometers. A depth tK of the cavities 4 is generally between 1 micrometer and 3.5 micrometers (Figure 5). Figure 6 shows a section of the process stage of Figure 3 in a plan view of the carrier 1. Due to the conformal deposition, the metal of the metal layer 7 forms an outer region 22, which surrounds an inner region 23 containing the solder 13 and / or the intermetallic phase 14 of the solder 13. In the method for producing electronic components according to the embodiment of Figures 7 and 8, a substrate 16 is first provided, as already described with reference to Figure 4. A capture layer 24 is applied to electrical connection points 19 of the substrate 16, for example by dispensing. The capture layer 24 comprises, for example, a flux.Electronic semiconductor chips 25 are then applied to the capture layer 24, for example, using a LIFT process. The electronic semiconductor chips 25 to be transferred are illuminated with laser light, for example, from the ultraviolet spectral range, and accelerated onto the substrate 16. There, they are captured by the flux applied locally to the electrical connection points 19 (Figure 7). 2023PF01692 March 12, 2025P2024,0137 WO N -. 27 –In the present case, radiation-emitting µLED chips 26 are used as electronic semiconductor chips 25. The µLED chip 26 has an epitaxial semiconductor layer sequence 27 with an active zone 28, which generates electromagnetic radiation during operation. A metal mirror 29 is arranged on a rear main surface and on side surfaces of the µLED chip 26, which directs electromagnetic radiation generated in the active zone 28 to a radiation exit surface 30 of the µLED chip 26. Furthermore, two electrical contacts 31 are arranged on the rear main surface, which are intended to electrically connect the µLED chip 26 to the electrical connection points 19 of the substrate 16. A passivation 32 is also applied over the metal mirror 29. A passivation layer 33 is also applied over the entire surface of the radiation exit surface 30 of the µLED chip 26.The electronic semiconductor chips 25 are soldered onto the electrical connection points 19 of the substrate 16 (Figure 8). In particular, the electrical contacts 31 of the µLED chips 26 are soldered onto the electrical connection points 19 of the substrate 16, for example, by heating or using a reflow process. The reflow process can be carried out in a vacuum. It is also possible to achieve the soldering process by thermocompression or to heat the additional solder 18 of the electrical connection points 19 with a laser beam in order to achieve a stable and integral connection between the electronic semiconductor chip 25 and the electrical connection points 19. During soldering, the additional solder 18 is melted so that it forms a 2023PF01692 March 12, 2025P2024,0137 WO N -. 28 –forms a curved surface that protrudes from the polymer layer 3. The electronic component according to the embodiment of Figures 9 and 10 has a carrier 1, for example, a flexible, transparent plastic film 2 comprising PET. A polymer layer 3 is applied to the plastic film 2, which has a plurality of cavities 4. Metallic base bodies 17 of electrical connection points 19 are arranged in the cavities 4. Furthermore, some cavities 4 also have metallic base bodies 17 that form the base of conductor tracks 20. A darkening layer 34, for example made of palladium, is applied to the metallic base bodies 17. A solder 35 is also applied to the darkening layer 34, which completely covers the metallic base bodies 17 (Figure 9). In the present case, a µLED chip 26 is electrically conductively and mechanically stably connected to the solder 35 of the electrical connection points 19.Furthermore, a protective layer 36, in this case a photoresist, is applied to areas of the polymer layer 3 that are free of electrical connection points 19 (Figure 10). In contrast to the electronic embodiment according to Figures 7 and 9, the electronic component according to the embodiment of Figure 11 has electrical connection points 19 and conductor tracks 20 that are free of a darkening layer 34. Therefore, an intermetallic phase 14 made of the metal of the metallic base body 17 and a solder 35 has formed at the electrical connection points 19 and the conductor tracks 20 of the substrate 16 of the electronic component according to Figure 11. The intermetallic phase 14 is surrounded by a further solder 182023PF01692 March 12, 2025P2024,0137 WO N -. 29 –covered, onto which the electrical contacts 31 of the µLED chip 26 are soldered. In the method for producing a substrate 16 according to the embodiment of Figures 12 and 13, the metal layer 7 and the solder layer 9 have different thicknesses than in the embodiment of Figures 1 to 4. In particular, the metal layer 7 is significantly thinner and has, for example, a thickness of approximately 0.5 micrometers. The solder layer 9 has a thickness of approximately 1.5 micrometers in this embodiment. However, no darkening layer 34 was arranged between the metal layer 7 and the solder layer 9, so that an intermetallic phase 14 forms between the metal of the metal layer 7 and the solder 13 of the solder layer 9. A further solder 18 is applied to the intermetallic phase 14. The further solder 18 is melted so that it forms an outwardly curved surface (Figure 13).When the additional solder 18 melts, a new contact angle is created between the additional solder 18 and the surface of the polymer layer 3, resulting in a curvature of the additional solder 18. The surface of the additional solder 18 protrudes in a vertical direction R. V beyond the polymer layer 3. In the method for producing an electronic component according to the embodiment of Figures 14 to 17, a substrate 16 is first provided, which has a flexible carrier 1, to which a polymer layer 3 is applied. The polymer layer 3 has cavities 4 filled with metallic base bodies 17. 2023PF01692 March 12, 2025P2024,0137 WO N - 30 –In this case, a darkening layer 34 is applied to the metallic base bodies 17, to which a solder 35 is applied. Areas of the substrate 16 that are not to be provided with an electronic semiconductor chip 25 are covered with a protective layer 36, such as a photoresist layer (Figure 14). In a next step, a capture layer 24, for example with a flux, is applied locally to the electrical connection points 19, while the rest of the substrate 16 is free of the capture layer 24 (Figure 15). Then, using a LIFT process, for example, an electronic semiconductor chip 25, in this case a µLED chip 26, is applied to the capture layer 24 (Figure 16). Electrical contacts 31 of the electronic semiconductor chip 25 are then mechanically and electrically connected to the electrical connection points 19 of the substrate 16 by soldering (Figure 17).The electronic component according to the embodiment of Figure 18, in contrast to the electronic component according to the embodiment of Figure 17, does not have a protective layer 36. In the method for producing a substrate according to the embodiment of Figures 19 to 22, a flexible carrier 1, for example a plastic film 2, is first provided (Figure 19).2023PF01692 March 12, 2025P2024,0137 WO N -. 31 –In a next step, a metal layer 7 is applied over the entire surface of the carrier 1 (Figure 20). For example, the metal layer 7 is a copper layer. The metal layer 7 is, for example, deposited electroplated onto the carrier 1 or laminated onto the carrier 1 as a metal foil. The metal layer 7 is then structured so that a plurality of metallic base bodies 17 are created on the carrier 1 (Figure 21). For example, the structuring of the metal layer 7 is carried out by etching. The metallic base bodies 17 are then covered with a solder 35 (Figure 22). The electronic component according to the exemplary embodiment of Figure 23 has, for example, a substrate 16, as produced using the method according to Figures 19 to 22. The substrate 16 has a carrier 1, such as a flexible, transparent plastic film 2, onto which metallic base bodies 17 are applied.The metallic base bodies 17 are each completely covered by a solder 35. The metallic base body 17 and the solder 35 form electrical connection points 19 and conductor tracks 20. The electronic component also has a µLED chip 26 applied to the electrical connection points 19. Furthermore, a copper nitride layer 37 is arranged on one of the metallic base bodies 17, which serves to at least reduce reflections from the underlying copper material. Furthermore, the metallic base body 17 with the copper nitride layer 37 is embedded in a protective layer 36. 2023PF01692 March 12, 2025P2024,0137 WO N -. 32 –The electronic component according to the exemplary embodiment of Figure 24 has a substrate 16 in which, in contrast to the electronic component according to the exemplary embodiment of Figure 23, a darkening layer 24 is applied to the base bodies 17 of the electrical connection points 19. In the present case, the darkening layer 34 has a thickness between 0.3 micrometers and 1 micrometer inclusive. Furthermore, the darkening layer 34 comprises nickel or is formed from nickel. The present application claims priority from German application DE 102024110075.3, the disclosure of which is hereby incorporated by reference. The invention is not limited to the description based on the exemplary embodiments.Rather, the invention encompasses any new feature and any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or combination itself is not explicitly stated in the patent claims or embodiments.

[0002] 2023PF01692 12 March 2025P2024,0137 WO N - 33 –List of reference symbols 1 transparent carrier 2 plastic film 3 polymer layer 4 cavity 5 structured main surface of the polymer layer 6 seed layer 7 metal layer 8 main surface of the metal layer 9 solder layer 10 main surface of the solder layer 11 flat surface 12 region with the solder of the solder layer and / or with an intermetallic phase of the solder of the solder layer 13 solder of the solder layer 14 intermetallic phase of the solder of the solder layer 15 region of the polymer layer 16 substrate 17 metallic base body 18 further solder 19 electrical connection point 20 conductor track 22 outer region 23 inner region 24 trap layer 25 electronic semiconductor chip 26 µLED chip 27 epitaxial semiconductor layer sequence 28 active zone 29 metal mirror 30 radiation exit surface 31 electrical contact 2023PF01692 March 12, 2025 P2024,0137 WO N - 34 – 32 Passivation 33 Passivation layer 34 Darkening layer 35 Solder 36 Protective layer 37 Copper nitride layer R V vertical direction R Llateral direction d1Thickness of the polymer layer d L lateral dimension of the cavity d2distance between the cavities t K Depth of the cavities

Claims

2023PF01692 12 March 2025P2024,0137 WO N - 35 –Patent claims:

1. A method for producing a substrate (16) for a plurality of electronic semiconductor chips (25), comprising the following steps: - providing a flexible carrier (1) onto which a polymer layer (3) is applied, - introducing cavities (4) into the polymer layer (3) to form a structured main surface (5) of the polymer layer (3), - applying a seed layer (6) to the structured main surface (5) of the polymer layer (3), - depositing a metal layer (7) on the seed layer (6), - depositing a solder layer (9) on or above the metal layer (7), - partially removing the solder layer (9) and the metal layer (7) to form a planar surface (11) on which regions (12) containing the solder (13) of the solder layer (7) and / or containing an intermetallic phase (14) of the solder (13) of the solder layer (9) are exposed.2.Method according to the preceding claim, wherein the regions (12) with the solder (13) of the solder layer (9) and / or with the intermetallic phase (14) of the solder (13) of the solder layer (9) are part of electrical connection points (19).

3. Method according to the preceding claim, wherein regions (15) of the polymer layer (13) that are not to be provided with electrical connection points (19) are covered with a protective layer (36) before the application of the solder layer (9).2023PF01692 March 12, 2025P2024,0137 WO N -. 36 –4. Method according to one of the preceding claims, wherein - metallic base bodies (17) comprising the material of the metal layer (7) are arranged in the cavities (4), and - the metallic base bodies (17) are covered with the solder (13) of the solder layer (9) and / or an intermetallic phase (14) of the metal of the base body (17) and the solder (13) of the solder layer (9).

5. Method according to one of the preceding claims, wherein the partial removal of the solder layer (9) and the metal layer (7) in a vertical direction (R V ) so that the polymer layer (3) is partially exposed and the areas (12) are connected to the solder (13) of the solder layer (9) and / or the intermetallic phase (14) of the solder (13) of the solder layer (9) in a lateral direction (R L) from each other.

6. Method according to one of the preceding claims, wherein - the solder layer (9) is applied directly to the metal layer (7), and - the exposed regions (12) at least partially comprise an intermetallic phase (14) of the solder (13) of the solder layer (9) with the metal of the metal layer (7).

7. Method according to one of claims 1 to 5, wherein a darkening layer (34) is deposited on the metal layer (7).

8. Method according to one of the preceding claims, wherein a further solder (18) is deposited on or over the exposed regions (12) with the solder (13) of the solder layer (9) and / or with the intermetallic phase (14) of the solder (13) of the solder layer (9). 2023PF01692 March 12, 2025P2024,0137 WO N - 37 –9. The method according to the preceding claim, wherein the additional solder (18) completely covers the exposed regions (12) with the solder (13) of the solder layer (7) and / or with the intermetallic phase (14) of the solder (13) of the solder layer (7).

10. The method according to one of claims 8 or 9, wherein the additional solder (18) is melted.

11. A substrate (16) for a plurality of electronic semiconductor chips (25) produced using a method according to one of the preceding claims, comprising: - a flexible carrier (1) with a polymer layer (3) into which cavities (4) are introduced, - electrical connection points (19) with metallic base bodies (17) that are introduced into the cavities (4), wherein - the metallic base bodies (17) are covered with a solder (35) and / or an intermetallic phase (14) of a solder (35). 12.Substrate according to the preceding claim, wherein the electrical connection points (19) have, in plan view, an inner region (23) with the solder (35) and / or the intermetallic phase (14), which is surrounded by an outer region (22) with the metal of the base body (17).2023PF01692 March 12, 2025P2024,0137 WO N -. 38 –13. The method according to the preceding claim, wherein - a polymer layer (3) is applied to the carrier (1), and - the metallic base bodies (17) of the electrical connection points (19) are introduced into cavities (4) in the polymer layer (3).

14. The method according to one of the preceding claims, wherein the metallic base bodies (17) are arranged on the carrier (1) using the following steps: - applying a metal layer (7) over the entire surface of the carrier (1), and - structuring the metal layer (7) so that the metallic base bodies (17) are formed on the carrier (1).

15. The method according to one of claims 13 to 14, wherein a darkening layer (34) is arranged between the metallic base bodies (17) and the solder (35).Method for producing a substrate (16) for a plurality of electronic semiconductor chips (25), comprising the following steps:- depositing a metal layer (7) on a carrier (1),- depositing a solder layer (9) on or above the metal layer (9),- structuring the metal layer (7) and the solder layer (9), so that metallic base bodies (17) are formed on the carrier (1) which are covered with the solder (13) of the solder layer (9), wherein side surfaces of the base bodies (17) are free of the solder (13) of the solder layer.2023PF01692 March 12, 2025P2024,0137 WO N -. 39 –17. A substrate for a plurality of electronic semiconductor chips produced by a method according to the preceding claim, comprising: - a flexible carrier (1) on or above which electrical connection points (19) with metallic base bodies (17) are arranged, wherein - the metallic base bodies (17) are at least partially covered by a solder (35).

18. A method for producing an electronic component, comprising the following steps: - providing a substrate (16) according to one of claims 11, 12, or 17, - applying a capture layer (24) to electrical connection points (19) of the substrate (16), - applying electronic semiconductor chips (25) to the electrical connection points (19) of the substrate (16).

19. An electronic component comprising:- a substrate (16) according to any one of claims 11, 12 or 17,and- a µLED chip, a mini-LED chip, an IC chip, a µIC chip or a µcomponent (25).

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