DML driver

Abstract

A DML driver (2e) comprises: a transistor (Q1), the base of which is connected to a signal input terminal (S0) and the emitter of which is connected to ground; a transistor (Q2) which is cascode-connected between the anode of a laser diode (1) and the collector of the transistor (Q1), and the base of which is connected to a bias voltage (Vcas); and a resistor (R2), one end of which is connected to a power supply voltage (VCC) and the other end of which is connected to the anode of the laser diode (1).

Description

DML Driver

[0001] The present invention relates to a technique for driving a directly modulated laser (DML), and more particularly to a shunt-type DML driver.

[0002] FIG. 15 shows the configuration of a transmission front end using a conventional DML driver (see Patent Document 1). The DML driver 2 includes an NPN transistor Q １ and resistance R ０ , R ２ , R １０ The DML driver 2 is configured as a shunt type LD driver that is connected in parallel to the laser diode (LD) 1. The shunt type LD driver receives an input signal D ０ The current I to LD1 is ＬＤ The shunt-type LD driver is a driver that modulates the LD1 by modulating the LD1. Because the shunt-type LD driver has a high output resistance, it is either monolithically integrated with the LD1 or mounted in the same package as the LD1. This eliminates the need for impedance matching with the LD1, and allows for high-speed operation with low power consumption.

[0003] However, in the transmission front-end configuration using the driver shown in FIG. １ Resistor R connected in series to the collector of １０ This causes a problem of degradation of the EO (Electrical-to-Optical) band of the transmission front end.

[0004] Japanese Patent Application Laid-Open No. 2018-186112

[0005] The present invention has been made to solve the above-mentioned problems, and has an object to improve the EO bandwidth of a transmission front end.

[0006] The DML driver of the present invention is characterized by comprising: a first transistor having a base or gate connected to a signal input terminal to which a signal is input from outside and an emitter or source connected to ground; a second transistor having a base or gate connected to a bias voltage and cascode-connected between an anode of a laser diode and a collector or drain of the first transistor; and a first resistor having one end connected to a power supply voltage and the other end connected to the anode of the laser diode.

[0007] According to the present invention, the EO bandwidth of a transmit front end consisting of a DML driver and a laser diode can be improved by using a second transistor cascoded between the anode of the laser diode and the collector or drain of the first transistor instead of a conventional resistor.

[0008] FIG. 1 is a circuit diagram showing the configuration of a transmission front-end using a DML driver according to a first embodiment of the present invention. FIG. 2 is a diagram showing the results of simulating the EO response characteristics of the transmission front-end for a conventional configuration and the first embodiment of the present invention. FIGS. 3A and 3B are diagrams showing the optical output waveforms of the LD for the conventional configuration and the first embodiment of the present invention. FIG. 4 is a circuit diagram showing the configuration of a transmission front-end using a DML driver according to a second embodiment of the present invention. FIG. 5 is a circuit diagram showing the configuration of a transmission front-end using a DML driver according to a third embodiment of the present invention. FIG. 6 is a circuit diagram showing another configuration of a transmission front-end using a DML driver according to the third embodiment of the present invention. FIG. 7 is a circuit diagram showing the configuration of a transmission front-end using a DML driver according to a fourth embodiment of the present invention. FIG. 8 is a circuit diagram showing another configuration of a transmission front-end using a DML driver according to the fourth embodiment of the present invention. FIG. 9 is a circuit diagram showing the configuration of a transmission front-end using a DML driver according to a fifth embodiment of the present invention. FIG. 10 is a circuit diagram showing another configuration of a transmission front-end using a DML driver according to the fifth embodiment of the present invention. Fig. 11 is a circuit diagram showing the configuration of a transmitting front end using a DML driver according to a sixth embodiment of the present invention. Fig. 12 is a circuit diagram showing another configuration of a transmitting front end using a DML driver according to the sixth embodiment of the present invention. Fig. 13 is a circuit diagram showing the configuration of a transmitting front end using a DML driver according to a seventh embodiment of the present invention. Fig. 14 is a circuit diagram showing another configuration of a transmitting front end using a DML driver according to the seventh embodiment of the present invention. Fig. 15 is a circuit diagram showing the configuration of a transmitting front end using a conventional DML driver.

[0009] [First embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 shows the configuration of a transmission front end using a DML driver according to a first embodiment of the present invention. A DML driver 2a has a base which receives a signal D ０ The signal input terminal S ０ NPN transistor Q connected to １ and the base is biased by V ｃａｓand the emitter is connected to the transistor Q １ and an NPN transistor Q whose collector is connected to the anode of LD1. ２ and one end of the transistor Q １ The other end of the resistor R is connected to the emitter of ０ and one end is the power supply voltage V ＣＣ (V ＣＣ >V ｃａｓ ) and the other end of resistor R ２ It is equipped with the following.

[0010] Input signal D ０ takes the value of "1" (high level) or "0" (low level). ０ and a resistor R connected between ｍ is a resistor for input matching, and in the case of a 50Ω input transmission line, R ｍ In Figure 1, I ＬＤ is the current flowing through LD1, I ０ is the transistor Q １ , Q ２ The current flowing through ＣＣ is the power supply voltage V ＣＣ This is the current supplied from the power supply circuit that generates

[0011] In this embodiment, the resistor R １０ Instead, the anode of LD1 and the transistor Q １ A transistor Q is cascode-connected between the collector of ２ Resistance R １０ The role of the transistor Q １ The purpose is to prevent breakdown of the resistor R １０ Instead of transistor Q ２ Even when using a transistor Q １ It is possible to prevent breakdown of the capacitor.

[0012] 15, band degradation occurs due to the Miller effect. Therefore, by using a cascode connection configuration as in this embodiment, it is possible to compensate for band degradation due to the Miller effect.

[0013] The effects of this embodiment are shown in Figures 2, 3A, and 3B. Creating an electrical equivalent circuit for the LD 1 and using a rate equation representing the electrical-to-optical conversion of the LD 1 enabled simulation in the optical domain. Figure 2 shows the results of simulations of the EO response characteristics of the transmit front end for a conventional configuration and this embodiment. Reference numeral 100 in Figure 2 indicates the EO response characteristics of the conventional configuration shown in Figure 15, while reference numeral 101 indicates the EO response characteristics of this embodiment. Comparing the conventional configuration and this embodiment with the focus on the -3 dB frequency, which is an index of the EO bandwidth, it can be seen that the EO bandwidth is improved by approximately 1 GHz when the DML driver 2a of this embodiment is used. The transistor and LD models used in the simulation were capable of high-speed operation. It is estimated that the improvement achieved by the cascode connection configuration would be more pronounced if low-speed transistors and LDs were used.

[0014] FIG. 3A shows the results of a simulation of the optical output waveform of the LD 1 for a conventional configuration, and FIG. 3B shows the results of a simulation of the optical output waveform of the LD 1 for the configuration of this embodiment. The examples in FIGS. 3A and 3B show the case where NRZ (Non Return to Zero) signal light with a signal speed of 28 Gbps is output from the LD 1. The amplitude scale on the vertical axis is 200 μW / div, and the time scale on the horizontal axis is 10 ps / div. In the conventional configuration, the horizontal axis magnitude of the eye opening ΔX is 31.51 ps, and the vertical axis magnitude ΔY is 0.809 mW. In the configuration of this embodiment, ΔX is 31.93 ps, and ΔY is 0.824 mW. As can be seen, the eye opening magnitudes ΔX and ΔY are improved in this embodiment compared to the conventional configuration. As with the results in FIG. 2, it is expected that the improvement effect of the cascode-connected configuration will be more pronounced when using low-speed transistors and LDs.

[0015] 4 shows the configuration of a transmission front end using a DML driver according to a second embodiment of the present invention. A DML driver 2b of this embodiment differs from the configuration of the DML driver 2a of the first embodiment in that it has a resistor R ２ and a capacitor C connected in parallel ２The capacitor C ２ By adding the above, in this embodiment, it is possible to suppress overshoot of the optical output waveform due to the relaxation oscillation frequency of the LD 1.

[0016] 5 shows the configuration of a transmission front end using a DML driver according to a third embodiment of the present invention. A DML driver 2c of this embodiment differs from the configuration of the DML driver 2a of the first embodiment in that it has a resistor R ０ and a capacitor C connected in parallel ０ The capacitor C ０ By adding the above, in this embodiment, it is possible to improve the band of the DML driver 2c in the high frequency range. This embodiment may be applied to the second embodiment. The configuration of the DML driver 2d in this case is shown in FIG.

[0017] [Fourth Example] In a driver that does not guarantee linearity, such as the DML driver 2e shown in FIG. 7, the resistor R ０ and transistor Q １ The emitter of the DML driver 2f may be connected to the ground. This embodiment may be applied to the second embodiment. The configuration of the DML driver 2f in this case is shown in FIG.

[0018] 9 shows the configuration of a PAM4 (4-level Pulse Amplitude Modulation) transmission front end using a DML driver according to a fifth embodiment of the present invention. A DML driver 2g of this embodiment has a base connected to a signal input terminal S on the LSB (Least Significant Bit) side. ０ n (n is an integer of 2 or more) NPN transistors Q １ -1 to Q １ -n and the base is biased by V ｃａｓ０ and the emitter is connected to the transistor Q １ -1 to Q １ -n, and the collectors of n NPN transistors Q are connected to the anodes of LD1. ２ -1 to Q ２ -n and one end of the transistor Q １ -1 to Q１ -n resistors R connected to the emitters of the n ０ -1 to R ０ -n, and the base is the MSB (Most Significant Bit) side signal input terminal S １ 2n NPN transistors Q connected to ３ -1 to Q ３ -2n and the base is biased by V ｃａｓ１ and the emitter is connected to the transistor Q ３ -1 to Q ３ 2n NPN transistors Q connected to the collectors of LD1 and LD2, and the collectors of LD1 and LD2 are connected to the anodes of LD1 and LD2. ４ -1 to Q ４ -2n and one end of the transistor Q ３ -1 to Q ３ -2n resistors R connected to the emitter of １ -1 to R １ -2n and one end is power supply voltage V ＣＣ (V ＣＣ >V ｃａｓ０ , V ｃａｓ１ ) and the other end of resistor R ２ It is equipped with the following.

[0019] Input signal D ０ , D １ The signal input terminal S ０ and ground, and signal input terminal S １ and a resistor R connected between ｍ is a resistor for input matching, and in the case of a 50Ω input transmission line, R ｍ becomes 50 Ω.

[0020] In this embodiment, the input signal D ０ Transistor Q on the １ -1 to Q １ -n, Q ２ -1 to Q ２ When the number of parallel inputs of -n is n, the MSB of the input signal D １ Transistor Q on the ３ -1 to Q３ −2n, Q ４ -1 to Q ４ By changing the number of parallel connections from -2n to 2n, it is possible to generate a PAM4 optical output waveform.

[0021] For example, the input signal D ０ , D １ If both are "1", transistor Q １ -1 to Q １ -n, Q ２ -1 to Q ２ -n, Q ３ -1 to Q ３ −2n, Q ４ -1 to Q ４ Current I flowing through -2n ０ is the maximum value I ０ｍａｘ and the current I flowing through LD1 ＬＤ is the minimum value I ＬＤｍｉｎ Therefore, the power supply voltage V ＣＣ The current I supplied from the power supply circuit that generates ＣＣ is I ０ｍａｘ +I ＬＤｍｉｎ On the other hand, the input signal D ０ , D １ If both are "0", the current I ０ becomes 0, and the current I ＬＤ is the maximum value I ＬＤｍａｘ Therefore, the current I ＣＣ is I ＬＤｍａｘ This becomes:

[0022] In the configuration of FIG. 9, transistor Q ２ -1 to Q ２ -n, Q ４ -1 to Q ４ The bias voltage to -2n is D ０ Side and D １ The bias voltage V ｃａｓ０ and V ｃａｓ１ may be shared to form a single power supply.

[0023] Also, as in the DML driver 2h shown in FIG. ０ -1 to R ０ -n, R １ -1 to R １ Eliminate -2n and transistor Q １ -1 to Q１ -n, Q ３ -1 to Q ３ The emitter of −2n may be connected to ground.

[0024] 11 shows the configuration of a PAM4 transmission front end using a DML driver according to a sixth embodiment of the present invention. A DML driver 2i of this embodiment differs from the configuration of the DML driver 2g of the fifth embodiment in that it has a resistor R ２ and a capacitor C connected in parallel ２ The capacitor C ２ By adding the above, in this embodiment, it is possible to suppress overshoot of the optical output waveform due to the relaxation oscillation frequency of the LD 1.

[0025] As shown in FIG. 12, the resistor R ０ -1 to R ０ -n, R １ -1 to R １ Eliminate -2n and transistor Q １ -1 to Q １ -n, Q ３ -1 to Q ３ The emitter of −2n may be connected to ground.

[0026] 13 shows the configuration of a PAM4 transmission front end using a DML driver according to a seventh embodiment of the present invention. A DML driver 2k of this embodiment differs from the configuration of the DML driver 2g of the fifth embodiment in that it has a resistor R ０ -1 to R ０ -n and a capacitor C connected in parallel ０ -1 to C ０ -n and resistance R １ -1 to R １ -2n and a capacitor C １ -1 to C １ -2n is added. ０ -1 to C ０ -n, C １ -1 to C １By adding -2n, in this embodiment, it is possible to improve the band of the DML driver 2k in the high frequency range. This embodiment may be applied to the sixth embodiment. The configuration of the DML driver 2l in this case is shown in FIG.

[0027] In the first to seventh embodiments, the transistor Q １ , Q １ -1 to Q １ -n, Q ３ -1 to Q ３ Transistor Q cascode-connected to -2n ２ , Q ２ -1 to Q ２ -n, Q ４ -1 to Q ４ -2n is used as one stage, but when using a transistor with low voltage resistance, the transistor Q １ , Q １ -1 to Q １ -n, Q ３ -1 to Q ３ The transistors cascoded to -2n may be two or more stages. The cascode connection of the transistors is achieved by connecting the emitter to the collector of the lower stage transistor and the collector to the emitter of the upper stage transistor or the anode of LD1.

[0028] In the first to seventh embodiments, the transistor Q １ , Q １ -1 to Q １ -n, Q ２ , Q ２ -1 to Q ２ -n, Q ３ -1 to Q ３ −2n, Q ４ -1 to Q ４ Although an example using a bipolar transistor as -2n is shown, a FET (Field Effect Transistor) may also be used. When using a FET, the base may be replaced with a gate, the collector with a drain, and the emitter with a source in the explanations of the first to seventh embodiments.

[0029] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes.

[0030] (Supplementary Note 1) The DML driver of the present invention comprises a first transistor having a base or gate connected to a signal input terminal to which a signal is input from outside and an emitter or source connected to ground, a second transistor having a base or gate connected to a bias voltage and cascode-connected between an anode of a laser diode and a collector or drain of the first transistor, and a first resistor having one end connected to a power supply voltage and the other end connected to the anode of the laser diode.

[0031] (Supplementary Note 2) The DML driver according to Supplementary Note 1 further comprises a second resistor inserted between the emitter or source of the first transistor and ground.

[0032] (Supplementary Note 3) The DML driver according to Supplementary Note 1 or 2 further includes a first capacitor connected in parallel with the first resistor.

[0033] (Supplementary Note 4) The DML driver according to Supplementary Note 2 further includes a second capacitor connected in parallel with the second resistor.

[0034] (Appendix 5) In the DML driver described in Appendix 1, n pieces (n is an integer of 2 or more) of the first and second transistors are arranged in parallel on the side of the first signal input terminal to which the first signal is input, and 2n pieces are arranged in parallel on the side of the second signal input terminal to which the second signal is input.

[0035] (Supplementary Note 6) The DML driver described in Supplementary Note 5 further includes n second resistors inserted between the emitters or sources of the n first transistors on the first signal input terminal side and ground, and 2n third resistors inserted between the emitters or sources of the 2n first transistors on the second signal input terminal side and ground.

[0036] (Supplementary Note 7) The DML driver according to Supplementary Note 5 or 6 further includes a first capacitor connected in parallel with the first resistor.

[0037] (Supplementary Note 8) The DML driver described in Supplementary Note 6 further includes n second capacitors connected in parallel with the n second resistors, and 2n third capacitors connected in parallel with the 2n third resistors.

[0038] The present invention can be applied to a technique for directly modulating the optical output of an LD.

[0039] 1...LD, 2a to 2l...DML driver, Q １ , Q １ -1 to Q １ -n, Q ２ , Q ２ -1 to Q ２ -n, Q ３ -1 to Q ３ −2n, Q ４ -1 to Q ４ -2n...NPN transistor, R ０ , R ０ -1 to R ０ -n, R １ -1 to R １ −2n, R ２ , R ｍ ...Resistance, C ０ , C ０ -1 to C ０ -n, C １ -1 to C １ -2n, C ２ ...Capacitor.

Claims

1. A DML driver comprising: a first transistor whose base or gate is connected to a signal input terminal to which an external signal is input and whose emitter or source is connected to ground; a second transistor whose base or gate is connected to a bias voltage and which is cascode-connected between the anode of a laser diode and the collector or drain of the first transistor; and a first resistor whose one end is connected to a power supply voltage and whose other end is connected to the anode of the laser diode.

2. A DML driver according to claim 1, further comprising a second resistor inserted between the emitter or source of said first transistor and ground.

3. A DML driver according to claim 1 or 2, further comprising a first capacitor connected in parallel with said first resistor.

4. The DML driver according to claim 2, further comprising a second capacitor connected in parallel with said second resistor.

5. A DML driver according to claim 1, wherein n pieces (n is an integer of 2 or more) of the first and second transistors are arranged in parallel on the side of a first signal input terminal to which a first signal is input, and 2n pieces are arranged in parallel on the side of a second signal input terminal to which a second signal is input.

6. A DML driver according to claim 5, further comprising: n second resistors inserted between the emitters or sources of the n first transistors on the side of the first signal input terminal and ground; and 2n third resistors inserted between the emitters or sources of the 2n first transistors on the side of the second signal input terminal and ground.

7. A DML driver according to claim 5 or 6, further comprising a first capacitor connected in parallel with said first resistor.

8. A DML driver according to claim 6, further comprising: n second capacitors connected in parallel with said n second resistors; and 2n third capacitors connected in parallel with said 2n third resistors.

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