Printed wiring board

Abstract

A printed wiring board according to the present invention comprises a base film and a layered part. The base film has a principal surface. The layered part is provided on the principal surface. The direction that is parallel to the principal surface and perpendicular to the linear extension direction of the layered part is a first direction. Crystal grains that are oriented to the {100} plane as seen from the first direction in a cross-section of the layered part as assessed by electron backscatter diffraction are first crystal grains. The crystal grains oriented to the {100} plane are crystal grains that are oriented to planes within a measurement tolerance of 15° from the {100} plane. Crystal grains that are not the crystal grains oriented to the {100} plane are second crystal grains, and the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is no more than 0.2.

Description

printed wiring board

[0001] The present disclosure relates to printed wiring boards.

[0002] International Publication No. 2019 / 208077 (Patent Document 1) discloses a printed wiring board including a base film and an electroless plating layer.

[0003] International Publication No. 2019 / 208077

[0004] The printed wiring board according to the present disclosure comprises a base film and a laminate portion. The base film has a main surface. The laminate portion is disposed on the main surface. A direction that is horizontal to the main surface and perpendicular to the linear extension direction of the laminate portion is defined as a first direction. When a cross section of the laminate portion is measured by electron backscatter diffraction, crystal grains oriented in the {100} plane as viewed from the first direction are defined as first crystal grains. Crystal grains oriented in the {100} plane are crystal grains oriented in a plane within a measurement tolerance of 15° from the {100} plane. When crystal grains other than the crystal grains oriented in the {100} plane are defined as second crystal grains, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.2 or less.

[0005] FIG. 1 is a cross-sectional view showing the configuration of a substrate for printed wiring boards according to the first embodiment. FIG. 2 is a flowchart showing a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 3 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 4 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 5 is a cross-sectional view showing a configuration of a modified example of a substrate for printed wiring boards according to the first embodiment. FIG. 6 is a flowchart showing a method for manufacturing a modified example of a substrate for printed wiring boards according to the first embodiment. FIG. 7 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 8 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 9 is a schematic configuration diagram of a plating apparatus. FIG. 10 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 11 is a cross-sectional view showing the configuration of a printed wiring board according to the second embodiment. FIG. 12 is a flowchart showing a method for manufacturing a printed wiring board according to the second embodiment. FIG. 13 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment. FIG. 14 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment. FIG. 15 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment.

[0006] [Problem to be Solved by the Present Disclosure] There is a demand for finer circuits on printed wiring boards. In a semi-additive process suitable for forming finer circuits, a circuit composed of a laminated portion including an underlayer and an electrolytic plated layer is formed on the surface of a base film on which an underlayer has been formed by undergoing the steps of resist pattern formation, electrolytic plating, resist removal, and underlayer etching. In the step of etching this underlayer, the laminated portion may be excessively etched, resulting in a circuit width that is narrower than the designed value.

[0007] An object of the present disclosure is to provide a printed wiring board that is free from circuit narrowing. [Advantages of the Present Disclosure] According to the present disclosure, it is possible to provide a printed wiring board that is free from circuit narrowing.

[0008] [Outline of the embodiment] First, the embodiments of the present disclosure will be listed and described.

[0009] (1) A printed wiring board according to the present disclosure includes a base film and a laminate portion. The base film has a main surface. The laminate portion is disposed on the main surface. A direction that is horizontal to the main surface and perpendicular to the linear extension direction of the laminate portion is defined as a first direction. When a cross section of the laminate portion is measured by electron backscatter diffraction, crystal grains oriented in the {100} plane as viewed from the first direction are defined as first crystal grains. Crystal grains oriented in the {100} plane are crystal grains oriented in a plane within a measurement tolerance of 15° from the {100} plane. When crystal grains other than the crystal grains oriented in the {100} plane are defined as second crystal grains, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.2 or less.

[0010] (2) In the printed wiring board according to (1) above, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains may be 0.15 or less.

[0011] (3) In the printed wiring board according to (1) or (2), the laminated portion may include adjacent first and second laminated portions. The widths of the first and second laminated portions may be 15 μm or less. The shortest distance in the first direction from the first laminated portion to the second laminated portion may be 15 μm or less.

[0012] (4) According to the printed wiring board of (3), the width of each of the first laminated portion and the second laminated portion may be 10 μm or less. The shortest distance from the first laminated portion to the second laminated portion in the first direction may be 10 μm or less.

[0013] (5) In the printed wiring board of (3) or (4), the width of each of the first laminated portion and the second laminated portion may be 2 μm or more. The shortest distance from the first laminated portion to the second laminated portion in the first direction may be 2 μm or more.

[0014] (6) In the printed wiring board according to any one of (1) to (5), the laminated portion may include an underlayer and an electroplated layer. The underlayer may be in contact with the main surface. The electroplated layer may be in contact with the underlayer.

[0015] [Details of the embodiment] The details of the embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated. The substrate for a printed wiring board and the printed wiring board according to the embodiment are referred to as a substrate for a printed wiring board 100 (100a, 100b) and a printed wiring board 200, respectively.

[0016] (Configuration of Substrate for Printed Wiring Board) The configuration of the substrate for printed wiring board 100a will be described below.

[0017] 1 is a cross-sectional view of a substrate 100a for a printed wiring board. As shown in FIG. 1, the substrate 100a for a printed wiring board includes a base film 1 and an underlayer 2.

[0018] The base film 1 has a main surface 1s. The base film 1 is made of a flexible insulating material, such as polyimide.

[0019] The base layer 2 is in contact with the principal surface 1s. The base layer 2 is composed of either a sputtered copper layer or a nano-copper sintered body layer. In the case of a nano-copper sintered body layer, the nano-copper sintered body layer is formed from a plurality of sintered copper particles. Therefore, the nano-copper sintered body layer is porous. The average particle size of the copper particles contained in the nano-copper sintered body layer may be 1 nm or more or 30 nm or more. The average particle size of the copper particles contained in the nano-copper sintered body layer may be 100 nm or less or 500 nm or less. In other words, the copper particles contained in the nano-copper sintered body layer may be nano-copper particles. The average particle size of the copper particles contained in the paste used to form the nano-copper sintered body layer is measured using a particle size distribution measurement device (e.g., a Microtrac particle size distribution meter UPA-150EX manufactured by Nikkiso Co., Ltd.). As described below, an electroless copper plating layer (not shown) may be formed on the principal surface 1s.

[0020] As shown in FIG. 1 , directions parallel to the main surface 1s are defined as a first direction X and a second direction Y. The second direction Y is a direction perpendicular to the first direction X. The direction perpendicular to the first direction X and the second direction Y is defined as a third direction Z. The underlayer 2 has an underlayer surface 2s. The underlayer surface 2s is the surface of the underlayer 2 opposite to the surface in contact with the main surface 1s. The distance H in the third direction Z from the main surface 1s to the underlayer surface 2s (thickness H of the underlayer 2) may be 1 μm or less or 0.5 μm or less.

[0021] (Method for manufacturing substrate for printed wiring board) A method for manufacturing the substrate for printed wiring board 100a will be described below. Fig. 2 is a flowchart illustrating the method for manufacturing the substrate for printed wiring board 100a. As shown in Fig. 2, the method for manufacturing the substrate for printed wiring board 100a includes a step S1a of preparing a base film 1 and a step S2a of forming an underlayer 2.

[0022] The step S2a of forming the underlayer is performed after the step S1a of preparing the base film 1.

[0023] 3 is a cross-sectional view illustrating the step S1a of preparing the base film 1. In the step S1a of preparing the base film 1, the base film 1 is prepared as shown in FIG. 3. In the step S1a of preparing the base film 1, the underlayer 2 is not disposed on the main surface 1s of the prepared base film 1.

[0024] Before disposing the underlayer 2, the main surface 1s may be subjected to an alkali treatment and an excimer treatment.

[0025] FIG. 4 is a cross-sectional view illustrating step S2a of forming the underlayer 2. In step S2a of forming the underlayer 2, the underlayer 2 is formed on the main surface 1s as shown in FIG. 4. In this step S2a, first, a paste containing copper particles is applied to the main surface 1s. Second, the solvent contained in the applied paste is dried. Third, the dried paste is fired. As a result, the copper particles contained in the dried paste are sintered to form the underlayer 2. The underlayer 2 may be formed by sputtering. The underlayer 2 may be formed using a plating apparatus 300 described below. After the underlayer 2 is formed using the plating apparatus 300, the printed wiring board substrate 100a is annealed for 1 hour at an annealing temperature of 300°C in an inert gas atmosphere such as nitrogen. As a result, the printed wiring board substrate 100a shown in FIG. 1 is manufactured.

[0026] (Configuration of a Modified Printed Wiring Board Substrate) FIG. 5 is a cross-sectional view of a modified printed wiring board substrate 100b according to embodiment 1. FIG. 5 corresponds to FIG. 1. The printed wiring board substrate 100b shown in FIG. 5 has a configuration similar to that of the printed wiring board substrate 100a shown in FIG. 1, but differs in that the base layer 2 includes an electroless copper plating layer. Specifically, the base layer 2 includes a first base layer 2a and a second base layer 2b. The first base layer 2a is specifically composed of either a sputtered copper layer or a nano-copper sintered body layer. The first base layer 2a has an intermediate base layer surface s. In the first base layer 2a, the intermediate base layer surface s is the surface opposite the main surface 1s. The second base layer 2b is in contact with the first base layer 2a at the intermediate base layer surface s. The second base layer 2b is, for example, a copper layer formed by electroless plating. In this manner, the base layer 2 is formed.

[0027] The distance Ha in the third direction Z from the main surface 1s to the intermediate underlayer surface s (the thickness Ha of the first underlayer 2a) may be 0.5 μm or less, or 0.1 μm or less.

[0028] The underlayer 2 does not necessarily have to include the first underlayer 2a. Specifically, the underlayer 2 may be composed of only the second underlayer 2b made of an electroless copper plating layer.

[0029] (Method for Manufacturing a Substrate for a Printed Wiring Board) A method for manufacturing the substrate for a printed wiring board 100b will be described below.

[0030] Fig. 6 is a flowchart illustrating a method for manufacturing the substrate 100b for printed wiring boards. Fig. 6 corresponds to Fig. 2. As shown in Fig. 6, the method for manufacturing the substrate 100b for printed wiring boards includes a step S1b of preparing a base film 1, a step S2b of forming a first underlayer 2a, a step S3b of forming a second underlayer 2b, and a step S4b of annealing the substrate 100b for printed wiring boards.

[0031] Step S2b of forming the first underlayer 2a is performed after step S1b of preparing the base film 1. Step S3b of forming the second underlayer 2b is performed after step S2b of forming the first underlayer 2a. Step S4b of annealing the printed wiring board substrate 100b is performed after step S3b of forming the second underlayer 2b.

[0032] 7 is a cross-sectional view illustrating step S1b of preparing a base film 1. In step S1b of preparing a base film 1, the base film 1 is prepared as shown in FIG. The base film 1 prepared in step S1b of preparing a base film 1 does not have an underlayer 2 disposed on the main surface 1s. Before disposing the underlayer 2, the main surface 1s is subjected to an alkali treatment and an excimer treatment.

[0033] 8 is a cross-sectional view illustrating step S2b of forming the first underlayer 2a. In step S2b of forming the first underlayer 2a, as shown in FIG. 8, the first underlayer 2a is formed on the main surface 1s. In this step S2b, first, a paste containing copper particles is applied to the main surface 1s. Second, the solvent contained in the applied paste is dried. Third, the dried paste is fired. As a result, the copper particles contained in the dried paste are sintered to each other, and the first underlayer 2a is formed. The first underlayer 2a may be formed by sputtering. Note that step S2b of forming the first underlayer 2a does not necessarily have to be performed.

[0034] The step S3b of forming the second underlayer 2b is performed using a plating apparatus 300. Fig. 9 is a schematic diagram of the plating apparatus 300 used in the step S3b of forming the second underlayer 2b. As shown in Fig. 9, the plating apparatus 300 includes a plating treatment tank 310, a plurality of rollers 320, electrode rollers 331 and 332, and a power source 340.

[0035] A plating solution is stored in the plating tank 310. The plating solution contains copper. The plating solution may also contain nickel. An electrode 311 is disposed inside the plating tank 310. The electrode 311 is made of a conductive material. The electrode 311 is made of titanium, for example. The electrode 311 is immersed in the plating solution.

[0036] The rollers 320 are aligned along the transport direction (see the arrow in FIG. 9 ) of the base film 1. The base film 1 is transported along the transport direction by rotating the rollers 320. During the transport process, the base film 1 passes through a plating solution stored in a plating treatment tank 310.

[0037] The electrode rollers 331 and 332 are disposed at positions where they come into contact with the base film 1 before it passes through the plating solution. At least one of the electrode rollers 331 and 332 comes into contact with the first underlayer 2 a. The electrode rollers 331 and 332 are made of, for example, stainless steel.

[0038] The power supply 340 is electrically connected to the electrode 311 and the electrode rollers 331 and 332. More specifically, the positive pole of the power supply 340 is electrically connected to the electrode 311, and the negative pole of the power supply 340 is electrically connected to the electrode rollers 331 and 332.

[0039] 10 is a cross-sectional view illustrating step S3b of forming the second underlayer 2b. In step S3b of forming the second underlayer 2b, a power source 340 applies current between the electrode 311 and the electrode rollers 331 and 332. As shown in FIG. 10 , driven by the electrical energy generated by this current application, the second underlayer 2b is rapidly formed on the surface (intermediate underlayer surface s) of the first underlayer 2a. Thereafter, the current application between the electrode 311 and the electrode rollers 331 and 332 is stopped.

[0040] Next, step S4b is performed to anneal the printed wiring board substrate 100b. Specifically, the printed wiring board substrate 100b is annealed at 300°C for 1 hour in an inert gas atmosphere such as nitrogen. As a result, the underlayer 2 is fixed to the base film 1. In this manner, the printed wiring board substrate 100b having the structure shown in FIG. 5 is manufactured.

[0041] (Configuration of Printed Wiring Board) The following describes the configuration of printed wiring board 200. Fig. 11 is a cross-sectional view of printed wiring board 200. As shown in Fig. 11, printed wiring board 200 includes base film 1 and a plurality of laminated portions 20.

[0042] The directions parallel to the main surface 1s are defined as a first direction X and a second direction Y. The second direction Y is a direction perpendicular to the first direction X. The direction perpendicular to the first direction X and the second direction Y is defined as a third direction Z.

[0043] The plurality of laminated units 20 are arranged on the main surface 1s. The plurality of laminated units 20 are formed so as to extend linearly along the second direction Y. The plurality of laminated units 20 are arranged at equal intervals in the first direction X. If the shortest distance S (distance between circuits) between two adjacent laminated units 20 in the first direction X and the width L (circuit width) of each of the plurality of laminated units 20 are less than 2 μm, forming the resist pattern 4 in the step S5 of forming the resist pattern 4, which will be described later, will require a long time. Therefore, as shown in FIG. 11 , the shortest distance S (distance between circuits) between two adjacent laminated units 20 in the first direction X may be 2 μm or more. The width L (circuit width) of each of the plurality of laminated units 20 may be 2 μm or more.

[0044] Specifically, the plurality of laminated units 20 include adjacent first laminated units 20 a and second laminated units 20 b. The shortest distance S in the first direction X from the first laminated unit 20 a to the second laminated unit 20 b may be 2 μm or more. The shortest distance S in the first direction X from the first laminated unit 20 a to the second laminated unit 20 b may be 15 μm or less, 10 μm or less, or 6 μm or less.

[0045] The width L of each of the plurality of laminated portions 20 may be 15 μm or less, 10 μm or less, or 6 μm or less. Specifically, the width L of each of the first laminated portion 20 a and the second laminated portion 20 b may be 15 μm or less, 10 μm or less, or 6 μm or less.

[0046] The laminated portion 20 includes an underlayer 2 and an electrolytically plated layer 3. The underlayer 2 is in contact with the main surface 1s. The electrolytically plated layer 3 is in contact with the underlayer 2. The electrolytically plated layer 3 is a copper layer formed by electrolytic plating.

[0047] (Method of Manufacturing Printed Wiring Board 200) A method of manufacturing the printed wiring board 200 will be described below.

[0048] 12 is a flowchart illustrating a method for manufacturing the printed wiring board 200. The printed wiring board 200 is basically manufactured using a semi-additive process. Specifically, as shown in FIG. 12 , the method for manufacturing the printed wiring board 200 includes a step S5 of forming a resist pattern 4, a step S6 of forming an electrolytic plating layer 3, a step S7 of removing the resist pattern 4, a step S8 of annealing the printed wiring board 200, and a step S9 of removing the base layer 2.

[0049] First, step S5 of forming a resist pattern 4 is performed. In step S5, the resist pattern 4 is formed on the base layer 2. Any method, such as photolithography, can be used to form the resist pattern 4. Step S6 of forming an electrolytic plated layer 3 is performed after step S5 of forming the resist pattern 4. Step S7 of removing the resist pattern 4 is performed after step S6 of forming the electrolytic plated layer 3. Step S8 of annealing the printed wiring board 200 is performed after step S7 of removing the resist pattern 4. Step S9 of removing the base layer 2 is performed after step S8 of annealing the printed wiring board 200. The printed wiring board 200 is manufactured using the printed wiring board substrate 100a or the printed wiring board substrate 100b according to the first embodiment.

[0050] 13 is a cross-sectional view illustrating step S5 of forming a resist pattern 4. In step S5 of forming a resist pattern 4, the resist pattern 4 is formed on the underlayer 2 as shown in FIG.

[0051] The resist pattern 4 has openings 4a. The openings 4a are regions where the resist pattern 4 is not formed. The underlying layer 2 is exposed from the openings 4a.

[0052] In step S5 of forming the resist pattern 4, first, a resist in the form of, for example, a film is applied onto the underlayer 2. Second, the resist placed on the underlayer 2 is exposed and developed. As a result, the remaining part of the resist that has not been removed becomes the resist pattern 4, and the removed part of the resist becomes the opening 4a.

[0053] The distance between adjacent resists is the width L (circuit width) of the laminated portion 20. That is, the circuit width is defined in the step S5 of forming the resist pattern 4.

[0054] 14 is a cross-sectional view illustrating step S6 of forming the electrolytic plated layer 3. In step S6 of forming the electrolytic plated layer 3, as shown in FIG. 14, the electrolytic plated layer 3 is formed on the base layer 2 exposed through the opening 4a. The electrolytic plated layer 3 is formed by passing a current through the base layer 2 in a copper-containing plating solution. If the distance between adjacent resists is reduced in step S5 of forming the resist pattern 4 in order to reduce the circuit width, the voltage generated during the formation of the electrolytic plated layer 3 will be concentrated. As a result, the segregation rate of the {100} plane in the electrolytic plated layer 3 increases.

[0055] 15 is a cross-sectional view illustrating step S7 of removing resist pattern 4. In step S7 of removing resist pattern 4, as shown in Fig. 15, resist pattern 4 is removed from underlayer 2. As a result, underlayer 2 is exposed between two adjacent electroplated layers 3.

[0056] Next, step S8 is performed to anneal printed wiring board 200. In step S8, printed wiring board substrate 100 having electrolytic plated layer 3 formed thereon is annealed at 100° C. for 1 hour in an inert gas atmosphere such as nitrogen. This reduces the segregation rate of the {100} plane in electrolytic plated layer 3.

[0057] In step S9 of removing the base layer 2, the portion of the base layer 2 exposed between two adjacent electroplated layers 3 is removed by etching. Specifically, the base layer 2 is removed using a sulfuric acid-hydrogen peroxide etching solution. The etching rate of the electroplated layer 3 varies depending on the crystal orientation segregated in the electroplated layer 3. Specifically, the closer to the {111} crystal orientation, the slower the etching rate. On the other hand, the closer to the {100} crystal orientation, the faster the etching rate. Therefore, if the {100} crystal orientation is segregated in the electroplated layer 3, etching will also progress on the side surfaces of the electroplated layer 3 before the base layer 2 is etched down to the main surface 1s, increasing the amount of removal of the electroplated layer 3. However, in step S8 of annealing the printed wiring board 200, the segregation rate of the {100} crystal orientation in the electroplated layer 3 is reduced. Therefore, the amount of removal of the electroplated layer 3 is suppressed. As a result, the electroplated layer 3 is not excessively etched. Therefore, even if the width L and the shortest distance S (see FIG. 11) of the laminated portion 20 are reduced, the laminated portion 20 can be formed without narrowing the circuit.

[0058] As a result of the above, a printed wiring board 200 having the structure shown in FIG. 11 is formed.

[0059] As will be described later, the segregation rate of the {100} plane of printed wiring board 200 is measured by electron backscattered diffraction (EBSD). As shown in FIG. 11 , laminate 20 is formed to include electrolytic plated layer 3 and underlayer 2. Electrolytic plated layer 3 contacts underlayer 2. Laminate 20 has first surface 21s. First surface 21s is positioned so that the height Ht of the laminate from main surface 1s to first surface 21s is 1 μm or more.

[0060] Before measuring the segregation rate of the {100} plane by EBSD, the cross section of the printed wiring board 200 is processed by argon ion polishing. The acceleration voltage of the ion beam is set to, for example, 6 kV.

[0061] Next, the segregation rate of the {100} plane as viewed from the first direction X in the stacked portion 20 shown in FIG. 11 is measured by EBSD. The segregation rate of the {100} plane is measured using a Germini 450 manufactured by ZEISS and a Symmetry manufactured by Oxford. The measurement conditions for the EBSD measurement are as follows: the acceleration voltage is 15 kV; the electron beam irradiation current is 20 nA; the electron beam integration time is 0.8 ms; the tilt angle of the SEM stage is 70°; and the working distance (WD) of the SEM is 15 mm.

[0062] In the cross section of the laminated portion 20, the value A1 / A2 obtained by dividing the first value A1 by the second value A2 is 0.10 or less. The first value A1 is the area occupied by the {100} plane when viewed from the first direction X in the laminated portion 20. The second value A2 is the area obtained by subtracting the area occupied by the {100} plane when viewed from the first direction X in the laminated portion 20 (first value A1) from the area of ​​the laminated portion 20. The value A1 / A2 obtained by dividing the first value A1 by the second value A2 may be 0.2 or less. From a different perspective, crystal grains oriented in the {100} plane when viewed from the first direction X are defined as first crystal grains. Crystal grains oriented in the {100} plane are crystal grains oriented in a plane that has a measurement tolerance of 15° or less from the {100} plane. When crystal grains other than those oriented in the {100} plane are defined as second crystal grains, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.2 or less. The ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains may be 0 or more and 0.15 or less. The second crystal grains include randomly oriented crystal grains.

[0063] (Effects) A printed wiring board 200 according to the present disclosure includes a base film 1 and a laminated portion 20. The base film 1 has a main surface 1s. The laminated portion 20 is disposed on the main surface 1s. A direction horizontal to the main surface 1s and perpendicular to the linear extension direction (second direction Y) of the laminated portion 20 is defined as a first direction X. When a cross section of the laminated portion 20 is measured by electron backscatter diffraction, crystal grains oriented in the {100} plane as viewed from the first direction X are defined as first crystal grains. Crystal grains oriented in the {100} plane are crystal grains oriented in a plane within a measurement tolerance of 15° from the {100} plane. When crystal grains other than the crystal grains oriented in the {100} plane are defined as second crystal grains, the ratio of the occupied area of ​​the first crystal grains to the occupied area of ​​the second crystal grains is 0.2 or less.

[0064] In this way, the segregation rate of the {100} plane is reduced when electrolytic plated layer 3 is formed, and as a result, the amount of electrolytic plated layer 3 that is removed is suppressed when underlayer 2 is etched. As a result, a printed wiring board 200 can be obtained in which fine circuits are formed with high precision and the circuits do not become thin.

[0065] In the printed wiring board 200, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains may be 0.15 or less.

[0066] In this way, a printed wiring board 200 can be obtained in which fine circuits are formed with high precision and the circuits are not narrowed.

[0067] In the printed wiring board 200, the laminate 20 may include adjacent first and second laminates 20a and 20b. The width L of each of the first and second laminates 20a and 20b may be 15 μm or less. The shortest distance S in the first direction X from the first laminate 20a to the second laminate 20b may be 15 μm or less.

[0068] In this way, a printed wiring board 200 can be obtained in which a fine circuit is formed with high precision and the circuit does not become thin.

[0069] In the printed wiring board 200, the width L of each of the first laminated portion 20a and the second laminated portion 20b may be 10 μm or less. The shortest distance S in the first direction X from the first laminated portion 20a to the second laminated portion 20b may be 10 μm or less.

[0070] In this way, a printed wiring board 200 can be obtained in which a fine circuit is formed with high precision and the circuit does not become thin.

[0071] In the printed wiring board 200, the width L of each of the first laminated portion 20a and the second laminated portion 20b may be 2 μm or more. The shortest distance S in the first direction X from the first laminated portion 20a to the second laminated portion 20b may be 2 μm or more.

[0072] In this way, a printed wiring board 200 can be obtained in which a fine circuit is formed with high precision and the circuit does not become thin.

[0073] In the printed wiring board 200, the laminate portion 20 may include an underlayer 2 and an electrolytic plated layer 3. The underlayer 2 may be in contact with the main surface 1 s. The electrolytic plated layer 3 may be in contact with the underlayer 2.

[0074] In this way, a laminated portion 20 is formed that includes the underlayer 2 and the electrolytic plated layer 3. In order to verify the effects of the printed wiring board 200 as described above, the following measurements were carried out.

[0075] (Sample Preparation) First, a printed wiring board 200 manufactured using a semi-additive process is prepared. The printed wiring board substrates 500 in Samples 1 to 3 are comparative examples. The printed wiring boards 200 in Samples 4 to 6 are working examples. In the printed wiring boards 200 in Samples 1 and 4, the design values ​​of the width L (circuit width) and shortest distance S (distance between circuits) of the multiple laminated portions 20 are 15 μm. In the printed wiring boards 200 in Samples 2 and 5, the design values ​​of the width L (circuit width) and shortest distance S (distance between circuits) of each of the multiple laminated portions 20 are 10 μm. In the printed wiring boards 200 in Samples 3 and 6, the design values ​​of the width L (circuit width) and shortest distance S (distance between circuits) of each of the multiple laminated portions 20 are 6 μm. Table 1 shows the evaluation results of the printed wiring boards 200 shown in Samples 1 to 6.

[0076]

[0077] In the printed wiring boards 200 of Samples 1 to 6, the step S8 of annealing the printed wiring boards 200 was not carried out after the step S6 of forming the electrolytic plating layer 3.

[0078] For printed wiring boards 200 in samples 4 to 6, step S8 of annealing printed wiring board 200 was performed after step S6 of forming electrolytic plated layer 3. In step S8 of annealing printed wiring board 200, printed wiring board substrate 100 on which electrolytic plated layer 3 was formed was annealed at 100° C. for 1 hour in an inert gas atmosphere such as nitrogen.

[0079] <Evaluation of Segregation Ratio of {100} Plane> Using the printed wiring boards 200 of Samples 1 to 6, the segregation ratio of the {100} plane in the laminated portion 20 as viewed from the first direction X was evaluated.

[0080] The first value A1 is the area occupied by the {100} plane when viewed from the first direction X in the laminate 20. A deviation of 15° or less from the {100} plane is considered an error, and the orientation distribution within 15° from the {100} plane is determined as the {100} plane. The second value A2 is the area obtained by subtracting the area occupied by the {100} plane when viewed from the first direction X in the laminate 20 (first value A1) from the area of ​​the laminate 20. When the value A1 / A2 obtained by dividing the first value A1 by the second value A2 satisfies 0.15 or less in the segregation rate of the {100} plane in the electroplated layer 3 when viewed from the first direction X, the segregation rate of the {100} plane is evaluated as A in Table 1. When the value A1 / A2 obtained by dividing the first value A1 by the second value A2 is greater than 0.15 and not greater than 0.2, the segregation rate of the {100} plane is evaluated as B in Table 1. When the value A1 / A2 obtained by dividing the first value A1 by the second value A2 is greater than 0.2, the segregation rate of the {100} plane is evaluated as C in Table 1.

[0081] As shown in Table 1, in Samples 1 to 3, the segregation rate of the {100} plane was evaluated as C. On the other hand, in Samples 4 and 6, the segregation rate of the {100} plane was evaluated as A or B. In particular, in Samples 4 and 5, the segregation rate of the {100} plane was evaluated as A.

[0082] That is, by annealing the laminated layer 20 before etching the underlayer 2, the segregation rate of the {100} plane was reduced.

[0083] <Evaluation of Amount of Scraping of Laminate Portion> Using the printed wiring boards 200 of Samples 1 to 6, the amount of scraping of the laminate portion 20 was evaluated.

[0084] The amount of scraping of the laminate portion 20 is evaluated from the difference between the width L1 of the electrolytic plated layer 3 before etching the base layer 2 and the width L2 of the laminate portion 20 after etching the base layer 2. When the difference between the width L2 of the laminate portion 20 after etching the base layer 2 and the width L1 of the electrolytic plated layer 3 before etching the base layer 2 is 1 μm or less, the amount of scraping of the laminate portion 20 is evaluated as A in Table 1. When the difference between the width L2 of the laminate portion 20 after etching the base layer 2 and the width L1 of the electrolytic plated layer 3 before etching the base layer 2 is more than 1 μm and 2 μm or less, the amount of scraping of the laminate portion 20 is evaluated as B in Table 1. When the difference between the width L2 of the laminate portion 20 after etching the base layer 2 and the width L1 of the electrolytic plated layer 3 before etching the base layer 2 is more than 2 μm, the amount of scraping of the laminate portion 20 is evaluated as C in Table 1.

[0085] As shown in Table 1, in Samples 1 to 3, the scraping amount of the laminated portion 20 was evaluated as C. On the other hand, in Samples 4 to 6, the scraping amount of the laminated portion 20 was evaluated as A or B. In particular, in Samples 4 and 5, the scraping amount of the laminated portion 20 was evaluated as A. As described above, it can be seen that the reduction in the segregation rate of the {100} plane suppresses the scraping amount of the laminated portion 20 caused by etching when the underlayer 2 is etched.

[0086] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present disclosure is defined by the claims, not by the above-described embodiments, and is intended to include any modifications within the scope of the claims and meanings equivalent to the claims.

[0087] 1 base film, 1s main surface, 2 underlayer, 2a first underlayer, 2b second underlayer, 2s underlayer surface, 3 electroplated layer, 4 resist pattern, 4a opening, 20 laminated portion, 20a first laminated portion, 20b second laminated portion, 21s first surface, 100, 100a, 100b printed wiring board substrate, 200 printed wiring board, 300 plating apparatus, 310 plating treatment tank, 311 electrode, 320 roller, 331, 332 electrode roller, 340 power supply, A1 first value, A2 second value, H, Ha distance, H, Ha thickness, Ht height, L width, S shortest distance, X first direction, Y second direction, Z third direction, s intermediate underlayer surface.

Claims

1. A printed wiring board comprising: a base film having a principal surface; and a laminate portion disposed on said principal surface; wherein a first direction is a direction that is horizontal to said principal surface and perpendicular to the linear extension direction of said laminate portion; when a cross section of said laminate portion is measured by electron backscatter diffraction, crystal grains oriented in the {100} plane as viewed from said first direction are defined as first crystal grains; said crystal grains oriented in the {100} plane are crystal grains oriented in a plane with a measurement tolerance of 15° or less from said {100} plane; and when crystal grains other than said crystal grains oriented in the {100} plane are defined as second crystal grains, the ratio of the area occupied by said first crystal grains to the area occupied by said second crystal grains is 0.2 or less.

2. The printed wiring board according to claim 1, wherein the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.15 or less.

3. A printed wiring board according to claim 1 or claim 2, wherein the laminate section includes adjacent first and second laminate sections, the width of each of the first and second laminate sections is 15 μm or less, and the shortest distance in the first direction from the first laminate section to the second laminate section is 15 μm or less.

4. The printed wiring board according to claim 3, wherein the width of each of the first laminated portion and the second laminated portion is 10 μm or less, and the shortest distance in the first direction from the first laminated portion to the second laminated portion is 10 μm or less.

5. A printed wiring board as set forth in claim 3 or claim 4, wherein the width of each of the first laminated portion and the second laminated portion is 2 μm or more, and the shortest distance in the first direction from the first laminated portion to the second laminated portion is 2 μm or more.

6. A printed wiring board according to any one of claims 1 to 5, wherein the laminated portion includes an underlayer in contact with the main surface and an electrolytic plating layer in contact with the underlayer.

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