Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of obtaining a high Q value. In a multilayer ceramic capacitor (1), a dielectric layer (40) contains at least one among (Ca1-x-y, Srx, Bay)m(Zr1-z-ɑ, Tiz)O3 (here, x is 0 to 1, y is 0 to 0.4, m is 1.0 to 1.1, z is 0 to 0.2, and ɑ is 0 to 0.3) and TiO2, and when a length of a straight line serving as a boundary line (65) between an internal electrode layer (30) and a dielectric layer (40) is S, and a length of an actual boundary line (66) between the internal electrode layer (30) and the dielectric layer (40) is A, A / S is at most 1.7, the thickness of an end portion (33) in the width direction W of the internal electrode layer (30) is at least 1.2 µm, the coverage of the end portion (33) in the width direction W of the internal electrode layer (30) is greater than the coverage of a central portion (34), and the average particle diameter of copper included in the internal electrode layer (30) is at least 2.2 µm.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors that can achieve a high Q value in the high frequency range are required for use in electronic devices equipped with high frequency circuits. Patent Document 1 discloses a technique for increasing the Q value of multilayer ceramic capacitors in the high frequency range by thickening the internal electrodes.

[0003] Japanese Patent Application Laid-Open No. 2000-306762

[0004] Electrical conduction in the high-frequency range is dominated by electrical conduction near the surface of the internal electrodes. This is due to the skin effect. Therefore, for example, increasing the thickness of the internal electrodes only increases the surface area to a small extent, and the Q value is not significantly improved. The object of the present invention is to provide a multilayer ceramic capacitor that can achieve a high Q value.

[0005] The multilayer ceramic capacitor of the present invention is a multilayer ceramic capacitor having a laminate formed by laminating a plurality of dielectric layers and a plurality of internal electrode layers, wherein the dielectric layers are １－ｘ－ｙ , Sr ｘ , Ba ｙ ) ｍ (Zr １－ｚ－α , Ti ｚ ) O ３ (wherein x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less) and TiO ２ and at an end portion in a width direction of the internal electrode layer in a cross section obtained by cutting the laminate with a plane perpendicular to the stacking direction, when the shape of the internal electrode layer in a plan view from the stacking direction is considered to be a polygon, the length of a straight line that is a boundary line between the internal electrode layer and the dielectric layer is S and the length of an actual boundary line between the internal electrode layer and the dielectric layer is A, A / S is 1.7 or less, the thickness of the end portion in the width direction of the internal electrode layer is 1.2 μm or more, the coverage of the end portion in the width direction of the internal electrode layer is larger than the coverage of a central portion in the width direction of the internal electrode layer, and the average grain size of copper contained in the internal electrode layer is 2.2 μm or more.

[0006] According to the present invention, a multilayer ceramic capacitor capable of obtaining a high Q value can be provided.

[0007] FIG. 1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line 201-201 in FIG. 1. FIG. 3 is a cross-sectional view taken along line 202-202 in FIG. 1. FIG. 4 is a cross-sectional view taken along line 203-203 in FIG. 1. FIG. 5 is an enlarged view of a first frame 111 in FIG. 4. FIG. 6 is a view showing an LT cross-section of an end portion in the width direction of an internal electrode layer. FIG. 7 is a view showing an LT cross-section of a center portion in the width direction of an internal electrode layer. FIG. 8 is a view showing an LW cross-section of the multilayer ceramic capacitor.

[0008] (Multilayer Ceramic Capacitor) An overview of a multilayer ceramic capacitor 1 according to an embodiment of the present invention is as follows. Fig. 1 is a perspective view of the multilayer ceramic capacitor 1 according to an embodiment of the present invention. As shown in Fig. 1, the multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 50. The external electrodes 50 include a first external electrode 51 and a second external electrode 52.

[0009] (Laminate) Fig. 2 is a cross-sectional view taken along line 201-201 in Fig. 1. Fig. 3 is a cross-sectional view taken along line 202-202 in Fig. 1. Fig. 4 is a cross-sectional view taken along line 203-203 in Fig. 1. As shown in Figs. 2 and 3, the laminate 2 includes internal electrode layers 30 and dielectric layers 40. A plurality of internal electrode layers 30 and dielectric layers 40 are included in the laminate 2. The internal electrode layers 30 and dielectric layers 40 are stacked in order.

[0010] (Laminate Direction) The laminate 2 is roughly shaped like a rectangular parallelepiped. The stacking direction T is the direction in which the internal electrode layers 30 and the dielectric layers 40 are stacked. The length direction L is one of the directions perpendicular to the stacking direction T. The width direction W is a direction perpendicular to the stacking direction T and the length direction L.

[0011] (Names of cross sections) The LT cross section is a cross section parallel to the length direction L and the stacking direction T. Fig. 2 shows the LT cross section. The WT cross section is a cross section parallel to the width direction W and the stacking direction T. Fig. 3 shows the WT cross section. The LW cross section is a cross section parallel to the length direction L and the width direction W. Fig. 4 shows the LW cross section.

[0012] (Surfaces of the laminate) The first main surface T1 and the second main surface T2 are two surfaces of the laminate that face each other in the stacking direction T. The first side surface W1 and the second side surface W2 are two surfaces of the laminate that face each other in the width direction W. The first end surface L1 and the second end surface L2 are two surfaces of the laminate that face each other in the length direction L.

[0013] (Internal electrode layers) The internal electrode layers 30 include a first internal electrode layer 31 and a second internal electrode layer 32. The first internal electrode layer 31 is an internal electrode layer 30 that is extended to the first end face L1. The second internal electrode layer 32 is an internal electrode layer 30 that is extended to the second end face L2. Fig. 4 shows the first internal electrode layer 31.

[0014] The internal electrode layers 30 contain copper as a main component, but may contain metals other than copper.

[0015] The total number of the internal electrode layers 30 is the sum of the number of the first internal electrode layers 31 and the number of the second internal electrode layers 32. The total number of layers is preferably 2 or more and 30 or less.

[0016] (Dielectric Layer) The dielectric layer 40 is a dielectric layer having a general formula (Ca １－ｘ－ｙ , Sr ｘ , Ba ｙ ) ｍ (Zr １－ｚ－α , Ti ｚ ) O ３ (where x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less), and a ceramic material represented by the formula (I) and titanium oxide (TiO ２ ) as a main component. Examples of the ceramic material represented by the above general formula include calcium zirconate (CaZrO ３ In addition to the above-mentioned main components, additives can be added depending on the purpose. Examples of such additives include oxides of rare earth elements such as Mn, Mg, Dy, and Cr, V, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, and Y, oxides of Co, Ni, Li, B, Na, K, and Si, and glass.

[0017] The preferred thickness of the dielectric layer 40 in the portion sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 in the stacking direction T is 0.3 μm or more and 20 μm or less.

[0018] (Size of laminate) The size of the laminate 2 is not limited. The preferred length of the laminate 2 in the longitudinal direction L is 0.2 mm or more and 10 mm or less. The preferred length of the laminate 2 in the width direction W is 0.1 mm or more and 5 mm or less. The preferred length of the laminate 2 in the stacking direction T is 0.1 mm or more and 5 mm or less.

[0019] (External Electrodes) The external electrodes 50 include a first external electrode 51 and a second external electrode 52. The first external electrode 51 is the external electrode 50 connected to the first internal electrode layer 31. The second external electrode 52 is the external electrode 50 connected to the second internal electrode layer 32.

[0020] The first external electrode 51 is disposed on the first end face L1, part of the first main face T1, part of the second main face T2, part of the first side face W1, and part of the second side face W2. The second external electrode 52 is disposed on the second end face L2, part of the first main face T1, part of the second main face T2, part of the first side face W1, and part of the second side face W2.

[0021] The external electrode 50 includes a base electrode layer 53 and a plating layer 55. The plating layer 55 includes a nickel plating layer 56 and a tin plating layer 57. The base electrode layer 53, the nickel plating layer 56, and the tin plating layer 57 are arranged in this order from the end face of the laminate 2.

[0022] The base electrode layer 53 includes a metal and a glass. Examples of the metal include copper, nickel, silver, palladium, a silver-palladium alloy, and gold. Examples of the glass include boron-based glass and silicon-based glass. The base electrode layer 53 is formed by firing a conductive paste. The conductive paste includes a metal and a glass. The conductive paste is fired after being applied to the laminate 2. The preferred thickness of the base electrode layer 53 is 3 μm or more and 100 μm or less.

[0023] The nickel plating layer 56 is disposed so as to cover the base electrode layer 53. The tin plating layer 57 is disposed so as to cover the nickel plating layer 56.

[0024] The multilayer ceramic capacitor 1 is mounted on a substrate using solder. The nickel plating layer 56 prevents the base electrode layer 53 from being corroded by the solder. The tin plating layer 57 improves the wettability of the solder to the multilayer ceramic capacitor 1. The tin plating layer 57 makes it easier to mount the multilayer ceramic capacitor 1 on a substrate.

[0025] (Size of Multilayer Ceramic Capacitor) The size of the multilayer ceramic capacitor 1 is not limited. The length in the longitudinal direction L of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 50 is preferably 0.2 mm or more and 10 mm or less. The length in the stacking direction T of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 50 is preferably 0.1 mm or more and 5 mm or less. The length in the width direction W of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 50 is preferably 0.1 mm or more and 10 mm or less.

[0026] (Linearity of Ends of Internal Electrode Layers) The linearity of the ends 33 of the internal electrode layers 30 in the width direction W of the multilayer ceramic capacitor 1 of this embodiment is as follows. As shown in Fig. 4, the ends 33 of the internal electrode layers 30 in the width direction W are the edges of the internal electrode layers 30 facing the first side face W1 or the second side face W2. In the multilayer ceramic capacitor 1 of this embodiment, the linearity of the ends 33 of the internal electrode layers 30 in the width direction W is high.

[0027] The lengthwise center line 131 shown in Figure 4 is a line drawn at the center of the length direction L of the laminate 2. The widthwise center line 132 is a line drawn at the center of the width direction W of the laminate 2. The center position 60 is the center position of the lengthwise direction L and width direction W of the laminate 2. The center position 60 is located at the intersection of the lengthwise center line 131 and the widthwise center line 132. The first position 71 and the second position 72 are located on the end 33 of the internal electrode layer 30 in the width direction W. The midpoint between the first position 71 and the second position 72 is located on the lengthwise center line 131.

[0028] (Length S) The first line segment 121 is a line segment connecting the first position 71 and the second position 72. The length S is the length of the first line segment 121. The length S has the following meaning: The shape of the internal electrode layer 30 in a plan view from the stacking direction T is considered to be a polygon. When the internal electrode layer 30 is polygonal, the boundary line between the internal electrode layer 30 and the dielectric layer 40 is a straight line. The shape of the internal electrode layer 30 shown in FIG. 4 can be considered to be a rectangle, which is a type of polygon. The boundary line between the internal electrode layer 30 and the dielectric layer 40 is a straight line in a simulated manner. FIG. 5 is an enlarged view of the frame 111 in FIG. 4. The dashed line 65 shown in FIG. 5 is the boundary line when the boundary line is considered to be a straight line. The length S is the length of the dashed line 65. The length of the dashed line 65 is the same as the length of the first line segment 121 in FIG. 4.

[0029] 5 is the actual boundary line between the internal electrode layer 30 and the dielectric layer 40. The actual boundary line 66 is not a straight line when viewed from above in the stacking direction T. Length A is the length of the actual boundary line 66.

[0030] (Length A / Length S) When the actual boundary line 66 between the internal electrode layer 30 and the dielectric layer 40 is a straight line, length A is equal to length S. When the actual boundary line 66 between the internal electrode layer 30 and the dielectric layer 40 is not a straight line, length A is longer than length S. The ratio of length A to length S is usually greater than 1.0. Length A / length S indicates the linearity of the end 33 of the internal electrode layer 30. When length A / length S approaches 1, the linearity improves. When length A / length S increases, the linearity deteriorates. Length A / length S of the multilayer ceramic capacitor 1 of this embodiment is 1.7 or less.

[0031] When the multilayer ceramic capacitor 1 is used in a high frequency range, current mainly flows on the surface of the internal electrode layer 30. The current mainly flows on the surface of the internal electrode layer 30 due to the skin effect. The current flows concentratedly at the actual boundary line 66 between the internal electrode layer 30 and the dielectric layer 40. When the length A, which is the length of the actual boundary line 66, is long, the resistance value is large. When the resistance value is large, the ESR per unit internal electrode layer increases. It is preferable that the length A is small. When the length A / length S is 1.7 or less, the ESR per unit electrode layer of the multilayer ceramic capacitor 1 in a high frequency range is reduced.

[0032] For example, in the relationship between length A / length S and ESR (Ω) at 1 GHz per internal electrode layer, the ESR when length A / length S is 1.7 was 78% of the ESR when length A / length S is 2.4. In other words, by reducing length A / length S from 2.4 to 1.7, the ESR could be reduced by 28%. Note that these measurements were performed on the multilayer ceramic capacitor 1.

[0033] (Method for measuring length A / length S) The method for measuring length A / length S is as follows. Length A and length S are determined based on the same cross-sectional image. The main surface of the multilayer ceramic capacitor 1 is polished. The LW cross section of the internal electrode layer 30 is exposed. A position corresponding to the first line segment 121 of the end 33 of the internal electrode layer 30 is observed under magnification with an electron microscope, and length A is measured. The length of the first line segment 121 when measuring length A is 80 μm. Length S is 80 μm. The magnification for observation is 2000 times.

[0034] (Thickness of Ends in Width Direction of Internal Electrode Layers) The thickness of the ends 33 in the width direction W of the internal electrode layers 30 of the multilayer ceramic capacitor 1 of this embodiment is as follows. In the multilayer ceramic capacitor 1 of this embodiment, the thickness of the ends 33 in the width direction W of the internal electrode layers 30 is large. The thickness of the ends 33 in the width direction W of the internal electrode layers 30 is 1.4 μm or more.

[0035] One example of a means for improving the linearity of the end 33 of the internal electrode layer 30 is to increase the thickness of the end 33 in the width direction W of the internal electrode layer 30. For example, when the thickness of the end 33 in the width direction W of the internal electrode layer 30 is made equal to or greater than a predetermined thickness, the ratio of length A / length S can be made equal to or less than a predetermined value. In this way, when the thickness of the end 33 in the width direction W of the internal electrode layer 30 is increased, the linearity of the end 33 of the internal electrode layer 30 is improved. Specifically, for example, by making the thickness of the end 33 in the width direction W of the internal electrode layer 30 equal to or greater than 1.4 μm, the ratio of length A / length S can be made equal to or less than 1.7.

[0036] (Method for measuring thickness of width direction end portion of internal electrode layer) The method for measuring the thickness of the end portion 33 of the internal electrode layer 30 in the width direction W is as follows. The end portion center position 61 in FIG. 4 is the position where the longitudinal center line 131 intersects with the end portion 33 of the internal electrode layer 30. The position for measuring the thickness of the internal electrode layer 30 is the end portion center position 61. The side surface of the multilayer ceramic capacitor 1 is polished. The LT cross section of the internal electrode layer 30 is exposed. The end portion center position 61 is enlarged with an electron microscope, and the thickness of the internal electrode layer 30 is measured. The magnification for observation is 2000 times.

[0037] The measurement of the length A / length S, i.e., linearity, and the measurement of the thickness of the end 33 of the internal electrode layer 30 in the width direction W can be performed, for example, in the order of linearity and thickness. In this case, first, the main surfaces of the multilayer ceramic capacitor 1 are polished. Then, the LW cross section of the internal electrode layer 30 is exposed, and the length A and the length S are measured. Next, the side surfaces of the multilayer ceramic capacitor 1 are polished. Then, the LT cross section of the internal electrode layer 30 is exposed, and the thickness of the internal electrode layer 30 is measured.

[0038] (Coverage of Internal Electrode Layers) The coverage of the internal electrode layers 30 of the multilayer ceramic capacitor 1 of this embodiment is as follows. The central portion 34 of the internal electrode layer 30 shown in FIG. 4 is the internal electrode layer 30 located on the widthwise center line 132. The central portion 34 of the internal electrode layer 30 is located at the center of the width direction W of the internal electrode layer 30. In the multilayer ceramic capacitor 1 of this embodiment, the coverage of the end portions 33 of the internal electrode layers 30 in the width direction W is greater than the coverage of the central portion 34 of the internal electrode layers 30 in the width direction W. The coverage includes line coverage and surface coverage. In at least one of the line coverage and surface coverage, the coverage of the end portions 33 of the internal electrode layers 30 in the width direction W is greater than the coverage of the central portion 34 of the internal electrode layers 30 in the width direction W.

[0039] (Line Coverage) Line coverage is the coverage measured on the LT cross section of the internal electrode layer 30. The cross section of the internal electrode layer 30 observed on the LT cross section can be considered as a line. Line coverage indicates the proportion of metal in the internal electrode layer 30 considered as a line. Specifically, the proportion of the length excluding the dividing portion 35 to the entire length of a predetermined line segment is calculated. The calculated proportion is defined as the line coverage. Figure 6 is a diagram showing the LT cross section of an end portion 33 in the width direction W of the internal electrode layer 30. The dividing portion 35 shown in Figure 6 is a portion where the internal electrode layer 30 is divided. The line coverage of the end portion 33 in the width direction W of the internal electrode layer 30 is greater than the line coverage of the center portion 34 in the width direction W of the internal electrode layer 30.

[0040] (Line Coverage at Ends) The method for measuring the line coverage at the ends 33 in the width direction W of the internal electrode layers 30 is as follows. The side surface of the laminate 2 is polished to expose the LT cross section of the end 33 of the internal electrode layer 30. In the exposed LT cross section, a position corresponding to the first line segment 121 of the internal electrode layer 30 is observed with an electron microscope. The position of the first line segment 121 and the like are as described with reference to FIG. 4. The line coverage is determined in the internal electrode layer 30 at the position corresponding to the first line segment 121.

[0041] (Line Coverage of Central Portion 34) The line coverage of the central portion 34 in the width direction W of the internal electrode layer 30 is measured as follows. The line coverage of the end portion 33 in the width direction W of the internal electrode layer 30 is measured at a position corresponding to the first line segment 121. The line coverage of the central portion 34 in the width direction W of the internal electrode layer 30 is measured at a position corresponding to the second line segment 122 shown in FIG. 4. The second line segment 122 is a line segment connecting the third position 73 and the fourth position 74. The second line segment 122 is on the width direction center line 132. The length of the second line segment 122 is the same as that of the first line segment 121. The position of the second line segment 122 in the length direction L is the same as that of the first line segment 121 in the length direction L. The third position 73 is at the same position in the length direction L as the first position 71. The fourth position 74 is at the same position as the second position 72 in the length direction L. The side surface of the laminate 2 is polished to expose the LT cross section on the W-direction center line 132 of the internal electrode layer 30. Fig. 7 is a diagram showing the LT cross section of the center portion 34 in the width direction W of the internal electrode layer 30. A position corresponding to the second line segment 122 of the internal electrode layer 30 is observed with an electron microscope to determine the line coverage.

[0042] The line coverage of the end portions 33 in the width direction W of the internal electrode layers 30 is greater than the line coverage of the central portions 34 in the width direction W of the internal electrode layers 30 .

[0043] (Surface Coverage) The surface coverage is the coverage measured when the internal electrode layer 30 is viewed in plan from the stacking direction T. The LW surface is the surface observed in plan from the stacking direction T. The internal electrode layer 30 observed in the LW surface can be considered as a surface. The surface coverage indicates the proportion of metal in the internal electrode layer 30 considered as a surface. FIG. 8 is a diagram showing the LW surface of the multilayer ceramic capacitor 1. The voids 37 shown in FIG. 8 are holes formed in the internal electrode layer 30. The metal material forming the internal electrode layer 30 is not present in the voids 37. The surface coverage is the ratio of the area of ​​the portion other than the voids 37 included in a given area of ​​the internal electrode layer 20. The surface coverage can be calculated from the number of pixels included in an image in image processing. Specifically, the surface coverage is the ratio of the number of pixels other than the voids 37 to the total number of pixels of the internal electrode layer 20 to the total number of pixels of the entire internal electrode layer 20 being observed. The surface coverage of the region near the end 33 in the width direction W of the internal electrode layer 30 is greater than the surface coverage of the central portion 34 in the width direction W of the internal electrode layer 30. In terms of surface coverage, the coverage of the end 33 in the width direction W of the internal electrode layer 30 means coverage in a predetermined range including the end 33. In terms of surface coverage, the coverage of the central portion 34 in the width direction W of the internal electrode layer 30 means coverage in a predetermined range including the central portion 34.

[0044] (Surface Coverage of Ends) The method for measuring the surface coverage of the ends 33 of the internal electrode layers 30 in the width direction W is as follows. The dielectric layers 40 and the internal electrode layers 30 of the laminate 2 are peeled off to expose the internal electrode layers 30. The above-mentioned surface coverage is determined for the exposed LW surfaces.

[0045] The third frame 113 has a square shape. The length of one side of the third frame 113 is 10 μm. One side of the third frame 113 is located on an end 33 of the internal electrode layer 30 in the width direction W. The third frame 113 is located at the center in the length direction L. The fifth position 75 is the position of one vertex on the end 33 of the third frame 113. The sixth position 76 is the position of another vertex on the end 33 of the third frame 113. The midpoint between the fifth position 75 and the sixth position 76 is located on the lengthwise center line 131.

[0046] (Surface coverage of central portion 34) The method for measuring the surface coverage of the central portion 34 in the width direction W of the internal electrode layer 30 is as follows. The following explanations are for matters that differ from the method for measuring the surface coverage of the end portion 33. Matters not explained below are the same as the method for measuring the surface coverage of the end portion 33. The surface coverage of the end portion 33 was measured in the third frame 113. The surface coverage of the central portion 34 in the width direction W of the internal electrode layer 30 is measured in the second frame 112.

[0047] The second frame 112 is shown in FIG. 4. The shape of the second frame 112 is square. The length of one side of the second frame 112 is 10 μm. Two sides of the second frame 112 are parallel to the length direction L. The other two sides of the second frame 112 are parallel to the width direction W. The second frame 112 is located at the center position of the laminate 2. The intersection of the two diagonals of the second frame 112 is at the center position 60.

[0048] In the multilayer ceramic capacitor 1 of this embodiment, the surface coverage of the end portions 33 of the internal electrode layers 30 in the width direction W is greater than the surface coverage of the central portion 34 of the internal electrode layers 30 in the width direction W. An end vicinity region 141 shown in FIG. 8 is a region near the end portions 33 of the internal electrode layers 30 in the width direction W. A central vicinity region 142 shown in FIG. 8 is a region near the central portion 34 of the internal electrode layers 30 in the width direction W. FIG. 8 shows a simulated distribution of voids 37 in the internal electrode layers 30. The voids 37 shown in FIG. 8 do not represent voids 37 that actually exist. As shown in FIG. 8, the distribution density of the voids 37 in the end vicinity region 141 is lower than the distribution density of the voids 37 in the central vicinity region 142.

[0049] In the multilayer ceramic capacitor 1 of this embodiment, the coverage of the end portions 33 of the internal electrode layers 30 in the width direction W is greater than the coverage of the central portion 34 of the internal electrode layers 30 in the width direction W. The resistance value of the end portions 33 of the internal electrode layers 30 in the width direction W is reduced. The multilayer ceramic capacitor 1 of this embodiment can obtain a high Q value.

[0050] (Average particle size of copper) The particle size of copper contained in the internal electrode layers 30 of the multilayer ceramic capacitor 1 of this embodiment is as follows. In the multilayer ceramic capacitor 1 of this embodiment, the average particle size of copper contained in the internal electrode layers 30 is 2.2 μm or more. In the multilayer ceramic capacitor 1 of this embodiment, the resistance value of the internal electrode layers 30 is reduced because the average particle size of copper contained in the internal electrode layers 30 is 2.2 μm or more.

[0051] The average grain size of copper contained in the internal electrode layer 30 can be determined by observing the LT cross section of the internal electrode layer 30 with a focused ion beam (FIB)-scanning ion microscope (SIM).

[0052] In the multilayer ceramic capacitor 1 of this embodiment, the linearity, thickness, coverage, and average copper grain size of the end portions 33 in the width direction W of the internal electrode layers 30 all have the above-described properties at the same time. In the multilayer ceramic capacitor 1 of this embodiment, a high Q value can be obtained.

[0053] (Manufacturing Method of Multilayer Ceramic Capacitor of Embodiment) A manufacturing method of the multilayer ceramic capacitor 1 will be described. (1) Dielectric sheets and conductive paste for the internal electrode layers 30 are prepared. The dielectric sheets and conductive paste contain a binder and a solvent. The binder and solvent may be known organic binders and organic solvents.

[0054] (2) A conductive paste for the internal electrode layers 30 is printed on the dielectric sheet in a predetermined pattern. That is, an internal electrode layer pattern is formed on the dielectric sheet. Examples of printing methods include screen printing and gravure printing.

[0055] (3) A predetermined number of dielectric sheets on which no internal electrode layer patterns are printed are stacked. A predetermined number of dielectric sheets on which internal electrode layer patterns are printed are stacked on top of these. A predetermined number of dielectric sheets on which no internal electrode layer patterns are printed are stacked on top of these.

[0056] (4) The stacked sheets are pressed in the stacking direction. An example of the pressing method is isostatic pressing. After pressing, the stacked sheets become a laminated block.

[0057] (5) The multilayer block is fired to form the laminate 2. In the multilayer ceramic capacitor 1 of this embodiment, the firing temperature is 980°C or higher and 1020°C or lower.

[0058] (6) External electrodes 50 are formed on two end surfaces of the laminate 2. The method for forming the external electrodes 50 may be a known method. For example, a conductive paste containing a conductive component such as copper or nickel as a main component is applied to the end surfaces, and then baked to form the base electrode layer 54. The base electrode layer 54 may also be formed by applying a conductive paste to both end surfaces of a precursor of the laminate 2 before firing, followed by firing. After forming the base electrode layer 53, a nickel plating layer 56 and a tin plating layer 57 are formed on the surface of the base electrode layer 53 by electrolytic plating. In this manner, a multilayer ceramic capacitor is manufactured.

[0059] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible.

[0060] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 33 End 34 Central portion 35 Divided portion 37 Hole 40 Dielectric layer 50 External electrode 51 First external electrode 52 Second external electrode 53 Base electrode layer 55 Plating layer 56 Nickel plating layer 57 Tin plating layer 60 Central position 61 End central position 65 Dashed line 66 Actual boundary line 71 First position 72 Second position 73 Third position 74 Fourth position 75 Fifth position 76 Sixth position 111 First frame 112 Second frame 113 Third frame 121 First line segment 122 Second line segment 131 Lengthwise center line 132 Widthwise center line 141 Area near the end 142 Area near the center A Actual length S Length of the straight line

Claims

1. A multilayer ceramic capacitor comprising a laminate formed by laminating a plurality of dielectric layers and a plurality of internal electrode layers, wherein the dielectric layers are made of (Ca １－ｘ－ｙ , Sr ｘ , Ba ｙ ) ｍ (Zr １－ｚ－α , Ti ｚ ) O ３ (wherein x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less) and TiO ２ a thickness of the end portion in the width direction of the internal electrode layer is 1.2 μm or more, a coverage of the end portion in the width direction of the internal electrode layer is greater than a coverage of a central portion in the width direction of the internal electrode layer, and an average grain size of copper contained in the internal electrode layer is 2.2 μm or more, wherein, at an end portion in the width direction of the internal electrode layer in a cross section obtained by cutting the laminate along a plane perpendicular to the stacking direction, when a shape of the internal electrode layer in a plan view from the stacking direction is considered to be a polygon, a length of a straight line that is a boundary line between the internal electrode layer and the dielectric layer is S and a length of an actual boundary line between the internal electrode layer and the dielectric layer is A, 2. The multilayer ceramic capacitor according to claim 1, wherein the coverage is evaluated by the number of disconnected portions of the internal electrode layer contained in a predetermined length of the internal electrode layer when the internal electrode layer is observed in a cross section of the laminate cut along a plane parallel to the lamination direction.

3. The multilayer ceramic capacitor according to claim 1, wherein the coverage is evaluated by the number of voids contained in the internal electrode layers within a predetermined area when the internal electrode layers are observed in the lamination direction.

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