Printed wiring board

Abstract

This printed wiring board includes a base film and a lamination part. The base film has a main surface. The lamination part is disposed on the main surface. A first area ratio is defined in the following way: the cross section of the lamination part is measured by an electron beam backward scattering diffraction method under a condition that a grain boundary threshold is 10° or less, and the ratio of the area occupied by crystal grains having an equivalent circle diameter of 3 μｍ or more in a first region is the first area ratio, the first area being an area up to 4 μｍ from the main surface. The first area ratio is 0.8 or more.

Description

printed wiring board

[0001] The present disclosure relates to a printed wiring board. This application claims priority to international application PCT / JP2024 / 014864, filed April 12, 2024, the entire contents of which are incorporated herein by reference.

[0002] International Publication No. 2019 / 208077 (Patent Document 1) discloses a substrate for a printed wiring board including a base film and an electroless plating layer.

[0003] International Publication No. 2019 / 208077

[0004] The printed wiring board according to the present disclosure includes a base film and a laminate portion. The base film has a main surface. The laminate portion is disposed on the main surface. When a cross section of the laminate portion is measured by electron backscatter diffraction under the condition that the grain boundary threshold is 10° or less, a first area ratio is defined as the proportion of the area occupied by crystal grains having a circle-equivalent diameter of 3 μm or more in a first region extending from the main surface to 4 μm. The first area ratio is 0.8 or more.

[0005] FIG. 1 is a cross-sectional view showing the configuration of a substrate for printed wiring boards according to the first embodiment. FIG. 2 is a flowchart showing a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 3 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 4 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 5 is a cross-sectional view showing a configuration of a modified example of a substrate for printed wiring boards according to the first embodiment. FIG. 6 is a flowchart showing a method for manufacturing a modified example of a substrate for printed wiring boards according to the first embodiment. FIG. 7 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 8 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 9 is a schematic configuration diagram of a plating apparatus. FIG. 10 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 11 is a cross-sectional view showing the configuration of a printed wiring board according to the second embodiment. FIG. 12 is a flowchart showing a method for manufacturing a printed wiring board according to the second embodiment. FIG. 13 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment. FIG. 14 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment. FIG. 15 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment. FIG. 16 is a printed wiring board showing an object to be measured for crystal orientation distribution. FIG. 17 is a schematic cross-sectional view of a laminate shown in region XVII of FIG. 11. FIG. 18 is a cross-sectional view of a printed wiring board substrate showing an object to be measured for crystal orientation distribution. FIG. 19 is a crystal grain distribution in a laminate part of sample 1. FIG. 20 is a crystal grain distribution in a laminate part of sample 7. FIG. 21 is a crystal grain distribution in a laminate part of sample 1. FIG. 22 is a crystal grain distribution in a laminate part of sample 7. FIG. 23 is a plan view of an evaluation TEG (Test Element Group).

[0006] [Problem to be Solved by the Present Disclosure] There is a demand for finer circuits on printed wiring boards. In a semi-additive process suitable for forming finer circuits, a circuit composed of a laminate including an underlayer and an electroplated layer is formed on the surface of a base film on which an underlayer has been formed by undergoing the steps of resist pattern formation, electroplating, resist removal, and underlayer etching. In the step of etching the underlayer, it is difficult to uniformly etch the underlayer and the electroplated layer, which may impair the rectangularity of the circuit.

[0007] An object of the present disclosure is to provide a printed wiring board having a circuit with excellent rectangularity.

[0008] Effect of the Present Disclosure According to the present disclosure, it is possible to provide a printed wiring board including a circuit with excellent rectangularity.

[0009] [Outline of the embodiment] First, the embodiments of the present disclosure will be listed and described.

[0010] (1) A printed wiring board according to the present disclosure includes a base film and a laminate portion. The base film has a main surface. The laminate portion is disposed on the main surface. When a cross section of the laminate portion is measured by electron backscatter diffraction under conditions where the grain boundary threshold is 10° or less, a first area ratio is defined as the proportion of the area occupied by crystal grains having a circle-equivalent diameter of 3 μm or more in a first region extending from the main surface to 4 μm. The first area ratio is 0.8 or more.

[0011] (2) In the printed wiring board of (1), the second area ratio may be a ratio of an area occupied by crystal grains having a circular equivalent diameter of 3 μm or more in a second region other than the first region in a cross section of the laminate. The first area ratio may be 0.8 times or more the second area ratio.

[0012] (3) In the printed wiring boards of (1) and (2) above, the direction perpendicular to the main surface may be the first direction. The direction perpendicular to the first direction may be the second direction. The direction perpendicular to the first direction and the second direction may be the third direction. The laminated portion may be formed to extend linearly along the second direction. The laminated portion may include adjacent first and second laminated portions. The width of each of the first and second laminated portions may be 15 μm or less. The shortest distance in the third direction from the first laminated portion to the second laminated portion may be 15 μm or less.

[0013] (4) In the printed wiring board of (3), the width of each of the first laminate portion and the second laminate portion may be 10 μm or less, and the shortest distance from the first laminate portion to the second laminate portion in the third direction may be 10 μm or less.

[0014] (5) In the printed wiring board of (3) or (4), the width of each of the first laminate portion and the second laminate portion may be 2 μm or more, and the shortest distance from the first laminate portion to the second laminate portion in the third direction may be 2 μm or more.

[0015] (6) In the printed wiring board according to any one of (1) to (5), the laminated portion may include an underlayer and an electroplated layer. The underlayer may be in contact with the main surface. The electroplated layer may be in contact with the underlayer.

[0016] [Details of the embodiment] The details of the embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated. The substrate for a printed wiring board and the printed wiring board according to the embodiment are referred to as a substrate for a printed wiring board 100 (100a, 100b) and a printed wiring board 200, respectively.

[0017] (Configuration of Substrate for Printed Wiring Board) The configuration of the substrate for printed wiring board 100a will be described below.

[0018] 1 is a cross-sectional view of a substrate 100a for a printed wiring board. As shown in FIG. 1, the substrate 100a for a printed wiring board includes a base film 1 and an underlayer 2.

[0019] The base film 1 has a main surface 1s. The base film 1 is made of a flexible insulating material, such as polyimide.

[0020] The base layer 2 is in contact with the principal surface 1s. The base layer 2 is composed of either a sputtered copper layer or a nano-copper sintered body layer. In the case of a nano-copper sintered body layer, the nano-copper sintered body layer is formed from a plurality of sintered copper particles. Therefore, the nano-copper sintered body layer is porous. The average particle size of the copper particles contained in the nano-copper sintered body layer may be 1 nm or more or 30 nm or more. The average particle size of the copper particles contained in the nano-copper sintered body layer may be 100 nm or less or 500 nm or less. In other words, the copper particles contained in the nano-copper sintered body layer may be nano-copper particles. The average particle size of the copper particles contained in the paste used to form the nano-copper sintered body layer is measured using a particle size distribution measurement device (e.g., a Microtrac particle size distribution meter UPA-150EX manufactured by Nikkiso Co., Ltd.). As described below, an electroless copper plating layer (not shown) may be formed on the principal surface 1s.

[0021] As shown in FIG. 1 , the direction perpendicular to the main surface 1s is defined as the first direction X. The base layer 2 has a base layer surface 2s. The base layer surface 2s is the surface of the base layer 2 opposite to the surface in contact with the main surface 1s. The distance H in the first direction from the main surface 1s to the base layer surface 2s (thickness H of the base layer 2) may be 1 μm or less or 0.5 μm or less. As will be described later, when the thickness H of the base layer 2 is 1 μm or less, the thin line formability of the laminate portion 20 is improved. As a result, the circuit of the printed wiring board 200 can be miniaturized.

[0022] (Method for manufacturing substrate for printed wiring board) A method for manufacturing the substrate for printed wiring board 100a will be described below. Fig. 2 is a flowchart illustrating the method for manufacturing the substrate for printed wiring board 100a. As shown in Fig. 2, the method for manufacturing the substrate for printed wiring board 100a includes a step S1a of preparing a base film 1 and a step S2a of forming an underlayer 2.

[0023] The step S2a of forming the underlayer is performed after the step S1a of preparing the base film 1.

[0024] 3 is a cross-sectional view illustrating step S1a of preparing the base film 1. In step S1a of preparing the base film 1, the base film 1 is prepared as shown in Fig. 3. In step S1a of preparing the base film 1, the underlayer 2 is not disposed on the main surface 1s of the prepared base film 1.

[0025] Before disposing the underlayer 2 on the principal surface 1s, the principal surface 1s is subjected to, for example, an alkali treatment and an excimer treatment. If the base film 1 is made of, for example, polyimide, the alkali treatment hydrolyzes the polyimide. Specifically, the alkali treatment is performed on the principal surface 1s of the base film 1 by spraying an alkaline solution onto the principal surface 1s of the base film 1. The alkali treatment may also be performed on the principal surface 1s of the base film 1 by immersing the base film 1 in the alkaline solution. The alkaline solution may be, for example, an aqueous solution containing potassium hydroxide or sodium hydroxide. The amount (by weight) of potassium hydroxide or sodium hydroxide contained in the alkaline solution is 200 g to 300 g per liter of alkaline solution. Next, the principal surface 1s of the base film 1 is subjected to a drying treatment for the purpose of dehydration. The drying temperature in the drying treatment is, for example, 30°C to 60°C. For example, if the drying temperature is 40°C, the drying time in the drying treatment may be, for example, 30 minutes to 5 hours. As a result, carboxyl groups are formed on the principal surface 1s, and the base film 1 becomes hydrophilic. When the principal surface 1s is metallized with copper by applying a paste or by electroless plating, crystal growth becomes uniform. Specifically, by laminating copper with uniform crystal grain size on the principal surface 1s, the structure of the electroplated layer 3 grows continuously with respect to the structure of the underlayer 2. As a result, the structure of the electroplated layer 3 becomes integrated with the structure of the underlayer 2, improving the integrity of the structure in the laminate 20.

[0026] To further enhance the hydrophilicity of the principal surface 1s, the principal surface 1s may be subjected to an excimer treatment after the alkali treatment. Specifically, the principal surface 1s is irradiated with excimer light. The wavelength of the excimer light is, for example, 172 nm. In this way, crystal growth can be controlled to be uniform.

[0027] FIG. 4 is a cross-sectional view illustrating step S2a of forming the underlayer 2. In step S2a of forming the underlayer 2, the underlayer 2 is formed on the main surface 1s as shown in FIG. 4. In this step S2a, first, a paste containing copper particles is applied to the main surface 1s. Second, the solvent contained in the applied paste is dried. Third, the dried paste is fired. As a result, the copper particles contained in the dried paste are sintered to form the underlayer 2. The underlayer 2 may be formed by sputtering. The underlayer 2 may be formed using a plating apparatus 300 described below. After the underlayer 2 is formed using the plating apparatus 300, the base film 1 is annealed at an annealing temperature of 300°C for 1 hour.

[0028] As described above, the printed wiring board substrate 100a shown in FIG. 1 is manufactured. In the printed wiring board substrate 100a manufactured in this manner, when an electrolytic plating layer 3 is formed on the base layer surface 2s, the structure of the electrolytic plating layer 3 grows integrally with the structure of the base layer 2, as shown in FIG. 18. In other words, if the integrity of the structure in the laminated portion 20 is improved, the etching rate of the laminated portion 20 in the first direction X becomes uniform. The laminated portion 20 is composed of the electrolytic plating layer 3 and the base layer 2. As described below, the etching solution used in the semi-additive process is generally a sulfuric acid-hydrogen peroxide etching solution. As a result, the laminated portion 20 has excellent rectangularity. In this manner, the printed wiring board 200 according to the second embodiment described below is obtained.

[0029] The integrity of the structure of the laminate 20 composed of the underlayer 2 and the electroplated layer 3 is evaluated by the proportion of the area occupied by crystal grains in the laminate 20. As described below, the area occupied by crystal grains in the printed wiring board substrate 100 is measured by electron backscattered diffraction (EBSD). Specifically, as shown in FIG. 18 , for example, when the laminate 20 is formed to include the electroplated layer 3 and the underlayer 2, the electroplated layer 3 contacts the underlayer 2. The laminate 20 has a first surface 21s. The first surface 21s is positioned so that the height Ht of the laminate from the main surface 1s to the first surface 21s is 1 μm or more. Before measuring the area occupied by the crystal grains in the printed wiring board substrate 500 on which the laminated portion 20 is formed in this manner by EBSD, the cross section of the printed wiring board substrate 500 is processed by argon ion polishing. The acceleration voltage of the ion beam is set to, for example, 6 kV. Next, the area occupied by the crystal grains in the laminated portion 20 is measured by EBSD. The area occupied by the crystal grains is measured using a Germini 450 manufactured by ZEISS and a Symmetry manufactured by Oxford. The EBSD measurement conditions are as follows: the acceleration voltage is 15 kV; the electron beam irradiation current is 20 nA; the electron beam integration time is 0.8 ms; the tilt angle of the SEM stage is 70°; and the working distance (WD) of the SEM is 15 mm.

[0030] When evaluating the structural integrity of the laminated portion 20, the crystal grains to be evaluated by EBSD are measured under the condition that the grain boundary threshold is 10° or less. Note that the crystal grains to be evaluated have an equivalent circle diameter of 3.0 μm or more so that minute crystal grains are not included as the crystal grains to be evaluated. Furthermore, twin grain boundaries are not included as the crystal grains to be evaluated. Note that the "equivalent circle diameter" is the diameter of a circle having the same area as the projected area of ​​the crystal grain.

[0031] The structural integrity of the laminate 20 is evaluated from the area occupied by the crystal grains contained in the laminate 20 in the first region V1. Specifically, the first region V1 is a region extending 4 μm from the main surface 1s. The ratio of the area occupied by crystal grains contained in the first region V1 and having a circular equivalent diameter of 3.0 μm or more is defined as the first area ratio r1. In other words, the first area ratio r1 is the ratio of the area occupied by crystal grains having a circular equivalent diameter of 3.0 μm or more to the area occupied by crystal grains in the first region V1. The first area ratio r1 in the printed wiring board substrate 100 according to the first embodiment is 0.8 or more. In this way, a printed wiring board substrate 100a having improved structural integrity in the laminate 20 is obtained.

[0032] The proportion of the area occupied by crystal grains included in the laminated unit 20 in each of the first region V1 and the second region V2 shown in FIG. 18 may be compared. The second region V2 is a region other than the first region V1 in the cross section of the laminated unit 20. In other words, the second region V2 is a region from the first surface 21s to the first region V1. The proportion of the area occupied by crystal grains included in the second region V2 and having a circle-equivalent diameter of 3.0 μm or more is defined as a second area ratio r2. In other words, the second area ratio r2 is the proportion of the area occupied by crystal grains having a circle-equivalent diameter of 3.0 μm or more in the second region V2.

[0033] The first area ratio r1 may be 0.8 times or more, or 1.0 times or more, of the second area ratio r2.

[0034] (Configuration of a Modified Printed Wiring Board Substrate) FIG. 5 is a cross-sectional view of a modified printed wiring board substrate 100a according to embodiment 1. FIG. 5 corresponds to FIG. 1. The printed wiring board substrate 100b shown in FIG. 5 has a configuration similar to that of the printed wiring board substrate 100a shown in FIG. 1, but differs in that the base layer 2 includes an electroless copper plating layer. Specifically, the base layer 2 includes a first base layer 2a and a second base layer 2b. The first base layer 2a is specifically composed of either a sputtered copper layer or a nano-copper sintered body layer. The first base layer 2a has an intermediate base layer surface s. In the first base layer 2a, the intermediate base layer surface s is the surface opposite the main surface 1s. The second base layer 2b is in contact with the first base layer 2a at the intermediate base layer surface s. The second base layer 2b is, for example, a copper plating formed by electroless plating. In this manner, the base layer 2 is formed.

[0035] The distance Ha in the first direction X from the main surface 1s to the intermediate underlayer surface s (thickness Ha of the first underlayer 2a) may be 0.5 μm or less, or 0.1 μm or less.

[0036] The underlayer 2 does not necessarily have to include the first underlayer 2a. Specifically, the underlayer 2 may be composed of only the second underlayer 2b made of an electroless copper plating layer.

[0037] (Method for Manufacturing a Substrate for a Printed Wiring Board) A method for manufacturing the substrate for a printed wiring board 100b will be described below.

[0038] Fig. 6 is a flowchart illustrating a method for manufacturing the substrate 100b for printed wiring boards. Fig. 6 corresponds to Fig. 2. As shown in Fig. 6, the method for manufacturing the substrate 100b for printed wiring boards includes a step S1b of preparing a base film 1, a step S2b of forming a first underlayer 2a, a step S3b of forming a second underlayer 2b, and a step S4b of annealing the substrate 100b for printed wiring boards.

[0039] Step S2b of forming the first underlayer 2a is performed after step S1b of preparing the base film 1. Step S3b of forming the second underlayer 2b is performed after step S2b of forming the first underlayer 2a. Step S4b of annealing the printed wiring board substrate 100b is performed after step S3b of forming the second underlayer 2b.

[0040] 7 is a cross-sectional view illustrating step S1b of preparing a base film 1. In step S1b of preparing a base film 1, the base film 1 is prepared as shown in FIG. The base film 1 prepared in step S1b of preparing a base film 1 does not have an underlayer 2 disposed on the main surface 1s. Before disposing the underlayer 2, the main surface 1s is subjected to an alkali treatment and an excimer treatment.

[0041] FIG. 8 is a cross-sectional view illustrating step S2b of forming the first underlayer 2a. In step S2b of forming the first underlayer 2a, as shown in FIG. 8, the first underlayer 2a is formed on the main surface 1s. In this step S2b, first, a paste containing copper particles is applied to the main surface 1s. Second, the solvent contained in the applied paste is dried. Third, the dried paste is fired. This sinters the copper particles contained in the dried paste to form the first underlayer 2a. The first underlayer 2a may be formed by heat-treating the paste containing copper particles using a batch-type hot air furnace. When heat-treating the paste containing copper particles using a batch-type hot air furnace, the paste containing copper particles is heat-treated at a firing temperature of 250°C or higher for 30 minutes or more. This promotes sintering between the copper particles. As a result, the growth rate of the copper plating can be made uniform when forming the electroplated layer 3 on the underlayer 2. When a paste containing copper particles is heat-treated using a batch-type hot air furnace, the paste containing copper particles may be heat-treated at a baking temperature of 300°C or higher for 30 minutes or more. The first underlayer 2a may be formed by photo-firing the paste containing copper particles using a flash lamp. When photo-firing the paste containing copper particles using a flash lamp, for example, a flash lamp supplied with a voltage of 2.5 kV irradiates the paste containing copper particles with light for 500 μs. As a result, the copper particles are instantaneously fired. In this way, the thermal load on the main surface 1s is reduced compared to heat treatment using a batch-type hot air furnace, and the copper particles can be fired without reducing the effects obtained by the alkali treatment and excimer treatment performed on the main surface 1s. As a result, the growth rate of the copper plating can be made uniform when forming the electroplated layer 3 on the underlayer 2. The first underlayer 2a may be formed by sputtering. Note that step S2b of forming the first underlayer 2a does not necessarily have to be performed.

[0042] The step S3b of forming the second underlayer 2b is performed using a plating apparatus 300. Fig. 9 is a schematic diagram of the plating apparatus 300 used in the step S3b of forming the second underlayer 2b. As shown in Fig. 9, the plating apparatus 300 includes a plating treatment tank 310, a plurality of rollers 320, electrode rollers 331 and 332, and a power source 340.

[0043] A plating solution is stored in the plating tank 310. The plating solution contains copper. The plating solution may also contain nickel. An electrode 311 is disposed inside the plating tank 310. The electrode 311 is made of a conductive material. The electrode 311 is made of titanium, for example. The electrode 311 is immersed in the plating solution.

[0044] The rollers 320 are aligned along the transport direction (see the arrow in FIG. 9 ) of the base film 1. The base film 1 is transported along the transport direction by rotating the rollers 320. During the transport process, the base film 1 passes through a plating solution stored in a plating treatment tank 310.

[0045] The electrode rollers 331 and 332 are disposed at positions where they come into contact with the base film 1 before it passes through the plating solution. At least one of the electrode rollers 331 and 332 comes into contact with the first underlayer 2 a. The electrode rollers 331 and 332 are made of, for example, stainless steel.

[0046] The power supply 340 is electrically connected to the electrode 311 and the electrode rollers 331 and 332. More specifically, the positive pole of the power supply 340 is electrically connected to the electrode 311, and the negative pole of the power supply 340 is electrically connected to the electrode rollers 331 and 332.

[0047] 10 is a cross-sectional view illustrating step S3b of forming the second underlayer 2b. In step S3b of forming the second underlayer 2b, a power source 340 applies current between the electrode 311 and the electrode rollers 331 and 332. As shown in FIG. 10 , driven by the electrical energy generated by this current application, the second underlayer 2b is rapidly formed on the surface (intermediate underlayer surface s) of the first underlayer 2a. Thereafter, the current application between the electrode 311 and the electrode rollers 331 and 332 is stopped.

[0048] Next, step S4b is performed to anneal the printed wiring board substrate 100b. Specifically, the printed wiring board substrate 100b is annealed for one hour at an annealing temperature of 300°C in an inert gas atmosphere such as nitrogen. As a result, the underlayer 2 is fixed to the base film 1. The oxygen concentration contained in the inert gas may be, for example, 50 ppm or less, or 10 ppm or less. This allows the crystalline state of the copper contained in the underlayer 2 to be uniform.

[0049] In this manner, the substrate 100b for printed wiring boards is manufactured, having the structure shown in Fig. 5. The substrate 100b for printed wiring boards manufactured in this manner has the base layer 2 formed thereon, which can improve the integrity of the structure in the laminate portion 20, similar to the substrate 100a for printed wiring boards.

[0050] (Configuration of Printed Wiring Board) The following describes the configuration of printed wiring board 200. Fig. 11 is a cross-sectional view of printed wiring board 200. As shown in Fig. 11, printed wiring board 200 includes base film 1 and a plurality of laminated portions 20.

[0051] The direction perpendicular to the main surface 1s is defined as a first direction X. The direction perpendicular to the first direction X is defined as a second direction Y. The direction perpendicular to the first direction X and the second direction Y is defined as a third direction Z.

[0052] The plurality of laminated portions 20 are arranged on the main surface 1s. The plurality of laminated portions 20 are formed so as to extend linearly along the second direction Y. The plurality of laminated portions 20 are arranged at equal intervals in the third direction Z. If the shortest distance S between two adjacent laminated portions 20 in the third direction Z and the width L of each of the plurality of laminated portions 20 are less than 2 μm, it will take a long time to form the resist pattern 4 in the step S5 of forming the resist pattern 4, which will be described later. Therefore, as shown in FIG. 11 , the shortest distance S between two adjacent laminated portions 20 in the third direction Z may be 2 μm or more. The width L of each of the plurality of laminated portions 20 may be 2 μm or more.

[0053] Specifically, the plurality of laminated units 20 include adjacent first laminated units 20 a and second laminated units 20 b. The shortest distance S in the third direction Z from the first laminated unit 20 a to the second laminated unit 20 b may be 2 μm or more. The shortest distance S in the third direction Z from the first laminated unit 20 a to the second laminated unit 20 b may be 15 μm or less, or may be 10 μm or less.

[0054] The width L of each of the plurality of laminated portions 20 may be 15 μm or less, or may be 10 μm or less. Specifically, the width L of each of the first laminated portion 20 a and the second laminated portion 20 b may be 15 μm or less, or may be 10 μm or less.

[0055] The laminated portion 20 includes an underlayer 2 and an electrolytically plated layer 3. The underlayer 2 is in contact with the main surface 1s. The electrolytically plated layer 3 is in contact with the underlayer 2. The electrolytically plated layer 3 is a copper layer formed by electrolytic plating.

[0056] (Method of Manufacturing Printed Wiring Board 200) A method of manufacturing the printed wiring board 200 will be described below.

[0057] 12 is a flowchart illustrating a method for manufacturing the printed wiring board 200. The printed wiring board 200 is basically manufactured using a semi-additive process. Specifically, as shown in FIG. 12 , the method for manufacturing the printed wiring board 200 includes a step S5 of forming a resist pattern 4, a step S6 of forming an electrolytic plating layer 3, a step S7 of removing the resist pattern 4, and a step S8 of removing the base layer 2.

[0058] First, step S5 of forming a resist pattern 4 is carried out. In step S5, the resist pattern 4 is formed on the base layer 2. Any method such as photolithography can be used to form the resist pattern 4. Step S6 of forming an electrolytic plated layer 3 is carried out after step S5 of forming the resist pattern 4. Step S7 of removing the resist pattern 4 is carried out after step S6 of forming the electrolytic plated layer 3. Step S8 of removing the base layer 2 is carried out after step S7 of removing the resist pattern 4. The printed wiring board 200 is manufactured using the printed wiring board substrate 100a or the printed wiring board substrate 100b according to the first embodiment.

[0059] 13 is a cross-sectional view illustrating step S5 of forming a resist pattern 4. In step S5 of forming a resist pattern 4, the resist pattern 4 is formed on the underlayer 2 as shown in FIG.

[0060] The resist pattern 4 has openings 4a. The openings 4a are regions where the resist pattern 4 is not formed. The underlying layer 2 is exposed from the openings 4a.

[0061] In step S5 of forming the resist pattern 4, first, a resist in the form of, for example, a film is applied onto the underlayer 2. Second, the resist placed on the underlayer 2 is exposed and developed. As a result, the remaining part of the resist that has not been removed becomes the resist pattern 4, and the removed part of the resist becomes the opening 4a.

[0062] 14 is a cross-sectional view illustrating step S6 of forming the electrolytic plated layer 3. In step S6 of forming the electrolytic plated layer 3, the electrolytic plated layer 3 is formed on the base layer 2 exposed from the opening 4a, as shown in FIG. 14. The electrolytic plated layer 3 is formed by passing a current through the base layer 2 in a plating solution containing copper.

[0063] 15 is a cross-sectional view illustrating step S7 of removing resist pattern 4. In step S7 of removing resist pattern 4, as shown in Fig. 15, resist pattern 4 is removed from underlayer 2. As a result, underlayer 2 is exposed between two adjacent electroplated layers 3.

[0064] In step S8 of removing the base layer 2, the portion of the base layer 2 exposed between two adjacent electroplated layers 3 is removed by etching. Specifically, the base layer 2 is removed using a sulfuric acid-hydrogen peroxide etching solution. If the texture of the base layer 2 and the texture of the electroplated layer 3 are not integrated, the etching rate of the laminate 20 will differ. If the texture of the base layer 2 and the texture of the electroplated layer 3 are not integrated, etching will also progress on the side surface 20s of the laminate 20 before the base layer 2 is etched down to the main surface 1s. As a result, the laminate 20 will have poor rectangularity. By using the printed wiring board substrate 100 according to embodiment 1, the texture integrity of the laminate 20 is improved. Therefore, the etching rate of the laminate 20 in the first direction X is uniform, resulting in a laminate 20 with excellent rectangularity.

[0065] As a result of the above, a printed wiring board 200 having the structure shown in FIG. 11 is formed.

[0066] FIG. 16 is a cross-sectional view of a printed wiring board 200 showing a measurement area for the crystal orientation distribution. The structural integrity of a laminate 20 composed of an underlayer 2 and an electroplated layer 3 is evaluated by the proportion of the area occupied by crystal grains in the laminate 20. As described below, the area occupied by crystal grains in a printed wiring board substrate 100 is measured by EBSD. Specifically, the laminate 20 includes an underlayer 2 and an electroplated layer 3. The underlayer 2 is in contact with the main surface 1s. The electroplated layer 3 is in contact with the underlayer 2. As shown in FIG. 16 , in the cross-section of the laminate 20, a first region V1 is a region extending 4 μm from the main surface 1s. The proportion of the area occupied by crystal grains in the first region V1 that have an equivalent circle diameter of 3.0 μm or more is defined as a first area ratio r1. In other words, the first area ratio r1 is the proportion of the area occupied by crystal grains with an equivalent circle diameter of 3.0 μm or more in the first region V1. The first area ratio r1 in printed wiring board 200 according to the first embodiment is equal to or greater than 0.8. In this manner, printed wiring board 200 with improved structural integrity in laminated portion 20 is obtained.

[0067] The proportion of the area occupied by crystal grains included in the laminated unit 20 in each of the first region V1 and the second region V2 shown in FIG. 16 may be compared. The second region V2 is a region other than the first region V1 in the cross section of the laminated unit 20. In other words, the second region V2 is a region from the first surface 21s to the first region V1. The proportion of the area occupied by crystal grains included in the second region V2 and having a circle-equivalent diameter of 3.0 μm or more is defined as a second area ratio r2. In other words, the second area ratio r2 is the proportion of the area occupied by crystal grains having a circle-equivalent diameter of 3.0 μm or more in the second region V2.

[0068] The first area ratio r1 may be 0.8 times or more, or 1.0 times or more, of the second area ratio r2.

[0069] FIG. 17 is a schematic cross-sectional view of the laminate 20 shown in region XVII of FIG. 11 . Depending on the integrity of the structure of the laminate 20, the width of the laminate 20 may vary in the first direction X. The rectangularity of the laminate 20 is evaluated using a rectangularity evaluation index Et. Specifically, in a cross-section of the laminate 20 perpendicular to the second direction Y, the laminate 20 has a first surface 21s, a second surface 22s, a minimum surface 23s, a maximum surface 24s, and two side surfaces 20s. The first surface 21s is the surface of the laminate 20 farthest from the main surface 1s in the first direction X. The second surface 22s is the surface of the laminate 20 in contact with the main surface 1s. The two side surfaces 20s connect the first surface 21s and the second surface 22s. The minimum surface 23s and the maximum surface 24s may be surfaces located between the first surface 21s and the second surface 22s. The minimum surface 23s and the maximum surface 24s may be surfaces along the main surface 1s. The minimum surface 23s has a minimum width W3. The minimum width W3 is the smallest width in the third direction Z of the stacked portion 20 in the third direction Z. Depending on the etching conditions, the first surface 21s may become the minimum surface 23s. The maximum surface 24s has a maximum width W4. The maximum width W4 is the largest width in the third direction Z of the stacked portion 20 in the third direction Z. Depending on the etching conditions, the second surface 22s may become the maximum surface 24s. In this case, if the rectangularity evaluation index is Et, then Et = W3 / W4.

[0070] The value obtained by dividing the maximum width W4 from the minimum width W3 (i.e., the rectangularity evaluation index Et) may be 0.8 or more. Specifically, the rectangularity evaluation index Et is 0.8 or more. The rectangularity evaluation index Et may be 0.9 or more. In this manner, the rectangularity of the laminated portion 20 is evaluated.

[0071] The rectangularity of the laminate 20 may be evaluated from another perspective. Specifically, the rectangularity of the laminate 20 may be evaluated by either the recess amount L1 or the protrusion amount L2. If the structure of the base layer 2 and the structure of the electroplated layer 3 are not integrated, the shape of the side surface 20s of the laminate 20 may be a V-shape that protrudes inward. Specifically, at least one of the two side surfaces 20s may include a first point p1 and a first recessed point p3a. The first point p1 is the point where the side surface 20s and the first surface 21s intersect. On the side surface 20s, the first recessed point p3a is located on the side where the first surface 21s is located in the third direction Z, as viewed from the first point p1. The first recessed point p3a is located at the position that is the furthest distance from the first point p1 in the third direction Z. From a different perspective, the first recessed point p3a is located at a position that overlaps with the first surface 21s in a plan view viewed from the first direction X. At this time, the recess amount L1 is expressed as L1=l1 / Ht, where l1 is the distance in the third direction Z from the first point p1 to the first recessed point p3a.

[0072] The distance l1 in the third direction Z from the first point p1 to the first recessed point p3a may be 0.15 times or less, 0.10 times or less, or 0.05 times or less of the height Ht of the stacked portion 20 from the main surface 1s to the first surface 21s. Specifically, the recess depth L1 is 0.15 or less. The recess depth L1 may be 0.10 times or less, or 0.05 times or less.

[0073] At least one of the two side surfaces 20s may include a second point p2 and a second recessed point p3b. The second point p2 is the point where the side surface 20s and the second surface 22s intersect. On the side surface 20s, the second recessed point p3b is located on the side where the second surface 22s is located in the third direction Z as viewed from the second point p2. The second recessed point p3b is located at the position that is the longest distance from the second point p2 in the third direction Z. In this case, the protrusion amount L2 is L2 = l2 / Ht. The distance l2 is the distance in the third direction Z from the second point p2 to the second recessed point p3b. The first recessed point p3a is a point for evaluating the recess amount L1, and the second recessed point p3b is a point for evaluating the protrusion amount L2. Furthermore, when the shape of the laminated portion 20 is symmetrical, the first recessed point p3a and the second recessed point p3b on the two side surfaces 20s are arranged at positions that are linearly symmetrical about the central axis (axis of symmetry) of the laminated portion 20.

[0074] The distance l2 in the third direction Z from the second point p2 to the second recessed point p3b may be 0.15 times or less, 0.10 times or less, or 0.05 times or less the height Ht of the stacked portion 20 from the main surface 1s to the first surface 21s. Specifically, the protrusion amount L2 is 0.15 or less. The protrusion amount L2 may be 0.10 or less, or 0.05 or less.

[0075] (Effects) A printed wiring board 200 according to the present disclosure includes a base film 1 and a laminated portion 20. The base film 1 has a main surface 1s. The laminated portion 20 is disposed on the main surface 1s. When a cross section of the laminated portion 20 is measured by electron backscatter diffraction under conditions where the grain boundary threshold is 10° or less, a first area ratio r1 is defined as the proportion of the area occupied by crystal grains having a circle-equivalent diameter of 3 μm or more in a first region V1 extending 4 μm from the main surface 1s. The first area ratio r1 is 0.8 or more.

[0076] In this way, the integrity of the structure in the laminated portion 20 is improved, and a printed wiring board 200 having a circuit with excellent rectangularity can be obtained.

[0077] In the printed wiring board 200, the ratio of the area occupied by crystal grains having a circular equivalent diameter of 3 μm or more in a second region V2 other than the first region V1 in the cross section of the laminate portion 20 is defined as a second area ratio r2. The first area ratio r1 is 0.8 times or more the second area ratio r2.

[0078] In this way, the integrity of the structure in the laminated portion 20 is improved, and a printed wiring board 200 having a circuit with excellent rectangularity can be obtained.

[0079] In the printed wiring board 200, the direction perpendicular to the main surface 1s is defined as the first direction X. The direction perpendicular to the first direction X is defined as the second direction Y. The direction perpendicular to the first direction X and the second direction Y is defined as the third direction Z. The laminated portion 20 is formed to extend linearly along the second direction Y. The laminated portion 20 includes adjacent first laminated portions 20a and second laminated portions 20b. The widths of the first laminated portion 20a and the second laminated portion 20b are each 15 μm or less. The shortest distance S in the third direction Z from the first laminated portion 20a to the second laminated portion 20b is 15 μm or less.

[0080] In this way, a printed wiring board 200 having a fine circuit can be obtained.

[0081] In the printed wiring board 200, the width of each of the first laminated portion 20a and the second laminated portion 20b is 10 μm or less. The shortest distance S in the third direction Z from the first laminated portion 20a to the second laminated portion 20b is 10 μm or less. The width of each of the first laminated portion 20a and the second laminated portion 20b may be 6 μm or less. The shortest distance S in the third direction Z from the first laminated portion 20a to the second laminated portion 20b may be 6 μm or less.

[0082] In this way, a printed wiring board 200 having a fine circuit can be obtained.

[0083] In the printed wiring board 200, the width of each of the first laminated portion 20a and the second laminated portion 20b is 2 μm or more. The shortest distance S in the third direction Z from the first laminated portion 20a to the second laminated portion 20b is 2 μm or more.

[0084] In this way, a printed wiring board 200 having a fine circuit can be obtained.

[0085] In the printed wiring board 200, the laminate portion 20 includes an underlayer 2 and an electrolytic plated layer 3. The underlayer 2 is in contact with the main surface 1 s. The electrolytic plated layer 3 is in contact with the underlayer 2.

[0086] In this way, a printed wiring board 200 having a fine circuit can be obtained.

[0087] In order to verify the effects of the above-described substrate 100 for a printed wiring board and the printed wiring board 200 manufactured from the substrate 100 for a printed wiring board, the following measurements were carried out.

[0088] (Sample Preparation) First, a substrate 500 for printed wiring boards is prepared, in which the material constituting the base film 1 is polyimide. The substrates 500 for printed wiring boards in Samples 1 to 6 are comparative examples. The substrates 500 for printed wiring boards in Samples 7 to 11 are examples. The manufacturing conditions and evaluation results of the substrates 500 for printed wiring boards shown in Samples 1 to 11 are shown in Tables 1 to 4.

[0089]

[0090]

[0091]

[0092]

[0093] The printed wiring board substrate 500 in Sample 1 was not subjected to alkali treatment or excimer treatment as pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of a Ni—Cr seed layer and a sputtered copper layer as the first base layer 2a, and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.006 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.355 μm. The thickness H of the base layer 2 was 0.361 μm. The thickness of the second base layer 2b was the thickness H of the base layer 2 minus the thickness Ha of the first base layer 2a. After the electroless copper plating layer was formed, annealing was not performed.

[0094] The printed wiring board substrate 500 in Sample 2 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.034 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.225 μm. The thickness H of the base layer 2 was 0.259 μm. After the electroless copper plating layer was formed, annealing was not performed.

[0095] The printed wiring board substrate 500 of Sample 3 was subjected to excimer treatment as a pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.041 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.223 μm. The thickness H of the base layer 2 was 0.264 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0096] The printed wiring board substrate 500 of Sample 4 was subjected to only alkali treatment as pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.026 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.185 μm. The thickness H of the base layer 2 was 0.211 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0097] The printed wiring board substrate 500 of Sample 5 was subjected to only excimer treatment as pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of an electroless copper plating layer. The thickness H of the base layer 2 was 1.150 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300° C. for 1 hour.

[0098] The printed wiring board substrate 500 in Sample 6 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.400 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 2.180 μm. The thickness H of the base layer 2 was 2.580 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0099] The printed wiring board substrate 500 of Sample 7 was subjected to alkali treatment and excimer treatment as pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of an electroless copper plating layer. The thickness H of the base layer 2 was 0.452 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300° C. for 1 hour.

[0100] The printed wiring board substrate 500 of Sample 8 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a sputtered copper layer. The thickness H of the base layer 2 was 0.070 μm. After the base layer 2 was formed, annealing was not performed.

[0101] The printed wiring board substrate 500 of Sample 9 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer. The thickness H of the base layer 2 was 0.155 μm. Because an electroless copper plating layer was not formed, annealing was not performed after the formation of the base layer 2.

[0102] The printed wiring board substrate 500 in Sample 10 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.156 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.130 μm. The thickness H of the base layer 2 was 0.286 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0103] The printed wiring board substrate 500 in Sample 11 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.195 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.672 μm. The thickness H of the base layer 2 was 0.867 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0104] By forming an electrolytic plating layer 3 on each of the samples 1 to 11 prepared as described above, a printed wiring board substrate 500 having a laminated portion 20 formed thereon as shown in FIG. 18 is prepared.

[0105] <Evaluation of structural integrity in laminate> The structural integrity in laminate 20 was evaluated using printed wiring board substrate 500 of samples 1 to 11. Fig. 18 is a cross-sectional view of printed wiring board substrate 500 on which electrolytic plated layer 3 is formed, showing the measurement area for crystal orientation distribution. The structural integrity in laminate 20 composed of base layer 2 and electrolytic plated layer 3 is evaluated by the proportion of the area occupied by crystal grains in laminate 20. The area occupied by crystal grains in printed wiring board 200 is measured by EBSD.

[0106] Before measuring the area occupied by the crystal grains by EBSD, the cross section of the printed wiring board substrate 500 having the electrolytic plating layer 3 formed thereon is processed by argon ion polishing. The acceleration voltage of the ion beam is set to, for example, 6 kV.

[0107] Next, the area occupied by the crystal grains in the laminated portion 20 is measured by EBSD. The area occupied by the crystal grains is measured using a Germini 450 manufactured by ZEISS and a Symmetry manufactured by Oxford. The EBSD measurement conditions are as follows: the acceleration voltage is 15 kV; the electron beam irradiation current is 20 nA; the electron beam integration time is 0.8 ms; the tilt angle of the SEM stage is 70°; and the working distance (WD) of the SEM is 15 mm.

[0108] When evaluating the integrity of the structure in the laminated portion 20, the crystal grains to be evaluated by EBSD are measured under the condition that the grain boundary threshold is 10° or less. Note that the crystal grains to be evaluated have a circle equivalent diameter of 3.0 μm or more so that minute crystal grains are not included as the crystal grains to be evaluated. Furthermore, twin grain boundaries are not included as the crystal grains to be evaluated.

[0109] The integrity of the structure in the laminated portion 20 is evaluated from the area occupied by the crystal grains contained in the laminated portion 20 in the first region V1. Specifically, the first region V1 is a region extending from the main surface 1s to 4 μm. The ratio of the area occupied by crystal grains contained in the first region V1 and having an equivalent circle diameter of 3.0 μm or more is defined as a first area ratio r1. In other words, the first area ratio r1 is the ratio of the area occupied by crystal grains having an equivalent circle diameter of 3.0 μm or more in the first region V1.

[0110] When the first area ratio r1 is 0.95 or more, the tissue integrity of the laminated portion 20 is evaluated as A in Tables 1 to 4. When the first area ratio r1 is 0.80 or more and less than 0.95, the tissue integrity of the laminated portion 20 is evaluated as B in Tables 1 to 4. When the first area ratio r1 is 0.70 or more and less than 0.80, the tissue integrity of the laminated portion 20 is evaluated as C in Tables 1 to 4. When the first area ratio r1 is less than 0.70, the tissue integrity of the laminated portion 20 is evaluated as D in Tables 1 to 4.

[0111] In sample 1, the first area ratio r1 was 0.650. In sample 2, the first area ratio r1 was 0.744. In sample 3, the first area ratio r1 was 0.795. In sample 4, the first area ratio r1 was 0.782. In sample 5, the first area ratio r1 was 0.759. In sample 6, the first area ratio r1 was 0.686.

[0112] In Sample 7, the first area ratio r1 was 0.933. In Sample 8, the first area ratio r1 was 0.836. In Sample 9, the first area ratio r1 was 0.993. In Sample 10, the first area ratio r1 was 0.981. In Sample 11, the first area ratio r1 was 0.936.

[0113] From the first area ratio r1 in Samples 1 to 11 described above, as shown in Tables 1 to 4, the evaluation of the tissue integrity in the laminated portion 20 in Samples 1 to 6 is C or D. On the other hand, the evaluation of the tissue integrity in the laminated portion 20 in Samples 7 to 11 is A or B. In particular, the evaluation of the tissue integrity in Samples 9 and 10 is A.

[0114] That is, when an electroless copper plating layer is not formed on the underlayer 2, the structural integrity of the laminate 20 is improved if the pretreatment involves an alkali treatment and an excimer treatment, and the thickness H of the underlayer 2 is 1 μm or less. Alternatively, when the pretreatment involves an alkali treatment and an excimer treatment, and the electroless copper plating layer is formed and then annealed under certain conditions, the structural integrity of the laminate 20 is improved if the thickness H of the underlayer 2 is 1 μm or less. That is, the larger the first area ratio r1, the more the structural integrity of the laminate 20 is improved. As a result, the rectangularity of the laminate 20 in Samples 7 to 11 is improved.

[0115] When neither alkali treatment nor excimer treatment was performed as pretreatment, the structural integrity of the laminated portion 20 was evaluated as D, as in Sample 1. When only either alkali treatment or excimer treatment was performed as pretreatment, the structural integrity of the laminated portion 20 was evaluated as C, as in Samples 3 and 4. When the base layer 2 includes an electroless copper plating layer and the printed wiring board substrate 500 is not annealed after the electroless copper plating layer is formed, the structural integrity of the laminated portion 20 was evaluated as C, as in Sample 2. When the thickness H of the base layer 2 exceeds 1 μm, the structural integrity of the laminated portion 20 was evaluated as C or D, as in Samples 5 and 6.

[0116] As will be described later, when evaluating the integrity of the structure in laminated portion 20 of printed wiring board 200 on which wiring is formed, the target region for the above-described measurements is first region V1 shown in FIG.

[0117] The ratio of the first area ratio r1 to the second area ratio r2 may be used to evaluate the integrity of the structure in the laminated portion 20. The value obtained by dividing the first area ratio r1 by the second area ratio r2 (=r1 / r2) may be 0.8 times or more, or 1.0 times or more, of the second area ratio r2.

[0118] Fig. 19 shows the crystal grain distribution in the laminated portion 20 of Sample 1. Fig. 20 shows the crystal grain distribution in the laminated portion 20 of Sample 7. The crystal grain distributions shown in Fig. 19 and Fig. 20 show the crystal grain boundaries measured by EBSD. As shown in Fig. 19, it can be seen that the crystal grain boundaries are concentrated in the vicinity of the underlayer 2 in Sample 1. On the other hand, as shown in Fig. 20, it can be seen that the crystal grain boundaries are not concentrated in the vicinity of the underlayer 2 in Sample 7.

[0119] <Evaluation of Rectangularity of Laminated Portion> The rectangularity of laminated portion 20 of printed wiring boards 200 manufactured using printed wiring board substrates 500 of Samples 1 to 11 was evaluated.

[0120] The rectangularity of the laminated portion 20 is evaluated using a rectangularity evaluation index Et. As shown in FIG. 17 , the minimum surface 23s and the maximum surface 24s may be surfaces located between the first surface 21s and the second surface 22s. The minimum surface 23s has a minimum width W3. The minimum width W3 is the smallest width of the laminated portion 20 in the third direction Z. The maximum surface 24s has a maximum width W4. The maximum width W4 is the largest width of the laminated portion 20 in the third direction Z. Depending on the etching conditions, the first surface 21s may become the minimum surface 23s. Depending on the etching conditions, the second surface 22s may become the maximum surface 24s. In this case, when the rectangularity evaluation index is Et, Et = W3 / W4.

[0121] When the rectangularity evaluation index Et is 0.9 or more, the rectangularity of the laminated portion is evaluated as A. When the rectangularity evaluation index Et is 0.8 or more and less than 0.9, the rectangularity of the laminated portion is evaluated as B. When the rectangularity evaluation index Et is 0.7 or more and less than 0.8, the rectangularity of the laminated portion is evaluated as C. When the rectangularity evaluation index Et is less than 0.7, the rectangularity of the laminated portion is evaluated as D.

[0122] As shown in Tables 1 to 4, in Samples 1 to 6, the rectangularity of the laminated portion 20 was evaluated as C or D. On the other hand, in Samples 7 to 11, the rectangularity of the laminated portion 20 was evaluated as A or B. In particular, in Samples 9 and 10, the rectangularity of the laminated portion 20 was evaluated as A. This is due to the large influence of the integrity of the structure in the laminated portion 20, as will be described later.

[0123] FIG. 21 shows the crystal grain distribution in the laminate 20 of Sample 1. FIG. 22 shows the crystal grain distribution in the laminate 20 of Sample 7. The crystal grain distributions shown in FIGS. 19 and 20 show grain boundaries measured by EBSD. As shown in FIG. 21 , in Sample 1, the width of the laminate 20 in the third direction Z is not uniform in the first direction X. This is because the structure of the base layer 2 and the structure of the electroplated layer 3 are not integrated, resulting in different etching rates in the laminate 20. On the other hand, in Sample 7, the structure of the base layer 2 and the electroplated layer 3 are integrated, resulting in uniform etching of the base layer 2 and the electroplated layer 3, improving the rectangularity of the laminate 20. Therefore, as shown in FIG. 22 , the width of the laminate 20 is substantially uniform in the first direction X.

[0124] <Evaluation of Fine Wire Formability in Laminated Portion> The fine wire formability in laminated portion 20 of printed wiring board 200 manufactured using printed wiring board substrate 500 of Samples 1 to 11 was evaluated.

[0125] An evaluation TEG was used to evaluate the fine line formability of the laminated portion 20. FIG. 23 is a plan view of the evaluation TEG. As shown in FIG. 23, the evaluation TEG has a base film 1 and a plurality of laminated portions 20. In the evaluation TEG, the main surface 1s has 20 wiring formation regions R1, 20 wiring formation regions R2, and 20 wiring formation regions R3. The 20 wiring formation regions R1, 20 wiring formation regions R2, and 20 wiring formation regions R3 are arranged in a row along the left-right direction.

[0126] A plurality of laminated portions 20 are formed on the wiring formation regions R1, R2, and R3. The laminated portion 20 formed on the wiring formation region R1 extends in the vertical direction (second direction Y in FIG. 23). The laminated portion 20 formed on the wiring formation region R2 and the laminated portion 20 formed on the wiring formation region R3 extend in directions inclined at 45° and −45° with respect to the vertical direction, respectively.

[0127] The L / S of the laminated portion 20 formed on the nth (n is a natural number equal to or less than 20) interconnect formation region R1 from the right is n μm / 100 μm. L is the width of each of the plurality of laminated portions 20. S is the shortest distance between two adjacent laminated portions 20. The L / S of the laminated portions 20 formed on the interconnect formation region R2 and the laminated portions 20 formed on the interconnect formation region R3 is n μm / 100 μm, similar to the L / S formed on the interconnect formation region R1. The aspect ratio of the laminated portion 20 (the value obtained by dividing the height Ht of the laminated portion 20 by the width L of the laminated portion 20) is set to 1 or more and 2 or less.

[0128] For each of the 20 wiring formation regions R1, each of the 20 wiring formation regions R2, and each of the 20 wiring formation regions R3, the stacked portion 20 was observed using a SEM (Scanning Electron Microscope) to determine whether the fine lines had been formed properly.

[0129] In Tables 1 to 4, when the minimum value of the width L of the laminated portion 20 that can be properly formed is 6 μm or less, the evaluation was given as A. When the minimum value of the width L of the laminated portion 20 that can be properly formed is more than 6 μm and not more than 10 μm, the evaluation was given as B. When the minimum value of the width L of the laminated portion 20 that can be properly formed is more than 10 μm and not more than 15 μm, the evaluation was given as C. When the minimum value of the width L of the laminated portion 20 that can be properly formed is more than 15 μm, the evaluation was given as D.

[0130] As shown in Tables 1 to 4, in Samples 5 and 6, the thin-line formability of the laminated portion 20 was evaluated as C or D. On the other hand, in Samples 1 to 4 and Samples 7 to 11, the thin-line formability of the laminated portion 20 was evaluated as A or B. From these results, it is considered that the thin-line formability of the laminated portion 20 is significantly affected by the thickness H of the base layer 2. In Samples 5 and 6, the thickness H of the base layer 2 is greater than 1 μm. On the other hand, in Samples 1 to 4 and Samples 7 to 11, the thickness H of the base layer 2 is less than 1 μm, and therefore the thin-line formability of the laminated portion 20 is good.

[0131] <Overall Evaluation> From the above, it can be seen that the rectangularity of laminated portion 20 of the printed wiring board is improved by improving the integrity of the structure in laminated portion 20. Furthermore, by improving the fine line formability of laminated portion 20, printed wiring board 200 having a fine circuit can be obtained. In particular, the rectangularity and fine line formability of laminated portion 20 in printed wiring boards 200 manufactured using the printed wiring board substrates of Samples 9 and 10 are good.

[0132] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The basic scope of the present disclosure is defined by the claims, not the above-described embodiments, and is intended to include all modifications within the meaning and scope of the claims.

[0133] 1 base film, 1s main surface, 2 underlayer, 2a first underlayer, 2b second underlayer, 2s underlayer surface, 3 electrolytic plating layer, 4 resist pattern, 4a opening, 20 laminated portion, 20a first laminated portion, 20b second laminated portion, 20s side, 21s first surface, 22s second surface, 23s smallest surface, 24s largest surface, 100, 100a, 100b, 500 printed wiring board substrate, 200 printed wiring board, 300 plating apparatus, 310 plating treatment tank, 311 electrode, 320 roller, 331, 332 electrode roller, 340 power supply, r1 first area ratio, r2 second area ratio, Et rectangularity evaluation index, H, Ha, l1, l2 distance, H, Ha thickness, Ht height, L width, L1 Recess amount, L2 protrusion amount, R1, R2, R3 wiring formation area, S shortest distance, V1 first area, V2 second area, W3 minimum width, W4 maximum width, X first direction, Y second direction, Z third direction, p1 first point, p2 second point, p3a first recess point, p3b second recess point, s intermediate base layer surface.

Claims

1. A printed wiring board comprising: a base film having a principal surface; and a laminate portion disposed on said principal surface; wherein, when a cross section of said laminate portion is measured by electron backscatter diffraction under the condition that the grain boundary threshold is 10° or less, the first area ratio is defined as the proportion of the area occupied by crystal grains having a circular equivalent diameter of 3 μm or more in a first region extending from said principal surface to 4 μm, and said first area ratio is 0.8 or more.

2. The printed wiring board according to claim 1, wherein, in a second region other than the first region in the cross section of the laminate, the proportion of the area occupied by crystal grains having a circle equivalent diameter of 3 μm or more is defined as a second area ratio, and the first area ratio is 0.8 times or more of the second area ratio.

3. The printed wiring board according to claim 1 or 2, wherein a direction perpendicular to said main surface is defined as a first direction, a direction perpendicular to said first direction is defined as a second direction, and a direction perpendicular to said first direction and said second direction is defined as a third direction, said laminate portion is formed to extend linearly along said second direction, and further said laminate portion includes adjacent first laminate portion and second laminate portion, each of said first laminate portion and said second laminate portion has a width of 15 μm or less, and the shortest distance in said third direction from said first laminate portion to said second laminate portion is 15 μm or less.

4. The printed wiring board according to claim 3, wherein the width of each of the first laminated portion and the second laminated portion is 10 μm or less, and the shortest distance in the third direction from the first laminated portion to the second laminated portion is 10 μm or less.

5. A printed wiring board as set forth in claim 3 or claim 4, wherein the width of each of the first laminated portion and the second laminated portion is 2 μm or more, and the shortest distance in the third direction from the first laminated portion to the second laminated portion is 2 μm or more.

6. A printed wiring board according to any one of claims 1 to 5, wherein the laminated portion includes an underlayer in contact with the main surface and an electrolytic plating layer in contact with the underlayer.

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