Structure, quantum processor, quantum computer, and method for manufacturing structure

Abstract

A structure according to the present disclosure comprises: a laminate in which a plurality of substrates containing a monocrystalline ceramic are laminated, and which has a first surface, a second surface opposite to the first surface, and a through-hole that penetrates the laminate from the first surface to the second surface; and a conductor layer positioned on the inner circumferential surface of the through-hole.

Description

Structure, quantum processor, quantum computer, and method for manufacturing structure

[0001] The present disclosure relates to structures, quantum processors, quantum computers, and methods for manufacturing structures.

[0002] 2. Description of the Related Art Conventionally, a through silicon via (TSV) technology has been known as a technology for increasing the integration density of integrated circuits (see, for example, Patent Document 1).

[0003] International Publication No. 2017 / 141547

[0004] The structure of the present disclosure comprises a laminate formed by stacking a plurality of substrates including a single crystal ceramic, the laminate having a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface, and a conductive layer located on the inner circumferential surface of the through hole.

[0005] The method for manufacturing the structure of the present disclosure includes a fabrication step of stacking a plurality of single crystal ceramic substrates, each having a substrate through-hole penetrating in the thickness direction, to produce a laminate having through-holes penetrating in the stacking direction of the plurality of substrates, and a film formation step of forming a conductive layer on the inner surface of the through-hole.

[0006] Objects, features, and advantages of the present disclosure will become more apparent from the following detailed description and drawings.

[0023] FIG. 1 is a plan view showing an example of a structure according to an embodiment of the present disclosure.

[0024] FIG. 2 is a cross-sectional view taken along the section line II-II of FIG. 1.

[0025] FIG. 3 is a cross-sectional view showing another example of a structure according to an embodiment of the present disclosure.

[0026] FIG. 4 is a cross-sectional view showing another example of a structure according to an embodiment of the present disclosure.

[0027] FIG. 5 is a cross-sectional view showing another example of a structure according to an embodiment of the present disclosure.

[0028] FIG. 6 is a cross-sectional view showing another example of a structure according to an embodiment of the present disclosure.

[0029] FIG. 7 is a cross-sectional view showing another example of a structure according to an embodiment of the present disclosure.

[0030] FIG. 8 is a plan view showing an example of a superconducting qubit circuit included in the quantum processor of FIG. 8.

[0031] FIG. 9 is a perspective view showing an example of a Josephson junction element included in the superconducting qubit circuit of FIG. 9.

[0032] FIG. 9 is a block diagram showing an example of a quantum computer according to an embodiment of the present disclosure.

[0033] FIG. 10 is a diagram illustrating a method for manufacturing a structure according to an embodiment of the present disclosure.

[0034] FIG. 11 is a diagram illustrating a method for manufacturing a structure according to an embodiment of the present disclosure.

[0035] FIG. 12 is a diagram illustrating a method for manufacturing a structure according to an embodiment of the present disclosure.

[0036] FIG. 13 is a diagram illustrating a method for manufacturing a structure according to an embodiment of the present disclosure.

[0007] In recent years, various quantum processors equipped with quantum bit circuits have been proposed. The quantum bit circuits are generally formed on a silicon substrate, and the quantum bit circuits are electromagnetically connected to external circuits via silicon through-hole electrodes (see Patent Document 1) that penetrate the silicon substrate.

[0008] To improve the performance of quantum processors, it is desirable to reduce the electrical and thermal losses in quantum processors.

[0009] Hereinafter, structures, quantum processors, quantum computers, and methods for manufacturing structures according to embodiments of the present disclosure will be described with reference to the drawings. The figures referred to below are schematic, and the dimensional ratios and the like in the figures do not necessarily correspond to the actual ones. In this specification, for convenience, a Cartesian coordinate system XYZ is defined in some of the figures. The X-axis and Y-axis indicate mutually orthogonal planar directions, and the Z-axis indicates the height direction. The X-axis direction is also referred to as the first direction. The Y-axis direction is also referred to as the second direction. The Z-axis direction is also referred to as the third direction or thickness direction. In this specification, the positive direction of the Z-axis direction is defined as upward, and terms such as upper surface and lower surface may be used.

[0010] Fig. 1 is a plan view showing an example of a structure according to an embodiment of the present disclosure, Fig. 2 is a cross-sectional view taken along the line II-II in Fig. 1, and Figs. 3 to 7 are cross-sectional views showing other examples of a structure according to an embodiment of the present disclosure. The cross-sectional views shown in Figs. 3 to 7 correspond to the cross-sectional view shown in Fig. 2.

[0011] 1 and 2, a structure 1 of this embodiment includes a stacked body 2 and a conductive layer 4. A quantum bit circuit can be mounted on the structure 1. A quantum processor including the structure 1 is used in an environment cooled to an extremely low temperature of about several mK.

[0012] The stack 2 is formed by stacking multiple substrates 3 in a predetermined stacking direction (Z-axis direction). The stack 2 has a first surface 2a, a second surface 2b opposite to the first surface 2a, and a third surface (also referred to as a side surface) 2c connecting the first surface 2a and the second surface 2b. The stack 2 may have a thickness T2 of, for example, approximately 0.05 to 1.0 mm, or may have a thickness T2 of approximately 0.3 mm. The quantum bit circuit may be mounted on the first surface 2a.

[0013] The laminate 2 has a through hole 21 that penetrates from the first surface 2a to the second surface 2b. The through hole 21 has a first opening 21a on the first surface 2a and a second opening 21b on the second surface 2b. The first opening 21a and the second opening 21b may be, for example, circular, elliptical, oblong, or other shapes, but the following describes an example in which the first opening 21a and the second opening 21b are circular. The opening diameter da of the first opening 21a and the opening diameter db of the second opening 21b may be the same or different. Hereinafter, when there is no need to distinguish between the first opening 21a and the second opening 21b, they may be referred to as openings 21a and 21b.

[0014] The through hole 21 may have a configuration in which the shape of the opening when viewed in a cross section parallel to the first surface 2a is similar to the shape of the first opening 21a and the second opening 21b in a plan view. As shown in Fig. 2, the through hole 21 may have a shape in which the opening diameter (also referred to as inner diameter) d when viewed in a cross section parallel to the first surface 2a is constant in the thickness direction (also referred to as a straight shape).

[0015] The through-hole 21 does not have to have a shape in which the opening diameter d is constant in the thickness direction. As shown in Fig. 3, the through-hole 21 may have a shape in which the opening diameter d gradually increases or decreases (tapered shape) in the thickness direction of the laminate 2. Fig. 3 shows an example in which the opening diameter d gradually decreases from the first opening 21a to the second opening 21b, but the opening diameter d may also gradually increase from the first opening 21a to the second opening 21b.

[0016] As shown in FIG. 4, the through hole 21 may have a narrowed portion 21d located between the first opening 21a and the second opening 21b. The narrowed portion 21d is the portion of the through hole 21 where the opening diameter d is smallest, and the opening diameter d at the narrowed portion 21d is smaller than the opening diameters da and db. The narrowed portion 21d may be located at a depth from the first surface 2a of approximately 0.3×T2 to 0.7×T2, or may be located at a depth of approximately 0.5×T2. The opening diameter d at the narrowed portion 21d may be approximately 0.5 to 0.9 times the opening diameters da and db.

[0017] The through holes 21 may have an aspect ratio of, for example, 5 or more, or 7 or more. The aspect ratio of the through holes 21 may be, for example, a value obtained by dividing the thickness T2 of the stack 2 by the larger of the opening diameters 21a and 21b. When the aspect ratio of the through holes 21 is 5 or more, the number of through holes 21 per unit area of ​​the first surface 2a can be increased. As a result, it is possible to highly integrate quantum bits.

[0018] The substrates 3 constituting the laminate 2 have a fourth surface 3a and a fifth surface 3b opposite to the fourth surface 3a. The substrates 3 have through holes (hereinafter also referred to as substrate through holes) 3c penetrating from the fourth surface 3a to the fifth surface 3b. The multiple substrates 3 are stacked so that the multiple substrate through holes 3c communicate with each other in the stacking direction and form through holes 21 of the laminate 2. While Fig. 2 shows an example in which the laminate 2 is composed of three substrates 3, this is not limiting. The laminate 2 may be composed of two substrates 3, or four or more substrates 3.

[0019] The substrate 3 may have, for example, a polygonal, circular, elliptical, or other shape in a plan view. Polygonal shapes include triangular, rectangular, pentagonal, hexagonal, etc. Multiple substrates 3 may be stacked such that their outer edges coincide with each other in a plan view.

[0020] The substrate 3 includes a single crystal ceramic. The substrate 3 is made of single crystal sapphire (Al ２ O ３ The substrate 3 is not limited to a sapphire substrate, and may be a ceramic substrate containing a ceramic material such as aluminum oxide, mullite, silicon carbide, aluminum nitride, or magnesium oxide.

[0021] The substrate 3 may have a thickness T3 of, for example, about 0.015 mm to 0.5 mm. The multiple substrates 3 may have the same thickness T3, or may have different thicknesses T3. The substrate through-hole 3c may have an inner diameter d' of, for example, about 0.01 mm to 0.1 mm. The substrate through-hole 3c may have a larger inner diameter d' as the thickness T3 of the substrate 3 increases. The substrate through-hole 3c may have a shape in which the inner diameter d' is constant in the thickness direction of the substrate 3.

[0022] The substrates 3 may have the same inner diameter d' of the substrate through holes 3c, in which case a laminate 2 having straight through holes 21 (see FIG. 2) can be formed. The substrates 3 may have different inner diameters d' of the substrate through holes 3c, in which case a laminate 2 having tapered through holes 21 (see FIG. 3) and a laminate 2 having a through hole 21 with a narrowed portion 21d (see FIG. 4) can be formed.

[0023] The conductor layer 4 is located on the inner circumferential surface 21c of the through hole 21 of the laminate 2. The conductor layer 4 is located from the first opening 21a to the second opening 21b. The conductor layer 4 can electrically connect the quantum bit circuit located on the first surface 2a to an external circuit (interposer). The conductor layer 4 may cover the entire inner circumferential surface 21c. The conductor layer 4 may be located so as to cover the entire inner circumferential surface 21c. In this case, the quantum bit circuit and the external circuit can be electrically connected well, thereby stabilizing the operation of the quantum processor. The conductor layer 4 may be located from the inner circumferential surface 21c to at least one of the first surface 2a and the second surface 2b. Connecting the quantum bit circuit and the external circuit with the conductor layer 4 extending in the thickness direction of the laminate 2 allows for high integration of the quantum bit circuit.

[0024] The conductor layer 4 may be made of a superconductor such as niobium (Nb), aluminum (Al), molybdenum (Mo), tungsten (W), or titanium nitride (TiN). The conductor layer 4 may have a thickness of, for example, about 0.1 μm to 2.0 μm. The thickness of the conductor layer 4 may be the thickness of the conductor layer 4 in the plane direction of the first surface 2 a (the XY plane direction).

[0025] In the structure 1, the plurality of substrates 3 are single-crystal ceramic substrates with low dielectric loss (tan δ) and high thermal conductivity, which reduces electrical and thermal losses in the quantum processor, thereby extending the coherence time of the quantum processor and improving the capabilities of the quantum processor and quantum computer.

[0026] When the substrates 3 are sapphire substrates with low dielectric loss and high thermal conductivity, the structure 1 can effectively reduce electrical and thermal losses in the quantum processor, thereby extending the coherence time of the quantum processor and improving the capabilities of the quantum processor and quantum computer.

[0027] When the plurality of substrates 3 are sapphire substrates and the conductive layer 4 is made of titanium nitride, the structure 1 can effectively reduce electrical and thermal losses in the quantum processor and can also improve the quality (high crystallinity, layer thickness with little variation, etc.) of the conductive layer 4. As a result, the coherence time of the quantum processor can be extended, and the capabilities of the quantum processor and quantum computer can be improved.

[0028] As shown in FIGS. 3 to 5 , the structure 1 may have an internal conductor layer 5 located inside the stack 2. The internal conductor layer 5 may be located between adjacent substrates 3 in the stacking direction. The internal conductor layer 5 may be electromagnetically connected to the conductor layer 4. The internal conductor layer 5 may have a wiring pattern according to the circuit characteristics of the quantum bit circuit and the interposer (see FIG. 8 ). In this case, electrical loss and thermal loss in the quantum processor can be reduced and the coherence time can be extended. As a result, the performance of the quantum processor can be improved.

[0029] The internal conductor layer 5 may include a through electrode that penetrates at least one substrate 3 and connects wiring patterns located at different positions in the stacking direction. In this case, the degree of freedom of the wiring pattern of the internal conductor layer 5 can be increased, and the wiring pattern of the internal conductor layer 5 can be made to correspond to the circuit characteristics of the quantum bit circuit and the interposer. As a result, the electrical loss and thermal loss of the quantum processor can be reduced and the coherence time can be extended. Therefore, the performance of the quantum processor can be improved.

[0030] The internal conductive layer 5 may be made of a superconductor such as Nb, Al, Mo, W, or TiN. The internal conductive layer 5 may have a thickness of, for example, about 0.1 μm to 2.0 μm.

[0031] 5 , the structure 1 may have a columnar body 6 located inside the conductor layer 4 in the through hole 21. The outer peripheral surface of the columnar body 6 may be in contact with the inner peripheral surface of the conductor layer 4. The columnar body 6 may be made of a metal material or a resin material.

[0032] The pillars 6 may be made of an alloy containing copper, or may be made of copper. Copper has a relatively high thermal conductivity at the temperature (about several mK) at which the quantum processor is operated. Therefore, when the pillars 6 contain copper, thermal loss in the quantum processor can be effectively reduced. As a result, the coherence time of the quantum processor can be extended, and the performance of the quantum processor can be improved.

[0033] The upper surfaces of the pillars 6 may be substantially flush with the first surface 2a of the laminate 2. The quantum bit circuit can be formed using photolithography and etching techniques, but if the upper surfaces of the pillars 6 are substantially flush with the first surface 2a of the laminate 2, it becomes easier to form a resist film on the first surface 2a, and as a result, it becomes easier to form a circuit pattern for the quantum bit circuit. Furthermore, the upper and lower surfaces of the pillars 6 may be substantially flush with the first surface 2a and the second surface 2b of the laminate 2, respectively. In this case, it becomes easier to suction the structure 1 using a suction nozzle or the like in the manufacturing process of the quantum processor, and the handleability of the structure 1 can be improved.

[0034] The multiple substrates 3 may be fixed to one another only by the conductive layer 4 located on the inner circumferential surface 21c of the through-hole 21. In this case, the influence of the mutual fixing of the multiple substrates 3 on the properties of the substrates 3 (e.g., dielectric loss tangent, thermal conductivity, etc.) can be reduced, thereby reducing electrical loss and thermal loss in the quantum processor and extending the coherence time. As a result, it is possible to improve the capabilities of the quantum processor and quantum computer.

[0035] The multiple substrates 3 may be bonded together when the substrates 3 are adjacent to each other in the stacking direction. The substrates 3 may be diffusion bonded together when the substrates 3 are adjacent to each other in the stacking direction. In this case, the multiple substrates 3 can be fixed to each other well, thereby improving the reliability of the quantum processor. Furthermore, the effect of fixing the multiple substrates 3 to each other on the characteristics of the substrates 3 can be reduced, thereby reducing electrical loss and thermal loss in the quantum processor and extending the coherence time. As a result, the performance of the quantum processor can be improved.

[0036] 6, the structure 1 may include an adhesive layer 7 located on the side surface 2c of the laminate 2. The multiple substrates 3 may be fixed to one another by the adhesive layer 7. In this case, the multiple substrates 3 can be fixed to one another well, thereby improving the reliability of the quantum processor. The adhesive layer 7 may be made of a thermosetting resin such as an epoxy resin or a phenolic resin.

[0037] As shown in Fig. 7, the structure 1 may include fastening parts 8 that mechanically fasten the outer edges of the plurality of substrates 3 together. The plurality of substrates 3 may be fixed to one another by the fastening parts 8. In this case, the plurality of substrates 3 can be fixed to one another satisfactorily, thereby improving the reliability of the quantum processor. The fastening parts 8 may be, for example, clips, screws, etc. The fastening parts 8 may be made of a metal material or a resin material.

[0038] Next, a quantum processor according to the present disclosure will be described. Fig. 8 is a cross-sectional view showing an example of a quantum processor according to an embodiment of the present disclosure, Fig. 9 is a plan view showing an example of a quantum bit circuit included in the quantum processor of Fig. 8, and Fig. 10 is a perspective view showing an example of a Josephson junction element included in the quantum bit circuit of Fig. 9.

[0039] The quantum processor 30 of this embodiment includes a quantum chip 31, an interposer 39, and a wiring substrate 42. The quantum chip 31, the interposer 39, and the wiring substrate 42 may be stacked in this order as shown in Fig. 8. The quantum processor 30 may include a support substrate 45 as shown in Fig. 8. The quantum chip 31, the interposer 39, and the wiring substrate 42 may be located on the support substrate 45.

[0040] 8, the quantum chip 31 includes a structure 1 and a quantum bit circuit 32. The quantum bit circuit 32 is mounted on the structure 1.

[0041] 9 , the quantum bit circuit 32 may include a quantum bit 33, a readout resonator 34, an inter-quantum bit coupling capacitor 35, and a detection electrode 46. The quantum bit 33, the readout resonator 34, and the inter-quantum bit coupling capacitor 35 may be mounted on the first surface 2 a of the stack 2.

[0042] The quantum bit 33 may include, for example, a central electrode 36, an annular electrode 37 surrounding the central electrode 36, and a Josephson junction element 38 connecting the central electrode 36 and the annular electrode 37. The central electrode 36 and the annular electrode 37 may be made of a superconductor such as niobium, aluminum, molybdenum, tungsten, or titanium nitride. The central electrode 36 may include a conductive layer 4. As shown in FIG. 10 , the Josephson junction element 38 has a structure in which an insulating thin film 38a is sandwiched between superconductors 38b and 38c. The insulating thin film 38a may be made of an oxide of aluminum, tantalum (Ta), titanium, or the like, and the superconductors 38b and 38c may be made of aluminum, tantalum, titanium, or the like. The quantum bit 33 can essentially form a two-level system and can maintain, for example, a quantum state (coherence state) composed of a ground state and a first excited state. The quantum bit 33 is not limited to the concentric quantum bit shown in FIG. 9. The quantum bit 33 may be configured to include, for example, a cross-shaped electrode, an adjacent electrode located adjacent to the cross-shaped electrode, and a Josephson junction element connecting the cross-shaped electrode and the adjacent electrode.

[0043] The readout resonator 34 is electromagnetically coupled to the quantum bit 33. The readout resonator 34 is configured to read out the quantum state held in the quantum bit 33. The state of the quantum bit 33 read out by the readout resonator 34 may be extracted as a detection signal to the outside of the quantum bit circuit 32 via the detection electrode 46. The detection signal may be extracted to the outside of the quantum bit circuit 32 via a conductive structure formed by the detection electrode 46 and the conductor layer 4. The readout resonator 34 is not limited to the meandering resonator shown in FIG. 9. The readout resonator 34 may be, for example, a linear resonator or a U-shaped resonator. The inter-qubit coupling capacitor 35 couples adjacent quantum bits 33 to each other.

[0044] The quantum bit circuit 32 may include a relaxation-reduction filter resonator (not shown) that reduces relaxation of the quantum bit 33. In this case, it is possible to reduce the damage to the quantum state of the quantum bit 33 caused by electromagnetic noise, thermal noise, etc., and therefore it is possible to extend the coherence time of the quantum bit circuit 32.

[0045] The quantum chip 31 may include a control circuit (not shown) for controlling the quantum bits 33. The control circuit may be located on the second surface 2b of the stack 2. The control circuit may be connected to the quantum bit circuit 32 via the conductive layer 4. The control circuit may be located on or inside the surface of the interposer 39, or on or inside the surface of the wiring substrate 42.

[0046] The interposer 39 may be made of, for example, single crystal silicon, a ceramic material, etc. The ceramic material used for the interposer 39 may be, for example, aluminum oxide, mullite, silicon carbide, aluminum nitride, magnesium oxide, etc. The interposer 39 may be made of low temperature co-fired ceramics (LTCC) and may have wiring conductors inside for controlling the quantum bit 33 circuit.

[0047] The interposer 39 has a third surface 39 a and a fourth surface 39 b opposite to the third surface 39 a. The interposer 39 is positioned such that the third surface 39 a faces the second surface 2 b of the laminate 2.

[0048] The interposer 39 has a through hole 40 that penetrates from the third surface 39a to the fourth surface 39b. The interposer 39 has a conductive layer 41 located on the inner surface of the through hole 40. The conductive layer 41 may be located from the inner surface of the through hole 40 to the third surface 39a and the fourth surface 39b. The upper end of the conductive layer 41 may be connected to the conductive layer 4 of the structure 1. The lower end of the conductive layer 41 may be connected to the wiring conductors 43, 44 of the wiring substrate 42. The conductive layer 41 may be a superconductor. The conductive layer 41 may be made of a superconductor such as niobium, aluminum, molybdenum, tungsten, or titanium nitride.

[0049] The interposer 39 does not need to have the conductive layer 41. The interposer 39 may have a wire located in the through hole 40, the upper end of which is electrically connected to the conductive layer 4, and the lower end of which is electrically connected to the wiring conductors 43 and 44. The wire may be made of a superconductor such as Nb, Al, Mo, W, or TiN. At least a portion of the outer circumferential surface of the wire may contact the inner circumferential surface of the through hole 40, and the wire may be fixed to the inner circumferential surface of the through hole 40 by friction.

[0050] The wiring board 42 may be composed of, for example, a printed wiring board, a ceramic wiring board, an organic wiring board, or the like. Wiring conductors 43 and 44 are located inside the wiring board 42. The wiring conductors 43 and 44 may include the wiring conductor 43 made of a superconductor and the wiring conductor 44 made of a normal conductor. The superconductor used for the wiring conductor 43 may be, for example, niobium, aluminum, molybdenum, tungsten, titanium nitride, or the like. The normal conducting material used for the wiring conductor 44 may be, for example, copper, silver (Ag), or the like.

[0051] The support substrate 45 may be made of a metal material such as copper, titanium, etc. The quantum chip 31, the interposer 39, and the wiring substrate 42 may be fixed within the freezing space of the refrigerator via the support substrate 45.

[0052] The quantum processor 30 includes the structure 1 that allows for easy three-dimensional mounting of the quantum chip 31 on the interposer 39 and wiring substrate 42, thereby enabling high integration and multi-bit operation of the quantum processor 30. Furthermore, the quantum processor 30 includes the laminate 2 in the structure 1 that is made of single crystal sapphire with a low dielectric loss tangent, thereby enabling the coherence time of the quantum bit circuit 32 to be extended and noise generated in the quantum bit circuit 32 to be reduced. Therefore, the quantum processor 30 can operate stably.

[0053] Next, a quantum computer according to an embodiment of the present disclosure will be described. Fig. 11 is a block diagram illustrating a quantum computer according to an embodiment of the present disclosure.

[0054] As shown in Fig. 11 , the quantum computer 50 of this embodiment includes a quantum processor 30. As shown in Fig. 11 , the quantum computer 50 may include a refrigerator 51, microwave amplifiers 52 and 53, a circulator 54, a cryogenic noise filter 55, a coaxial cable connector 56, a microwave input / output device 57, and a control computer 58.

[0055] The refrigerator 51 has a refrigeration space 51a. The quantum processor 30, microwave amplifiers 52 and 53, circulator 54, cryogenic noise filter 55, and coaxial cable connector 56 are located within the refrigeration space 51a. The microwave input / output device 57 and control computer 58 are located outside the refrigeration space 51a. The refrigerator 51 cools the refrigeration space 51a to a temperature below (or equal to) the transition temperature of the superconducting material that constitutes the quantum processor 30. The transition temperature is the phase transition temperature between the normal conducting phase and the superconducting phase. The refrigerator 51 may be configured as a dilution refrigerator. A dilution refrigerator is a refrigerator that cools a liquid phase ４ He in liquid phase ３ This refrigerator utilizes the heat of dilution generated when diluting with He.

[0056] The quantum processor 30 may be located in a region of the refrigerated space 51a that is particularly low temperature (for example, about several mK). This reduces thermal loss in the quantum processor 30, thereby extending the coherence time of the quantum processor 30 and enabling stable operation of the quantum processor 30. The refrigerator 51 may include a vacuum pump that reduces the pressure in the refrigerated space 51a. By reducing the pressure in the refrigerated space 51a, temperature changes around the quantum processor 30 can be reduced, thereby stabilizing operation of the quantum processor 30.

[0057] Control computer 58 generates control signals for controlling quantum processor 30, and the control signals are supplied to quantum processor 30 via microwave input / output device 57, coaxial cable connector 56, and cryogenic noise filter 55. Quantum processor 30 performs quantum computation based on the control signals supplied from control computer 58. The computation results are output to control computer 58 via the microwave controller and microwave input / output device 57.

[0058] The quantum computer 50 is highly integrated (i.e., miniaturized) because the quantum processor 30 includes the structure 1. Therefore, even if the volume of the freezing space 51a of the refrigerator 51 is limited, it is easy to place the quantum processor 30 in a region of the freezing space 51a that is particularly cold. As a result, the operation of the quantum processor 30 can be stabilized. Furthermore, because the quantum processor 30 of the quantum computer 50 is configured to include the structure 1, the operation of the quantum processor 30 can be stabilized.

[0059] Next, an example of a method for manufacturing a structure according to an embodiment of the present disclosure will be described. Figures 12 to 19 are views illustrating a method for manufacturing a structure according to an embodiment of the present disclosure.

[0060] The method for manufacturing the structure 1 of this embodiment includes a fabrication step and a film formation step.

[0061] The fabrication process is a process for fabricating a laminate 2 having through holes 21. In the fabrication process, first, a substrate precursor 100 that will become the substrate 3 is prepared. Then, through holes that will become the substrate through holes 3c are formed in the substrate precursor 100 to fabricate the substrate 3 (see FIG. 13 ). The substrate precursor 100 may be a sapphire substrate, or a ceramic substrate containing a ceramic material such as aluminum oxide, mullite, silicon carbide, aluminum nitride, or magnesium oxide. In the fabrication process, the thickness T100 of the substrate precursor 100 may be adjusted by polishing the substrate precursor 100. Adjusting the thickness T100 of the substrate precursor 100 makes it possible to adjust the inner diameter of the through holes formed in the substrate precursor 100 (i.e., the inner diameter d' of the substrate through holes 3c). Furthermore, adjusting the surface roughness of the upper surface 100a and the lower surface 100b of the substrate precursor 100 makes it possible to favorably form the quantum bit circuit 32, the internal conductor layer 5, and the like.

[0062] The through holes that become the substrate through holes 3c can be formed by laser processing in which laser light L is irradiated onto the substrate precursor 100, as shown in FIG. 12 . Laser processing can be performed using, for example, a fiber laser, a YAG (Yttrium Aluminum Garnet) laser, an excimer laser, or the like. The power of the laser light L may be approximately 1 to 100 W, or may be approximately 1 to 10 W. The frequency of the laser light L may be approximately 1 to 100 kHz. Note that the method for forming the through holes is not limited to laser processing. The through holes may also be formed using an etching technique such as reactive ion etching (RIE).

[0063] When forming a through hole in the substrate precursor 100 by laser processing, the inner diameter of the through hole can be adjusted by adjusting the thickness T100 of the substrate precursor 100. The thicker the thickness T100 of the substrate precursor 100, the larger the inner diameter of the through hole can be, and the thinner the thickness T100 of the substrate precursor 100, the smaller the inner diameter of the through hole can be.

[0064] Next, the plurality of substrates 3 are stacked to produce the laminate 2. In the production process, as shown in Fig. 14, the plurality of substrates 3 are stacked so that the plurality of substrate through holes 3c communicate in the stacking direction to form through holes 21. Note that in the production process, it is sufficient to stack the plurality of substrates 3 on top of each other, and the plurality of substrates 3 do not need to be fixed to each other.

[0065] 15 , the film formation step is a step of forming a conductor layer 4 on the inner circumferential surface 21 c of the through hole 21. In the film formation step, the conductor layer 4 may be formed so as to be located only on the inner circumferential surface 21 c of the through hole 21, or the conductor layer 4 may be formed so as to be located from the inner circumferential surface 21 c to at least one of the first surface 2 a and the second surface 2 b.

[0066] In the film formation step, the conductor layer 4 may be formed by a thin film formation method such as a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method. The CVD method may be, for example, a thermal CVD method, a plasma CVD method, or an atomic layer deposition (ALD) method.

[0067] In the film formation step, the conductor layer 4 may be formed by a CVD method. In this case, by appropriately selecting the type of source gas, the type of carrier gas, the film formation temperature, the film formation time, etc., it is possible to form a high-quality conductor layer 4 (highly crystalline and with little variation in layer thickness).

[0068] In this manner, the structure 1 can be manufactured. In the manufacturing process, stacking a plurality of substrates 3 having the same inner diameter d' of the substrate through holes 3c can produce a laminate 2 having a straight through hole 21 (see FIG. 2). Stacking a plurality of substrates 3 having different inner diameters d' of the substrate through holes 3c can produce a laminate 2 having a tapered through hole 21 (see FIG. 3) or a laminate 2 having a through hole 21 with a narrowed portion 21d (see FIG. 4). When stacking a plurality of substrates 3 having different inner diameters d' of the substrate through holes 3c, misalignment of the plurality of substrate through holes 3c can be reduced.

[0069] The method for manufacturing the structure 1 may include a pressurizing step. The pressurizing step is a step of diffusion-bonding the substrates 3 adjacent to each other in the stacking direction, and is performed between the fabrication step and the film-forming step. In the pressurizing step, as shown in FIG. 16 , a stacked body 2 formed by stacking the substrates 3 is heated and pressurized in the stacking direction. In the pressurizing step, the stacked body 2 may be heated to a temperature of, for example, room temperature to 2000° C. Furthermore, in the pressurizing step, the stacked body 2 may be pressed in the stacking direction at a pressure of, for example, 50 MPa to 1000 MPa. In the pressurizing step, pressure and heat may be applied uniformly to the substrate 3 located at the top of the stacked body 2. In this case, the substrates 3 adjacent to each other in the stacking direction can be favorably diffusion-bonded to each other.

[0070] The fabrication process may include forming an internal conductor layer 5 (see FIGS. 3 to 5 ). In the fabrication process, as shown in FIG. 17 , before stacking the multiple substrates 3, a conductor layer containing a superconductor such as niobium, aluminum, molybdenum, tungsten, or titanium nitride may be formed on the fourth surface 3 a of at least one substrate 3, and the conductor layer may be patterned into a desired shape to form the internal conductor layer 5. In the fabrication process, the internal conductor layer 5 may be formed using photolithography and etching. A structure 1 having the internal conductor layer 5 (see FIG. 18 ) can be manufactured by stacking multiple substrates 3, including the substrate 3 on which the internal conductor layer 5 is formed, and then forming a conductor layer 4 on the inner circumferential surface 21 c of the through hole 21. When forming the internal conductor layer 5, a thin conductor layer located on the inner circumferential surface of the substrate through hole 3 c may be simultaneously formed. The thin conductor layer may constitute a part of the conductor layer 4.

[0071] The manufacturing method of the structure 1 may include a forming step. The forming step is a step of forming the pillars 6 (see FIG. 5 ) located inside the conductive layer 4 in the through-holes 21, and is performed after the film-forming step. In the forming step, an organic solvent, a binder, and the like are added to copper powder to prepare a metal paste 9. Next, the through-holes 21 are filled with the metal paste 9, and the metal paste 9, the laminate 2, and the conductive layer 4 are co-fired (see FIG. 19 ). The firing may be performed in an oxygen-free atmosphere, which reduces the risk of the thermal conductivity of the pillars 6 decreasing due to oxidation. The firing temperature may be, for example, approximately 700°C to 900°C, or approximately 800°C.

[0072] The manufacturing method of the structure 1 may include an adhesion step, which is a step of applying an adhesive to the side surface 2 c of the laminate 2 and curing the adhesive to form an adhesive layer 7 (see FIG. 6 ) to fix the plurality of substrates 3 to each other, and may be performed after the film formation step.

[0073] The method for manufacturing the structure 1 may include a fastening step, which is a step of fixing the plurality of substrates 3 to each other using fastening parts 8 (see FIG. 7 ) such as clips or screws, and may be performed after the film formation step.

[0074] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-described embodiments. Various modifications, improvements, etc. are possible within the scope of the gist of the present disclosure. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included within the technical scope of the invention of the present disclosure. For example, functions contained in each component, etc., can be rearranged so as not to cause logical contradictions, and multiple components, etc., can be combined into one or separated. In other words, it should be noted that a person skilled in the art would easily be able to make various modifications or alterations based on the present disclosure. It should also be noted that these modifications, alterations, or alterations are included within the scope of the present disclosure.

[0075] According to the present disclosure, electrical and thermal losses in quantum processors can be reduced, and the capabilities of quantum processors and quantum computers can be improved.

[0076] The present disclosure can be implemented in the following aspects (1) to (12).

[0077] (1) A structure comprising: a laminate formed by stacking a plurality of substrates including a single crystal ceramic, the laminate having a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a conductive layer located on the inner circumferential surface of the through hole.

[0078] (2) The structure according to (1) above, wherein the plurality of substrates comprise sapphire.

[0079] (3) The structure according to (1) or (2) above, wherein the conductive layer is a superconductor.

[0080] (4) The structure according to (3) above, wherein the conductive layer comprises titanium nitride.

[0081] (5) The structure according to any one of (1) to (4) above, further comprising a columnar body located inside the through-hole and on the inner side of the conductive layer.

[0082] (6) The structure according to (5) above, wherein the pillars contain copper.

[0083] (7) A quantum processor comprising the structure according to any one of (1) to (6) above.

[0084] (8) A quantum computer comprising the quantum processor described in (7) above.

[0085] (9) A method for manufacturing a structure, comprising: a manufacturing step of stacking a plurality of single crystal ceramic substrates, each having a substrate through-hole penetrating in the thickness direction, to produce a laminate having through-holes penetrating in the stacking direction of the plurality of substrates; and a film-forming step of forming a conductive layer on the inner surface of the through-hole.

[0086] (10) The method for producing a structure according to (10) above, further comprising a pressurizing step between the fabrication step and the film-forming step, in which the laminate is pressurized in the stacking direction while being heated.

[0087] (11) The method for manufacturing a structure according to (9) or (10) above, wherein the pressurizing step includes diffusion bonding the substrates adjacent to each other in the stacking direction.

[0088] (12) A method for manufacturing a structure according to any one of (9) to (11) above, comprising, after the film-forming step, a firing step of filling the inside of the conductive layer in the through hole with a metal paste and firing the metal paste.

[0089] REFERENCE SIGNS LIST 1 Structure 2 Laminate 2a First surface 2b Second surface 2c Third surface (side surface) 21 Through hole 21a First opening 21b Second opening 21c Inner peripheral surface 21d Narrowed portion 3 Substrate 3a Fourth surface 3b Fifth surface 3c Substrate through hole 4 Conductive layer 5 Internal conductive layer 6 Column 7 Adhesive layer 8 Fastening part 9 Metal paste 30 Quantum processor 31 Quantum chip 32 Quantum bit circuit 33 Quantum bit 34 Readout resonator 35 Inter-quantum bit coupling capacitor 36 Central electrode 37 Ring electrode 38 Josephson junction element 38a Insulator thin film 38b Superconductor 39 Interposer 39a Third surface 39b Fourth surface 40 Through hole 41 Conductive layer 42 Wiring substrate 43, 44 Wiring conductor 45 Support substrate 46 Detection electrode 50 Quantum computer 51 Refrigerator 51a Refrigerated space 52, 53 Microwave amplifier 54 Circulator 55 Cryogenic noise filter 56 Coaxial cable connector 57 Microwave input / output device 58 Control computer 100 Substrate precursor 100a Upper surface 100b Lower surface

Claims

1. A structure comprising: a laminate formed by stacking a plurality of substrates including single-crystal ceramic, the laminate having a first surface, a second surface opposite the first surface, and a through hole extending from the first surface to the second surface; and a conductive layer located on the inner circumferential surface of the through hole.

2. The structure of claim 1, wherein said plurality of substrates comprises sapphire.

3. The structure of claim 1 or 2, wherein the conductive layer is a superconductor.

4. The structure of claim 3, wherein said conductive layer comprises titanium nitride.

5. The structure according to any one of claims 1 to 4, further comprising a columnar body located inside the conductive layer within the through-hole.

6. The structure of claim 5, wherein the pillars comprise copper.

7. A quantum processor comprising a structure according to any one of claims 1 to 6.

8. A quantum computer comprising the quantum processor according to claim 7.

9. A method for manufacturing a structure, comprising: a manufacturing step of stacking a plurality of single crystal ceramic substrates, each having a substrate through-hole penetrating in the thickness direction, to produce a laminate having through-holes penetrating the plurality of substrates in the stacking direction; and a film-forming step of forming a conductive layer on the inner surface of the through-hole.

10. The method for producing the structure according to claim 9, further comprising a pressurizing step between the fabrication step and the film-forming step, in which the laminate is pressurized in the lamination direction while being heated.

11. The method for manufacturing a structure according to claim 9 or 10, wherein the pressure application step includes diffusion bonding the substrates adjacent to each other in the stacking direction.

12. A method for manufacturing a structure according to any one of claims 9 to 11, comprising, after the film-forming step, a forming step of filling the inside of the conductive layer in the through-hole with a metal paste and firing the metal paste.

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