Integrity and data encryption (IDE) shared across multiple interconnect controllers

Abstract

Technologies directed to integrity and data encryption (IDE) shared across multiple interconnect controllers are described. A device includes multiple interconnect controllers and a single IDE circuit coupled with the multiple interconnect controllers. The single IDE circuit includes arbitration logic to enable concurrent support of the multiple interconnect controllers with a reconfigurable bandwidth allocation.

Description

INTEGRITY AND DATA ENCRYPTION (IDE) SHARED ACROSS MULTIPLE INTERCONNECT CONTROLLERSBACKGROUND

[0001] Modern computer systems generally include one or more interconnects used to connect a host device to one or more peripheral devices. These interconnects can use interface protocols, such as the Peripheral Component Interconnect Express (PCIe) protocol, and the Compute Express Link® (CXL®) protocol, to send and receive data between two devices.

[0002] PCIe provides a high-speed, point-to-point serial interface that connects components like central processing units (CPUs), graphics processing units (GPUs), solid-state drives (SSDs, and network cards to a motherboard. A PCIe (Peripheral Component Interconnect Express) controller is the hardware and logic responsible for managing PCIe communication between a host system (typically a CPU or chipset) and PCIe-connected devices (e.g., GPUs, SSDs, network cards). The PCIe controller acts as an interface between the system bus and PCIe devices, handling packetized communication, error checking, power management, and data transfer.

[0003] Compute Express Link® (CXL®) is an industry-supported cache-coherent interconnect for processors, memory expansion, and accelerators. Compute Express Link (CXL) is an open, high-bandwidth, low-latency interconnect standard designed to improve memory and accelerator communication in high-performance computing (HPC), artificial intelligence (Al), machine learning (ML), and cloud computing environments. It operates on top of PCIe, leveraging PCIe’s physical layer while introducing new protocol layers optimized for cache-coherent data sharing between CPUs, accelerators (GPUs, FPGAs, Al chips), and memory devices.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0005] FIG. 1 A is a block diagram of a device with a single IDE circuit that concurrently supports integrity and data encryption (IDE) for multiple interconnect controllers according to at least one embodiment.

[0006] FIG. IB illustrates a first lane configuration, a second lane configuration, and a third lane configuration using a single IDE circuit according to at least one embodiment.

[0007] FIG. 2 is a block diagram of a cryptographic circuit for shared IDE according to at least one embodiment.

[0008] FIG. 3 is a block diagram of a device with a single IDE circuit and four interconnect controllers according to at least one embodiment.

[0009] FIG. 4 is a block diagram of a device with a PCIe IDE standalone engine and four PCIe controllers according to at least one embodiment.

[0010] FIG. 5 is a block diagram of a single IDE circuit according to at least one embodiment.

[0011] FIG. 6 is a flow diagram of a method for shared IDE support for multiple interconnect controllers according to at least one embodiment.

[0012] FIG. 7 is a flow diagram of a method for shared IDE support for multiple interconnect controllers according to at least one embodiment.DETAILED DESCRIPTION

[0013] Technologies directed to integrity and data encryption (IDE) shared across multiple interconnect controllers are described. The following description sets forth numerous specific details, such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of several embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that at least some embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or presented in simple block diagram format to avoid obscuring the present disclosure unnecessarily. Thus, the specific details set forth are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the scope of the present disclosure.

[0014] Datacenter architectures are evolving to support the workloads of emerging applications in Artificial Intelligence and Machine Learning that require a high-speed, low latency, cache-coherent interconnect. The PCIe and CXL® technologies defines mechanisms, referred to as Integrity and Data Encryption (IDE), for providing confidentiality, integrity, and replay protection for data transferred over a link. In particular, the latest PCIe protocol incorporates IDE for security of transaction layer packets (TLPs). An IDE circuit (also referred to herein as “IDE engine,” “hardware IDE engine,” or "IDE standalone engine") can implement an IDE algorithm to secure data traffic between two device. One IDE algorithm is Advanced Encryption Standard (AES)Galois / Counter Mode (GCM) (hereinafter the AES-GCM algorithm. The AES-GCM algorithm uses AES-256 for the encryption and a hash function, called GHASH, to produce a message authentication code (MAC) for an authentication tag. AES-GCM also supports Additional Authenticated Data (AAD) which is authenticated using GHASH but transmitted as plaintext. The GHASH algorithm belongs to a class of Wegman-Carter polynomial universal hashes. Other encryption and authentication algorithms can be used. For example, a basic AES operation can include expanding a key, performing an initial process on input data, and then a number of round calculations that are repeated multiple times to provide an output.

[0015] As described above, a PCIe controller uses its IDE engine for carrying out cryptographic operations on TLPs. The PCIe controllers can support features, such as PCIe lane bifurcation that allows the division of data lanes in a PCIe slot. PCIe lane bifurcation is a technique that allows a single PCIe slot (or root port) to split its lanes into multiple logical connections, enabling multiple devices to share the same physical PCIe interface. This is particularly useful in multi-GPU setups, NVMe storage configurations, and server environments. A PCIe slot includes multiple lanes, which are individual data pathways. Common PCIe slot configurations include xl, x4, x8, and xl6, where the number represents the number of lanes available. In a standard operation, a PCIe xl6 slot delivers all 16 lanes to a single device (e.g., a GPU). With lane bifurcation, the same xl6 slot can be split into multiple smaller sets of lanes, allowing multiple devices to use the slot. For example, PCIe xl6 slot can be used as PCIe xl6 lanes (e.g., xl6), two PCIe x8 lanes (e.g., x8 / x8), or four PCIe x4 lanes (e.g., x4 / x4 / x4 / x4).

[0016] In a traditional design approach for lane bifurcation, each division of physical lanes (referred to as PHY lanes) will need a corresponding PCIe controller and IDE engine. The IDE engine is typically integrated with the PCIe controller. Thus, a PCIe slot that has been divided into four sets of lanes would require four separate PCIe controllers, each having its own respective IDE engine. The cryptographic logic of the IDE engine can consume a lot of area on silicon. Thus, the traditional design approach is area intensive due to the size of the cryptographic logic used for each of the PCIe controllers. Also, because the IDE engine is integrated inside the PCIe controller, the IDE engine's configuration remains supplier specific. Also, security keys should be distributed to each of the PCIe controllers, so all the PCIe controllers will need to be part of a security perimeter.

[0017] Aspects and embodiments of the present disclosure can address these problems and others by providing a single IDE circuit (i.e., single IDE engine) with arbitration logic to enable concurrent support of multiple interconnect controllers. Aspects and embodiments of the present disclosure can provide concurrent support of the multiple interconnect controllers with a reconfigurable bandwidth allocation. The single IDE circuit is shareable across multiple controllers for supporting simultaneous or concurrent operation with reconfigurable, dynamic bandwidth allocation and efficient bandwidth utilization. The single IDE circuit can be coupled to multiple PCIe controllers, multiple CXL controllers, multiple Universal Chiplet Interconnect Express controllers (UCIe controllers), multiple Ultra Accelerator Link controllers (UALink controllers), or other types of interconnect controllers.

[0018] Aspects and embodiments of the present disclosure can provide various advantages by sharing the single IDE circuit. Aspects and embodiments of the present disclosure can optimize area for a device with multiple interconnect controllers with IDE support by using the shareable IDE engine. Aspects and embodiments of the present disclosure can provide reconfigurability of bandwidth per controller, per stream, per link, as per the system configuration. Aspects and embodiments of the present disclosure can provide bandwidth optimization by allowing static configurations or dynamic reconfigurations. Aspects and embodiments of the present disclosure can provide security perimeter optimization by a centralized entity (i.e., the single IDE circuit), instead of a security perimeter for multiple distributed controllers.

[0019] FIG. 1A is a block diagram of a device 100 with a single IDE circuit 104 that concurrently supports integrity and data encryption (IDE) for multiple Interconnect controllers 102 according to at least one embodiment. The device 100 can be a CPU, a GPU, a chipset, a System on Chip (SoC), a solid-state storage drive (SSD), a storage controller, a networking device (e.g., a network switch, a network card (e.g., a network interface card (NIC)), a smart NIC, a data processing unit (DPU), a network adapter, etc.), an accelerator (e.g., an Al or ML accelerator), a field programable gate array (FPGA) device, an expander device, a memory expansion device, an Internet of Things (loT) device, an embedded system, etc.

[0020] The device 100 can be an integrated circuit having multiple physical data lanes 122 in one or more physical ports. The device 100 includes multiple interconnect controllers 102 coupled between the single IDE circuit 104 and the multiple physical data lanes 122. The interconnect controllers 102 can be coupled to multiple ports 108 ofthe single IDE circuit 104 via internal data lanes 114. The internal data lanes 114 can be interconnects inside the silicon of the integrated circuit. The data lanes 114 can be fixed width, but the data throughput on these data lanes 114 will be changed dynamically when the corresponding link widths change based on the bifurcation configuration, as described herein. The single IDE circuit 104 includes arbitration logic 106, multiple ports 108, a cryptographic circuit 110, and one or more registers 112. The single IDE circuit 104 can support lane bifurcation. The single IDE circuit 104 can be configured to operate in multiple lane configurations, as described herein. As described above, lane bifurcation allows the division of physical data lanes 122 of a physical interface. The physical interface can be a physical interconnect slot that supports bifurcation in which the physical data lanes 122 are split into multiple independent logical connections, each independent logical connection corresponding to one of the interconnect controllers 102. Splitting the physical data lanes 122 into multiple logical connections to share the same physical interconnect slot (e.g., same PCIe slot). In at least one embodiment, the physical data lanes 122 can be individual pathways. In at least one embodiment, the device 100 can include a set of L number of physical data lanes 122. Each data lane includes a first pair of differential signal lines for transmitting data (referred to herein as “transmit data” or “TX data”) and a second pair of differential signal lines for receiving data (referred to herein as “receive data” or “RX data”). Each data lane can include an independent bi-directional bandwidth that is reconfigurable according to a reconfigurable bandwidth allocation, as described herein.

[0021] As described above, the single IDE circuit 104 can be configured to operate in multiple lane configurations with different bandwidth allocations. These bandwidth allocations can be configured per interconnect controller, per stream, per link, as per various system configurations. In at least one embodiment, the set of L number of data lanes 122 is configured as either a single port having the L number of data lanes (x(L) port) or M number of ports having N number of data lanes (M x(N) ports), where M times N is equal to L. The single IDE circuit 104 can serve (i.e., provide IDE to) the x(L) port in a first lane configuration and the M x(N) ports in a second lane configuration. As described in more detail below, in the second lane configuration, the arbitration logic 106 can arbitrate data from the M x(N) ports according to bandwidths allocated to each of the M x(N) ports in the reconfigurable bandwidth allocation. Examples of three lane configurations are illustrated in FIG. IB.

[0022] FIG. IB illustrates a first lane configuration 116, a second lane configuration 118, and a third lane configuration 120 using a single IDE circuit 104 according to at least one embodiment. In the first lane configuration 116, the single IDE circuit 104 is coupled to a single interconnect controller 102, which is coupled to all 16 data lanes 122 (labeled " 16x PHY"). In the second lane configuration 118, the single IDE circuit 104 is coupled to two interconnect controllers 102, each being coupled to 8 data lanes (8x PHY) of the 16 data lanes 122 (16x PHY). In the second lane configuration 118, the single IDE circuit 104 is coupled to four interconnect controllers 102, each being coupled to 4 data lanes (4x PHY) of the 16 data lanes 122 (16x PHY).

[0023] As described above, in any of the bifurcation lane configurations, the arbitration logic 106 can arbitrate between the interconnect controllers 102 according to a reconfigurable bandwidth allocation. For example, in the second lane configuration 118, the reconfigurable bandwidth allocation can specify a 50% individual bandwidth for each of the two interconnect controllers 102. For another example, in the third lane configuration 120, the reconfigurable bandwidth allocation can specify a 25% individual bandwidth for each of the four interconnect controllers 102.

[0024] In at least one embodiment, the interconnect controllers 102 are PCIe controllers that support bifurcation of a PCIe slot. The PCIe slot includes multiple data lanes, which are individual data pathways. Common PCIe slot configurations include xl, x4, x8, and xl6, where the number represents the number of lanes available. In a standard operation, a PCIe xl6 slot delivers all 16 lanes to a single device (e.g., a GPU). With lane bifurcation, the same xl6 slot can be split into multiple smaller sets of lanes, allowing multiple devices to use the slot. The PCIe xl6 slot can be used as PCIe xl6 lanes (e.g., xl6) as illustrated in first lane configuration 116 of FIG. IB), as two PCIe x8 lanes (e.g., x8 / x8) as illustrated in second lane configuration 118 of FIG. IB), or four PCIe x4 lanes (e.g., x4 / x4 / x4 / x4) as illustrated in third lane configuration 120 of FIG. IB. In at least one embodiment, the PCIe controllers are separate controller instances. In other embodiments, a bifurcated PCIe interface can be implemented in such a away to be represented by a single PCIe controller instance where certain PCIe functions can be shared. As such, a single PCIe controller that supports PCIe bifurcation can also be used in connection with the single IDE circuit 104.

[0025] In some embodiments, the single IDE circuit 104 can be configured in the different lane configurations using one or more registers 112. The registers 112 can store configuration data representing a current lane configuration for a set of L number of datalanes 122. The registers 112 can store first configuration data representing the first lane configuration 116 for the set of L number of data lanes 122. The registers 112 can store second configuration data representing the second lane configuration 118 for the set of L number of data lanes 122. The registers 112 can store third configuration data representing the third lane configuration 120 for the set of L number of data lanes 122. In some embodiments, the registers 112 can store data that represents the reconfigurable bandwidth allocation. In some cases, the reconfigurable bandwidth allocation can be implied based on the specified lane configuration. In at least one embodiment, the interconnect slot of data lanes 122 can have a total bandwidth. The total bandwidth can be split between the interconnect controllers 102 according to the reconfigurable and dynamic bandwidth allocation per each of the multiple independent logical connections. For example, each of the PCIe controllers can be coupled to a group of data lanes, and the arbitration logic 106 of the single IDE circuit 104 can arbitrate a specified individual bandwidth for each of the groups of data lanes according to the reconfigurable and dynamic bandwidth allocation. The reconfigurable bandwidth allocation can also be specified on a stream basis, a link basis, or the like. Also, each data lane can include an independent bi-directional bandwidth that is reconfigurable according to the reconfigurable bandwidth allocation.

[0026] In at least one embodiment, the single IDE circuit 104 includes the cryptographic circuit 110. The cryptographic circuit 110 can also be referred to as an IDE engine, IDE circuit, or IDE block. An example of the cryptographic circuit 110 is illustrated and described below with respect to FIG. 2. In at least one embodiment, the cryptographic circuit 110 can encrypt and decrypt data. As described above, each of the data lanes 122 can include a first pair of differential signal lines for the TX data and a second pair of differential signal lines for the RX data. In at least one embodiment, the cryptographic circuit 110 can encrypt the TX data and decrypt the RX data. In other embodiments, the cryptographic circuit 110 can encode the TX data and decode the RX data. In at least one embodiment, the cryptographic circuit 110 can be an IDE engine or a hardware IDE engine or a IDE standalone engine. The cryptographic circuit 110 can implement an IDE algorithm to secure data. One IDE algorithm is the AES-GCM algorithm. The AES-GCM algorithm uses AES-256 for the encryption and a hash function, called GHASH, to produce a MAC for an authentication tag. AES-GCM also supports Additional Authenticated Data (AAD) which is authenticated using GHASH but transmitted as plaintext. In other embodiments, the cryptographic circuit 110 canimplement other encryption and authentication algorithms can be used. In at least one embodiment, the cryptographic circuit 110 can generate authentication tags for the TX data and verify authentication tags for the RX data. Similarly, the cryptographic circuit 110 can generate AAD for the TX data and verify AAD for the RX data. In at least one embodiment, the cryptographic circuit 110 includes an encryption circuit to encrypt TX data and a decryption circuit to decrypt RX data.

[0027] In some embodiments, the single IDE circuit 104 includes stream association circuitry to associate the data with the appropriate encryption key. For example, different streams or different channels can use different encryption keys. In at least one embodiment, the stream association circuitry can include a first stream association circuit to associate a first encryption key with the TX data, and a second stream association circuit to associate a second encryption key with the RX data. The first and second encryption keys can be the same key when the TX data and the RX data are from the same stream. In other cases, the first and second encryption keys can be different.

[0028] FIG. 2 is a block diagram of a cryptographic circuit 200 for shared IDE according to at least one embodiment. The cryptographic circuit 200 provides encryption, decryption and authentication for packets exchanged between a first device (e.g., CPU) and a second device (e.g., peripheral device). The second device can be an input / output (I / O device). The second device is sometimes referred to as the link partner, an endpoint device, a downstream device, an upstream device, or the like. The cryptographic circuit 200 can be instantiated on a host system (e.g., System on Chip (SoC) or Field Programmable Gate Array (FPGA)). The cryptographic circuit 200 can be implemented in hardware, software, firmware, or any combination thereof. The cryptographic circuit 200 can receive plaintext data 202 from the arbitration logic 106. If the single IDE circuit 104 is configured to operate with a single port, the plaintext data 202 can be passed through without arbitration. The cryptographic circuit 200 can encrypt the plaintext data 202 into ciphertext data, generate an authentication tag 216, and provide an output 204 back to the arbitration logic 106. The output 204 includes final ciphertext data 218 and the authentication tag 216. The cryptographic circuit 200 can receive ciphertext data and authentication tag from the arbitration logic 106, decrypt the data and provide the decrypted data back to the arbitration logic 106. The cryptographic circuit 200 can implement encryption and authentication algorithm, such as the AES- GCM algorithm. The AES-GCM algorithm uses AES-256 for the encryption and GMAC for the authentication. The GMAC internally uses the GHASH functions to generates theauthenti cation tag 216. In at least one embodiment, the cryptographic circuit 200 can generate a Message Authentication code (MAC) tag for each segment (or portion) or for multiple segments (or portions) received from the arbitration logic 106. As illustrated in FIG. 2, the generation of the MAC tag is performed in connection with an authentication algorithm that uses a hashing function to compute the MAC tag. In other embodiments, the generation of the MAC tag is performed in connection with another operation, such as an encryption operation. In at least one embodiment, the authentication algorithm is the GMAC algorithm and the hash function is the GHASH function. Alternatively, other authentication algorithms and / or hash functions can be used.

[0029] In at least one embodiment, the cryptographic circuit 200 includes an encryption engine 206, an authentication engine 208, and additional logic and SRAMs 210, including a latency controller 220. The additional logic and SRAMs 210 can be used to perform other operations and store information in connection with the encryption and authentication operations. For simplicity, the cryptographic circuit 200 shows a process flow of encryption with an encryption engine 206. The encryption engine 206 (also referred to herein as encryption logic) can receive the plaintext data 202 as segments (or portions) and encrypt the segments into segments 214 (or portions) of ciphertext data. The segments or portions can be epochs or flits of an epoch. The authentication engine 208 can use GMAC for authentication, including the GHASH function, to generate the authentication tag 216. Before outputting the final authentication tag 216, the authentication engine 208 can output an intermediate state that is stored by the additional logic and SRAMs 210 in the event of an error. The intermediate state can include an intermediate hash state of a hash computation and an intermediate initialization vector (IV). The intermediate state can also store a counter output.

[0030] In at least one embodiment, the encryption engine 206 (encryption logic) receives segments 212 of plaintext data 202 of a data burst and outputs segments 214 of cyphertext data of the data burst. The authentication engine 208 (authentication logic) receives the segments 214 of the cyphertext data, and outputs a final authentication tag 216 associated with the data burst, along with the final ciphertext data 218. Although not illustrated in FIG. 2, the cryptographic circuit 200 can include a decryption engine (decryption logic) that receives segments of ciphertext data of a data burst and outputs segments of plaintext data of the data burst. The authentication engine 208 can receive a corresponding authentication tag associated with the data burst to authenticate the data burst.

[0031] In at least one embodiment, the cryptographic circuit 200 includes data-integrity (DI) detection logic to detect an error. The DI detection logic can be part of, or coupled to, the encryption engine 206. The DI detection logic can be part of, or coupled to, the authentication engine 208. The DI detection logic can be part of, or coupled to the additional logic and SRAMs 210. In other embodiments, each stage of the cryptographic circuit 200 can include DI detection logic to detect errors in the authentication operations, the encryption operations, SRAM operations, I / O operations, or the like. The error can be a result of an DI error in one or more of an encryption computation by the encryption engine 206, an authentication computation by the authentication engine 208, a SRAM operation by the additional logic and SRAMs 210, or an I / O operation.

[0032] It should be noted that the embodiments described herein can be used for port management of a switch. The ports and corresponding data lanes can be managed in a similar fashion as described herein.

[0033] FIG. 3 is a block diagram of a device 300 with a single IDE circuit 302 and four interconnect controllers according to at least one embodiment. The device 300 includes the single IDE circuit 302 coupled to four interconnect controllers, including a first interconnect controller 308, a second interconnect controller 310, a third interconnect controller 312, and a fourth interconnect controller 314. The four interconnect controllers 308, 310, 312, and 314 are coupled to a set of L number of data lanes 306. In this example, there are 16 data lanes 306. The single IDE circuit 302 includes an IDE engine 304 (e.g., such as described above with respect to cryptographic circuit 200 of FIG. 2), an arbiter 324, stream association circuitry 326, and four ports, including a first port 316, a second port 318, a third port 320, and a fourth port 322.

[0034] The four interconnect controllers 308, 310, 312, and 314 can be configured in different lane configurations, as described herein. The set of L number of data lanes can be configured as either (i) a single port having the L number of data lanes in a first lane configuration or (ii) M number of ports having N number of data lanes in one or more lane configurations, wherein M times N is equal to L. There can be different second lane configurations depending on M and N. In the first lane configuration, the first interconnect controller 308 is coupled to all the data lanes 306. In one of the other lane configuration, different numbers of the first interconnect controller 308, second interconnect controller 310, third interconnect controller 312, and fourth interconnect controller 314 are coupled to the data lanes 306. In this first lane configuration, the first port 316 supports all of the data lanes 306 (e.g., xl6). For example, in a second laneconfiguration, the first interconnect controller 308 is coupled to half of the data lanes 306, and the second interconnect controller 310 is coupled to half of the data lanes 306. In this second lane configuration, the first port 316 supports half of the data lanes 306 (e.g., x8), and the second port 318 supports the other half of the data lanes 306. For another example, in a third lane configuration, the first interconnect controller 308 is coupled to a quarter of the data lanes 306, the second interconnect controller 310 is coupled to a quarter of the data lanes 306, the third interconnect controller 312 is coupled to a quarter of the data lanes 306, and the fourth interconnect controller 314 is coupled to a quarter of the data lanes 306. In this third lane configuration, the first port 316 supports a quarter of the data lanes 306 (e.g., x4), the second port 318 supports a quarter of the data lanes 306 (e.g., x4), the third port 320 supports a quarter of the data lanes 306 (e.g., x4), the fourth port 322 supports a quarter of the data lanes 306 (e.g., x4).

[0035] In at least one embodiment, the arbiter 324 can receive first data from a single port in the first lane configuration (i.e., no lane bifurcation). When there is no lane bifurcation, the arbiter 324 does not arbitrate the first data since there is no need for bandwidth allocation. The single IDE circuit 302 can support the first interconnect controller 308 with all data lanes 306 via the single first port 316. The arbiter 324 can arbitrate data from the M number of ports in the one or more other lane configurations according to a reconfigurable bandwidth allocation. The IDE engine 304 is coupled to the arbiter 324 and can be configured to encrypt or decrypt the first data received on the single port (e.g., first port 316) in the first lane configuration and encrypt or decrypt arbitrated data received from the arbiter 324 in the lane bifurcation configurations. In at least one embodiment, the IDE engine 304 includes an encryption circuit (or encryption engine) and a decryption circuit (or decryption engine).

[0036] In at least one embodiment, each of the data lanes 306 includes a first pair of differential signal lines for transmit data and a second pair of differential signal lines for receive data. The single IDE circuit 302 can include stream association circuitry 326 to associate encryption keys with the TX and the RX data. In other embodiments, the stream association circuitry 326 can associate different streams with different encryption keys. In other embodiments, the single IDE circuit 302 can support different links, and the stream association circuitry 326 can associate different links with different encryption keys.

[0037] In at least one embodiment, the single IDE circuit 302 can be configured in different lane configurations at different times during operation. This makes the single IDE circuit 302 reconfigurable and dynamic. In at least one embodiment, at a first time, the set of L number of data lanes 306 is configured as (i) the single port in the first lane configuration. The IDE engine 304 can receive first data from the first port 316. The IDE engine 304 can encrypt or decrypt the first data and return the first data to the first port 316. At a second time, the set of L number of data lanes 306 is configured as (ii) the M number of ports in the second lane configuration. For example, the first port 316 of the M number of ports can receive second data, and the second port 318 of the M number of ports can receive third data concurrently with the second data. The arbiter 324 can select the second data (or the third data) as the arbitrated data. The IDE engine 304 can receive the arbitrated data from the arbiter 324. The IDE engine 304 can encrypt or decrypt the arbitrated data, and return the arbitrated data back to the first port 316 (or the second port 318 if the third data is selected).

[0038] In a further embodiment, at a third time, the set of L number of data lanes 306 is configured as (ii) the M number of ports in a third lane configuration. For example, the first port 316 of the M number of ports can receive second data, the second port 318 of the M number of ports can receive third data, the third port 320 of the M number of ports can receive fourth data, and the fourth port 322 of the M number of ports can receive fifth data concurrently with the second data, the third data, and the fourth data. The arbiter 324 can select the second data (or the third data, the fourth data, or the fifth data) as the arbitrated data. The IDE engine 304 can receive the arbitrated data from the arbiter 324. The IDE engine 304 can encrypt or decrypt the arbitrated data, and return the arbitrated data back to the first port 316 (or the second port 318 if the third data is selected or the third port 320 if the fourth data is selected or the fourth port 322 if the fifth data is selected).

[0039] In at least one embodiment, the single IDE circuit 302 can be configured to arbitrate the bandwidth as per bifurcation setup. The stream association circuitry 326 can help track and manage the number of incoming streams (e.g., PCIe streams) from various channels to the individual GCM streams. The IDE engine 304 can support multi-stream GCM cryptographic operations.

[0040] In at least one embodiment, the arbiter 324 includes arbitration for both TX and RX data, as illustrated and described below with respect to FIG. 4. In at least oneembodiment, the arbiter 324 includes a transmit (TX) arbiter and a receive (RX) arbiter, such as illustrated and described below with respect to FIG. 5.

[0041] FIG. 4 is a block diagram of a device 400 with a PCIe IDE standalone engine 402 and four PCIe controllers according to at least one embodiment. In this embodiment, the PCIe IDE standalone engine 402 is coupled to a first PCIe controller 404, a second PCIe controller 406, a third PCIe controller 408, and a fourth PCIe controller 410. The PCIe IDE standalone engine 402 is similar to the single IDE circuit 104 of FIG. 1A or the single IDE circuit 302 of FIG. 3. The PCIe IDE standalone engine 402 include arbitration logic 412, a cryptographic circuit 414, a TX association circuit 416, and an RX association circuit 418. The arbitration logic 412 can be similar to the arbitration logic 106 of FIG. 1 or the arbiter 324 of FIG. 3.

[0042] In this embodiments, the device 400 is configured to operate in a lane configuration in which four PCIe controllers are used and the data lanes are bifurcated between the four PCIe controllers. The arbitration logic 412 of the PCIe IDE standalone engine 402 can enable concurrent support of the four PCIe controllers with a reconfigurable bandwidth allocation, such as 25% bandwidth per PCIe controller. The arbitration logic 412 can arbitrate incoming TX data from each of the PCIe controllers and provide arbitrated TX data to the TX association circuit 416. The TX association circuit 416 can associate one of multiple encryption keys to the arbitrated TX data. In at least one embodiment, the TX association circuit 416 can associate a first encryption key based on a memory address of the incoming TX data. The cryptographic circuit 414 can encrypt or decrypt the arbitrated TX data, and return the arbitrated TX data back to the TX association circuit 416 or the arbitration logic 412 to be sent back to the respective one of the PCIe controllers from which the incoming TX data was received. Similarly, the arbitration logic 412 can arbitrate incoming RX data from each of the PCIe controllers and provide arbitrated RX data to the RX association circuit 418. The RX association circuit 418 can associate one of multiple encryption keys to the arbitrated RX data. The RX association circuit 418 can associate an encryption key with the arbitrated RX data based on an identifier in the incoming RX data (e.g., a stream identifier in the RX data). The cryptographic circuit 414 can encrypt or decrypt the arbitrated RX data, and return the arbitrated RX data back to the RX association circuit 418 or the arbitration logic 412 to be sent back to the respective one of the PCIe controllers from which the incoming RX data was received.

[0043] In some embodiments, the PCIe IDE standalone engine 402 can include multiple instances of the cryptographic circuit 414. Each of the cryptographic circuits 414 can use a configuration control interface (e.g., an advanced peripheral bus (APB) control) for each instance.

[0044] In at least one embodiment, the PCIe IDE standalone engine 402 is shared among the single PCIe IDE engine is shared among multiple controllers, including PCIe controller 404, PCIe controller 406, PCIe controller 408, and PCIe controller 410. The PCIe IDE standalone engine 402 can be sized to support full bandwidth of the PCIe slot. The arbitration logic 412 is configured for the configuration of interest, such as four PCIe controllers as illustrated in FIG. 4. The arbitration logic 412 can be configured for other configurations, including different numbers of PCIe controllers. As described herein, internal operations of the PCIe IDE standalone engine 402 can be structured as multiple channels or streams corresponding to each controller link between the PCIe controllers and the PCIe IDE standalone engine 402. In at least one embodiment, the cryptographic circuit 414 (i.e, a combined IDE engine) uses a wide interface to support full bandwidth of the link, whereas the instantaneous bandwidth among the PCIe controllers can be adapted.

[0045] In at least one embodiment, the arbitration logic 412 can arbitrate incoming TX data and RX data in a time-division multiplexed manner according to the reconfigurable bandwidth allocation. The arbitration logic 412 can use various arbitration schemes to arbitrate according to the reconfigurable bandwidth allocation. In at least one embodiment, the arbitration logic 412 is implemented using combinational logic. In another, the arbitration logic 412 is implemented using a hardware state machine or other circuitry.

[0046] FIG. 5 is a block diagram of a single IDE circuit 500 according to at least one embodiment. The single IDE circuit 500 includes a port TLP processing engine 502, a TX arbiter 526, an RX arbiter 528, an encoder 530, and a decoder 532. The port TLP processing engine 502 can process the incoming transaction layer packets (TLPs) from any one of N interconnect controllers (not illustrated in FIG. 5). The port TLP processing engine 502 can include a first TX FIFO buffer 504 that receives TX TLPs from a first interconnect controller. The port TLP processing engine 502 can include up to an Nth TX FIFO buffer 508 that receives TX TLPs from an Nth interconnect controller. The port TLP processing engine 502 can include a first RX FIFO buffer 512 that receives RX TLPs from the first interconnect controller. The port TLP processing engine 502 caninclude up to a Nth RX FIFO buffer 516 that receives RX TLPs from the Nth interconnect controller.

[0047] The port TLP processing engine 502 can include a first TX stream association circuit 506 coupled to the first TX FIFO buffer 504 and a first RX stream association circuit 514 coupled to the Nth TX FIFO buffer 508. The port TLP processing engine 502 can include an Nth TX stream association circuit 510 coupled to the Nth TX FIFO buffer 508 and a Nth RX stream association circuit 518 coupled to the Nth RX FIFO buffer 516. Each of the TX stream association circuits (506, and 510) are coupled to the TX arbiter 526, which is coupled to the encoder 530. Each of the RX stream association circuits (514 and 518) are coupled to the RX arbiter 528, which is coupled to the decoder 532. The port TLP processing engine 502 can also include key management logic 524 that manages a set of encryption keys, one key per stream. The key management logic 524 is coupled to the encoder 530 and the decoder 532. Once incoming TX data is associated with a stream, the corresponding encryption key can be stored in a key set buffer 534. The encryption key stored in the key set buffer 534 can be used for an encryption operation of the TX data by the encoder 530. Once incoming RX data is associated with a stream, the corresponding encryption key can be stored in a key set buffer 536. The encryption key stored in the key set buffer 536 can be used for an decryption operation of the RX data by the decoder 532. Once the TX data is encrypted, the TX data is returned to the TX arbiter 526, which returns the encrypted data back to the respective TX stream association circuit, which directs the encrypted data back to the respective interconnect controller that sent the TX data to be encrypted. Similarly, once the RX data is decrypted, the RX data is returned to the RX arbiter 528, which returns the decrypted data back to the respective RX stream association circuit, which directs the decrypted data back to the respective interconnect controller that sent the RX data to be decrypted.

[0048] In at least one embodiment, the port TLP processing engine 502 includes a first register 520, and up to a Nth register 522. Each register can store configuration data representing a lane configuration for the single IDE circuit 500.

[0049] FIG. 6 is a flow diagram of a method 600 of operating a single IDE circuit for shared IDE support for multiple interconnect controllers according to at least one embodiment. The method 600 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device to perform hardware simulation), or acombination thereof. In one embodiment, the method 600 is performed by the device 100 of FIG. 1 A, the device 300 of FIG. 4, the device 400 of FIG. 4, or the single IDE circuit 500 of FIG. 5. In at least one embodiment, the single IDE circuit 104 of FIG. 1A, the single IDE circuit 302 of FIG. 3, or the PCIe IDE standalone engine 402 of FIG. 4 performs the method 600. Alternatively, other devices can perform the method 600 .

[0050] Referring to FIG. 7, the method 700 begins with the processing logic configuring, at a first time, a plurality of data lanes of an interface as a single port coupled to a first interconnect controller (block 602). At block 604, the processing logic performs a first cryptographic operation on first data received from the single port. At block 606, the processing logic configures, at a second time, the plurality of data lanes of the interface as a plurality of ports, each port being coupled to one of a plurality of interconnect controllers and having a specified bandwidth allocation. The plurality of interconnect controllers includes the first interconnect controller. At block 608, the processing logic arbitrates, according to the specified bandwidth allocations, between second data and third data received from the plurality of ports to select arbitrated data. At block 610, the processing logic performs, using the single IDE circuit, a second cryptographic operation on the arbitrated data.

[0051] In at least one embodiment, the processing logic configures the plurality of data lanes at the first time at block 602 by configuring a set of L number of data lanes as the single port having the L number of data lanes. In at least one embodiment, configuring the plurality of data lanes at the first time is done in response to first configuration data being stored in a set of registers, the first configuration data representing a first lane configuration for the plurality of data lanes.

[0052] In at least one embodiment, the processing logic configures the plurality of data lanes at the second time at block 606 by configuring the set of L number of data lanes as M number of ports having N number of data lanes (M x(N) ports), where M times N is equal to L. At block 606, the processing logic configures each of the M x(N) ports with the specified bandwidth allocation. In at least one embodiment, configuring the plurality of data lanes at the second time is done in response to second configuration data being stored in the set of registers, the second configuration data representing a second lane configuration for the plurality of data lanes.

[0053] In at least one embodiment, the processing logic performs the first cryptographic operation on the first data at block 604 by associating a first key of a plurality of encryption keys with the first data, and encrypting or decrypting the firstdata using the first key. In at least one embodiment, the processing logic performs the second cryptographic operation on the arbitrated data at block 610 by associating a second key of the plurality of encryption keys with the arbitrated data, and encrypting or decrypting the arbitrated data using the second key. The method 600 can include other operation as described herein.

[0054] FIG. 7 is a flow diagram of a method 700 for shared IDE support for multiple interconnect controllers according to at least one embodiment. The method 700 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device to perform hardware simulation), or a combination thereof. In one embodiment, the method 700 is performed by the device 100 of FIG. 1A, the device 300 of FIG. 4, the device 400 of FIG. 4, or the single IDE circuit 500 of FIG. 5. In at least one embodiment, the single IDE circuit 104 of FIG. 1A, the single IDE circuit 302 of FIG. 3, or the PCIe IDE standalone engine 402 of FIG. 4 performs the method 700. Alternatively, other devices can perform the method 700.

[0055] Referring to FIG. 7, the method 700 begins with the processing logic configuring, at a first time, a plurality of data lanes of the interface as a single port coupled to a first interconnect controller (block 702). At block 704, the processing logic receives, at a single integrity and data encryption (IDE) circuit communicatively coupled to the first interconnect controller at the first time, first data from the single port. At block 706, the processing logic performs, using the single IDE circuit, a first cryptographic operation on the first data. At block 708, the processing logic configures, at a second time, the plurality of data lanes of the interface as a plurality of ports. Each port is coupled to one of a plurality of interconnect controllers. Each port has a specified bandwidth allocation. The plurality of interconnect controllers includes the first interconnect controller. At block 710, the processing logic receives, at the single IDE circuit coupled to the plurality of interconnect controllers at the second time, second data from each of two or more of the plurality of ports. At block 712, the processing logic arbitrates the second data received from each of two or more of the plurality of ports according to the bandwidth allocation. At block 714, the processing logic performs, using the single IDE circuit, a second cryptographic operation on the second data.

[0056] In at least one embodiment, the processing logic configures the plurality of data lanes at the first time at block 702 by configuring a set of L number of data lanes as the single port having the L number of data lanes. In at least one embodiment, configuringthe plurality of data lanes at the first time is done in response to first configuration data being stored in a set of registers, the first configuration data representing a first lane configuration for the plurality of data lanes.

[0057] In at least one embodiment, the processing logic configures the plurality of data lanes at the second time at block 708 by configuring the set of L number of data lanes as M number of ports having N number of data lanes (M x(N) ports), where M times N is equal to L. At block 708, the processing logic configures each of the M x(N) ports with the specified bandwidth allocation. In at least one embodiment, configuring the plurality of data lanes at the second time is done in response to second configuration data being stored in the set of registers, the second configuration data representing a second lane configuration for the plurality of data lanes.

[0058] In at least one embodiment, the processing logic performs the first cryptographic operation on the first data at block 706 by associating a first key of a plurality of encryption keys with the first data, and encrypting or decrypting the first data using the first key. In at least one embodiment, the processing logic performs the second cryptographic operation on the arbitrated data at block 714 by associating a second key of the plurality of encryption keys with the arbitrated data, and encrypting or decrypting the arbitrated data using the second key. The method 700 can include other operation as described herein.

[0059] It is to be understood that the above description is intended to be illustrative and not restrictive. Many other implementations will be apparent to those of skill in the art upon reading and understanding the above description. Therefore, the disclosure scope should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0060] In the above description, numerous details are set forth. It will be apparent, however, to one skilled in the art that the aspects of the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the present disclosure.

[0061] Some portions of the detailed descriptions above are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to the desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0062] However, it should be borne in mind that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as “receiving,” “determining,” “selecting,” “storing,” “setting,” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system’s registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

[0063] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable ROMs (EPROMs), electrically erasable programmable ROMs (EEPROMs), magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0064] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatuses to perform the required method steps. The required structure for a variety of these systems will appear as set forth in the description. In addition, aspects of the present disclosure are not described with reference to any particular programming language. It will be appreciated that a variety ofprogramming languages may be used to implement the teachings of the present disclosure as described herein.

[0065] Aspects of the present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any procedure for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.).

Claims

CLAIMSWhat is claimed is:

1. A device comprising: a plurality of interconnect controllers; and a single integrity and data encryption (IDE) circuit communicatively coupled with the plurality of interconnect controllers, the single IDE circuit comprising arbitration logic to enable concurrent support of the plurality of interconnect controllers with a reconfigurable bandwidth allocation.

2. The device of claim 1, wherein the single IDE circuit comprises an interface comprising a set of L number of data lanes, wherein the set of L number of data lanes is configured as either a single port having the L number of data lanes (x(L) port) or M number of ports having N number of data lanes (M x(N) ports), wherein M times N is equal to L, wherein the IDE circuit is configured to serve the x(L) port in a first lane configuration and the M x(N) ports in a second lane configuration, and wherein the arbitration logic is to arbitrate data from the M x(N) ports according to bandwidths allocated to each of the M x(N) ports in the reconfigurable bandwidth allocation.

3. The device of claim 2, wherein the single IDE circuit comprises a set of registers to store first configuration data representing the first lane configuration for the set of L number of data lanes or second configuration data representing the second lane configuration for the set of L number of data lanes.

4. The device of claim 1, wherein the single IDE circuit comprises a cryptographic circuit to encrypt transmit data and decrypt receive data.

5. The device of claim 1, wherein the single IDE circuit comprises: an encryption circuit to encrypt transmit data; and a decryption circuit to decrypt receive data.

6. The device of claim 1, wherein the single IDE circuit comprises: a cryptographic circuit to encrypt transmit data and decrypt receive data; a first stream association circuit to associate one of a plurality of encryption keys with the transmit data; anda second stream association circuit to associate another one of the plurality of encryption keys with the receive data.

7. The device of claim 1, further comprising: a physical interconnect slot that supports bifurcation in which a plurality of data lanes is split into a plurality of independent logical connections, each independent logical connection corresponding to one of the plurality of interconnect controllers, and wherein the arbitration logic is to arbitrate data between the plurality of interconnect controllers and the single IDE circuit according to the reconfigurable bandwidth allocation.

8. The device of claim 1, wherein at least one of the plurality of interconnect controllers is at least one of: a Peripheral Component Interconnect Express controller (PCIe controller); a Universal Chiplet Interconnect Express controller (UCIe controller); an Ultra Accelerator Link controller (UALink controller); or a Compute Express Link controller (CXL controller).

9. A method of checking integrity and data encryption (IDE) of data at an interface of a device, the method comprising: configuring, at a first time, a plurality of data lanes of the interface as a single port coupled to a first interconnect controller; performing, using a single IDE circuit, a first cryptographic operation on first data received from the single port; configuring, at a second time, the plurality of data lanes of the interface as a plurality of ports, each port being coupled to one of a plurality of interconnect controllers and having a specified bandwidth allocation, wherein the plurality of interconnect controllers comprises the first interconnect controller; arbitrating, according to the specified bandwidth allocations, between second data and third data received from the plurality of ports to select arbitrated data; and performing, using the single IDE circuit, a second cryptographic operation on the arbitrated data.

10. The method of claim 9, wherein: configuring the plurality of data lanes at the first time comprises configuring a set of L number of data lanes as the single port having the L number of data lanes; and configuring the plurality of data lanes at the second time comprises: configuring the set of L number of data lanes as M number of ports havingN number of data lanes (M x(N) ports), wherein M times N is equal to L; and configuring each of the M x(N) ports with the specified bandwidth allocation.

11. The method of claim 9, wherein: configuring the plurality of data lanes at the first time is done in response to first configuration data being stored in a set of registers, the first configuration data representing a first lane configuration for the plurality of data lanes; and configuring the plurality of data lanes at the second time is done in response to second configuration data being stored in the set of registers, the second configuration data representing a second lane configuration for the plurality of data lanes.

12. The method of claim 9, wherein: performing the first cryptographic operation on the first data comprises: associating a first key of a plurality of encryption keys with the first data; and encrypting or decrypting the first data using the first key; and performing the second cryptographic operation on the arbitrated data comprises: associating a second key of the plurality of encryption keys with the arbitrated data; and encrypting or decrypting the arbitrated data using the second key.

13. An integrity and data encryption (IDE) engine comprising: a set of L number of data lanes coupled to a plurality of interconnect controllers, wherein the set of L number of data lanes is configured as either (i) a single port having the L number of data lanes in a first lane configuration or (ii) M number of ports having N number of data lanes in a second lane configuration, wherein M times N is equal to L;arbitration logic coupled to the set of L number of data lanes, wherein the arbitration logic, in the second lane configuration, is to arbitrate data from the M number of ports according to a reconfigurable bandwidth allocation; and a cryptographic circuit coupled to the arbitration logic, wherein the cryptographic circuit is configured to encrypt or decrypt first data received on the single port in the first lane configuration and encrypt or decrypt arbitrated data received from the arbitration logic in the second lane configuration.

14. The IDE engine of claim 13, further comprising a set of registers to store first configuration data representing the first lane configuration for the set of L number of data lanes or second configuration data representing the second lane configuration for the set of L number of data lanes.

15. The IDE engine of claim 13, wherein each data lane comprising a first pair of differential signal lines for transmit data and a second pair of differential signal lines for receive data, wherein the IDE engine further comprises: a first stream association circuit to associate a first encryption key with the transmit data; and a second stream association circuit to associate a second encryption key with the receive data.

16. The IDE engine of claim 13, wherein the cryptographic circuit comprises: an encryption circuit; and a decryption circuit.

17. The IDE engine of claim 13, wherein: at a first time: the set of L number of data lanes is configured as (i) the single port in the first lane configuration; the cryptographic circuit is to receive the first data from the single port; the cryptographic circuit is to encrypt or decrypt the first data; and the cryptographic circuit is to return the first data to the single port; and at a second time:the set of L number of data lanes is configured as (ii) the M number of ports in the second lane configuration; a first port of the M number of ports is to receive second data; a second port of the M number of ports is to receive third data concurrently with the second data; the arbitration logic is to select the second data as the arbitrated data; the cryptographic circuit is to receive the arbitrated data from the arbitration logic; the cryptographic circuit is to encrypt or decrypt the arbitrated data; and the cryptographic circuit is to return the arbitrated data back to the first port.

18. The IDE engine of claim 13, wherein the arbitration logic comprising: a transmit (TX) arbiter; and a receive (RX) arbiter.

19. The IDE engine of claim 13, wherein the plurality of interconnect controllers are Peripheral Component Interconnect Express controllers (PCIe controllers).

20. The IDE engine of claim 13, wherein at least one of the plurality of interconnect controllers is at least one of a Peripheral Component Interconnect Express controller (PCIe controller); a Universal Chiplet Interconnect Express controller (UCIe controller); an Ultra Accelerator Link controller (UALink controller); or a Compute Express Link controller (CXL controller).

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