Memory device and operation method therefor, memory system, and memory controller

Abstract

Disclosed in embodiments of the present application are a memory device and an operation method therefor, a memory system, a memory controller, and a storage medium. The memory device comprises: a memory cell array comprising a plurality of memory cells, a preset number of memory cells forming a code word; and a peripheral circuit coupled with the memory cell array and configured to: acquire M corresponding first results of at least one code word under M target read voltages, the first results representing the number of bits flipped in two read results of the at least one code word under a first read voltage and a second read voltage, and the difference between the first read voltage and the second read voltage being less than a preset voltage; on the basis of the M first results and the M target read voltages, in combination with a preset function model representing the relationship between the first results and the target read voltages, obtain a predicted minimum operating voltage; and determine a target minimum operating voltage on the basis of the predicted minimum operating voltage, the target minimum operating voltage being used as a read voltage when performing a read operation on the at least one code word, wherein M is an integer greater than or equal to 1.

Description

Memory device and operating method thereof, memory system, and memory controller TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and relate to, but are not limited to, a memory device and operating method thereof, a memory system, a memory controller, and a storage medium. BACKGROUND

[0002] With the development of technology, the market size of the integrated circuit industry is becoming larger and larger, and the process and technology of the non-volatile memory device in the entire integrated circuit industry have developed by leaps and bounds in recent years. Among them, the application of NAND type memory is particularly widespread. The NAND type memory realizes the function of data storage by capturing and storing electric charges in the gate dielectric layer of the storage unit it contains. However, as the use time increases, the electric charges stored in the storage unit will change with the increase of the use time, repeated read operations, cross temperature, etc., thereby affecting the correctness of reading the data stored in the storage unit.

[0003] SUMMARY

[0004] In a first aspect, embodiments of the present application provide a memory device, comprising: a storage unit array comprising a plurality of storage units, a preset number of the storage units forming a code word; a peripheral circuit coupled to the storage unit array and configured to: obtain M first results corresponding to at least one code word under M target read voltages; the first result comprises the number of bits representing the flipping of the twice reading results of at least one code word under a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; obtain a predicted valley bottom voltage according to the M first results and the M target read voltages, combined with a preset function model; the preset function model represents the relationship between the first result and the target read voltage; and determine a target valley bottom voltage based on the predicted valley bottom voltage; the target valley bottom voltage is used as a read voltage when performing a read operation on at least one code word; wherein M is an integer greater than or equal to 1.

[0005] In a second aspect, embodiments of the present application provide a memory system, one or more memory devices as described in any of the first aspects; and a memory controller coupled to the memory device and controlling the memory device.

[0006] In a third aspect, an embodiment of the present application provides a memory controller coupled with at least one memory device, the memory device including a plurality of memory cells, a preset number of the memory cells forming a code word; the memory controller including: a control unit configured to: obtain M first results corresponding to at least one code word under M target read voltages; the first result including a number of bits representing a flipping in two read results of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage being less than a preset voltage; obtaining a predicted valley voltage based on the M first results and the M target read voltages in combination with a preset function model; the preset function model representing a relationship between the first result and the target read voltage; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage being used as a read voltage for the at least one code word when performing a read operation; wherein the M is an integer greater than or equal to 1.

[0007] In a fourth aspect, an embodiment of the present application provides an operation method of a memory device, the memory device including a plurality of memory cells, a preset number of the memory cells forming a code word; the operation method including: obtaining M first results corresponding to at least one code word under M target read voltages; the first result including a number of bits representing a flipping in two read results of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage being less than a preset voltage; obtaining a predicted valley voltage based on the M first results and the M target read voltages in combination with a preset function model; the preset function model representing a relationship between the first result and the target read voltage; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage being used as a read voltage for the at least one code word when performing a read operation; wherein the M is an integer greater than or equal to 1.

[0008] In a fifth aspect, an embodiment of the present application provides a storage medium, the storage medium having stored thereon executable instructions which, when executed, can implement the steps of any one of the operation methods provided in the fourth aspect. BRIEF DESCRIPTION OF DRAWINGS

[0009] In the drawings, like reference numerals refer to like elements throughout the various drawings. These drawings are not necessarily to scale, and the proportions of certain parts have been exaggerated for the sake of clarity. It should be understood that these drawings are only illustrative and are not intended to limit the scope of the application.

[0010] FIG. 1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0011] FIG. 2A is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0012] FIG. 2B is a schematic diagram of an exemplary solid state drive having a memory system according to an embodiment of the present application;

[0013] FIG. 3 is a schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present application;

[0014] FIG. 4 is a schematic diagram of a cross-section of an array of memory cells including NAND type memory strings according to an embodiment of the present application;

[0015] FIG. 5 is a schematic diagram of an exemplary memory device including an array of memory cells and a peripheral circuit according to an embodiment of the present application;

[0016] FIG. 6 is a schematic diagram of an exemplary read operation flow of a memory system according to an embodiment of the present application;

[0017] FIG. 7 is a schematic diagram of an implementation flow of a method of operations performed by a peripheral circuit of a memory device according to an embodiment of the present application;

[0018] FIG. 8A is a schematic diagram of a threshold voltage distribution of a pair of memory cells including 2 storage bits according to an embodiment of the present application;

[0019] FIG. 8B is a schematic diagram of a threshold voltage distribution of a pair of memory cells including 3 storage bits according to an embodiment of the present application;

[0020] FIG. 8C is a schematic diagram of a threshold voltage distribution of a pair of memory cells including 4 storage bits according to an embodiment of the present application;

[0021] FIG. 9 is a schematic diagram of a threshold voltage distribution of a memory cell when a first result is obtained according to an embodiment of the present application;

[0022] FIG. 10 is a schematic diagram of a preset function model according to an embodiment of the present application;

[0023] FIG. 11 is a schematic diagram of determining a predicted valley bottom voltage according to a preset function model according to an embodiment of the present application;

[0024] FIG. 12 is a schematic diagram of determining a predicted valley bottom voltage according to a preset function model according to an embodiment of the present application;

[0025] FIG. 13 is a schematic diagram of determining a predicted valley bottom voltage according to a preset function model according to an embodiment of the present application;

[0026] FIG. 14A is a schematic diagram of a method of determining a preset threshold value corresponding to a fifth level read voltage of a lower page as shown in FIG. 8B according to an embodiment of the present application;

[0027] FIG. 14B is a second diagram illustrating a method of determining a preset threshold corresponding to a fifth level read voltage according to an embodiment of the present application;

[0028] FIG. 15 is a diagram illustrating a result of determining a target valley voltage of a fifth level read voltage L5 according to an embodiment of the present application;

[0029] FIG. 16 is a diagram illustrating a result of determining a target valley voltage of a sixth level read voltage L6 according to an embodiment of the present application;

[0030] FIG. 17 is a diagram illustrating a result of determining a target valley voltage of a seventh level read voltage L7 according to an embodiment of the present application;

[0031] FIG. 18 is a diagram illustrating an exemplary configuration of a memory system according to an embodiment of the present application;

[0032] FIG. 19 is a block diagram of a memory system according to an embodiment of the present application;

[0033] FIG. 20 is a timing diagram illustrating an exemplary operation of starting a single level read mode according to an embodiment of the present application;

[0034] FIG. 21 is a timing diagram illustrating a method of determining a target valley voltage and performing a read operation according to an embodiment of the present application;

[0035] FIG. 22 is a diagram illustrating an exemplary configuration of a storage medium according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] Example embodiments of the present application will now be described in detail with reference to the accompanying drawings. Although example embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0037] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one of ordinary skill in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily obscure the present application.

[0038] Furthermore, the accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present application and, as such, a change in the drawings can be made for clarity of explanation and emphasis. In the drawings, the same reference numbers and indicators can be used throughout the different drawings to refer to same or like parts.

[0039] The flowcharts shown in the drawings are only exemplary illustrations, and do not necessarily include all the steps. For example, some steps can be further decomposed, and some steps can be combined or partially combined, so the actual execution order can be changed according to the actual situation.

[0040] The terms used herein are only for the purpose of describing specific embodiments and not as a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprise", and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0041] The memory device in the embodiments of the present application includes, but is not limited to, a three-dimensional NAND type memory. For ease of understanding, the three-dimensional NAND type memory is taken as an example for description.

[0042] FIG. 1 illustrates a block diagram of an exemplary system 100 having a memory device, in accordance with some aspects of the present application. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Argument Reality (AR) device, or any other suitable electronic device having a storage. As shown in FIG. 1, the system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 can be a processor (e.g., a Central Processing Unit (CPU)) or a System of Chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 108 can be configured to send or receive data to or from the memory device 104.

[0043] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104, and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0044] In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Muti Media Card (eMMC) used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., and enterprise storage arrays.

[0045] The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes with respect to data read from or written to the memory device 104.

[0046] The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0047] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of memory devices, such as included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0048] In one example as shown in FIG. 2A, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 with a host (e.g., the host 108 in FIG. 1).

[0049] In another example as shown in FIG. 2B, the memory controller 106 and the multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 with a host (e.g., the host 108 in FIG. 1). In some implementations, the SSD 206 has a larger storage capacity and / or a faster operating speed than the memory card 202.

[0050] In some embodiments, each memory block can be coupled with a plurality of word lines, and each word line is coupled with a plurality of memory cells to form a physical page.

[0051] FIG. 3 shows a schematic circuit diagram of an exemplary memory device 300 including a peripheral circuit, in accordance with some aspects of the present application. The memory device 300 can be an example of the memory device 104 in FIG. 1. The memory device 300 can include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. By way of example, the memory cell array 301 is a three-dimensional NAND-type memory cell array, in which the memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each of which extends vertically above a substrate (not shown). In some implementations, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, e.g., a voltage or a charge, that depends on the number of electrons trapped in a region of the memory cell 306. Each memory cell 306 can be a floating-gate type of memory cell that includes a floating gate transistor, or a charge-trapping type of memory cell that includes a charge-trapping transistor.

[0052] In some embodiments, each storage unit 306 is a single-level cell (SLC) that has two possible storage states and thus can store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In some embodiments, each storage unit 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take on one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell, a fourth nominal storage value can be used for the erased state.

[0053] It is noted that the storage states referred to herein are also referred to as storage states of the storage units of the present disclosure. Different storage units have different numbers of storage states. For example, a SLC type storage unit has two storage states (i.e., two memory states), which include one programmed state and one erased state. For another example, a MLC type storage unit has four storage states, which include one erased state and three programmed states. For yet another example, a TLC type storage unit has eight storage states, which include one erased state and seven programmed states. In some embodiments, a QLC type storage unit has sixteen storage states, which include one erased state and fifteen programmed states.

[0054] As shown in FIG. 3, each memory string 308 can include a bottom select transistor (BSG) 310 (also referred to as a source side select transistor) at its source end and a top select transistor (TSG) 312 (also referred to as a drain side select transistor) at its drain end. The BSG 310 and TSG 312 can be configured to activate a selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a respective bit line (BL) 316 from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than a threshold voltage of the transistor having the TSG 312) or a deselect voltage (e.g., 0 V) to the respective TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than a threshold voltage of the transistor having the BSG 310) or a deselect voltage (e.g., 0 V) to the respective BSG 310 via one or more BSG lines 315.

[0055] As shown in FIG. 3, the memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same face as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20 V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable fraction of any suitable number of memory blocks or memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318 that select which row of memory cells 306 is affected by read and program operations.

[0056] Referring to FIG. 3, each memory cell 306 of the plurality of memory cells is coupled to a respective word line 318, and each memory string 308 is coupled to a respective bit line 316 by a respective select transistor (e.g., a top select transistor (TSG) 312).

[0057] FIG. 4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 in NAND as an example, according to some aspects of the present application. As shown in FIG. 4, the NAND memory cell array 301 can include a stack structure 410 including a plurality of gate layers 411 and a plurality of insulating layers 412 alternately and sequentially stacked, and a channel structure vertically penetrating the gate layers 411 and the insulating layers 412, wherein the channel structure and each gate layer form a memory cell, and the channel structure and the plurality of gate layers in the stack structure 410 form a memory string 308. The gate layers 411 and the insulating layers 412 can be alternately stacked, and two adjacent gate layers 411 are separated by an insulating layer 412.

[0058] The constituent material of the gate layers 411 can include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 can include a control gate surrounding a memory cell. The gate layers 411 at the top of the stack structure 410 can laterally extend as upper select gate lines, the gate layers 411 at the bottom of the stack structure 410 can laterally extend as lower select gate lines, and the gate layers 411 laterally extending between the upper select gate lines and the lower select gate lines can serve as word line layers.

[0059] In some embodiments, the stack structure 410 can be disposed on a substrate 401. The substrate 401 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0060] In some embodiments, the storage string 308 includes a channel structure that extends vertically through the stack structure 410. In some implementations, the channel structure includes a channel hole that is filled with a semiconductor material(s) (e.g., as a semiconductor channel) and a dielectric material(s) (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a “charge-trapping / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a column shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0061] Referring back to FIG. 3, the peripheral circuitry 302 can be coupled to the array of memory cells 301 through the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the array of memory cells 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 306 via the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 5 illustrates some exemplary peripheral circuitry including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, registers 514, an interface 516, and a data bus 518. It should be appreciated that additional peripheral circuitry not shown in FIG. 5 can also be included in some examples.

[0062] The page buffer / sense amplifier 504 can be configured to read data from and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed to the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense low power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify small voltage swings to identifiable logic levels in read operations. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying bit line voltages generated from the voltage generator 510.

[0063] The row decoder / word line driver 508 can be configured to be controlled by the control logic 512 and select / deselect memory blocks 304 of the memory cell array 301 and select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from the voltage generator 510. In some implementations, the row decoder / word line driver 508 can also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform program operations on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic 512 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, channel boost voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0064] Control logic 512 can be coupled to each of the other portions of the peripheral circuitry described above and configured to control operation of each of the other portions of the peripheral circuitry. Registers 514 can be coupled to control logic 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control operation of each of the peripheral circuitry. Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic 512, and to buffer status information received from control logic 512 and relay them to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and act as a data I / O interface and data buffer to buffer data and relay them to or from memory cell array 301.

[0065] The basic principle of a three-dimensional NAND type memory is that a carrier (electron or hole) injects a certain amount of charge into a memory cell to complete the data writing process, and then the stored data can be read according to the threshold voltage when the memory cell is turned on. Therefore, in order to read the correct data, a high-efficiency error correction algorithm with strong error correction capability is usually introduced during data reading.

[0066] However, as the use time increases, the charge stored in the memory cell will change with the increase of the use time, repeated read operations, cross temperature, etc., thereby affecting the correctness of data reading. When the threshold voltage shifts upward or downward significantly, the possibility of reading error will be very large when the original read voltage is used to read the data of the memory cell, and when the read error exceeds the error correction capability, it will also cause the data reading of the memory cell to fail.

[0067] Figure 6 shows a schematic diagram of an exemplary read operation flow of a memory system. In conjunction with Figure 6, when the memory controller controls the memory device to perform a read operation, first, the default read operation (FW default read) is performed on the memory cell of the corresponding physical address, and when the default read operation fails, the read retry operation is performed, and when the read retry operation fails, the soft decode operation is performed, and when the soft decode operation fails, the redundant array of independent disk (RAID) operation is performed, and when the RAID operation fails, the read operation stops and fails to correct the error, and the memory controller sends a read fail signal to the host 108. The read retry operation and the default read operation can be applied to the hard decode (Hard decode).

[0068] In some embodiments, a retry operation can be generally performed by querying a retry table provided by a manufacturer. The essence of the retry operation is an error correction mechanism, and the retry table can provide a reference voltage for reading data. By querying the retry table, the read voltage deviating from the normal threshold voltage is tried to read each memory cell again and correct errors with an error correction algorithm, trying to correctly read the data. If the read error data is corrected, the querying of the retry table is stopped. If the read error data cannot be corrected, the retry table is queried until the entire retry table is traversed.

[0069] The above-mentioned retry operation mode will inevitably increase the number of trial and error and consume a lot of time because the retry table is queried piece by piece. In addition, the retry table provided by the manufacturer is only a reference value in some specific environment, and the real use scenario is changing, so the retry table provided by the manufacturer cannot cover many scenarios. Therefore, the data may not be corrected even if the retry table is traversed, which will waste a lot of processing command time. In summary, the retry operation mode by repeatedly polling the retry table consumes a lot of time and affects the response time of subsequent commands, thereby affecting the performance of the device.

[0070] Based on one or more of the above problems, in a first aspect, an embodiment of the present application proposes a memory device.

[0071] As shown in FIG. 7, the memory device includes: a memory cell array including a plurality of memory cells, a preset number of memory cells forming a code word; a peripheral circuit coupled to the memory cell array and configured to perform the following steps:

[0072] Step S10: obtaining M first results corresponding to at least one code word under M target read voltages; the first result includes the number of bits representing the flipping in the two read results of the at least one code word under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage.

[0073] Step S20: obtaining a predicted valley voltage according to the M first results and the M target read voltages in combination with a preset function model; the preset function model represents the relationship between the first result and the target read voltage.

[0074] Step S30: determining a target valley voltage based on the predicted valley voltage; the target valley voltage is used as a read voltage when performing a read operation on the at least one code word; wherein M is an integer greater than or equal to 1.

[0075] It should be noted that the predicted valley voltage can be directly used as a target valley voltage to perform a read operation on the read data according to requirements, or a target valley voltage can be obtained after further processing. The specific way of obtaining the predicted valley voltage will be further described below.

[0076] Here, the structure of the memory device is referred to the aforementioned FIG. 3, which will not be described again here.

[0077] In some embodiments, the memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of word lines and a plurality of memory cells coupled on each word line. All memory cells coupled on a word line form a physical page. A predetermined number of memory cells form a code word (CW). A physical page includes one or more code words.

[0078] In some embodiments, a code word contains the same number of memory cells as the number of memory cells contained in one encoding or decoding when performing error correction encoding or decoding. In some specific embodiments, a code word contains a number of memory cells that can be less than or equal to the number of memory cells coupled to a physical page, such as a code word containing 1 / 4 of the number of memory cells coupled to a physical page. In some specific embodiments, a code word can include a number of memory cells ranging from 2 4 to 2 12 . For example, a code word can include 2 4 , 2 8 , or 2 12 memory cells.

[0079] In general, different memory systems can choose different sizes of code words to meet their performance, reliability, and storage requirements. The number of bits stored by memory cells in different types of memory devices (such as MLC, TLC, or QLC) is different. It can be understood that a code word can include a plurality of memory cells, and the number of memory cells included in a code word can be adjusted according to actual conditions.

[0080] It should be noted that in practice, a code word will have some additional reserved space for management and error correction, so the actual number of memory cells required may be slightly more than the calculation result above.

[0081] Here, the target valley voltage is used as a read voltage when performing a read operation on at least one of the code words. The way of obtaining the target valley voltage in the memory device according to the combination of a limited number of target read voltages and the first result according to a predetermined function model can reduce the number of loop iterations and determine the target valley voltage faster.

[0082] The following introduces the meaning of the first result and the specific way to obtain the first result.

[0083] Here, the first result represents the number of bits that flip in the twice reading results of the codeword to be executed for the read operation under the first read voltage and the second read voltage.

[0084] In some embodiments, in the process of reading the memory device, one read operation reads out the data of one physical page, and when the number of storage units included in one codeword is less than the number of storage units coupled by one physical page, the codeword is the unit that can be executed to obtain the first result, but it is not excluded that it is multiple codewords. That is, at least one codeword corresponding to the first result under the target read voltage can be obtained here. For example, one physical page can correspond to 4 codewords, and the page buffer hardware operation can count the Fail Bit Count (FBC) of the 4 codewords respectively at one time, and then the FBC of the four codewords is added to obtain the FBC of one physical page, and the subsequent calculation uses the added value. It can be understood that the first result here can be based on the data of one physical page, and one physical page can correspond to multiple codewords.

[0085] In some embodiments, the storage unit array includes storage units with P storage bits, and the P storage bits correspond to P pages, and the P storage bits are read by Q-level read voltages; P and Q are both integers greater than 1, and Q = 2 P -1.

[0086] For example, when the number of storage bits of the storage unit includes two bits, the corresponding storage states include the 0th state to the 4th state. Referring to FIG. 8A, the four states are the 0th state (also referred to as the erase state) E, the 1st state (also referred to as the 1st storage state) P1, the 2nd state (also referred to as the 2nd storage state) P2, and the 3rd state (also referred to as the 3rd storage state) P3. The binary data corresponding to the four states are 11, 10, 00, and 01, respectively. Accordingly, the memory device includes two pages, which are the lower page (LP) and the upper page (UP).

[0087] For example, referring to the storage unit shown in FIG. 8A, the two-bit storage unit reads the storage data of the four states of the two bits by three-level read voltages (the first-level read voltage L1, the second-level read voltage L2, and the third-level read voltage L3 shown in FIG. 8A).

[0088] Exemplarily, one page corresponds to multiple levels of read voltage, and another page corresponds to one level of read voltage, as shown in FIG. 8A, the binary data corresponding to the lower page is 1001 respectively, and the first level of read voltage L1 and the third level of read voltage L3 are needed to read the lower page. The binary data corresponding to the upper page is 1100 respectively, and the second level of read voltage L2 is needed to read the upper page.

[0089] Exemplarily, when the number of storage bits of the storage unit includes three bits, the corresponding storage states include the 0th state to the 7th state, as shown in FIG. 8B, the 8 states are the 0th state (also referred to as the erase state) E, the 1st state (also referred to as the 1st storage state) P1, the 2nd state (also referred to as the 2nd storage state) P2, …, the 7th state (also referred to as the 7th storage state) P7 respectively, and the binary data corresponding to the 8 states are 111, 110, 100, 000, 010, 011, 001, 101 respectively. Accordingly, the memory device includes three pages, which are the lower page, the middle page (MP), and the upper page.

[0090] Exemplarily, when the number of storage bits of the storage unit includes three bits, the corresponding storage states include the 0th state to the 7th state, as shown in FIG. 8B, the 8 states are the 0th state (also referred to as the erase state) E, the 1st state (also referred to as the 1st storage state) P1, the 2nd state (also referred to as the 2nd storage state) P2, …, the 7th state (also referred to as the 7th storage state) P7 respectively, and the binary data corresponding to the 8 states are 111, 110, 100, 000, 010, 011, 001, 101 respectively. Accordingly, the memory device includes three pages, which are the lower page, the middle page (MP), and the upper page.

[0091] Exemplarily, one page corresponds to multiple levels of read voltage, and another page corresponds to one level of read voltage, as shown in FIG. 8A, the binary data corresponding to the lower page is 1001 respectively, and the first level of read voltage L1 and the third level of read voltage L3 are needed to read the lower page. The binary data corresponding to the upper page is 1100 respectively, and the second level of read voltage L2 is needed to read the upper page.

[0092] Exemplarily, when the number of storage bits of the storage unit includes three bits, the corresponding storage states include the 0th state to the 7th state, as shown in FIG. 8B, the 8 states are the 0th state (also referred to as the erase state) E, the 1st state (also referred to as the 1st storage state) P1, the 2nd state (also referred to as the 2nd storage state) P2, …, the 7th state (also referred to as the 7th storage state) P7 respectively, and the binary data corresponding to the 8 states are 111, 110, 100, 000, 010, 011, 001, 101 respectively. Accordingly, the memory device includes three pages, which are the lower page, the middle page (MP), and the upper page.

[0093] For example, the four-bit memory cell shown in FIG. 8C reads its four-bit sixteen-state stored data through the 15-level read voltage (the first-level read voltage L1, the second-level read voltage L2, the third-level read voltage L3, the fourth-level read voltage L4, the fifth-level read voltage L5, the sixth-level read voltage L6, the seventh-level read voltage L7, the eighth-level read voltage L8, the ninth-level read voltage L9, the tenth-level read voltage L10, the eleventh-level read voltage L11, the twelfth-level read voltage L12, the thirteenth-level read voltage L13, the fourteenth-level read voltage L14, and the fifteenth-level read voltage L15 shown in FIG. 8C).

[0094] For example, each page corresponds to a plurality of levels of read voltage, as shown in FIG. 8C, the binary data corresponding to the lower page is 1100000011111100, respectively, and the second-level read voltage L2, the eighth-level read voltage L8, and the fourteenth-level read voltage L14 are required to read the lower page. The binary data corresponding to the middle page is 1110000110000111, respectively, and the third-level read voltage L3, the seventh-level read voltage L7, the ninth-level read voltage L9, and the thirteenth-level read voltage L13 are required to read the middle page. The binary data corresponding to the upper page is 1111100000110001, respectively, and the fifth-level read voltage L5, the tenth-level read voltage L10, the twelfth-level read voltage L12, and the fifteenth-level read voltage L15 are required to read the upper page. The binary data corresponding to the extra page is 1000110000011111, respectively, and the first-level read voltage L1, the fourth-level read voltage L4, the sixth-level read voltage L6, and the eleventh-level read voltage L11 are required to read the extra page.

[0095] The lower page is usually closest to the source / drain, so the target valley voltage of each level of read voltage corresponding to the level of read voltage of the lower page is determined in priority, the access speed is the fastest, the response time is the shortest, and the balanced performance and durability during data access can be ensured.

[0096] It should be noted that the manner of determining the target valley voltage of each level of read voltage corresponding to the level of read voltage of the lower page in priority is only an example, and is not used to limit the determination order of the target valley voltage of each level of read voltage in the plurality of levels of read voltage corresponding to at least part of the pages.

[0097] Here, the first read voltage and the second read voltage are both generic concepts, and a difference between the first read voltage and the second read voltage is less than a preset voltage. In some embodiments, the second read voltage is greater than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of 5 mV to 20 mV. For example, the difference between the first read voltage and the second read voltage can be 5 mV, 10 mV, 15 mV, or 20 mV. In other embodiments, the second read voltage is less than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of -5 mV to -20 mV. For example, the difference between the first read voltage and the second read voltage can be -5 mV, -10 mV, -15 mV, or -20 mV.

[0098] In some embodiments, the peripheral circuit is configured to: read the stored data of the at least one code word at the first read voltage to obtain a second result; read the stored data of the at least one code word at the second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count a number of bits in the fourth result that represent a flip of the third result relative to the second result to obtain the first result.

[0099] In some embodiments, the peripheral circuit includes: a first latch, a second latch, and a third latch. The first latch is configured to store the second result. The second latch is configured to store the third result. The third latch is configured to store the fourth result.

[0100] Here, the first read voltage and the second read voltage are associated in sequence, that is, the second read voltage is obtained by a third adjustment based on the first read voltage. Based on this, a pressure difference between the first read voltage and the second read voltage is the third step. In some embodiments, the first step is set to a range of 5 mV to 20 mV. For example, the third step can be 5 mV, 10 mV, 15 mV, or 20 mV. The preset voltage is related to the third step, and can be a voltage slightly greater than the third step. In some embodiments, the preset voltage is set to a range of 6 mV to 21 mV. For example, the preset voltage can be 6 mV, 11 mV, 16 mV, or 21 mV. In other embodiments, the preset voltage is set to a range of -6 mV to -21 mV. For example, the preset voltage can be -6 mV, -10 mV, -16 mV, or -21 mV.

[0101] It is to be noted that the first read voltage and the second read voltage are generic concepts, and the target read voltage and the read voltage obtained after the first adjustment and the second adjustment of the target read voltage can all be referred to as the first read voltage, and the read voltage obtained after the third adjustment of the first read voltage can all be referred to as the second read voltage. That is, the first read voltage is a generic concept, which can be understood as the target read voltage or the target adjusted read voltage (the voltage obtained after the target read voltage is adjusted by a target step, and the range of the target step can be set to 20 mV to 40 mV, for example, the first step of the first adjustment can be 20 mV, 30 mV, or 40 mV, and the range of the target step can also be set to 50 mV to 150 mV, for example, the second step of the second adjustment can be 50 mV, 60 mV, 70 mV, 80 mV, 100 mV, 120 mV, or 150 mV).

[0102] In some embodiments of the present application, the first result corresponding to a specific voltage (for example, the first read voltage V0 shown in FIG. 9) can be understood as follows: the third adjustment is performed on the specific voltage, that is, the specific voltage and the specific voltage after the third adjustment (for example, the second read voltage V1 shown in FIG. 9) have a first voltage difference AV1, and the number of bits that flip in the two read results of the preset number of storage units at the specific voltage and the specific voltage after the third adjustment can be used as the first result corresponding to the specific voltage, wherein the preset number of storage units can form at least one codeword.

[0103] In some embodiments, before obtaining the first result corresponding to the target read voltage of the at least one codeword, the read mode of the memory device is set to a single level read (SLR) mode; the single level read mode includes reading at least one bit of storage data stored in the storage unit by a first level read voltage.

[0104] In some specific embodiments, the memory device is configured to enter the single level read mode in response to a mode setting command, and obtain the first result corresponding to the target read voltage of the at least one codeword in the single level read mode.

[0105] In some specific embodiments, the storage data of the codeword is read at the first read voltage to obtain a second result; and the second result is stored in a first latch of the memory device. For example, as shown in FIG. 9, the storage data of the at least one codeword is read at the first read voltage V0 to obtain a second result. Specifically, the storage unit with a threshold voltage less than the target read voltage V0 is marked as bit 1, and the storage unit with a threshold voltage greater than the target read voltage V0 is marked as bit 0 to obtain the second result, and the second result is stored in the first latch of the memory device.

[0106] Next, the first read voltage is adjusted for a third time to obtain a second read voltage, at which the stored data of the at least one codeword is read to obtain a third result; the third result is stored in a second latch of the memory device. Exemplarily, as shown in FIG. 9, the first read voltage V0 is adjusted for a third time to obtain a second read voltage V1 at which the stored data of the codeword is read to obtain a third result. Specifically, the storage cells with threshold voltages less than the second read voltage V1 are marked as bit 1, and the storage cells with threshold voltages greater than the second read voltage V1 are marked as bit 0 to obtain the third result, which is stored in a second latch of the memory device.

[0107] Next, the second result and the third result are subjected to a logical operation to obtain a fourth result; the fourth result is stored in a third latch of the memory device. Exemplarily, as shown in FIG. 9, the second result and the third result are subjected to an exclusive-OR operation to obtain a fourth result; the fourth result is stored in a third latch of the memory device.

[0108] It should be noted that the exclusive-OR operation is one of the basic logical operations, in binary, if two binary numbers at the same position are the same, the result is “0”, and if two binary numbers at the same position are different, the result is “1” (i.e., same is 0, different is 1).

[0109] Next, the number of bits in the fourth result representing the flipping of the third result relative to the second result is counted to obtain the first result. Exemplarily, as shown in FIG. 9, the part of the fourth result with bit 1 represents the number of storage cells with threshold voltages different between the first read voltage V0 and the second read voltage V1, in other words, the part of the fourth result with bit 1 represents the number of bits flipped in the two read results of the codeword at the first read voltage V0 and the second read voltage V1, which is denoted as the first result Y1 corresponding to the first read voltage V0.

[0110] It should be noted that the first result is also referred to as FBC in the embodiments of the present application.

[0111] In some embodiments, the preset function model is related to the characteristics of the memory device, and the preset function model can be fitted from a large number of experimental results before the memory device is shipped and saved in the memory device.

[0112] Exemplarily, the preset function model is encoded into a code, and the code is saved in the firmware or software of the memory device.

[0113] In some embodiments, a large amount of data is collected through a large number of experiments before the memory device is shipped, which can be preprocessed by removing outliers, sorting, denoising, etc. and analyzed using statistical methods, machine learning or other modeling techniques to fit a preset function model to describe the relationship between the target read voltage and the first result.

[0114] Exemplarily, a regression analysis method is used to fit a preset function model through a large amount of collected target read voltage and corresponding first result.

[0115] Exemplarily, a data-driven method such as machine learning or deep learning is used to establish a preset function model to represent the relationship between the target read voltage and the first result through a large amount of collected target read voltage and corresponding first result.

[0116] In some embodiments, the preset function model includes a quadratic function model including the following function relationship: y = a(x + b) 2 + c

[0117] where y is the first result, x is the target read voltage, b represents the prediction parameter, a is the first parameter, and c is the second parameter.

[0118] As shown in FIG. 10, in combination with the function relationship included in the above-mentioned quadratic function model, it can be known that the extreme value of the curve of the quadratic function model is located at the position of the symmetry axis x = -b, i.e. the position where the derivative of the curve of the quadratic function model is 0. Exemplarily, when the first parameter is greater than 0, the y value (first result) corresponding to x = -b is the minimum value of the curve of the quadratic function model, and the coordinates of the extreme point (black solid point shown in FIG. 10) are (-b, c).

[0119] In some embodiments, the prediction parameter takes the value of the opposite of b, i.e. the prediction parameter represents the horizontal coordinate corresponding to the minimum value of the curve of the quadratic function model.

[0120] As shown in FIG. 10, the symmetry axis of the curve of the quadratic function model (at x = -b) is offset from the y-axis (at x = 0) by -b, i.e. the distance between the symmetry axis of the curve of the quadratic function model and the y-axis is the absolute value |b| of b.

[0121] Here, x=0 can be understood as a position of a default read voltage, and the default read voltage can be a read voltage when a threshold voltage of the storage unit has not been shifted, such as a read voltage corresponding to the time of just writing, and the corresponding shift value is 0. It can be understood that when the shift value of the target read voltage compared to the default read voltage (x=0) is -b, the corresponding first result at the target read voltage is the minimum value. It can be understood that the target read voltage (here equivalent to the predicted valley bottom voltage) corresponding to the time when the first result is the minimum value is taken as the predicted valley bottom voltage, and based on the predicted valley bottom voltage, the target valley bottom voltage is determined, and the error rate of the read result is low and the reliability is high.

[0122] It should be noted that when there is only one set of prediction parameters, the prediction parameters are directly taken as the predicted valley bottom voltage. However, when there are multiple sets of prediction parameters, the predicted valley bottom voltage needs to be determined based on the multiple sets of prediction parameters.

[0123] In some embodiments, the peripheral circuit is configured to: obtain N sets of prediction parameters according to the M first results, the M target read voltages, and the quadratic function model; wherein, the i is an integer, and 1≤i≤M; and obtain the predicted valley bottom voltage according to the N sets of prediction parameters.

[0124] Exemplarily, the M first results corresponding to the at least one codeword at the M target read voltages are obtained according to the manner of obtaining the first result in the foregoing embodiments.

[0125] When M is greater than or equal to 2, the voltage difference between the M target read voltages can be equal to the first adjusted step size or equal to the second adjusted step size.

[0126] In some embodiments, i is equal to 1, and the first parameter and the second parameter are both constants; and the peripheral circuit is configured to: obtain N sets of prediction parameters according to the M first results, the M target read voltages, the quadratic function model, the first parameter, and the second parameter.

[0127] Exemplarily, when i is equal to 1, N is equal to M.

[0128] Here, the first parameter and the second parameter can be obtained when fitting the preset function model, and are saved in the memory device. Exemplarily, the preset function model includes the quadratic function model, and the quadratic function model includes the following function relationship: y=a(x+b) 2 +c

[0129] The first parameter and the second parameter in the function relationship can be optimized using, but not limited to, least squares method, gradient descent method, Bayesian optimization, Newton method and quasi-Newton method, and the optimal first parameter and the second parameter are saved in the memory device. Among them, the least squares method is a parameter estimation method that estimates the parameters by minimizing the sum of squares of residuals between the actually collected data and the predicted values of the quadratic function model. The gradient descent method is to take the parameters of the quadratic function model as the optimization target, use the gradient descent method to find the parameter value that minimizes the fitting error of the quadratic function model, calculate the gradient of the loss function with respect to the first parameter and the second parameter, and then update the value of the first parameter and the second parameter in the opposite direction of the gradient until convergence is reached.

[0130] In some embodiments, i is equal to M; the peripheral circuit is configured to: obtain a set of predicted parameters according to the M first results, the M target read voltages, and the quadratic function model; and take the predicted parameters as the predicted valley bottom voltage.

[0131] In some implementations, M is equal to 1, as shown in FIG. 11, a target read voltage and a corresponding first result at the target read voltage are obtained, the point (the hollow point shown in FIG. 11) corresponds to coordinates (x1, y1), and according to the function relationship of the quadratic function model and the fact that the first parameter and the second parameter are constants, the calculation formula (1) of b is as follows:

[0132] As shown in FIG. 11, the distance between the symmetry axis x = b of the curve of the quadratic function model and the y-axis is the absolute value |b| of the predicted parameter.

[0133] In some embodiments, each level of read voltage has a corresponding preset function model.

[0134] In some specific implementations, the specific calculation formula of the predicted parameter is related to the level number of the target read voltage and / or the use scenario (such as a data retention scenario or a read disturb scenario) of the memory device.

[0135] Exemplarily, in the data retention scenario, taking TLC as an example, the target valley bottom voltage of the seventh level read voltage L7 of the upper page is to be determined, the level number of the target read voltage is L7, and according to the characteristics of the memory device, it can be considered that the threshold voltage of the memory cell of the memory device is in a strong left shift state, and the calculation formula (1-1) of b at this time is:

[0136] Exemplarily, in the read operation interference scenario, taking TLC as an example, to determine the target valley bottom voltage of the seventh level read voltage L7 of the upper page, i.e., the level number of the target read voltage is L7, according to the characteristics of the memory device, it can be considered that the threshold voltage of the memory cell of the memory device is in a strong left shift state, and at this time, the calculation formula (1-1) of b is:

[0137] Exemplarily, in the read operation interference scenario, taking TLC as an example, to determine the target valley bottom voltage of the first level read voltage L1 of the lower page, i.e., the level number of the target read voltage is L1, according to the characteristics of the memory device, it can be considered that the threshold voltage of the memory cell of the memory device is in a strong right shift state, and at this time, the calculation formula (1-2) of b is:

[0138] It should be noted that in the case where the use scenario of the memory device is unknown and the shift state of the threshold voltage of the memory cell of the memory device is unknown, two different values of b are obtained according to the calculation formula (1), and then two different prediction parameters are obtained, and two prediction valley bottom voltages are determined based on the two prediction parameters. In some embodiments, according to the first result corresponding to the prediction valley bottom voltage being less than a preset threshold, the prediction valley bottom voltage is taken as the target valley bottom voltage. The preset threshold will be described in detail later.

[0139] In this way, by obtaining a target read voltage and a first result corresponding to the target read voltage, a prediction parameter can be calculated, the prediction parameter is taken as a prediction valley bottom voltage, and based on the prediction valley bottom voltage, a target valley bottom voltage is determined, and the error rate of the read result is low and the reliability is high.

[0140] In some embodiments, the peripheral circuit is configured to: determine outliers of the N groups of prediction parameters; and take the median or average of the remaining prediction parameters after removing the outliers of the N groups of prediction parameters as the prediction valley bottom voltage.

[0141] In some embodiments, the peripheral circuit is configured to: determine outliers based on the median and standard deviation of the N groups of prediction parameters, or take the maximum and minimum values in the N groups of prediction parameters as the outliers, and take the median or average of the remaining prediction parameters after removing the outliers of the N groups of prediction parameters as the prediction valley bottom voltage.

[0142] In some embodiments, i is equal to 1, M is greater than 1, N is equal to M, and based on M target read voltages and M first results, M groups of prediction parameters can be obtained by referring to the calculation formula (1) of b. The peripheral circuit is configured to: determine outliers of the M groups of prediction parameters; and take the median or average of the remaining prediction parameters after removing the outliers of the M groups of prediction parameters as the prediction valley bottom voltage.

[0143] In this way, by obtaining multiple target reading voltages and multiple first results corresponding to the multiple target reading voltages, multiple sets of prediction parameters can be calculated. By determining the outliers of the multiple sets of prediction parameters and removing the outliers, the accuracy and reliability of the remaining prediction parameters when determining the predicted valley voltage can be ensured.

[0144] In some embodiments, i is equal to 2, the first parameter is a variable, and the second parameter is a constant; the peripheral circuit is configured to obtain N groups of prediction parameters and the first parameter based on M first results, M target read voltages, a quadratic function model, and the second parameter.

[0145] For example, when i is equal to 2, N is equal to

[0146] Here, the second parameter may be obtained when fitting the preset function model and stored in the memory device.

[0147] In some embodiments, M is equal to 2, then N is equal to 1. As shown in FIG12 , two target read voltages and two first results corresponding to the two target read voltages are obtained. The coordinates corresponding to the two points (the hollow points shown in FIG12 ) are (x1, y1) and (x2, y2). Based on the functional relationship of the quadratic function model and the second parameter being a constant, the calculation formula (2) for b can be obtained as follows:

[0148] By obtaining two target read voltages and the first results corresponding to the two target read voltages, b can be calculated, and then a set of prediction parameters can be obtained, and the prediction parameters are used as the predicted valley voltage.

[0149] Based on the calculation formula (2) of b, according to the functional relationship of the quadratic function model and the second parameter being a constant, the calculation formula (3) of the first parameter can be obtained as follows:

[0150] In some embodiments, i is equal to 2, M is greater than 2, and N is equal to Based on the M target read voltages and the M first results, we can obtain A combination method of two target read voltages and their corresponding two first results, based on Combining these two combinations with the calculation formula (2) of b, we can obtain Set of prediction parameters. The outliers of the group prediction parameters; The median or average value of the remaining prediction parameters after removing outliers in the group prediction parameters is used as the predicted valley voltage.

[0151] In some embodiments, i is equal to 3, the first parameter and the second parameter are variables; the peripheral circuit is configured to obtain N groups of predicted parameters, the first parameter and the second parameter according to the M first results, the M target read voltages and the quadratic function model.

[0152] Exemplarily, when i is equal to 3, N is equal to

[0153] In some embodiments, M is equal to 3, and N is equal to 1. As shown in FIG. 13, three target read voltages and corresponding three first results under the three target read voltages are obtained, and the coordinates of the three points (the hollow points shown in FIG. 13) are (x1, y1), (x2, y2) and (x3, y3). According to the function relationship of the quadratic function model, the calculation formula (4) of b is as follows:

[0154] By obtaining the three target read voltages and the corresponding first results under the three target read voltages, b can be calculated, and then a group of predicted parameters can be obtained, and the predicted parameters are used as the predicted valley bottom voltage.

[0155] Based on the calculation formula (4) of b, according to the function relationship of the quadratic function model, the calculation formula (5) of the first parameter is as follows:

[0156] And the calculation formula (6) of the second parameter is as follows: c=y1-a×(x1 2 +b)

[0157] In some embodiments, i is equal to 3, M is greater than 3, and N is equal to Based on the M target read voltages and the M first results, a combination of three target read voltages and corresponding three first results can be obtained, based on the combination and the calculation formula (4) of b, a group of predicted parameters can be obtained. The outliers of the group of predicted parameters are determined; and the median or the average of the remaining predicted parameters after the group of predicted parameters is removed from the outliers is used as the predicted valley bottom voltage.

[0158] In some embodiments, the peripheral circuit is configured to obtain a preset threshold according to the first result corresponding to the first target read voltage in the M target read voltages; and the preset threshold is used to represent the first result corresponding to the maximum value in the effective range of the predicted valley bottom voltage.

[0159] ​In some embodiments, the first target read voltage among the M target read voltages can be set according to an empirical value (e.g., a read voltage corresponding to successful reading of data); or can be a default value configured for the memory device at the time of shipment of the memory device, which is obtained through a large number of simulation experiments before the memory device is shipped; the default read voltage can be a default value configured for the memory device at the time of shipment of the memory device, which is obtained through a large number of simulation experiments.

[0160] The first result corresponding to the first target read voltage among the M target read voltages can be referred to as a first-time first result, and the first result corresponding to the default read voltage can be referred to as a default first result.

[0161] In some embodiments, the preset threshold value is positively correlated with the offset degree, and the offset degree is the absolute value of the difference between the first-time first result and the default first result.

[0162] Here, the preset threshold value is used to represent the maximum value in the range of the predicted effective valley voltage. The preset threshold value can be determined according to the first result under the first target read voltage. It can be understood that when the read operation is performed, the further the threshold voltage of the storage unit deviates from the threshold voltage at the time of writing, the larger the first result read by using the first target read voltage will generally be. Based on this, the specific value of the first result read by using the first target read voltage can be used to confirm the preset threshold value, which is used to represent the change (elevation) of the valley voltage caused by the deviation of the threshold voltage of the storage unit.

[0163] It should be noted that when the first result is less than the preset threshold value, it indicates that the target valley voltage can be directly determined next.

[0164] In some embodiments, when the first result is less than the preset threshold value, it indicates that the predicted valley voltage corresponding to the first result at this time can be taken as the target valley voltage.

[0165] For example, the larger the absolute value of the difference between the first-time first result and the default first result, the larger the preset threshold value. As shown in FIG. 14A, the difference between the first-time first result Y11 and the default first result Y13 is smaller than that in FIG. 14B, and the preset threshold value (Y12 shown in FIG. 14A) is smaller than that in FIG. 14B (Y12 shown in FIG. 14B).

[0166] In some embodiments, the peripheral circuit is configured to: take the predicted valley bottom voltage as the target valley bottom voltage according to that a first result corresponding to the predicted valley bottom voltage is less than a preset threshold. Illustratively, as shown in FIG. 9, the peripheral circuit is configured to: take the predicted valley bottom voltage (V0 shown in FIG. 9) as the target valley bottom voltage according to that a first result (Y1 shown in FIG. 9) corresponding to the predicted valley bottom voltage (V0 shown in FIG. 9) is less than a preset threshold.

[0167] In some embodiments, the memory cell array comprises memory cells with a number of storage bits; the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of orders; the plurality of orders comprises a first order and a second order, and the read voltage of the second order is less than the read voltage of the first order; the peripheral circuit is configured to: obtain the predicted valley bottom voltage of the second order and / or the predicted valley bottom voltage of the remaining first order with lower read voltage from the predicted valley bottom voltage of the first order of each page in the plurality of pages; and perform a read operation on at least one codeword according to the predicted valley bottom voltage of the first order of each page and the predicted valley bottom voltage of the second order.

[0168] In some embodiments, at least one page corresponds to a plurality of order read voltages, and the plurality of order read voltages comprises a read voltage of a first order and a read voltage of a second order, wherein the read voltage of the second order is less than the read voltage of the first order. Illustratively, the read voltage of the first order can be understood as the highest read voltage in the plurality of order read voltages of each page, and the read voltage of the second order can be understood as the other read voltages less than the highest read voltage in the plurality of order read voltages of each page.

[0169] It should be noted that the first order and the second order are used to distinguish the high-level read voltage and the low-level read voltage in the plurality of order read voltages corresponding to at least part of the pages, and the low-level read voltage is less than the high-level read voltage. For a memory cell comprising a plurality of storage bits, a page corresponding to one storage bit can comprise one order or a plurality of orders, and one order can comprise one level or a plurality of levels.

[0170] Illustratively, referring to FIG. 8A, the memory device comprises a lower page and an upper page, wherein the lower page corresponds to a plurality of orders, and the plurality of orders corresponding to the lower page comprises a first level and a third level, and the first level read voltage L1 is less than the third level read voltage L3. Here, the third level read voltage L3 corresponds to the read voltage of the first order of the lower page (the high-level read voltage of the lower page), and the first level read voltage L1 corresponds to the read voltage of the second order of the lower page (the low-level read voltage of the lower page).

[0171] For example, referring to FIG. 8B, the memory device includes a lower page, a middle page, and an upper page, each of which corresponds to multiple orders, the multiple orders corresponding to the lower page include a first order and a fifth order, the first order read voltage L1 is less than the fifth order read voltage L5, the multiple orders corresponding to the middle page include a second order, a fourth order, and a sixth order, the second order read voltage L2 and the fourth order read voltage L4 are both less than the sixth order read voltage L6, the multiple orders corresponding to the upper page include a third order and a seventh order, the third order read voltage L3 is less than the seventh order read voltage L7. Here, the fifth order read voltage L5, the sixth order read voltage L6, and the seventh order read voltage L7 correspond to the read voltages of the first order of the lower page, the middle page, and the upper page respectively, the first order read voltage L1, the second order read voltage L2, and the fourth order read voltage L4, and the third order read voltage L3 correspond to the read voltages of the second order of the lower page, the middle page, and the upper page respectively.

[0172] For example, referring to FIG. 8C, the memory device includes a lower page, a middle page, an upper page, and an additional page, each of which corresponds to multiple orders, the multiple orders corresponding to the lower page include a second order, an eighth order, and a fourteenth order, the second order read voltage L2 and the eighth order read voltage L8 are both less than the fourteenth order read voltage L14, the multiple orders corresponding to the middle page include a third order, a seventh order, a ninth order, and a thirteenth order, the third order read voltage L3, the seventh order read voltage L7, and the ninth order read voltage L9 are all less than the thirteenth order read voltage L13, the multiple orders corresponding to the upper page include a fifth order, a tenth order, a twelfth order, and a fifteenth order, the fifth order read voltage L5, the tenth order read voltage L10, and the twelfth order read voltage L12 are less than the fifteenth order read voltage L15, the multiple orders corresponding to the additional page include a first order, a fourth order, a sixth order, and an eleventh order, the first order read voltage L1, the fourth order read voltage L4, and the sixth order read voltage L6 are less than the eleventh order read voltage L11. Here, the fourteenth order read voltage L14, the thirteenth order read voltage L13, the fifteenth order read voltage L15, and the eleventh order read voltage L11 correspond to the read voltages of the first order of the lower page, the middle page, the upper page, and the additional page respectively, the second order read voltage L2 and the eighth order read voltage L8 correspond to the read voltages of the second order of the lower page, the third order read voltage L3, the seventh order read voltage L7, and the ninth order read voltage L9 correspond to the read voltages of the second order of the middle page, the fifth order read voltage L5, the tenth order read voltage L10, and the twelfth order read voltage L12 correspond to the read voltages of the second order of the upper page, and the first order read voltage L1, the fourth order read voltage L4, and the sixth order read voltage L6 correspond to the read voltages of the second order of the additional page.

[0173] The following provides an optional example of obtaining the predicted valley voltage of the second order and / or the predicted valley voltage of the remaining first order with lower read voltage according to the predicted valley voltage of the first order of each page in multiple pages.

[0174] In the embodiments of the present application, the high-order (first-order) predicted valley voltage can be used to obtain the low-order (second-order) predicted valley voltage and the remaining high-order (first-order) predicted valley voltage. Specifically, the predicted valley voltage of the to-be-predicted order (second-order and the remaining first-order with lower read voltage) can be obtained according to the high-order (first-order) predicted valley voltage, the order of the to-be-predicted order and the mapping function. Here, the mapping function is related to the performance of the memory device (especially the offset performance of the threshold voltage of the memory cell), and the mapping function can be fitted by a large number of experimental results before the memory device is shipped and saved in the memory device.

[0175] It should be noted that the above mapping function does not support loop iteration.

[0176] In some embodiments, the peripheral circuit is configured to perform a read operation on the at least one codeword according to the first-order predicted valley voltage and the second-order predicted valley voltage of each page.

[0177] In some embodiments, the peripheral circuit is configured to determine the predicted valley voltage of each order as the target valley voltage according to the read result of the read operation; after determining the predicted valley voltage of each order, the peripheral circuit does not perform the confirmation of the predicted valley voltage, but directly performs the read operation on the at least one codeword according to the first-order predicted valley voltage and the second-order predicted valley voltage of each page, and performs error correction decoding on the read result of the read operation through the controller. If the error correction decoding is successful, it indicates that the obtained predicted valley voltage can be used as the target valley voltage.

[0178] In some embodiments, the peripheral circuit is configured to reacquire the first result corresponding to the at least one codeword under a target read voltage of the first order according to the read result of the read operation; reacquire the predicted parameter according to the plurality of first results and the plurality of target read voltages in combination with the preset function model; perform the read operation on the at least one codeword based on the reacquired predicted parameter until the read result of the read operation is successfully error correction decoded.

[0179] Exemplarily, as shown in FIG. 11, when the first parameter and the second parameter are constants, i is equal to 1, and M is equal to 1, a set of predicted parameters can be obtained according to one point (x1, y1) and according to the quadratic function model corresponding to the first order of each page in the plurality of pages, and the predicted parameters are used as the predicted valley voltage corresponding to the first order of each page in the plurality of pages. According to the mapping function, the predicted valley voltage of the second order in the plurality of orders of each page and / or the predicted valley voltage of the remaining first order with lower read voltage are obtained, and the read operation is performed on the at least one codeword according to the predicted valley voltage of the first order and the predicted valley voltage of the second order of each page.

[0180] If the error correction decoding of the read result of the read operation fails, a first result corresponding to the at least one code word at a target read voltage of the first order is re-acquired, and the point can be marked as (x2, y2) (as shown in FIG. 12); b is re-acquired according to the two points (x1, y1) and (x2, y2) in combination with the quadratic function model and the calculation formula (2) of b, and the prediction parameter is re-acquired based on the re-acquired b; the prediction valley voltage of the first order of each page in the multiple pages is obtained based on the re-acquired prediction parameter, and the prediction valley voltage of the second order and / or the prediction valley voltage of the remaining first order with a lower read voltage in each page is re-acquired according to the mapping function. The read operation is performed on the at least one code word according to the prediction valley voltage of the first order and the prediction valley voltage of the second order of each page.

[0181] If the error correction decoding of the read result of the read operation fails, a first result corresponding to the at least one code word at a target read voltage of the first order is re-acquired, and the point can be marked as (x2, y2) (as shown in FIG. 12); b is re-acquired according to the two points (x1, y1) and (x2, y2) in combination with the quadratic function model and the calculation formula (2) of b, and the prediction parameter is re-acquired based on the re-acquired b; the prediction valley voltage of the first order of each page in the multiple pages is obtained based on the re-acquired prediction parameter, and the prediction valley voltage of the second order and / or the prediction valley voltage of the remaining first order with a lower read voltage in each page is re-acquired according to the mapping function. The read operation is performed on the at least one code word according to the prediction valley voltage of the first order and the prediction valley voltage of the second order of each page.

[0182] It should be noted that, according to the error correction decoding of the read result of the read operation, the first result corresponding to the at least one code word at a target read voltage of the first order is re-acquired, that is, the first result at a target read voltage is re-acquired based on the M target read voltages and the M first results, and then the prediction parameter is re-acquired based on the (M+1) first results and the (M+1) target read voltages in combination with the preset function model. M can be any integer greater than or equal to 1.

[0183] In this way, the read operation is directly performed on the at least one code word according to the acquired prediction valley voltage, and whether the prediction valley voltage is determined as the target valley voltage is determined according to whether the error correction decoding of the read result of the read operation is successful or not, which can shorten the time period to some extent and determine the target valley voltage more quickly.

[0184] In some embodiments, the memory cell array includes memory cells with a number of memory bits; the plurality of memory bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of levels; and the peripheral circuit is configured to determine the target valley voltage of the at least one code word at the target level, and determine the target valley voltage of other levels except the target level in the plurality of levels respectively.

[0185] For example, the target valley voltage of the third level read voltage L3 is obtained in a similar manner to obtaining the target valley voltage of the seventh level read voltage L7, and the target valley voltage of the seventh level read voltage L7 and the third level read voltage L3 can be used to read the data of the upper page of the at least one code word. The target valley voltage of the first level read voltage L1 and the fifth level read voltage L5 is obtained in a similar manner to obtaining the target valley voltage of the seventh level read voltage L7, and is used to read the data of the lower page of the at least one code word. The target valley voltage of the second level read voltage L2, the target valley voltage of the fourth level read voltage L4 and the target valley voltage of the sixth level read voltage L6 are obtained in a similar manner to obtaining the target valley voltage of the seventh level read voltage L7, and are used to read the data of the middle page of the at least one code word.

[0186] As shown in FIG. 15, the offset value corresponding to the default read voltage is 0, the difference between the target read voltage and the default read voltage is taken as the abscissa, and the first result corresponding to the target read voltage is taken as the ordinate, and the abscissa and the ordinate form a point. The point of the target valley voltage is the point corresponding to the target valley voltage as the abscissa. Curve one (solid line shown in FIG. 15) is the actual threshold voltage distribution curve corresponding to the fifth level read voltage L5 shown in FIG. 8B, and curve two (dashed line shown in FIG. 15) is the curve where the preset function model corresponding to the fifth level read voltage L5 shown in FIG. 8B is located. As shown in FIG. 15, the actual target valley voltage on curve one (the abscissa position corresponding to the hollow point in FIG. 15) is almost coincident with the target valley voltage on curve two (the abscissa position corresponding to the black solid point in FIG. 15), indicating that the manner of determining the target valley voltage by the preset function model of the present application is not only faster but also has higher accuracy.

[0187] For example, as shown in FIG. 16, curve one (solid line shown in FIG. 16) is the actual threshold voltage distribution curve corresponding to the sixth level read voltage L6 shown in FIG. 8B, and curve two (dashed line shown in FIG. 16) is the curve where the preset function model corresponding to the sixth level read voltage L6 shown in FIG. 8B is located. As shown in FIG. 16, the actual target valley voltage on curve one (the abscissa position corresponding to the hollow point in FIG. 16) is almost coincident with the target valley voltage on curve two (the abscissa position corresponding to the black solid point in FIG. 16).

[0188] Exemplarily, as shown in FIG. 17, curve one (solid line shown in FIG. 17) is an actual threshold voltage distribution curve corresponding to the seventh level read voltage L7 shown in FIG. 8B, and curve two (dashed line shown in FIG. 17) is a preset function model corresponding to the seventh level read voltage L7 shown in FIG. 8B. As shown in FIG. 17, the actual target valley bottom voltage on curve one (the horizontal coordinate position corresponding to the hollow point in FIG. 17) is almost the same as the target valley bottom voltage on curve two (the horizontal coordinate position corresponding to the black solid point in FIG. 17).

[0189] In the first aspect, the embodiments of the present application provide various memory devices. The first result (the size of the first result can be several bytes) is transmitted without transmitting at least one code word (for example, the size of the code word can be 4 KB), and the amount of data transmitted is reduced. The process of obtaining the first result converges in the memory device, and does not occupy the space of, for example, a memory controller, and the dependence on, for example, a memory controller is low. The process of obtaining the target valley bottom voltage according to a limited number of target read voltages and the first result in combination with a preset function model is completed in the memory device, the speed of determining the target valley bottom voltage is accelerated, the influence of data noise is reduced to a certain extent, the reliability is improved, and the transmission time of the output port is reduced. The memory device is suitable for MLC, TLC or QLC type memory devices.

[0190] In the second aspect, the embodiments of the present application provide a memory system. As shown in FIG. 18 and FIG. 19, the memory system 102 includes one or more memory devices 104 provided in the first aspect, and a memory controller 106 coupled with the memory device 104 and controlling the memory device 104.

[0191] As shown in FIG. 18, in some specific embodiments, the memory system 102 is coupled with a host, and performs various feedbacks in response to the instructions of the host. The memory system 102 can include a memory controller 106 and a memory device 104. The memory controller 106 is used to control the memory device 104 to perform read, write, erase and other operations. The memory controller 106 and the memory device 104 can also be coupled in any suitable manner.

[0192] The memory controller 106 can include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, a data buffer 1067, and a bus 1060. The host interface 1061 is a connection interface between the host 108 and the memory controller 106, and allows the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104, and is used to implement data transmission between the memory controller 106 and the memory device 104. The control unit 1063 is used to control the memory system 106 as a whole, and the specific steps performed by the memory controller described above are mainly performed and completed by the control unit 1063 here. In some embodiments, the control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MCU), or the like. The ROM 1069 generally contains firmware or firmware program code of the memory controller 106, which is used to initialize and operate the components of the memory controller, and the RAM 1070 is generally used to cache data. The error correction module 1064 can further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain check data, and the decoding unit is used to decode the check data to detect and correct possible error data during data transmission.

[0193] The garbage collection module 1065 is used to read out valid data on some storage blocks, rewrite them, and then mark the storage blocks to obtain new spare storage blocks after the storage space of the memory device reaches a certain threshold. The general implementation of garbage collection can be divided into three steps: selecting a source storage block with less valid data; finding valid data from the source storage block; and writing the valid data to a target storage block. At this time, all data in the source storage block becomes invalid data, and the source storage block is marked and can be used as a new spare storage block. The wear leveling module 1066 is used to keep the wear (number of erasures) of each storage block in the memory system balanced through data statistics and algorithms. The general implementation of wear leveling can be divided into two steps: selecting a source storage block where cold data is located; and reading valid data on the source storage block and writing it to a storage block with a relatively large number of erasures, at which time the valid data in the source storage block becomes invalid data and is marked. The buffer 1067 is used to cache data.

[0194] In some embodiments, the memory controller 106 is configured to control the memory device 104 to perform a read operation on the at least one codeword.

[0195] In some embodiments, the memory device 104 comprises: a memory cell array comprising a plurality of memory cells, a preset number of the memory cells forming one codeword; a peripheral circuit of the memory device 104 coupled with the memory cell array and configured to: obtain M first results corresponding to the at least one codeword under M target read voltages; the first result comprising a number of bits representing a flipping in a read result of the at least one codeword under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage being less than a preset voltage; obtain a predicted valley voltage based on the M first results and the M target read voltages in combination with a preset function model; the preset function model representing a relationship between the first result and the target read voltage; and determine a target valley voltage based on the predicted valley voltage; the target valley voltage being used as a read voltage when performing a read operation on the at least one codeword; wherein M is an integer greater than or equal to 1.

[0196] In some embodiments, the preset function model comprises a quadratic function model, the quadratic function model comprising a function relationship: y = a(x + b) 2 + c

[0197] wherein y is the first result, x is the target read voltage, b is used to represent a prediction parameter, a is a first parameter, and c is a second parameter.

[0198] In some embodiments, the peripheral circuit of the memory device 104 is configured to obtain N sets of prediction parameters based on the M first results, the M target read voltages, and the quadratic function model; wherein, i is an integer, and 1≤i≤M; and obtain the predicted valley voltage based on the N sets of prediction parameters.

[0199] In some embodiments, i is equal to 1, and the first parameter and the second parameter are both constants; the peripheral circuit of the memory device 104 is configured to obtain N sets of prediction parameters based on the M first results, the M target read voltages, the quadratic function model, the first parameter, and the second parameter.

[0200] In some embodiments, i is equal to 2, the first parameter is a variable, and the second parameter is a constant; the peripheral circuit of the memory device 104 is configured to obtain N sets of prediction parameters and the first parameter based on the M first results, the M target read voltages, the quadratic function model, and the second parameter.

[0201] In some embodiments, i is equal to 3, the first parameter and the second parameter are variables; the peripheral circuit of the memory device 104 is configured to obtain N groups of predicted parameters, the first parameter and the second parameter according to the M first results, the M target read voltages and the quadratic function model.

[0202] In some embodiments, i is equal to M; the peripheral circuit of the memory device 104 is configured to obtain one group of predicted parameters according to the M first results, the M target read voltages and the quadratic function model; and the predicted parameters are taken as the predicted valley voltage.

[0203] In some embodiments, i is less than M; the peripheral circuit of the memory device 104 is configured to determine outliers of the N groups of predicted parameters; and the median or the average of the remaining predicted parameters after removing the outliers of the N groups of predicted parameters is taken as the predicted valley voltage.

[0204] In some embodiments, the memory cell array comprises memory cells with a plurality of bits; the plurality of bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of orders; the plurality of orders comprises a first order and a second order, and the read voltage of the second order is less than that of the first order; the peripheral circuit of the memory device 104 is configured to obtain the predicted valley voltage of the second order and / or the predicted valley voltage of the remaining first order with lower read voltage according to the predicted valley voltage of the first order of each page in the plurality of pages; and perform a read operation on at least one codeword according to the predicted valley voltage of the first order of each page and the predicted valley voltage of the second order.

[0205] In some embodiments, the peripheral circuit of the memory device 104 is configured to determine that the predicted valley voltage of each order is a target valley voltage according to that the read result of the read operation is successfully error correction decoding; and re-obtain a first result corresponding to at least one codeword under a target read voltage of a first order according to that the read result of the read operation is unsuccessfully error correction decoding; re-obtain predicted parameters according to the obtained plurality of first results and the plurality of target read voltages in combination with a preset function model; and perform a read operation on at least one codeword based on the re-obtained predicted parameters until the read result of the read operation is successfully error correction decoding.

[0206] In some embodiments, the peripheral circuit of the memory device 104 is configured to obtain a preset threshold according to a first result corresponding to a first target read voltage in the M target read voltages; the preset threshold is used to represent a first result corresponding to a maximum value in an effective range of the predicted valley voltage; and the predicted valley voltage is taken as a target valley voltage according to that the first result corresponding to the predicted valley voltage is less than the preset threshold.

[0207] In some embodiments, the array of memory cells includes memory cells with a number of storage bits; the number of storage bits corresponds to a number of pages; at least one page corresponds to a number of levels; the peripheral circuit of the memory device 104 is configured to determine target valley bottom voltages of the other levels except the target level after determining the target valley bottom voltage of the target level of the at least one codeword.

[0208] In some embodiments, the peripheral circuit of the memory device 104 is configured to read the stored data of the at least one codeword at a first read voltage to obtain a second result; read the stored data of the at least one codeword at a second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result representing the flipping of the third result relative to the second result to obtain the first result.

[0209] In some embodiments, the peripheral circuit of the memory device 104 includes a first latch, a second latch, and a third latch; the first latch is configured to store the second result; the second latch is configured to store the third result; and the third latch is configured to store the fourth result.

[0210] As shown in FIG. 19, in some embodiments, the memory controller 106 is configured to send a data acquisition instruction, the data acquisition instruction indicating to acquire a target valley bottom voltage; the memory device 104 is configured to receive the data acquisition instruction, acquire the target valley bottom voltage, and send information including the target valley bottom voltage to the memory controller; and the memory controller 106 is further configured to perform a read operation on the data stored in the memory device according to the target valley bottom voltage in the information.

[0211] In some embodiments, the memory controller 106 is further configured to perform an error correction code decoding operation on the read result of the read operation. In some implementations, the error correction code decoding operation includes a hard decoding operation using a low density parity check code (LDPC).

[0212] In some embodiments, the memory controller 106 is configured to send a mode setting command, the mode setting command indicating to set a read mode of the memory device to a single-level read mode; the single-level read mode includes reading at least one bit of stored data of a memory cell by a one-level read voltage; the memory device 104 is configured to enter the single-level read mode in response to the mode setting command, and in the single-level read mode, acquire a first result corresponding to the at least one codeword at a target read voltage.

[0213] In a second aspect, the memory system provided by the embodiments of the present application can reduce the amount of data transmitted between the memory device and the memory controller by transmitting the first result (the size of the first result can be several bytes) without transmitting at least one codeword (for example, the size of the codeword can be 4 KB); the process of obtaining the first result converges in the memory device, and does not occupy the space of the memory controller, and the dependence on the memory controller is low; the process of obtaining the target bottom voltage by combining the first result and the preset function model in the memory device reduces the transmission time of the input and output ports of the memory device and / or the time of the error correction decoding operation of the memory controller, saves the iteration time of the error correction decoding algorithm of the memory controller, and makes the error correction decoding faster; and the memory system is suitable for MLC, TLC or QLC type memory systems.

[0214] In a third aspect, the embodiments of the present application provide a memory controller coupled with at least one memory device, the memory device including a plurality of storage units, and a preset number of storage units forming a codeword; the memory controller includes a control unit configured to: obtain M first results corresponding to at least one codeword under M target read voltages; the first result includes the number of bits that flip in the twice reading results of the at least one codeword under a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; obtain a predicted bottom voltage by combining the M first results and the M target read voltages with a preset function model; the preset function model represents the relationship between the first result and the target read voltage; and determine a target bottom voltage based on the predicted bottom voltage; the target bottom voltage is used as a read voltage for the at least one codeword when performing a read operation; and M is an integer greater than or equal to 1.

[0215] In some embodiments, the preset function model includes a quadratic function model, and the quadratic function model includes the following function relationship: y = a(x + b) 2 +c

[0216] wherein y is the first result, x is the target read voltage, b represents a prediction parameter, a is a first parameter, and c is a second parameter.

[0217] In some embodiments, the control unit is configured to: obtain N groups of prediction parameters according to the M first results, the M target read voltages, and the preset function model; wherein, i is an integer, and 1≤i≤M; and the predicted bottom voltage is obtained according to the N groups of prediction parameters.

[0218] In some embodiments, i is equal to 1, the first parameter and the second parameter are constants; the control unit is configured to obtain N groups of predicted parameters according to the M first results, the M target read voltages, the preset function model, the first parameter, and the second parameter.

[0219] In some embodiments, i is equal to 2, the first parameter is a variable, and the second parameter is a constant; the control unit is configured to obtain N groups of predicted parameters and the first parameter according to the M first results, the M target read voltages, the preset function model, and the second parameter.

[0220] In some embodiments, i is equal to 3, the first parameter and the second parameter are variables; the control unit is configured to obtain N groups of predicted parameters, the first parameter, and the second parameter according to the M first results, the M target read voltages, and the preset function model.

[0221] In some embodiments, i is equal to M; the control unit is configured to obtain one group of predicted parameters according to the M first results, the M target read voltages, and the preset function model; and the predicted parameters are used as the predicted valley bottom voltage.

[0222] In some embodiments, i is less than M; the control unit is configured to determine outliers of the N groups of predicted parameters; and the median or the average of the remaining predicted parameters after removing the outliers of the N groups of predicted parameters is used as the predicted valley bottom voltage.

[0223] In some embodiments, the memory cell array includes memory cells with a plurality of memory bits; the plurality of memory bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of orders; the plurality of orders include a first order and a second order, and the read voltage of the second order is less than the read voltage of the first order; the control unit is configured to obtain the predicted valley bottom voltage of the second order according to the predicted valley bottom voltage of the first order of each page of the plurality of pages; and perform a read operation on at least one code word according to the predicted valley bottom voltage of the first order of each page and the predicted valley bottom voltage of the second order.

[0224] In some embodiments, the control unit is configured to determine that the predicted valley bottom voltage of each order is a target valley bottom voltage when the read result of the read operation is successfully error correction decoded; re-obtain a first result corresponding to at least one code word at a target read voltage of the first order according to the read result of the read operation when the read result of the read operation fails error correction decoding; re-obtain predicted parameters according to the obtained plurality of first results and the plurality of target read voltages in combination with the preset function model; and perform a read operation on at least one code word based on the re-obtained predicted parameters until the read result of the read operation is successfully error correction decoded.

[0225] In some embodiments, the control unit is configured to: obtain a preset threshold according to a first result corresponding to a first target read voltage among the M target read voltages; the preset threshold is used to represent a first result corresponding to a maximum value in the effective range of the predicted valley voltage; and determine the predicted valley voltage as the target valley voltage according to that the first result corresponding to the predicted valley voltage is less than the preset threshold.

[0226] In some embodiments, the memory device includes memory cells with a plurality of storage bits; the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of orders; and the control unit is configured to: after determining the valley voltage of the at least one codeword at the target order, determine the target valley voltage of the other orders in the plurality of orders except the target order respectively.

[0227] In some embodiments, the data amount of the first result is less than a preset data amount threshold. For example, the data amount of the first result ranges from 1 byte to 4 bytes, so that the data amount transmitted between the memory device and the memory controller is small and fast during the process of determining the target valley voltage, which is conducive to improving the overall speed of the read operation.

[0228] Here, the control unit can be understood in combination with the control unit shown in FIG. 18. It should be noted that in this embodiment of the present application, the execution subject is replaced from the peripheral circuit to the control unit in the memory controller. That is, in this embodiment of the present application, the M target read voltages and the M first results are obtained by the memory device; and the control unit analyzes and processes the M target read voltages and the M first results, and determines the target valley voltage according to the analysis and processing.

[0229] In the third aspect, the memory controller provided by the embodiments of the present application, the first result (the size of the first result can be several bytes) is transmitted between the memory device and the memory controller without transmitting the at least one codeword (for example, the size of the codeword can be 4 KB), so that the data amount transmitted between the memory device and the memory controller is reduced; the process of obtaining the first result converges in the memory device, without occupying the space of the memory controller, and the dependence on the memory controller is low; compared with in the memory device, the efficiency of completing the process of obtaining the target valley voltage according to the limited number of target read voltages and first results in combination with the preset function model in the memory controller is higher, the transmission time of the input and output port of the memory device and / or the time of the error correction decoding operation of the memory controller is reduced, the iteration time of the error correction decoding algorithm of the memory controller is saved, and the speed of the error correction decoding is faster; and the memory controller is suitable for MLC, TLC or QLC type memory systems.

[0230] In a fourth aspect, an embodiment of the present application provides an operation method of a memory device, the memory device including a plurality of memory cells, a preset number of memory cells forming a code word; the operation method of the memory device including: obtaining M first results corresponding to at least one code word under M target read voltages; the first result including a number of bits representing a flip in two reading results of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage being less than a preset voltage; obtaining a predicted valley bottom voltage according to the M first results and the M target read voltages, in combination with a preset function model; the preset function model representing a relationship between the first result and the target read voltage; and determining a target valley bottom voltage based on the predicted valley bottom voltage; the target valley bottom voltage being used as a read voltage for the at least one code word when performing a reading operation; wherein M is an integer greater than or equal to 1.

[0231] In some embodiments, the preset function model includes a quadratic function model, the quadratic function model including the following function relationship: y = a(x + b) 2 +c

[0232] wherein y is the first result, x is the target read voltage, b is used to represent a prediction parameter, a is a first parameter, and c is a second parameter.

[0233] In some embodiments, the operation method of the memory device includes: obtaining N groups of prediction parameters according to the M first results, the M target read voltages, and the preset function model; wherein, i is an integer, and 1≤i≤M; and the predicted valley bottom voltage is obtained according to the N groups of prediction parameters.

[0234] In some embodiments, i is equal to 1, and the first parameter and the second parameter are both constants; the operation method of the memory device includes: obtaining N groups of prediction parameters according to the M first results, the M target read voltages, the preset function model, the first parameter, and the second parameter.

[0235] In some embodiments, i is equal to 2, the first parameter is a variable, and the second parameter is a constant; the operation method of the memory device includes: obtaining N groups of prediction parameters and the first parameter according to the M first results, the M target read voltages, the preset function model, and the second parameter.

[0236] In some embodiments, i is equal to 3, and the first parameter and the second parameter are both variables; the operation method of the memory device includes: obtaining N groups of prediction parameters, the first parameter, and the second parameter according to the M first results, the M target read voltages, and the preset function model.

[0237] In some embodiments, i is equal to M; the operation method of the memory device comprises: obtaining a set of predicted parameters according to the M first results, the M target read voltages, and a preset function model; and taking the predicted parameters as the predicted valley voltage.

[0238] In some embodiments, i is less than M; the operation method of the memory device comprises: determining outliers of the N sets of predicted parameters; and taking the median or average of the remaining predicted parameters after removing the outliers of the N sets of predicted parameters as the predicted valley voltage.

[0239] In some embodiments, the memory cell array comprises memory cells with a number of storage bits; the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of orders; the plurality of orders comprises a first order and a second order, and the read voltage of the second order is less than that of the first order; the operation method of the memory device comprises: obtaining the predicted valley voltage of the second order according to the predicted valley voltage of the first order of each page; and performing a read operation on at least one code word according to the predicted valley voltage of the first order and the predicted valley voltage of the second order of each page.

[0240] In some embodiments, the operation method of the memory device comprises: determining that the predicted valley voltage of each order is a target valley voltage according to that the error correction decoding of the read result of the read operation is successful; re-obtaining the first result corresponding to at least one code word under a target read voltage of the first order according to that the error correction decoding of the read result of the read operation is unsuccessful; re-obtaining the predicted parameters according to the obtained plurality of first results and the plurality of target read voltages, and combining a preset function model; and performing a read operation on at least one code word based on the re-obtained predicted parameters until the error correction decoding of the read result of the read operation is successful.

[0241] In some embodiments, the operation method of the memory device comprises: obtaining a preset threshold according to the first result corresponding to the first target read voltage in the M target read voltages; the preset threshold is used to represent the first result corresponding to the maximum value in the effective range of the predicted valley voltage; and taking the predicted valley voltage as the target valley voltage according to that the first result corresponding to the predicted valley voltage is less than the preset threshold.

[0242] In some embodiments, the memory device comprises memory cells with a number of storage bits; the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of orders; and the operation method of the memory device comprises: determining the target valley voltage of other orders in the plurality of orders except for a target order after determining the valley voltage of the target order of at least one code word.

[0243] It should be noted that the execution subject in the operation method of the memory device can be a peripheral circuit or a memory controller.

[0244] In a fifth aspect, an embodiment of the present application provides an operation method of a memory system, comprising: a memory controller in the memory system sending a data acquisition instruction, the data acquisition instruction indicating to acquire a target valley voltage; a memory device in the memory system receiving the data acquisition instruction, acquiring the target valley voltage according to the operation method of the memory device of the fourth aspect, and sending information including the target valley voltage to the memory controller; and the memory controller performing a read operation on data stored in the memory device according to the target valley voltage in the information.

[0245] In some embodiments, the memory device in the memory system includes a plurality of storage units, and a preset number of the storage units form a code word; the operation method of the memory system includes: acquiring M first results corresponding to at least one code word under M target read voltages; the first result includes a number of bits that flip in two read results of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage is less than a preset voltage; obtaining a predicted valley voltage according to the M first results and the M target read voltages in combination with a preset function model; the preset function model represents a relationship between the first result and the target read voltage; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage is used as a read voltage when performing a read operation on the at least one code word; and the M is an integer greater than or equal to 1.

[0246] In a sixth aspect, an embodiment of the present application provides an operation method of a memory controller, the memory controller being coupled with at least one memory device, the memory device including a plurality of storage units, and a preset number of the storage units forming a code word; the operation method of the memory controller of the memory device includes: acquiring M first results corresponding to at least one code word under M target read voltages; the first result includes a number of bits that flip in two read results of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage is less than a preset voltage; obtaining a predicted valley voltage according to the M first results and the M target read voltages in combination with a preset function model; the preset function model represents a relationship between the first result and the target read voltage; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage is used as a read voltage when performing a read operation on the at least one code word; and the M is an integer greater than or equal to 1.

[0247] In some embodiments, the preset function model includes a quadratic function model, and the quadratic function model includes the following function relationship: y = a(x + b) 2 +c

[0248] wherein y is the first result, x is the target read voltage, b is used to represent the prediction parameter, a is the first parameter, and c is the second parameter.

[0249] In some embodiments, the operation method of the memory controller comprises: obtaining N groups of the prediction parameters according to the M first results, the M target read voltages, and the preset function model; wherein, the i is an integer, and 1≤i≤M; and obtaining the prediction valley voltage according to the N groups of the prediction parameters.

[0250] In some embodiments, i is equal to 1, and the first parameter and the second parameter are constants; the operation method of the memory controller comprises: obtaining N groups of the prediction parameters according to the M first results, the M target read voltages, the preset function model, the first parameter, and the second parameter.

[0251] In some embodiments, i is equal to 2, the first parameter is a variable, and the second parameter is a constant; the operation method of the memory controller comprises: obtaining N groups of the prediction parameters and the first parameter according to the M first results, the M target read voltages, the preset function model, and the second parameter.

[0252] In some embodiments, i is equal to 3, and the first parameter and the second parameter are variables; the operation method of the memory controller comprises: obtaining N groups of the prediction parameters, the first parameter, and the second parameter according to the M first results, the M target read voltages, and the preset function model.

[0253] In some embodiments, i is equal to M; the operation method of the memory controller comprises: obtaining one group of the prediction parameters according to the M first results, the M target read voltages, and the preset function model; and taking the prediction parameter as the prediction valley voltage.

[0254] In some embodiments, i is less than M; the operation method of the memory controller comprises: determining outliers of the N groups of the prediction parameters; and taking the median or the average of the remaining prediction parameters after removing the outliers of the N groups of the prediction parameters as the prediction valley voltage.

[0255] In some embodiments, the memory cell array comprises memory cells with a plurality of bits; the plurality of bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of orders; the plurality of orders comprise a first order and a second order, and the read voltage of the second order is less than the read voltage of the first order; the operation method of the memory controller comprises: obtaining the prediction valley voltage of the second order according to the prediction valley voltage of the first order of each page in the plurality of pages; and performing a read operation on at least one codeword according to the prediction valley voltage of the first order of each page and the prediction valley voltage of the second order.

[0256] In some embodiments, the operation method of the memory controller includes: determining the predicted valley voltage of each order as the target valley voltage according to the read result of the read operation and the success of error correction decoding; reacquiring a first result corresponding to at least one code word under a target read voltage of a first order according to the read result of the read operation and the failure of error correction decoding; reacquiring the prediction parameter according to the acquired multiple first results and multiple target read voltages in combination with a preset function model; and performing the read operation on at least one code word based on the reacquired prediction parameter until the read result of the read operation is successfully error correction decoded.

[0257] In some embodiments, the operation method of the memory controller includes: acquiring a preset threshold according to a first result corresponding to a first target read voltage in the M target read voltages; the preset threshold is used to represent a first result corresponding to a maximum value in the effective range of the predicted valley voltage; and taking the predicted valley voltage as the target valley voltage according to the first result corresponding to the predicted valley voltage being less than the preset threshold.

[0258] In some embodiments, the memory device includes a storage unit with a storage bit number of multiple bits; the multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple orders; and the operation method of the memory controller includes: determining the target valley voltage of each order except the target order in the multiple orders after determining the valley voltage of at least one code word in the target order.

[0259] FIG. 20 is a timing diagram of an exemplary operation of starting a single-level read mode provided by the present application. DQx can represent a data bus signal, and Cycle Type can further represent the type of the data bus signal.

[0260] As shown in FIG. 20, the set function command can include, for example, one subcommand (e.g., EFh), and the memory device starts the single-level read mode in response to the received subcommand EFh, for example. In the single-level read mode, the memory device transmits the address ADDR (e.g., two column addresses C1-C2 and three row addresses R1-R3) of the data to be read between the received subcommands 00h and 30h. In the read time, the corresponding data DATA (e.g., Dn) in the page of the received address can be buffered in the page buffer first, and then the data DATA is read on demand. It should be noted that the above embodiment needs to frequently transmit (Din / Dout) the data (e.g., Dn) corresponding to one physical page between the memory device and the memory controller when performing the re-reading operation, and the transmission of the data consumes a relatively long time.

[0261] FIG. 21 is a timing diagram of determining a target valley voltage and performing a read operation according to an embodiment of the present application. As shown in FIG. 21, a read command can include, for example, two sub-commands (e.g., 00h and 30h). Exemplarily, the memory device transmits an address ADDR (e.g., two column addresses C1-C2 and three row addresses R1-R3) of data to be read between the received sub-commands 00h and 30h. After the memory device receives the sub-command 30h, the corresponding data DATA (e.g., Dn) in the page of the received address can be buffered in a page buffer first, and then the data DATA is read on demand within a read time.

[0262] In an exemplary embodiment, the memory device 104 transmits an address ADDR (e.g., two column addresses C1-C2 and three row addresses R1-R3) of data to be read between the received sub-commands 00h and 30h. After the memory device 104 receives the sub-command 30h, the memory device 104 receives a sub-command EFh and xxh of a data acquisition instruction, acquires M first results corresponding to M target read voltages of the codeword under the indication of the data acquisition instruction, and sends the M target read voltages and the M first results to the memory controller. The memory controller determines a target valley voltage according to the M target read voltages and the M first results received from the memory device in combination with a preset function model, and performs a read operation on the data stored in the memory device according to the target valley voltage.

[0263] It should be noted that the data acquisition instruction provided in the embodiments of the present application is only an example, and should not be overly limited to the protection scope of the present application.

[0264] In some embodiments, the data amount of the first result is less than a preset data amount threshold, for example, the data amount of the first result ranges from 1 byte to 4 bytes, so that the data amount transmitted between the memory device and the memory controller is small and fast during the process of determining the target valley voltage, which is beneficial to improve the overall speed of the read operation.

[0265] The embodiments of the present application also provide a storage medium having stored executable instructions, which can implement the steps of the operation method in the above embodiments of the present application when executed.

[0266] In some embodiments, the storage medium can be a ferromagnetic random access memory (FRAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disc, or a compact disc read-only memory (CD-ROM), and the like. It can also be various apparatuses including one or any combination of the above memory devices.

[0267] In some embodiments, the executable instructions can be in the form of programs, software, modules, scripts, or code, written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0268] As an example, the executable instructions can, but need not, correspond to a file in a file system, be stored in a portion of a file that holds other programs or data, for example in one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, for example, files that store one or more modules, sub programs, or portions of code.

[0269] As an example, the executable instructions can be deployed to be executed on one electronic device or on multiple electronic devices that are located at one site, or that are distributed across multiple sites and that are interconnected by a communication network.

[0270] In some embodiments, referring to FIG. 22, which is a schematic diagram of a storage medium according to an embodiment of the present application. The storage medium includes a first storage medium corresponding to the memory device 104, a second storage medium corresponding to the memory controller 104, and a third storage medium corresponding to the memory system 102. When the executable instructions are executed by the memory device, the first storage medium can be used to implement the steps of the operation method of the memory device according to the embodiments of the present application. When the executable instructions are executed by the memory controller, the second storage medium can be used to implement the steps of the operation method of the memory controller according to the embodiments of the present application. When the executable instructions are executed by the memory system, the third storage medium can be used to implement the steps of the operation method of the memory system according to the embodiments of the present application.

[0271] It should be understood that every feature, structure, or characteristic mentioned herein in relation to an embodiment is included in at least one embodiment of the present application. Therefore, the occurrence of the phrase "in one embodiment" or "in an embodiment" in various places in the specification is not necessarily referring to the same embodiment. In addition, these features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the size of the serial number of each process in various embodiments of the present application does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The serial number of the above embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0272] The above description is only the preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation made according to the content of the specification and drawings of the present application, or direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cells, a preset number of the memory cells forming a codeword; a peripheral circuit coupled to the memory cell array and configured to: obtain M first results corresponding to at least one codeword under M target read voltages; the first results comprising a number of bits representing a flipping in a first read result and a second read result of the at least one codeword under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage being less than a preset voltage; obtain a predicted valley voltage based on the M first results and the M target read voltages in combination with a preset function model; the preset function model representing a relationship between the first results and the target read voltages; and determine a target valley voltage based on the predicted valley voltage; the target valley voltage being used as a read voltage for the at least one codeword when performing a read operation; wherein the M is an integer greater than or equal to 1.

2. The memory device of claim 1, wherein, The preset function model includes a quadratic function model, and the quadratic function model includes the following function relationship: y=a(x+b) 2 +c wherein the y is a first result, the x is a target read voltage, the b is used to represent a predicted parameter, the a is a first parameter, and the c is a second parameter.

3. The memory device of claim 2, wherein, the peripheral circuit is configured to: According to the M first results, the M target reading voltages, and the quadratic function model, N groups of the predicted parameters are obtained; wherein, the i is an integer and 1≤i≤M; obtain the predicted valley voltage based on N groups of the predicted parameters.

4. The memory device of claim 3, wherein, the i is equal to 1, and the first parameter and the second parameter are constants; the peripheral circuit is configured to: obtain N groups of the predicted parameters based on the M first results, the M target read voltages, the quadratic function model, the first parameter, and the second parameter.

5. The memory device of claim 3, wherein, the i is equal to 2, the first parameter is a variable, and the second parameter is a constant; the peripheral circuit is configured to: obtain N groups of the predicted parameters and the first parameter based on the M first results, the M target read voltages, the quadratic function model, and the second parameter.

6. The memory device of claim 3, wherein, the i is equal to 3, and the first parameter and the second parameter are variables; the peripheral circuit is configured to: obtain N groups of the predicted parameters, the first parameter, and the second parameter based on the M first results, the M target read voltages, and the quadratic function model.

7. The memory device of any one of claims 4 to 6, wherein, the i is equal to the M; the peripheral circuit is configured to: obtain one group of the predicted parameters based on M first results, M target read voltages, and the quadratic function model; use the predicted parameter as the predicted valley voltage.

8. The memory device of any one of claims 4 to 6, wherein, the i is less than the M; the peripheral circuit is configured to: determine an outlier of N groups of the predicted parameters; use a median or an average of the remaining predicted parameters after removing the outlier from N groups of the predicted parameters as the predicted valley voltage.

9. The memory device of claim 3, wherein, the memory cell array comprises memory cells with a plurality of bits; a plurality of memory bits correspond to a plurality of pages; at least one page corresponds to a plurality of orders; the plurality of orders comprises a first order and a second order, and a read voltage of the second order is less than a read voltage of the first order; the peripheral circuit is configured to: According to the predicted valley voltage of the first order of each page in the plurality of pages, a predicted valley voltage of a second order in the plurality of orders and / or a predicted valley voltage of a remaining first order with a lower read voltage is obtained; and At least one of the code words is executed according to the predicted valley voltage of each page and the predicted valley voltage of the second order. The peripheral circuit is configured to:

10. The memory device of claim 9, wherein, According to the read result of the read operation, if error correction decoding is successful, the predicted valley voltage of each order is determined as a target valley voltage; According to the read result of the read operation, if error correction decoding fails, a first result corresponding to at least one of the code words at a target read voltage of a first order is re-obtained; According to the obtained plurality of first results and a plurality of target read voltages, the predicted parameters are re-obtained in combination with a preset function model; At least one of the code words is executed based on the re-obtained predicted parameters until the read result of the read operation is successfully error correction decoded. The peripheral circuit is configured to:

11. The memory device of claim 1, wherein, According to the first result corresponding to the first target read voltage in the M target read voltages, a preset threshold value is obtained; The preset threshold value is used to represent the first result corresponding to the maximum value in the effective range of the predicted valley voltage; According to the first result corresponding to the predicted valley voltage being less than the preset threshold value, the predicted valley voltage is taken as the target valley voltage. The storage unit array includes storage units with a plurality of storage bits; a plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of orders; and the peripheral circuit is configured to:

12. The memory device of claim 1, wherein, After determining the target valley voltage of at least one of the code words at a target order, the target valley voltages of other orders in the plurality of orders except the target order are determined respectively. The peripheral circuit is configured to:

13. The memory device of claim 1, wherein, Read the storage data of at least one of the code words at the first read voltage to obtain a second result; Read the storage data of at least one of the code words at the second read voltage to obtain a third result; Logical operation is performed on the second result and the third result to obtain a fourth result; The number of bits in the fourth result representing the flipping of the third result compared with the second result is counted to obtain the first result. The peripheral circuit includes a first latch, a second latch, and a third latch; 14. The memory device of claim 13, wherein, The first latch is configured to store the second result; The second latch is configured to store the third result; The third latch is configured to store the fourth result.

15. A memory system, comprising, one or more memory devices as claimed in any one of claims 1 to 14; and a memory controller coupled to the memory device and controlling the memory device.

16. The memory system of claim 15, wherein the memory controller is configured to send a data acquisition instruction indicating to obtain a target valley voltage; the memory device is configured to receive the data acquisition instruction, obtain a target valley voltage, and send information including the target valley voltage to the memory controller; ​ The memory controller is further configured to perform a read operation on data stored in a memory device according to the target valley voltage in the information.

17. The memory system of claim 16, wherein, The memory controller is further configured to perform an error correction code decoding operation on a read result of the read operation.

18. A memory controller coupled to at least one memory device, the memory device comprising a plurality of memory cells, a predetermined number of the memory cells forming a code word. The memory controller comprises: The control unit is configured to: obtain M first results corresponding to the at least one code word under M target read voltages; the first results include a number of bits representing a flipping in two read results of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage is less than a preset voltage; obtain a predicted valley voltage according to the M first results and the M target read voltages and in combination with a preset function model; the preset function model represents a relationship between the first results and the target read voltages; and determine a target valley voltage based on the predicted valley voltage; the target valley voltage is used as a read voltage of the at least one code word when performing a read operation; wherein the M is an integer greater than or equal to 1.

19. The memory controller of claim 18, wherein, The preset function model includes a quadratic function model, and the quadratic function model includes the following function relationship: y=a(x+b) 2 +c wherein y is the first result, x is the target read voltage, b is used to represent a predicted parameter, a is a first parameter, and c is a second parameter.

20. The memory controller of claim 19, wherein, The control unit is configured to: According to the M first results, the M target reading voltages, and the preset function model, N groups of predicted parameters are obtained; wherein The i is an integer, and 1≤i≤M; obtain the predicted valley voltage according to N groups of the predicted parameters.

21. The memory controller of claim 20, wherein, The i is equal to 1, and the first parameter and the second parameter are constants; the control unit is configured to: obtain N groups of the predicted parameters according to the M first results, the M target read voltages, the preset function model, the first parameter, and the second parameter.

22. The memory controller of claim 20, wherein, The i is equal to 2, the first parameter is a variable, and the second parameter is a constant; the control unit is configured to: obtain N groups of the predicted parameters and the first parameter according to the M first results, the M target read voltages, the preset function model, and the second parameter.

23. The memory controller of claim 20, wherein, The i is equal to 3, and the first parameter and the second parameter are variables; the control unit is configured to obtain N groups of the predicted parameters, the first parameter, and the second parameter according to the M first results, the M target read voltages, and the preset function model.

24. The memory controller of any one of claims 21 to 23, wherein, The i is equal to the M; the control unit is configured to: obtain one group of the predicted parameters according to M first results, M target read voltages, and the preset function model; use the predicted parameter as the predicted valley voltage.

25. The memory controller of any one of claims 21 to 23, wherein, The i is less than the M; the control unit is configured to: determine outliers of N groups of the predicted parameters; use a median or an average of the remaining predicted parameters after removing the outliers from N groups of the predicted parameters as the predicted valley voltage.

26. The memory controller of claim 20, wherein, The memory cell array comprises memory cells with a number of bits; a plurality of memory bits correspond to a plurality of pages; at least one page corresponds to a plurality of orders; the plurality of orders include a first order and a second order, and a read voltage of the second order is less than a read voltage of the first order; and the control unit is configured to: According to the first-order predicted valley voltage of each page in the multiple pages, a second-order predicted valley voltage is obtained; and A read operation is performed on at least one of the code words according to the first-order predicted valley voltage of each page and the second-order predicted valley voltage.

27. The memory controller of claim 26, wherein, The control unit is configured to: If error correction decoding of a read result of the read operation is successful, determine that the predicted valley voltage of each order is a target valley voltage; If error correction decoding of a read result of the read operation fails, re-obtain a first result corresponding to at least one of the code words at a target read voltage of a first order; According to the obtained multiple first results and multiple target read voltages, the preset function model is combined to re-obtain the predicted parameter; At least one of the code words is read based on the re-obtained predicted parameter until error correction decoding of a read result of the read operation is successful.

28. The memory controller of claim 18, wherein, The control unit is configured to: According to the first result corresponding to a first target read voltage in the M target read voltages, a preset threshold value is obtained; The preset threshold value is used to represent a maximum value in an effective range of a predicted valley voltage corresponding to a first result; If the first result corresponding to the predicted valley voltage is less than the preset threshold value, the predicted valley voltage is taken as the target valley voltage. The memory device includes a storage unit with a plurality of storage bits; a plurality of storage bits correspond to a plurality of pages; at least one page corresponds to a plurality of orders; and the control unit is configured to:

29. The memory controller of claim 18, wherein, After determining the valley voltage of at least one of the code words at a target order, the target valley voltage of each order other than the target order in the multiple orders is determined.

30. An operating method of a memory device, the memory device including a plurality of storage units, and a preset number of the storage units forming a code word; the operating method comprising: Obtaining M first results corresponding to at least one of the code words at M target read voltages; The first result includes a number of bits representing a flip of a read result of at least one of the code words at a first read voltage and a second read voltage; and a difference between the first read voltage and the second read voltage is less than a preset voltage; According to the M first results and the M target read voltages, a predicted valley voltage is obtained by combining a preset function model; and the preset function model represents a relationship between the first result and the target read voltage; and Based on the predicted valley voltage, a target valley voltage is determined; and the target valley voltage is used as a read voltage for at least one of the code words when performing a read operation. Wherein, M is an integer greater than or equal to 1. Wherein, y is the first result, x is the target read voltage, b represents a predicted parameter, a is a first parameter, and c is a second parameter.

31. The method of operating of claim 30, wherein, The preset function model includes a quadratic function model, and the quadratic function model includes the following function relationship: y=a(x+b) 2 +c The method comprises:

32. The method of operating of claim 31, wherein, The i is an integer, and 1≤i≤M; According to the M first results, the M target reading voltages, and the preset function model, N groups of predicted parameters are obtained; wherein, According to N groups of the predicted parameters, the predicted valley voltage is obtained.

33. A storage medium having stored thereon executable instructions which, when executed, implement the steps of the operating method of any one of claims 30-32. ​

Images