Memory apparatus and operating method therefor, and memory system and memory controller

Abstract

Disclosed in the embodiments of the present application are a memory apparatus and an operation method therefor, and a memory system, a memory controller and a storage medium. The memory apparatus comprises: a memory cell array, which comprises a plurality of memory cells, wherein a preset number of memory cells form a codeword; and a peripheral circuit, which is coupled to the memory cell array, wherein the peripheral circuit is configured to acquire M first results corresponding to at least one codeword under M reference read voltages, each first result comprising the number of bits flipped in two read results of the at least one codeword under a first read voltage and a second read voltage, and M being an integer greater than or equal to 2; and the peripheral circuit is further configured to acquire predicted valley voltages on the basis of the M first results within a first preset interval and the M reference read voltages and in combination with a preset function model that represents the relationship between the first results and the reference read voltages, and determine a target valley voltage on the basis of the predicted valley voltages, which target valley voltage is used as a read voltage for performing a read operation on the at least one codeword.

Description

Memory device and operating method thereof, memory system, and memory controller TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and relate to, but are not limited to, a memory device and operating method thereof, a memory system, a memory controller, and a storage medium. BACKGROUND

[0002] With the development of technology, the market size of the integrated circuit industry is becoming larger and larger, and the process and technology of the non-volatile memory device in the entire integrated circuit industry have developed by leaps and bounds in recent years. Among them, the application of NAND type memory is particularly widespread. The NAND type memory realizes the function of data storage by capturing and storing electric charges in the gate dielectric layer of the storage unit it contains. However, as the use time increases, the electric charges stored in the storage unit will change with the increase of the use time, repeated read operations, cross temperature, etc., thereby affecting the correctness of reading the data stored in the storage unit.

[0003] SUMMARY

[0004] In a first aspect, embodiments of the present application provide a memory device, comprising: a storage unit array comprising a plurality of storage units, a preset number of the storage units forming a code word; a peripheral circuit coupled to the storage unit array and configured to: obtain M first results corresponding to at least one code word under M reference read voltages; the first result comprises the number of bits representing the flipping of the at least one code word in the two read results under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; according to the M first results and the M reference read voltages, a preset function model is combined to obtain a predicted valley bottom voltage; the preset function model represents the relationship between the first result and the reference read voltage; the M first results are all within a first preset interval; and based on the predicted valley bottom voltage, a target valley bottom voltage is determined; the target valley bottom voltage is used as a read voltage when performing a read operation on at least one code word.

[0005] In a second aspect, embodiments of the present application provide a memory system, one or more memory devices as described in any of the first aspects; and a memory controller coupled to the memory device and controlling the memory device.

[0006] In a third aspect, an embodiment of the present application provides a memory controller coupled with at least one memory device, the memory device including a plurality of memory cells, a preset number of the memory cells forming a code word; the memory controller including: a control unit configured to: obtain M first results corresponding to at least one code word under M reference read voltages; the first result including a number of bits representing a flip in two reading results of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage being less than a preset voltage; the M being an integer greater than or equal to 2; obtaining a predicted valley voltage according to the M first results and the M reference read voltages in combination with a preset function model; the preset function model representing a relationship between the first result and the reference read voltage; the M first results being all within a first preset interval; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage being used as a read voltage for the at least one code word when performing a read operation.

[0007] In a fourth aspect, an embodiment of the present application provides an operation method of a memory device, the memory device including a plurality of memory cells, a preset number of the memory cells forming a code word; the operation method including: obtaining M first results corresponding to at least one code word under M reference read voltages; the first result including a number of bits representing a flip in two reading results of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage being less than a preset voltage; the M being an integer greater than or equal to 2; obtaining a predicted valley voltage according to the M first results and the M reference read voltages in combination with a quadratic function model; the preset function model representing a relationship between the first result and the reference read voltage; the M first results being all within a first preset interval; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage being used as a read voltage for the at least one code word when performing a read operation.

[0008] In a fifth aspect, an embodiment of the present application provides a storage medium, the storage medium storing executable instructions, when the executable instructions are executed, steps of the operation method of any one of the fourth aspect can be implemented. BRIEF DESCRIPTION OF DRAWINGS

[0009] In the drawings, like reference numerals refer to like elements throughout the various drawings. The drawings are not necessarily to scale, emphasis instead being placed on illustrating principles of the application. It should be understood that the drawings are merely depictions of some embodiments of the application and should not be construed as limiting the scope of the application.

[0010] FIG. 1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0011] FIG. 2A is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0012] FIG. 2B is a schematic diagram of an exemplary solid state drive having a memory system according to an embodiment of the present application;

[0013] FIG. 3 is a schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present application;

[0014] FIG. 4 is a schematic diagram of a cross-section of an array of memory cells including NAND type memory strings according to an embodiment of the present application;

[0015] FIG. 5 is a schematic diagram of an exemplary memory device including an array of memory cells and a peripheral circuit according to an embodiment of the present application;

[0016] FIG. 6 is a schematic diagram of an exemplary read operation flow of a memory system according to an embodiment of the present application;

[0017] FIG. 7 is a schematic diagram of an implementation flow of a method of operations performed by a peripheral circuit of a memory device according to an embodiment of the present application;

[0018] FIG. 8A is a schematic diagram of a threshold voltage distribution of a pair of memory cells including 2 storage bits according to an embodiment of the present application;

[0019] FIG. 8B is a schematic diagram of a threshold voltage distribution of a pair of memory cells including 3 storage bits according to an embodiment of the present application;

[0020] FIG. 8C is a schematic diagram of a threshold voltage distribution of a pair of memory cells including 4 storage bits according to an embodiment of the present application;

[0021] FIG. 9 is a schematic diagram of a threshold voltage distribution of a memory cell when a first result is obtained according to an embodiment of the present application;

[0022] FIG. 10 is a schematic diagram of a preset function model according to an embodiment of the present application;

[0023] FIG. 11 is a schematic diagram of determining a first preset interval according to an embodiment of the present application;

[0024] FIG. 12 is a schematic diagram of obtaining a reference read voltage according to an embodiment of the present application;

[0025] FIG. 13 is a schematic diagram of obtaining a reference read voltage according to an embodiment of the present application;

[0026] FIG. 14 is a schematic diagram of obtaining a reference read voltage according to an embodiment of the present application;

[0027] FIG. 15 is a schematic diagram of a method for obtaining a reference read voltage according to an embodiment of the present application;

[0028] FIG. 16A is a schematic diagram of a method for confirming a preset threshold corresponding to a fifth level read voltage according to a lower page shown in FIG. 8B according to an embodiment of the present application;

[0029] FIG. 16B is a schematic diagram of a method for confirming a preset threshold corresponding to a fifth level read voltage according to a lower page shown in FIG. 8B according to an embodiment of the present application;

[0030] FIG. 17 is a flow chart diagram of a method for operating a memory device according to an embodiment of the present application;

[0031] FIG. 18 is a schematic diagram of an exemplary configuration of a memory system according to an embodiment of the present application;

[0032] FIG. 19 is a block diagram of a memory system according to an embodiment of the present application;

[0033] FIG. 20 is a timing diagram of an exemplary operation for starting a single level read mode according to an embodiment of the present application;

[0034] FIG. 21 is a timing diagram of a method for determining a target valley voltage and performing a read operation according to an embodiment of the present application;

[0035] FIG. 22 is a schematic diagram of an exemplary configuration of a storage medium according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] Exemplary embodiments of the present application will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be embodied in various forms without being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0037] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail in order to avoid unnecessarily complicating this disclosure. As used herein, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0038] Furthermore, the accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present application and, as such, a change in the drawings can be made for clarity of explanation and emphasis. In the drawings, the same reference numbers and indicators can be used throughout the different drawings to refer to same or like parts.

[0039] The flowcharts shown in the drawings are only illustrative and do not necessarily include all the steps. For example, some steps can be further decomposed, and some steps can be combined or partially combined, so the actual execution order can be changed according to the actual situation.

[0040] The terms used herein are only for the purpose of describing specific embodiments and not as a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprise" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0041] The memory device in the embodiments of the present application includes, but is not limited to, a three-dimensional NAND type memory. For ease of understanding, the three-dimensional NAND type memory is taken as an example for description.

[0042] FIG. 1 illustrates a block diagram of an exemplary system 100 with a memory device, in accordance with some aspects of the present application. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Argument Reality (AR) device, or any other suitable electronic device with a storage. As shown in FIG. 1, the system 100 can include a host 108 and a memory system 102 with one or more memory devices 104 and a memory controller 106. The host 108 can be a processor (e.g., a Central Processing Unit (CPU)) or a System of Chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 108 can be configured to send or receive data to or from the memory device 104.

[0043] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104, and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0044] In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Muti Media Card (eMMC) used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., and enterprise storage arrays.

[0045] The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes with respect to data read from or written to the memory device 104.

[0046] The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0047] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of memory devices, such as included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0048] In one example as shown in FIG. 2A, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 with a host (e.g., the host 108 in FIG. 1).

[0049] In another example as shown in FIG. 2B, the memory controller 106 and the multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 with a host (e.g., the host 108 in FIG. 1). In some implementations, the SSD 206 has a larger storage capacity and / or operating speed than the memory card 202.

[0050] In some embodiments, each memory block can be coupled with a plurality of word lines, and each word line is coupled with a plurality of memory cells to form a physical page.

[0051] FIG. 3 shows a schematic circuit diagram of an exemplary memory device 300 including a peripheral circuit, in accordance with some aspects of the present application. The memory device 300 can be an example of the memory device 104 in FIG. 1. The memory device 300 can include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. By way of example, the memory cell array 301 is a three-dimensional NAND-type memory cell array, in which the memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each of which extends vertically above a substrate (not shown). In some implementations, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, e.g., a voltage or a charge, that depends on the number of electrons trapped in a region of the memory cell 306. Each memory cell 306 can be a floating-gate type of memory cell that includes a floating gate transistor, or a charge-trapping type of memory cell that includes a charge-trapping transistor.

[0052] In some embodiments, each storage unit 306 is a single-level cell (SLC) that has two possible storage states and thus can store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In some embodiments, each storage unit 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take on one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell, a fourth nominal storage value can be used for the erased state.

[0053] It is noted that the storage states referred to herein are also referred to as storage states of the storage units of the present disclosure. Different storage units have different numbers of storage states. For example, a SLC type storage unit has two storage states (i.e., two memory states), which include one programmed state and one erased state. For another example, a MLC type storage unit has four storage states, which include one erased state and three programmed states. For yet another example, a TLC type storage unit has eight storage states, which include one erased state and seven programmed states. In some embodiments, a QLC type storage unit has sixteen storage states, which include one erased state and fifteen programmed states.

[0054] As shown in FIG. 3, each memory string 308 can include a bottom select transistor (BSG) 310 (also referred to as a source side select transistor) at its source end and a top select transistor (TSG) 312 (also referred to as a drain side select transistor) at its drain end. The BSG 310 and TSG 312 can be configured to activate a selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a respective bit line (BL) 316 from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than a threshold voltage of the transistor having the TSG 312) or a deselect voltage (e.g., 0 V) to the respective TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than a threshold voltage of the transistor having the BSG 310) or a deselect voltage (e.g., 0 V) to the respective BSG 310 via one or more BSG lines 315.

[0055] As shown in FIG. 3, the memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same face as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20 V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318 that select which row of memory cells 306 is affected by read and program operations.

[0056] Referring to FIG. 3, each memory cell 306 of the plurality of memory cells is coupled to a respective word line 318, and each memory string 308 is coupled to a respective bit line 316 by a respective select transistor (e.g., a top select transistor (TSG) 312).

[0057] FIG. 4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 in NAND as an example, according to some aspects of the present application. As shown in FIG. 4, the NAND memory cell array 301 can include a stack structure 410 including a plurality of gate layers 411 and a plurality of insulating layers 412 alternately and sequentially stacked, and a channel structure vertically penetrating the gate layers 411 and the insulating layers 412, wherein the channel structure and each gate layer form a memory cell, and the channel structure and the plurality of gate layers in the stack structure 410 form a memory string 308. The gate layers 411 and the insulating layers 412 can be alternately stacked, and two adjacent gate layers 411 are separated by an insulating layer 412.

[0058] The constituent material of the gate layers 411 can include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 can include a control gate surrounding a memory cell. The gate layers 411 at the top of the stack structure 410 can laterally extend as upper select gate lines, the gate layers 411 at the bottom of the stack structure 410 can laterally extend as lower select gate lines, and the gate layers 411 laterally extending between the upper select gate lines and the lower select gate lines can serve as word line layers.

[0059] In some embodiments, the stack structure 410 can be disposed on a substrate 401. The substrate 401 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0060] In some embodiments, the storage string 308 includes a channel structure that extends vertically through the stack structure 410. In some implementations, the channel structure includes a channel hole that is filled with a semiconductor material(s) (e.g., as a semiconductor channel) and a dielectric material(s) (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a “charge-trapping / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a column shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0061] Referring back to FIG. 3, the peripheral circuitry 302 can be coupled to the array of memory cells 301 through the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the array of memory cells 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 306 via the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 5 illustrates some exemplary peripheral circuitry including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, registers 514, an interface 516, and a data bus 518. It should be appreciated that additional peripheral circuitry not shown in FIG. 5 can also be included in some examples.

[0062] The page buffer / sense amplifier 504 can be configured to read data from and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed to the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense low power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify small voltage swings to identifiable logic levels in read operations. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying bit line voltages generated from the voltage generator 510.

[0063] The row decoder / word line driver 508 can be configured to be controlled by the control logic 512 and select / deselect memory blocks 304 of the memory cell array 301 and select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from the voltage generator 510. In some implementations, the row decoder / word line driver 508 can also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform program operations on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic 512 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, channel boost voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0064] Control logic 512 can be coupled to each of the other portions of the peripheral circuitry described above and configured to control operation of each of the other portions of the peripheral circuitry. Registers 514 can be coupled to control logic 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control operation of each of the peripheral circuitry. Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic 512, and to buffer status information received from control logic 512 and relay them to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and act as a data I / O interface and data buffer to buffer data and relay them to or from memory cell array 301.

[0065] The basic principle of a three-dimensional NAND type memory is that a carrier (electron or hole) injects a certain amount of charge into a memory cell to complete the data writing process, and then the stored data can be read according to the threshold voltage when the memory cell is turned on. Therefore, in order to read the correct data, a high-efficiency error correction algorithm with strong error correction capability is usually introduced during data reading.

[0066] However, as the use time increases, the charge stored in the memory cell will change with the increase of the use time, repeated read operations, cross temperature, etc., thereby affecting the correctness of data reading. When the threshold voltage shifts significantly upwards or downwards, the possibility of reading error will be very large when the original read voltage is used to read the data of the memory cell, and when the read error exceeds the error correction capability, it will also cause the data reading of the memory cell to fail.

[0067] Figure 6 shows a schematic diagram of an exemplary read operation flow of a memory system. In conjunction with Figure 6, when the memory controller controls the memory device to perform a read operation, first, the default read operation (FW default read) is performed on the memory cell of the corresponding physical address, and when the default read operation fails, the read retry operation is performed, and when the read retry operation fails, the soft decode operation is performed, and when the soft decode operation fails, the redundant array of independent disk (RAID) operation is performed, and when the RAID operation fails, the read operation stops and fails to correct the error, and the memory controller sends a read fail signal to the host 108. The read retry operation and the default read operation can be applied to the hard decode (Hard decode).

[0068] In some embodiments, a retry operation can be generally performed by querying a retry table provided by a manufacturer. The essence of the retry operation is an error correction mechanism, and the retry table can provide a reference voltage for reading data. By querying the retry table, the read voltage deviating from the normal threshold voltage is tried to read each memory cell again and correct errors with an error correction algorithm, trying to correctly read the data. If the read error data is corrected, the querying of the retry table is stopped. If the read error data cannot be corrected, the retry table is queried until the entire retry table is traversed.

[0069] The above-mentioned retry operation mode will inevitably increase the number of trial and error and consume a lot of time because the retry table is queried piece by piece. In addition, the retry table provided by the manufacturer is only a reference value in some specific environment, and the real use scenario is changing, so the retry table provided by the manufacturer cannot cover many scenarios. Therefore, the data may not be corrected even if the retry table is traversed, which will waste a lot of processing command time. In summary, the retry operation mode by repeatedly polling the retry table consumes a lot of time and affects the response time of subsequent commands, thereby affecting the performance of the device.

[0070] Based on one or more of the above problems, in a first aspect, an embodiment of the present application provides a memory device.

[0071] As shown in FIG. 7, the memory device includes: a memory cell array including a plurality of memory cells, a preset number of memory cells forming a code word; a peripheral circuit coupled with the memory cell array and configured to perform the following steps:

[0072] Step S10: obtaining M first results corresponding to at least one code word under M reference read voltages; the first result includes the number of bits representing the flipping in the two read results of the at least one code word under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2;

[0073] Step S20: obtaining a predicted valley voltage according to the M first results and the M reference read voltages in combination with a preset function model; the preset function model represents the relationship between the first result and the reference read voltage; the M first results are all within a first preset interval;

[0074] Step S30: determining a target valley voltage based on the predicted valley voltage; the target valley voltage is used as a read voltage for performing a read operation on the at least one code word.

[0075] Here, the structure of the memory device is referred to the aforementioned FIG. 3, which will not be described here.

[0076] In some embodiments, a memory device includes an array of memory cells, the array of memory cells including a plurality of memory blocks, each memory block including a plurality of word lines and a plurality of memory cells coupled on each word line. All memory cells coupled on a word line form a physical page. A preset number of memory cells form a code word (CW). A physical page includes one or more code words.

[0077] In some embodiments, a code word includes the same number of memory cells as the number of memory cells included in one encoding or decoding when performing error correction encoding or decoding. In some specific embodiments, a code word includes a number of memory cells that is less than or equal to the number of memory cells coupled on a physical page, such as a code word includes 1 / 4 of the number of memory cells coupled on a physical page. In some specific embodiments, a code word can include a number of memory cells ranging from 2 4 to 2 12 . For example, a code word can include 2 4 , 2 8 , or 2 12 memory cells.

[0078] In general, different memory systems can choose different sizes of code words to meet their performance, reliability, and storage requirements. The number of bits stored by memory cells in different types of memory devices (e.g., MLC, TLC, or QLC) can be different. It can be understood that a code word can include a plurality of memory cells, and the number of memory cells included in a code word can be adjusted according to actual conditions.

[0079] It should be noted that in practice, a code word will have some additional reserved space for management and error correction, so the actual number of memory cells required may be slightly more than the calculation result above.

[0080] The meaning of the first result and the specific way to obtain the first result are introduced below.

[0081] Here, the first result represents the number of bits that flip in the two read results of a code word to be executed for a read operation under a first read voltage and a second read voltage.

[0082] Here, the first read voltage and the second read voltage are both generic concepts, and a difference between the first read voltage and the second read voltage is less than a preset voltage. In some embodiments, the second read voltage is greater than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of 5 mV to 20 mV. For example, the difference between the first read voltage and the second read voltage can be 5 mV, 10 mV, 15 mV, or 20 mV. In other embodiments, the second read voltage is less than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of -5 mV to -20 mV. For example, the difference between the first read voltage and the second read voltage can be -5 mV, -10 mV, -15 mV, or -20 mV.

[0083] In some embodiments, the peripheral circuit is configured to: read the stored data of the at least one code word at the first read voltage to obtain a second result; read the stored data of the at least one code word at the second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count a number of bits in the fourth result that represent a flip of the third result compared to the second result to obtain the first result. In some embodiments, the peripheral circuit includes: a first latch, a second latch, and a third latch; the first latch is configured to store the second result; the second latch is configured to store the third result; and the third latch is configured to store the fourth result.

[0084] Here, the first read voltage and the second read voltage are associated in sequence, that is, the second read voltage is obtained by a third adjustment on the first read voltage. Based on this, a difference between the first read voltage and the second read voltage is a third step. In some embodiments, the third step is set to a range of 5 mV to 20 mV. For example, the third step can be 5 mV, 10 mV, 15 mV, or 20 mV. The preset voltage is related to the third step, and can be a voltage slightly greater than the third step. In some embodiments, the preset voltage is set to a range of 6 mV to 21 mV. For example, the preset voltage can be 6 mV, 11 mV, 16 mV, or 21 mV. In other embodiments, the preset voltage is set to a range of -6 mV to -21 mV. For example, the preset voltage can be -6 mV, -10 mV, -16 mV, or -21 mV.

[0085] It is to be noted that the first read voltage and the second read voltage are generic concepts, and the target read voltage and the read voltage obtained after the first adjustment and the second adjustment of the target read voltage can all be referred to as the first read voltage, and the read voltage obtained after the third adjustment of the first read voltage can all be referred to as the second read voltage. That is, the first read voltage is a generic concept, which can be understood as the target read voltage or the target adjusted read voltage (a voltage obtained after the target read voltage is adjusted by a target step, and the range of the target step can be set to 20 mV to 40 mV, for example, the first step of the first adjustment can be 20 mV, 30 mV, or 40 mV, and the range of the target step can also be set to 50 mV to 150 mV, for example, the second step of the second adjustment can be 50 mV, 60 mV, 70 mV, 80 mV, 100 mV, 120 mV, or 150 mV).

[0086] It is to be noted that the target read voltage (the first read voltage) for initial use can refer to a preset read voltage capable of distinguishing two adjacent storage states of the memory cells in the previous read process, and the preset read voltage can be an empirical value; or a default value configured when the memory device is shipped, which is obtained through a large number of simulation experiments before the memory device is shipped.

[0087] In some embodiments, in the process of reading the memory device, one read operation reads the data of one physical page, and when the number of memory cells included in one code word is less than the number of memory cells coupled to one physical page, the code word is the unit on which the first result can be obtained, but it is not excluded that multiple code words are actually obtained. That is, at least one code word corresponding to the first result at the target read voltage can be obtained here. For example, one physical page can correspond to four code words, and the page buffer hardware operation can count the Fail Bit Count (FBC) of the four code words respectively at one time, and then the FBC of the four code words is added to obtain the FBC of one physical page, and the subsequent calculation uses the added value. It can be understood that the first result here can be based on the data of one physical page, and one physical page can correspond to multiple code words.

[0088] In some embodiments, the peripheral circuit is configured to: obtain the first result corresponding to at least one code word at the target read voltage; and when the first result corresponding to at least one code word at the target read voltage is in a first preset interval, take the target read voltage as a reference read voltage, and take the corresponding first result as the first result at the reference read voltage. In some embodiments, the first preset interval represents a numerical interval of the first result corresponding to a preset region of the curve of the preset function model.

[0089] In some embodiments, the preset function model can be fitted by a large amount of experimental data before the memory device is shipped. The first preset interval refers to a numerical interval of the first result corresponding to the experimental data that can accurately reflect the distribution of the actual valley voltage when the preset function model is fitted. It can be understood that in the process of determining the target valley voltage of the at least one code word, the at least one code word corresponding to the plurality of first results obtained at a plurality of different target read voltages has different numerical values, and the target read voltage corresponding to the first result in the first preset interval is taken as the reference read voltage, and the corresponding first result is taken as the first result at the reference read voltage, in other words, the data used to obtain the predicted valley voltage / target valley voltage is filtered by the first preset interval, and thus, according to the reference read voltage and the corresponding first result at the reference read voltage combined with the preset function model, the accuracy of the predicted valley voltage / target valley voltage obtained is higher.

[0090] It should be noted that the predicted valley voltage can be directly used as the target valley voltage to perform a read operation on the data to be read, or the target valley voltage is obtained after further processing. The specific way of obtaining the predicted valley voltage will be further described below.

[0091] The target valley voltage is used as the read voltage when the at least one code word performs a read operation. In the memory device, the target valley voltage is obtained according to a limited number of reference read voltages and M first results in the first preset interval corresponding to the M reference read voltages, combined with the preset function model, which can reduce the number of loop iterations and more quickly and accurately determine the target valley voltage.

[0092] In some embodiments, the storage unit array includes a storage unit with P bits of storage, and the P bits of storage correspond to P pages, and the P-bit storage unit reads its P-bit storage data through Q-level read voltages; P and Q are both integers greater than 1, and Q=2 P -1.

[0093] For example, when the number of storage bits of the storage unit includes two bits, the corresponding storage states include the 0th state to the 4th state. Referring to FIG. 8A, the four states are the 0th state (also referred to as the erase state) E, the 1st state (also referred to as the 1st storage state) P1, the 2nd state (also referred to as the 2nd storage state) P2, and the 3rd state (also referred to as the 3rd storage state) P3, and the binary data corresponding to the four states are 11, 10, 00, and 01, respectively. Accordingly, the memory device includes two pages, namely, the lower page (LP) and the upper page (UP).

[0094] For example, the storage unit shown in FIG. 8A, a two-bit storage unit reads its two-bit four-state storage data through three levels of read voltages (the first level read voltage L1, the second level read voltage L2 and the third level read voltage L3 shown in FIG. 8A).

[0095] For example, one page corresponds to multiple levels of read voltages, and another page corresponds to one level of read voltage. As shown in FIG. 8A, the binary data corresponding to the lower page is 1001, and the first level read voltage L1 and the third level read voltage L3 are required to read the lower page. The binary data corresponding to the upper page is 1100, and the second level read voltage L2 is required to read the upper page.

[0096] For example, when the storage unit has three storage bits, the corresponding storage states include the 0th state to the 7th state. Referring to FIG. 8B, the eight states are the 0th state (also referred to as the erase state) E, the 1st state (also referred to as the 1st storage state) P1, the 2nd state (also referred to as the 2nd storage state) P2, …, the 7th state (also referred to as the 7th storage state) P7, and the binary data corresponding to the eight states are 111, 110, 100, 000, 010, 011, 001 and 101, respectively. Accordingly, the memory device includes three pages, namely the lower page, the middle page (MP) and the upper page.

[0097] For example, the storage unit shown in FIG. 8B, a three-bit storage unit reads its three-bit eight-state storage data through seven levels of read voltages (the first level read voltage L1, the second level read voltage L2, the third level read voltage L3, the fourth level read voltage L4, the fifth level read voltage L5, the sixth level read voltage L6 and the seventh level read voltage L7 shown in FIG. 8B).

[0098] For example, each page corresponds to multiple levels of read voltages. As shown in FIG. 8B, the binary data corresponding to the lower page is 10000111, and the first level read voltage L1 and the fifth level read voltage L5 are required to read the lower page. The binary data corresponding to the middle page is 11001100, and the second level read voltage L2, the fourth level read voltage L4 and the sixth level read voltage L6 are required to read the middle page. The binary data corresponding to the upper page is 11100001, and the third level read voltage L3 and the seventh level read voltage L7 are required to read the upper page.

[0099] Exemplarily, when the storage bit number of the storage unit includes four bits, the corresponding storage states include the 0th state to the 15th state. Referring to FIG. 8C, the 16 states are the 0th state (also referred to as the erase state) E, the 1st state (also referred to as the 1st storage state) P1, the 2nd state (also referred to as the 2nd storage state) P2, …, and the 15th state (also referred to as the 15th storage state) P15, respectively. The binary data corresponding to the 16 states are 1111, 0111, 0110, …, and 1110, respectively. Correspondingly, the memory device includes four pages, which are the lower page, the middle page, the upper page, and the extra page (XP). Here, the four storage bits corresponding to the 16 states are stored in the lower page, the middle page, the upper page, and the extra page, respectively.

[0100] Exemplarily, referring to the storage unit shown in FIG. 8C, the four-bit storage unit reads the storage data of the four-bit sixteen states by the 15-level read voltage (the first-level read voltage L1, the second-level read voltage L2, the third-level read voltage L3, the fourth-level read voltage L4, the fifth-level read voltage L5, the sixth-level read voltage L6, the seventh-level read voltage L7, the eighth-level read voltage L8, the ninth-level read voltage L9, the tenth-level read voltage L10, the eleventh-level read voltage L11, the twelfth-level read voltage L12, the thirteenth-level read voltage L13, the fourteenth-level read voltage L14, and the fifteenth-level read voltage L15 shown in FIG. 8C).

[0101] Exemplarily, each page corresponds to a plurality of levels of read voltage. As shown in FIG. 8C, the binary data corresponding to the lower page are 1100000011111100, respectively. The second-level read voltage L2, the eighth-level read voltage L8, and the fourteenth-level read voltage L14 are required to read the lower page. The binary data corresponding to the middle page are 1110000110000111, respectively. The third-level read voltage L3, the seventh-level read voltage L7, the ninth-level read voltage L9, and the thirteenth-level read voltage L13 are required to read the middle page. The binary data corresponding to the upper page are 1111100000110001, respectively. The fifth-level read voltage L5, the tenth-level read voltage L10, the twelfth-level read voltage L12, and the fifteenth-level read voltage L15 are required to read the upper page. The binary data corresponding to the extra page are 1000110000011111, respectively. The first-level read voltage L1, the fourth-level read voltage L4, the sixth-level read voltage L6, and the eleventh-level read voltage L11 are required to read the extra page.

[0102] The lower page is usually closest to the source / drain, so the target valley voltage of each level of read voltage corresponding to the lower page is determined in priority. The access speed is the fastest, the response time is the shortest, and the balance performance and durability in the data access process can be ensured.

[0103] It should be noted that the target valley bottom voltage determination of each level read voltage corresponding to the next page is only an example, and is not used to limit the determination order of the target valley bottom voltage of each level read voltage corresponding to the plurality of level read voltages of at least one page in the embodiments of the present application.

[0104] In the embodiments of the present application, the first result corresponding to a specific voltage (for example, the first read voltage V0 shown in FIG. 9) can be understood as follows: the third adjustment is performed on the specific voltage, that is, the specific voltage and the third adjusted specific voltage (for example, the second read voltage V1 shown in FIG. 9) have a first voltage difference AV1, and the number of bits that flip in the two read results of the preset number of storage units at the specific voltage and the third adjusted specific voltage can be used as the first result corresponding to the specific voltage, wherein the preset number of storage units can form at least one codeword.

[0105] In some embodiments, before obtaining the first result corresponding to the target read voltage of the at least one codeword, the read mode of the memory device is set to a single level read (SLR) mode; the single level read mode includes reading at least one bit of storage data stored in the storage unit by a level read voltage.

[0106] In some specific embodiments, the memory device is configured to enter the single level read mode in response to a mode setting command, and obtain the first result corresponding to the target read voltage of the at least one codeword in the single level read mode.

[0107] In some specific embodiments, the storage data of the codeword is read at the first read voltage to obtain a second result; the second result is stored in the first latch of the memory device. For example, as shown in FIG. 9, the storage data of the at least one codeword is read at the first read voltage V0 to obtain a second result. Specifically, the storage unit with a threshold voltage less than the target read voltage V0 is marked as bit 1, and the storage unit with a threshold voltage greater than the target read voltage V0 is marked as bit 0 to obtain the second result, and the second result is stored in the first latch of the memory device.

[0108] Next, the first read voltage is adjusted for a third time to obtain a second read voltage, and the stored data of the at least one codeword is read at the second read voltage to obtain a third result; the third result is stored in a second latch of the memory device. Exemplarily, as shown in FIG. 9, the first read voltage V0 is adjusted for a third time, and the stored data of the codeword is read at the second read voltage V1 obtained after the adjustment to obtain a third result. Specifically, the storage cells with threshold voltages less than the second read voltage V1 are marked as bit 1, and the storage cells with threshold voltages greater than the second read voltage V1 are marked as bit 0 to obtain the third result, and the third result is stored in a second latch of the memory device.

[0109] Next, a logical operation is performed on the second result and the third result to obtain a fourth result; the fourth result is stored in a third latch of the memory device. Exemplarily, as shown in FIG. 9, an exclusive-OR operation is performed on the second result and the third result to obtain a fourth result; the fourth result is stored in a third latch of the memory device.

[0110] It should be noted that the exclusive-OR operation is one of basic logical operations, and in binary, two binary numbers at the same position are the same, and the result is “0”, and two binary numbers at the same position are different, and the result is “1” (i.e., the same is 0, and the different is 1).

[0111] Next, the number of bits in the fourth result representing the flipping of the third result compared with the second result is counted to obtain the first result. Exemplarily, as shown in FIG. 9, the part with bit 1 in the fourth result represents the number of storage cells with threshold voltages different between the first read voltage V0 and the second read voltage V1, in other words, the part with bit 1 in the fourth result represents the number of bits flipped in the two reading results of the codeword at the first read voltage V0 and the second read voltage V1, and the number is recorded as the first result Y1 corresponding to the first read voltage V0.

[0112] It should be noted that the first result is also referred to as FBC in the embodiments of the present application.

[0113] In some embodiments, the preset function model is related to the characteristics of the memory device, and the preset function model can be fitted by a large number of experimental results before the memory device is shipped and saved in the memory device.

[0114] Exemplarily, the preset function model is encoded into a code, and the code is saved in the firmware or software of the memory device.

[0115] In some embodiments, a large amount of data is collected through a large number of experiments before the memory device is shipped, and the data can be preprocessed by removing outliers, sorting, denoising, etc. before analysis. A statistical method, machine learning or other modeling technique is used to fit a preset function model to describe the relationship between the reference read voltage and the first result.

[0116] It should be noted that a large amount of data is collected through a large number of experiments before the memory device is shipped, which can be understood as obtaining a plurality of first results corresponding to a plurality of different target read voltages for at least one codeword before the memory device is shipped, and taking the target read voltage corresponding to the first result in the first preset interval in the plurality of first results as the reference read voltage, and taking the corresponding first result as the first result at the reference read voltage, to fit the preset function model based on the plurality of reference read voltages and the corresponding plurality of first results before the memory device is shipped.

[0117] Exemplarily, a regression analysis method is used to fit a preset function model through a large amount of collected reference read voltages and corresponding first results.

[0118] Exemplarily, a data-driven method such as machine learning or deep learning is used to establish a preset function model to represent the relationship between the reference read voltage and the first result through a large amount of collected reference read voltages and corresponding first results.

[0119] In some embodiments, the peripheral circuit is configured to: obtain a prediction parameter of the preset function model according to the M first results and the M reference read voltages in combination with the preset function model; the prediction parameter is the reference read voltage corresponding to the minimum first result on the curve of the preset function model; and obtain the predicted valley bottom voltage according to the prediction parameter.

[0120] In some specific embodiments, the function relationship in the fitted preset function model includes a related parameter, and when the predicted valley bottom voltage is obtained, the value of the related parameter can be obtained according to the M first results, the M reference read voltages and the function relationship, and further the reference read voltage corresponding to the minimum first result on the curve of the preset function model is obtained, and the reference read voltage corresponding to the minimum first result on the curve of the preset function model is taken as the predicted valley bottom voltage. In some embodiments, the preset function model includes a quadratic function model including the following function relationship: y = a(x + b) 2 + c

[0121] Where y is the first result, x is the reference read voltage, b is used to represent the prediction parameter, a is the first parameter, and c is the second parameter.

[0122] As shown in FIG. 10, in combination with the function relationship included in the above-mentioned quadratic function model, it can be known that the extreme value of the curve of the quadratic function model is located at the position of the symmetry axis x = -b, i.e., the position where the derivative of the curve of the quadratic function model is 0. Exemplarily, when the first parameter is greater than 0, the y value (the first result) corresponding to x = -b is the minimum value of the curve of the quadratic function model, and the coordinates of the extreme point (point A shown in FIG. 10) are (-b, c).

[0123] In some embodiments, the value of the prediction parameter is the opposite of b, i.e., the prediction parameter represents the horizontal coordinate corresponding to the minimum value of the curve of the quadratic function model.

[0124] As shown in FIG. 10, the symmetry axis (at x = -b) of the curve of the quadratic function model is offset from the y axis (at x = 0) by -b, i.e., the distance between the symmetry axis of the curve of the quadratic function model and the y axis is the absolute value |b| of b.

[0125] Here, x = 0 can be understood as the position of the default read voltage, and the term "the first result corresponding to the default read voltage" in the present application can be referred to as "default first result" for short. The default first result (point B shown in FIG. 10) corresponds to the coordinates (0, a 2 b + c). The default read voltage can be the read voltage when the threshold voltage of the storage unit has not been offset, such as the read voltage corresponding to the time of just writing, at which time the offset value is 0. It can be understood that when the offset value of the target read voltage from the default read voltage (x = 0) is -b, the first result corresponding to the target read voltage is the minimum value. It can be understood that the target read voltage corresponding to the minimum value of the first result (equivalent to the prediction parameter herein) is taken as the predicted valley bottom voltage, and based on the predicted valley bottom voltage, the target valley bottom voltage is determined, and the error rate of the read result is low and the reliability is high.

[0126] It should be noted that the target read voltage corresponding to the minimum value of the first result (equivalent to the prediction parameter herein) is taken as the predicted valley bottom voltage, i.e., -b is taken as the predicted valley bottom voltage, which represents that the offset value of the predicted valley bottom voltage from the default read voltage is -b, rather than representing that the predicted valley bottom voltage is negative. When -b is greater than 0, it indicates that the size of the rightward offset of the predicted valley bottom voltage from the default read voltage is |b|, and when -b is less than 0, it indicates that the size of the rightward offset of the predicted valley bottom voltage from the default read voltage is |b|. In other words, the relationship between the actual voltage of the predicted valley bottom voltage (denoted as Vpre) and the actual voltage of the default read voltage (denoted as Vdefault) is as follows: Vpre = Vdefault + (-b)

[0127] Similarly, after determining the target valley voltage based on the predicted valley voltage, using the target valley voltage to perform the read operation on the at least one codeword refers to using the actual voltage of the target valley voltage to perform the read operation on the at least one codeword. It should be noted that when there is only one set of prediction parameters, the prediction parameters are directly used as the predicted valley voltage. However, when there are multiple sets of prediction parameters, the predicted valley voltage needs to be determined based on the multiple sets of prediction parameters.

[0128] In some embodiments, as shown in FIG. 10, the first preset interval represents a range between the first threshold (Th1) and the second threshold (Th2) of the curve of the quadratic function model. The first threshold (Th1) is greater than the second threshold (Th2).

[0129] FIG. 11 is a schematic diagram of determining the first preset interval according to an embodiment of the present application. In some embodiments, the solid dots shown in FIG. 11 are a large amount of data (a plurality of target read voltages and a plurality of first results corresponding to the plurality of target read voltages) collected through a large number of experiments before the memory device is shipped. When the preset function model is fitted based on the data shown in FIG. 11, the selection of the data directly relates to the accuracy of the preset function model fitted. For example, when the FBC of the selected data is too high (for example, the solid dots in the dashed box area A1 or the dashed box area A2 shown in FIG. 11), the preset function model fitted will not match the distribution curve of the actual valley voltage. Specifically, the preset function model fitted based on the solid dots in the dashed box area A1 or the dashed box area A2 is a quadratic function model with the opening facing downward, which does not match the distribution curve of the actual valley voltage (a quadratic function model with the opening facing upward). When the FBC of the selected data is too low (for example, the solid dots in the dashed box area A3 shown in FIG. 11), the error of the preset function model fitted is too large, resulting in a large deviation between the target valley voltage obtained based on the preset function model and the actual valley voltage.

[0130] Therefore, it can be seen that the selection of the data is particularly important when fitting the preset function model, otherwise the preset function model will not accurately reflect the distribution of the actual valley voltage. For example, when the FBC of the selected data is in the first preset interval (for example, the range between the first threshold (Th1) and the second threshold (Th2) shown in FIG. 11), the preset function model fitted can accurately reflect the distribution of the actual valley voltage. When a large amount of data is collected through a large number of experiments before the memory device is shipped and the preset function model is fitted based on the data in the first preset interval, the accuracy is high. It can be understood that the accuracy of the predicted valley voltage obtained based on the M reference read voltages, the M first results in the first preset interval, and the preset function model is also ensured.

[0131] In some embodiments, the first preset interval ranges from 50 to 200.

[0132] It should be noted that the range of the first preset interval provided in the embodiments of the present application is only an example, and the range of the first preset interval is related to the characteristics of the memory device, and should not be overly limited to the protection scope of the present application.

[0133] In some embodiments, the first parameter and the second parameter are both constants; the peripheral circuit is configured to: obtain a first result corresponding to the at least one code word under the target read voltage; and according to the first result corresponding to the at least one code word under the target read voltage being within the first preset interval, take the target read voltage as a reference read voltage; according to the first result corresponding to the at least one code word under the target read voltage being outside the first preset interval, re-obtain at least one new target read voltage, obtain a first result corresponding to the at least one new target read voltage, until the first result corresponding to the at least one new target read voltage is within the first preset interval.

[0134] Here, the first parameter and the second parameter can be obtained when fitting the preset function model, and saved in the memory device.

[0135] Exemplarily, the preset function model includes a quadratic function model, and the quadratic function model includes the following function relationship formula (1): y = a(x + b) 2 +c

[0136] The first parameter and the second parameter in the function relationship formula can be optimized using, but not limited to, least squares method, gradient descent method, Bayesian optimization, Newton method and quasi-Newton method, and the optimal first parameter and second parameter are saved in the memory device. The least squares method is a parameter estimation method, which estimates the parameters by minimizing the sum of squares of residuals between the actually collected data and the predicted values of the quadratic function model. The gradient descent method is to take the parameters of the quadratic function model as the optimization target, and use the gradient descent method to find the parameter value that minimizes the fitting error of the quadratic function model, by calculating the gradient of the loss function with respect to the first parameter and the second parameter, and then updating the values of the first parameter and the second parameter in the opposite direction of the gradient until convergence is reached.

[0137] In some embodiments, as shown in FIG. 12, the peripheral circuit is configured to: obtain a first result corresponding to the at least one code word under the target read voltage, i.e., obtain the C point (x c ,y c ) shown in FIG. 12; the first result (y c ) corresponding to the C point is within the first preset interval, and the target read voltage (x c ) corresponding to the C point is taken as a reference read voltage.

[0138] It should be noted that Figure 12 uses point C as an example, which should not unduly limit the scope of protection of this application. Furthermore, point C corresponds to the first result obtained at the default read voltage according to the method for obtaining the first result in the aforementioned embodiment. Therefore, point C is an actual value that may or may not lie on the curve of the quadratic function model.

[0139] In some embodiments, as shown in FIG13 , the peripheral circuit is configured as follows: c ,y c ) corresponds to the first result (y c ) is outside the first preset interval, re-obtain at least one new target read voltage, and obtain the first result corresponding to the at least one new target read voltage until the first result corresponding to the latest target read voltage is within the first preset interval.

[0140] It is understood that only when the first result corresponding to the target read voltage is within the first predetermined range can the target read voltage be used as the reference read voltage for obtaining the predicted valley voltage. This can enhance the accuracy and reliability of obtaining the predicted valley voltage based on multiple reference read voltages and multiple first results.

[0141] In some embodiments, at least two of the M reference read voltages are on both sides of the axis of symmetry of the curve where the quadratic function model is located; the peripheral circuit is configured to: when obtaining the reference read voltage, obtain the reference read voltage on the first side of the two sides of the axis of symmetry of the curve where the quadratic function model is located; and determine the reference read voltage on the second side of the two sides of the axis of symmetry based on the reference read voltage on the first side.

[0142] In some embodiments, the first and second parameters can be derived when fitting a preset function model and stored in a memory device. Based on the coordinates of point C in FIG. 12 or FIG. 13 , the functional relationship of the quadratic function model, the first and second parameters, an initial b value can be obtained. Based on this initial b value, the axis of symmetry x = -b of the curve on which the quadratic function model resides can be determined.

[0143] It should be noted that the first side refers to one side of the symmetry axis of the curve where the quadratic function model is located (such as at x = -b in Figures 12 and 13), and the second side refers to the other side of the symmetry axis of the curve where the quadratic function model is located. When the first side is on the right side of the symmetry axis, the second side is on the left side of the symmetry axis. When the first side is on the left side of the symmetry axis, the second side is on the right side of the symmetry axis.

[0144] For example, the target read voltage (x c ) is the reference reading voltage on the first side of the two sides of the symmetry axis of the curve where the quadratic function model is located.

[0145] Next, the process of obtaining the reference read voltage on the first side of the symmetry axis of the curve in the quadratic function model and obtaining the reference read voltage on the second side of the symmetry axis will be expanded in detail.

[0146] In some embodiments, when the first result corresponding to the at least one code word at the target read voltage is outside the first preset interval, the manner of re-obtaining at least one new target read voltage includes but is not limited to adjusting the target read voltage by a target step to obtain a read voltage as the new target read voltage. For example, as shown in FIG. 13, adjusting the target read voltage (x c ) by a target step to obtain a read voltage (x d ) as the new target read voltage, obtaining the first result (y e ) corresponding to the at least one code word at the new target read voltage, that is, obtaining the E point (x d , y e ) shown in FIG. 13, at this time, the E point is an actual value, when the first result (y e ) corresponding to the E point is within the first preset interval, the new target read voltage (x d ) corresponding to the E point is taken as a reference read voltage. The range of the target step can be set to 20mV to 40mV, for example, the first adjustment step can be 20mV, 30mV, 40mV, the range of the target step can also be set to 50mV to 150mV, for example, the second adjustment step can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV or 150mV.

[0147] In some embodiments, the peripheral circuit is configured to: when the first result corresponding to the at least one code word at the target read voltage is outside the first preset interval, obtain the fitting read voltage on the first side corresponding to the target first result based on the target read voltage, the first result corresponding to the target read voltage, the target first result and the first mapping function; the first mapping function is obtained according to the quadratic function model, the first parameter and the second parameter; the target first result is within the second preset interval, and the first preset interval is within the range of the second preset interval.

[0148] For example, as shown in FIG. 13, the peripheral circuit is configured to: when the first result (y c ) corresponding to the C point (x c , y c ) is outside the first preset interval, obtain the fitting read voltage on the first side corresponding to the target first result (y c ) based on the target read voltage (x c ), the first result (y c ) corresponding to the target read voltage, the target first result (y d) and a first mapping function, to obtain a fitting read voltage (x d ) on the first side corresponding to the target first result (y d ) of the actual point, i.e., according to the coordinates of the C point, the target first result (y d ), and the first mapping function, to obtain the D point (x d , y d ). The first mapping function includes the following relationship (2):

[0149] wherein x1 and y1 represent the horizontal coordinate and the vertical coordinate of the actual point that has been obtained, y2 represents a value selected from the second preset interval, and x2 represents the fitting read voltage. The first mapping function aims to obtain the fitting read voltage (e.g., x d in FIG. 13) according to a value in the second preset interval in combination with the actual point (e.g., the C point) that has been obtained. The first preset interval is within the range of the second preset interval. Optionally, the range of the second preset interval is 30 to 220.

[0150] The coordinates of the C point, the target first result (y d ), the first parameter, and the second parameter are substituted into the relationship (2) of the first mapping function, so as to obtain the D point (x d , y d ).

[0151] It should be noted that FIG. 13 and the first mapping function are described with the first side as the axis of symmetry, the right side, and the C point located on the first side.

[0152] At this time, the D point (x d , y d ) is a fitting point, and the horizontal coordinate x d of the D point is the fitting read voltage on the first side. The peripheral circuit is configured to: take the fitting read voltage as a new target read voltage, obtain the first result (y e ) corresponding to the fitting read voltage (x d ) on the first side of at least one code word, i.e., obtain the E point (x d , y e ), the E point being an actual point; and according to the first result (the vertical coordinate y e of the E point) corresponding to the fitting read voltage (x d ) on the first side, take the fitting read voltage (x d ) on the first side as a reference read voltage on the first side.

[0153] In some embodiments, the fitting read voltage (x d) as the new target reading voltage, and obtain the fitting reading voltage (x d ) corresponds to the first result (y f )), that is, get point F (x d ,y f The peripheral circuit is further configured to: according to the first result corresponding to the fitting read voltage at the first side (the vertical coordinate y of point F f ) is outside the first preset range, based on the previous fitting reading voltage on the first side, the first result corresponding to the previous fitting reading voltage on the first side, the target first result and the first mapping function, the next fitting reading voltage on the first side corresponding to the target first result is obtained, until the first result corresponding to the latest fitting reading voltage on the first side is within the first preset range, and the latest fitting reading voltage on the first side is used as a reference reading voltage on the first side. It can be understood that at this time, it is based on the previous known actual point F (x d ,y f ), target first result (any one in the second preset interval and y d Different values) and the first mapping function (relationship (2)), obtain the next fitted read voltage on the first side corresponding to the target first result, until the first result corresponding to the latest fitted read voltage on the first side is within the first preset interval, and use the latest fitted read voltage on the first side as a reference read voltage for the first side.

[0154] In some embodiments, the peripheral circuit is configured to: adjust the value of the first parameter and adjust the first mapping function accordingly based on the number of times that the first result corresponding to the latest fitted read voltage on the first side is outside the first preset interval is greater than or equal to the preset number of times; based on the previous fitted read voltage on the first side, the first result corresponding to the previous fitted read voltage on the first side, the target first result and the adjusted first mapping function, obtain the next adjusted fitted read voltage on the first side corresponding to the target first result, until the first result corresponding to the latest adjusted fitted read voltage on the first side is within the first preset interval.

[0155] Here, the preset number of times represents the upper limit of the number of trial and error times using the preset function model. If the first results corresponding to the fitted read voltage of the first side obtained using the preset function model after the preset number of times are all outside the first preset range, it means that the selected preset function model may not meet actual needs and requires more in-depth parameter adjustment. The preset number of times can be adjusted according to actual conditions. In some embodiments, the preset number of times is 3-7 times, and illustratively, the preset number of times can be 3, 5, or 7 times.

[0156] In some embodiments, when the number of times that the corresponding first result of the first side under the fitting read voltage obtained by the method in the foregoing embodiments is outside the first preset interval is greater than or equal to a preset number of times, it is indicated that a plurality of actual points have been obtained at this time. According to the plurality of actual points obtained, in combination with the function relationship formula (1) of the quadratic function model and the second parameter (constant), the value of the adjusted first parameter can be obtained. It can be understood that the adjustment of the first parameter of the quadratic function model in combination with the actual points in actual use can improve the accuracy and reliability of the quadratic function model, and can make the adjusted first parameter infinitely close to the first parameter corresponding to the actual valley bottom voltage distribution curve. In this way, the actual situation can be better reflected, and the quadratic function model can be flexibly applied to changes in actual use scenarios, improving the practicality of the quadratic function model.

[0157] Exemplarily, the preset number of times is 3 times, and the number of times that the corresponding first result of the first side under the fitting read voltage obtained by the method in the foregoing embodiments is outside the first preset interval is equal to 3 times, that is, at least 3 actual points are obtained at this time. The coordinates of the 3 actual points are denoted as (x3, y3) and (x4, y4), and (x5, y5), respectively. According to any two of the 3 actual points obtained, for example, (x3, y3) and (x4, y4), in combination with the function relationship formula (1) of the quadratic function model, the calculation formula (1) of b can be obtained as follows:

[0158] Based on the calculation formula (1) of b, according to the function relationship formula of the quadratic function model and the second parameter being a constant, the calculation formula (2) of the first parameter can be obtained as follows:

[0159] Exemplarily, according to the 3 actual points obtained, in combination with the function relationship formula (1) of the quadratic function model, the calculation formula (3) of b can be obtained as follows:

[0160] Based on the calculation formula (3) of b, according to the function relationship formula (1) of the quadratic function model and the second parameter being a constant, the calculation formula (4) of the first parameter can be obtained as follows:

[0161] In this way, the value of the adjusted first parameter is obtained, and the value of the adjusted first parameter is substituted into the function relationship formula (2) of the first mapping function to adjust the first mapping function.

[0162] In some embodiments, the peripheral circuit is configured to: obtain a fitted read voltage on the second side corresponding to the target first result based on a reference read voltage on the first side, a first result corresponding to a reference read voltage on the first side, a target first result, and a second mapping function; the second mapping function is obtained according to a quadratic function model, a first parameter / adjusted first parameter, and a second parameter; obtain a first result corresponding to at least one codeword at the fitted read voltage on the second side; and based on the first result corresponding to the fitted read voltage on the second side being within a preset interval, use the fitted read voltage on the second side as a reference read voltage on the second side.

[0163] For example, as shown in FIG14 , the peripheral circuit is configured as follows: based on a reference read voltage on the first side (the horizontal coordinate x corresponding to the G point) g ), the first result corresponding to a reference read voltage on the first side (the vertical coordinate y corresponding to point G g ), target first result (y h ) and the second mapping function to obtain the first result (y h ) corresponds to the fitting read voltage (x h ), that is, according to the coordinates of point G, obtain the first result (y h ) corresponds to the fitting read voltage (x h ), specifically, according to the coordinates of point G, the first target result (y h ) and the second mapping function, obtain the H point (x h ,y h ). The second mapping function includes the following relational formula (3):

[0164] Wherein, x1 and y1 represent the horizontal and vertical coordinates of the actual point obtained, respectively, y2 represents the target first result, which is a value selected within the second preset interval, and x2 represents the fitted reading voltage. The second mapping function is intended to obtain the fitted reading voltage (e.g., x1 shown in FIG. 14 ) based on a value within the second preset interval combined with the actual point obtained (e.g., point G). h ).

[0165] The coordinates of point G, the first result of the target (y h ), the first parameter / adjusted first parameter and the second parameter are substituted into the relational equation (3) of the second mapping function to obtain the H point (x h ,y h ).

[0166] At this time, point H (x h ,y h ) is a fitting point, and the horizontal coordinate x corresponding to point H is hThat is, the fitting read voltage on the second side, the peripheral circuit is configured to: use the fitting read voltage as the new target read voltage, and obtain the fitting read voltage (x h ) corresponds to the first result (y i )), that is, get point I (x h ,y i ), point I is the actual point; according to the first result corresponding to the fitting reading voltage on the second side (the ordinate y corresponding to point I i ) is within the first preset interval, the fitting reading voltage (x h ) as a reference read voltage on the second side.

[0167] In some embodiments, the peripheral circuit is configured to: according to the first result corresponding to the fitted read voltage on the second side being outside the preset interval, based on the previous fitted read voltage on the second side, the first result corresponding to the previous fitted read voltage on the second side, the target first result and the third mapping function, obtain the next fitted read voltage on the second side corresponding to the target first result, until the first result corresponding to the latest fitted read voltage on the second side is within the first preset interval, and use the latest fitted read voltage on the second side as a reference read voltage for the second side; the third mapping function is obtained according to the quadratic function model, the first parameter / the adjusted first parameter and the second parameter.

[0168] In some embodiments, as shown in FIG. 14 and FIG. 15 , the fitting reading voltage on the second side (the horizontal coordinate x corresponding to point H) is h ) as the new target reading voltage, and the fitting reading voltage (x h ) corresponds to the first result (y j )), that is, get point J (x h ,y j The peripheral circuit is further configured to: according to the first result corresponding to the fitting read voltage at the second side (the vertical coordinate y of point J j ) is outside the first preset range, based on the previous fitting reading voltage on the second side (the horizontal coordinate x of point J h ), the first result corresponding to the previous fitting reading voltage on the second side (the vertical coordinate y of point J j ), target first result (y k ) and the third mapping function to obtain the first result (y k ) corresponds to the next fitting read voltage (x k ), that is, obtain the K point (x ky k ) until the corresponding first result (y k ) at the latest fitting read voltage (x l ) on the second side is within the first preset interval, i.e., the ordinate at the L point (x k ,y l ) shown in FIG. 15 is within the first preset interval, the latest fitting read voltage (x k ) on the second side is taken as a reference read voltage on the second side; the third mapping function is obtained according to the quadratic function model, the first parameter / adjusted first parameter, and the second parameter. The third mapping function includes the following relationship (4):

[0169] wherein x1 and y1 represent the abscissa and ordinate of the obtained actual point respectively, y2 represents a target first result, which is an optional value within the second preset interval, and x2 represents a fitting read voltage. The third mapping function aims to obtain the fitting read voltage (e.g., x k ) shown in FIG. 15) according to a value within the second preset interval in combination with the obtained actual point (e.g., the J point).

[0170] The coordinates of the J point, the target first result (y k ), the first parameter / adjusted first parameter, and the second parameter are substituted into the relationship (4) of the third mapping function, so that the K point (x k ,y k ) can be obtained.

[0171] At this time, the K point (x k ,y k ) is a fitting point, and the abscissa x k corresponding to the K point is the fitting read voltage on the second side. The peripheral circuit is configured to: take the fitting read voltage as a new target read voltage, obtain the first result (y l ) corresponding to at least one code word at the fitting read voltage (x k ) on the second side, i.e., obtain the L point (x k ,y l ), and the L point is an actual point; and according to the first result (the ordinate y l corresponding to the L point) at the latest fitting read voltage on the second side being within the first preset interval, take the latest fitting read voltage (x k ) on the second side as a reference read voltage on the second side.

[0172] It should be noted that the A point, the B point, the D point, the H point and the K point in the embodiments of the present application are fitting points, which are located on the curve of the quadratic function model. The C point, the E point, the F point, the G point, the I point, the J point and the L point are actual points, which can be located on the curve of the quadratic function model or not.

[0173] In the embodiments of the present application, the M reference read voltages and the M first results corresponding to the combination of the two reference read voltages can be obtained by using the manner of obtaining the reference read voltages of the first side / second side in the foregoing embodiments, and the prediction parameters can be obtained according to the M reference read voltages and the M first results.

[0174] In some embodiments, the first parameter is a variable and the second parameter is a constant, and the peripheral circuit is configured to: obtain the prediction parameters according to the M first results and the M reference read voltages in combination with the quadratic function model; and take the prediction parameters as the predicted valley bottom voltage.

[0175] Exemplarily, N groups of prediction parameters are obtained according to the M first results, the M reference read voltages, the quadratic function model and the second parameter, where N is equal to

[0176] Here, the second parameter can be obtained when fitting the preset function model and saved in the memory device.

[0177] In some embodiments, M is equal to 2, N is equal to 1, the two reference read voltages and the two first results are substituted into the calculation formula (1) of b, b is calculated, and then one group of prediction parameters is obtained, and the prediction parameters are taken as the predicted valley bottom voltage.

[0178] In some embodiments, M is greater than 2, and N is equal to Based on the M reference read voltages and the M first results, the combination of the two reference read voltages and the two first results can be obtained, based on the combination and the calculation formula (1) of b, the N groups of prediction parameters can be obtained. The outlier of the N groups of prediction parameters is determined; based on the median and the standard deviation of the N groups of prediction parameters, the outlier is determined or the maximum value and the minimum value in the N groups of prediction parameters are taken as the outlier, and the median or the average value of the remaining prediction parameters in the N groups of prediction parameters after removing the outlier is taken as the predicted valley bottom voltage.

[0179] In this way, by determining the outlier of the multiple groups of prediction parameters and removing the outlier, the accuracy and reliability of the remaining prediction parameters when used to determine the predicted valley bottom voltage are ensured.

[0180] In some embodiments, the first parameter and the second parameter are both variables; the peripheral circuit is configured to: obtain a predicted parameter according to the M first results and the M reference read voltages, in combination with the quadratic function model; obtain a first result corresponding to at least one code word under a predicted parameter as a target read voltage; obtain a new predicted parameter according to the M first results, the M reference read voltages, the predicted parameter, and the first result corresponding to at least one code word under the predicted parameter as the target read voltage, in combination with the quadratic function model; and take the new predicted parameter as the predicted valley bottom voltage.

[0181] In some embodiments, the second parameter is a variable, but an initial value of the second parameter can be obtained when fitting the preset function model and saved in the memory device.

[0182] For example, according to the M first results, the M reference read voltages, the quadratic function model, and the initial value of the second parameter, a group of predicted parameters can be obtained in combination with the calculation formula (1) of b, where N is equal to

[0183] In some embodiments, M is equal to 2, N is equal to 1, the two reference read voltages and the two first results corresponding to the coordinates are substituted into the calculation formula (1) of b, b can be calculated, and a group of predicted parameters can be obtained; the predicted parameter is taken as a target read voltage, a first result corresponding to at least one code word under the predicted parameter as the target read voltage is obtained, that is, an actual point is obtained at this time; next, the coordinates of the three actual points (the two reference read voltages and the two first results corresponding thereto, the predicted parameter, and the first result corresponding to at least one code word under the predicted parameter as the target read voltage) are substituted into the calculation formula (3) of b, b can be calculated, a new group of predicted parameters can be obtained, and the new predicted parameter is taken as the predicted valley bottom voltage.

[0184] In this way, the predicted parameter and the first result corresponding to at least one code word under the predicted parameter as the read voltage are used to further obtain a new predicted parameter, which can improve the accuracy of the obtained predicted valley bottom voltage.

[0185] In some embodiments, the M reference read voltages are on the same side of the axis of symmetry of the curve of the quadratic function model, for example, the M reference read voltages are all on the first side of the axis of symmetry of the curve of the quadratic function model, or the M reference read voltages are all on the second side of the axis of symmetry of the curve of the quadratic function model.

[0186] In some embodiments, at least two of the M reference read voltages are on both sides of the symmetry axis of the curve of the quadratic function model. The points on both sides of the symmetry axis of the curve of the quadratic function model are more representative and can cover a wider range of data, thereby improving the accuracy and reliability of determining the predicted valley voltage from the reference read voltage.

[0187] In some embodiments, the memory cell array includes memory cells with a number of memory bits; the plurality of memory bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of orders; and the peripheral circuit is configured to determine the target valley voltage of the at least one code word at the target order, and then determine the target valley voltage of the other orders in the plurality of orders except the target order respectively.

[0188] For example, in the TLC, the target valley voltage of the third order read voltage L3 is obtained in a similar manner to that of the seventh order read voltage L7, and the target valley voltages of the seventh order read voltage L7 and the third order read voltage L3 can be used to read the data of the upper page of the at least one code word. The target valley voltages of the first order read voltage L1 and the fifth order read voltage L5 are obtained in a similar manner to that of the seventh order read voltage L7 to read the data of the lower page of the at least one code word. The target valley voltages of the second order read voltage L2, the fourth order read voltage L4 and the sixth order read voltage L6 are obtained in a similar manner to that of the seventh order read voltage L7 to read the data of the middle page of the at least one code word.

[0189] In some embodiments, the plurality of orders includes a first order and a second order, and the read voltage of the second order is lower than that of the first order; and the peripheral circuit is configured to, when the order corresponding to the determined target valley voltage belongs to the first order, obtain the predicted valley voltage of the second order and / or the predicted valley voltage of the remaining first order with lower read voltage according to the target valley voltage determined for the first order.

[0190] In some embodiments, at least one page corresponds to a plurality of order read voltages, and the plurality of order read voltages includes a first order read voltage and a second order read voltage, wherein the second order read voltage is lower than the first order read voltage. For example, the first order read voltage can be understood as the highest read voltage in the plurality of order read voltages of each page, and the second order read voltage can be understood as the other read voltages lower than the highest read voltage in the plurality of order read voltages of each page.

[0191] It should be noted that the first order and the second order are used to distinguish the high-level read voltage and the low-level read voltage in the multi-order read voltage corresponding to at least part of the page, and the low-level read voltage is smaller than the high-level read voltage. For a memory cell containing a plurality of storage bits, a page corresponding to one storage bit can include one order or multiple orders, and one order can include one level or multiple levels.

[0192] Exemplarily, referring to FIG. 8A, the memory device includes a lower page, an upper page, wherein the lower page corresponds to a multi-order, and the multi-order corresponding to the lower page includes a first level and a third level, and the first level read voltage L1 is smaller than the third level read voltage L3. Here, the third level read voltage L3 corresponds to the read voltage of the first order of the lower page (the high-level read voltage of the lower page), and the first level read voltage L1 corresponds to the read voltage of the second order of the lower page (the low-level read voltage of the lower page).

[0193] Exemplarily, referring to FIG. 8B, the memory device includes a lower page, a middle page and an upper page, wherein each page corresponds to a multi-order, the multi-order corresponding to the lower page includes a first level and a fifth level, the first level read voltage L1 is smaller than the fifth level read voltage L5, the multi-order corresponding to the middle page includes a second level, a fourth level and a sixth level, the second level read voltage L2 and the fourth level read voltage L4 are both smaller than the sixth level read voltage L6, and the multi-order corresponding to the upper page includes a third level and a seventh level, the third level read voltage L3 is smaller than the seventh level read voltage L7. Here, the fifth level read voltage L5, the sixth level read voltage L6 and the seventh level read voltage L7 correspond to the read voltage of the first order of the lower page, the middle page and the upper page respectively, and the first level read voltage L1, the second level read voltage L2 and the fourth level read voltage L4, the third level read voltage L3 correspond to the read voltage of the second order of the lower page, the middle page and the upper page respectively.

[0194] For example, referring to FIG. 8C, the memory device includes a lower page, a middle page, an upper page, and an extra page, each of which corresponds to multiple orders, the multiple orders corresponding to the lower page include the second order, the eighth order, and the fourteenth order, the second order read voltage L2 and the eighth order read voltage L8 are both less than the fourteenth order read voltage L14, the multiple orders corresponding to the middle page include the third order, the seventh order, the ninth order, and the thirteenth order, the third order read voltage L3, the seventh order read voltage L7, and the ninth order read voltage L9 are all less than the thirteenth order read voltage L13, the multiple orders corresponding to the upper page include the fifth order, the tenth order, the twelfth order, and the fifteenth order, the fifth order read voltage L5, the tenth order read voltage L10, and the twelfth order read voltage L12 are less than the fifteenth order read voltage L15, and the multiple orders corresponding to the extra page include the first order, the fourth order, the sixth order, and the eleventh order, the first order read voltage L1, the fourth order read voltage L4, and the sixth order read voltage L6 are less than the eleventh order read voltage L11. Here, the fourteenth order read voltage L14, the thirteenth order read voltage L13, the fifteenth order read voltage L15, and the eleventh order read voltage L11 correspond to the read voltages of the first order of the lower page, the middle page, the upper page, and the extra page, respectively, the second order read voltage L2 and the eighth order read voltage L8 correspond to the read voltages of the second order of the lower page, the third order read voltage L3, the seventh order read voltage L7, and the ninth order read voltage L9 correspond to the read voltages of the second order of the middle page, the fifth order read voltage L5, the tenth order read voltage L10, and the twelfth order read voltage L12 correspond to the read voltages of the second order of the upper page, and the first order read voltage L1, the fourth order read voltage L4, and the sixth order read voltage L6 correspond to the read voltages of the second order of the extra page.

[0195] The following provides an optional example of determining a target valley bottom voltage according to the first order of each page in a plurality of pages, obtaining a predicted valley bottom voltage of a second order in the plurality of orders and / or a predicted valley bottom voltage of a remaining first order with a lower read voltage.

[0196] In the embodiments of the present application, the predicted valley bottom voltage of a high order (first order) or the determined target valley bottom voltage can be used to obtain a predicted valley bottom voltage of a low order (second order) and a predicted valley bottom voltage of a remaining high order (first order). Specifically, the predicted valley bottom voltage of the high order (first order) or the determined target valley bottom voltage, the order number of the order to be predicted (second order and remaining first order with a lower read voltage), and a fourth mapping function can be used to obtain the predicted valley bottom voltage of the order to be predicted. Here, the fourth mapping function is related to the performance of the memory device (especially the threshold voltage shift performance of the memory cell), and the fourth mapping function can be fitted according to a large number of experimental results before the memory device is shipped and saved in the memory device.

[0197] It should be noted that the fourth mapping function does not support loop iteration.

[0198] In some embodiments, the peripheral circuit is configured to: obtain a preset threshold value according to a first result corresponding to the at least one code word at the target read voltage; the preset threshold value is used to represent a first result corresponding to a maximum value in a predicted effective valley voltage range; and determine the predicted valley voltage as the target valley voltage according to the first result corresponding to the predicted valley voltage being less than the preset threshold value.

[0199] In some specific embodiments, the preset threshold value is obtained according to a first result corresponding to the at least one code word at a first target read voltage; the first target read voltage can be set according to an empirical value (for example, a read voltage corresponding to successful reading of data); or can be a default value configured when the memory device is shipped after a large number of simulation experiments, which is obtained before the memory device is shipped after a large number of simulation experiments. The term "first result corresponding to the first target read voltage" in this application can be referred to as "first result".

[0200] The default read voltage can be a default value configured when the memory device is shipped after a large number of simulation experiments.

[0201] In some embodiments, the preset threshold value is positively correlated with the offset degree, and the offset degree is an absolute value of a difference between the first result and a default first result.

[0202] Here, the preset threshold value is used to represent a maximum value in a predicted effective valley voltage range. The preset threshold value can be determined according to the first result at the first target read voltage. It can be understood that when the read operation is performed, the further the threshold voltage of the storage unit deviates from the threshold voltage when written, the larger the first result read by the first target read voltage will generally be. Based on this, the specific value of the first result read by the first target read voltage can be used to confirm the preset threshold value, and the preset threshold value is used to represent the change (lifting) of the valley voltage caused by the threshold voltage deviation of the storage unit.

[0203] It should be noted that when the first result is less than the preset threshold value, it indicates that the target valley voltage can be directly determined next.

[0204] In some embodiments, when the first result is less than the preset threshold value, it indicates that the predicted valley voltage corresponding to the first result at this time can be taken as the target valley voltage.

[0205] [Corrected according to Rule 91 on 27.05.2024] Exemplarily, the greater the absolute value of the difference between the first first result and the default first result, the greater the preset threshold value. As the difference between the first first result Y11 and the default first result Y13 in FIG. 16A is less than the difference between the first first result Y11 and the default first result Y13 in FIG. 16B, the preset threshold value (Y12 shown in FIG. 16A) in FIG. 16A is less than the preset threshold value (Y12 shown in FIG. 16B) in FIG. 16B.

[0206] In some embodiments, the peripheral circuit is configured to: according to the first result corresponding to the predicted valley bottom voltage being less than the preset threshold value, take the predicted valley bottom voltage as the target valley bottom voltage. Exemplarily, as shown in FIG. 9, the peripheral circuit is configured to: according to the first result (Y1 shown in FIG. 9) corresponding to the predicted valley bottom voltage (V0 shown in FIG. 9) being less than the preset threshold value, take the predicted valley bottom voltage (V0 shown in FIG. 9) as the target valley bottom voltage.

[0207] In the first aspect, in each of the memory devices provided by the embodiments of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one code word (for example, the size of the code word can be 4 KB), and the amount of data transmitted is reduced; the process of obtaining the first result converges in the memory device, and does not occupy space of, for example, a memory controller, and the dependence on, for example, the memory controller is low; according to a limited number of reference read voltages and a limited number of first results in a first preset interval, the process of obtaining the target valley bottom voltage by combining the preset function model is completed in the memory device, since the first preset interval is a reasonable interval determined when fitting the preset function model, selecting data in the first preset interval to determine the target valley bottom voltage not only can improve the accuracy of determining the target valley bottom voltage, to a certain extent, but also reduces the influence of data noise, improves reliability, at the same time, can reduce the number of loop iterations, speeds up the speed of determining the target valley bottom voltage, and reduces the transmission time of the output port; and is suitable for MLC, TLC or QLC type memory devices.

[0208] FIG. 17 is a flow block diagram of an operation method of a memory device provided by an embodiment of the present application. The detailed process of determining the target valley bottom voltage will be described in detail below with reference to FIG. 17. It should be noted that here and below, the target valley bottom voltage refers to the voltage used to perform a read operation on the to-be-read data.

[0209] In step S101, the program of obtaining the target valley bottom voltage is triggered, and the process of obtaining the target valley bottom voltage is started to be executed. Next, step S102 is executed.

[0210] As mentioned above, according to the multi-bit of the storage unit, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage of each level of the at least one level read voltage corresponding to each page in the multiple pages is determined in sequence. In step S103, one level is selected from the multiple levels corresponding to one page as a target level, and the target valley voltage corresponding to the target level read voltage is determined first. For example, taking TLC as an example, the target valley voltage of the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page is determined first, and one of L1 or L5 can be selected as the target level. After the target level is determined, step S103 is performed.

[0211] In step S103, the type of the target level is mainly determined. Here, the target level can be divided into two categories, the first level (also referred to as the high level) and the second level (also referred to as the low level), wherein the read voltage of the first level is greater than the read voltage of the second level. For example, still taking the next page of TLC as an example, L5 is the first level and L1 is the second level. If L1 is selected as the target level in step S103, the target level is the second level, i.e. the low level; if L5 is selected as the target level in step S103, the target level is the first level, i.e. the high level. According to the low level of the target level, step S104 is performed; according to the high level of the target level, step S106 is performed.

[0212] In step S104, the predicted valley voltage is obtained, and the predicted valley voltage is obtained according to the target valley voltage corresponding to the high level and the fourth mapping function corresponding to the predicted valley voltage of the low level. Here and below, the fourth mapping function can be obtained by a large number of experimental results before the memory device is shipped, and is saved in the memory device. Next, step S105 is performed.

[0213] In step S105, it is determined whether the two-step prediction is successful. Here, the two-step prediction can include a first step prediction and a second step prediction. The first step prediction is to obtain a predicted valley bottom voltage of a high order, specifically, by obtaining the predicted valley bottom voltage of the high order according to a first result corresponding to the target read voltage, an order in which the high order is located, and a first mapping function. It should be noted that in some embodiments, the value of the first target read voltage is equal to the value of the default read voltage. The second step prediction is to obtain a predicted valley bottom voltage of a low order, specifically, by obtaining the predicted valley bottom voltage of the low order according to the predicted valley bottom voltage of the high order, an order in which the low order is located, and a fourth mapping function. After the two-step prediction, no confirmation of the predicted valley bottom voltage is performed, and the hard decoding is directly performed using the predicted valley bottom voltage of the high order and the predicted valley bottom voltage of the low order. If the hard decoding is successful, it indicates that the two-step prediction is successful, and the search for the target valley bottom voltage is directly stopped, and step S120 is performed. If the hard decoding fails, it indicates that the two-step prediction fails, and the point corresponding to the predicted valley bottom voltage is taken as the starting point of the subsequent iteration, and step S107 is continued.

[0214] If the target order is the high order, step S106 is performed, and the default read voltage is taken as the target read voltage. Here, the target read voltage can be used as the initial value of the subsequent search or loop. In some embodiments, the default read voltage can be the read voltage when the threshold voltage of the storage unit has not been shifted, such as the read voltage corresponding to the time of writing, and the corresponding shift value is 0 DAC. After step S106, step S107 is performed.

[0215] It should be noted that here and below, the conversion relationship between DAC and the aforementioned mv is 1 DAC = 10 mv.

[0216] For the process of performing the loop for the first time, in step S107, the first result under the target read voltage is obtained. It can be understood that for the process of performing the loop for the subsequent times, in step S107, the first result under the adjusted target read voltage is obtained. Step S108 is performed after step S107.

[0217] In step S108, it is determined whether the first result corresponding to the target read voltage is within a first preset interval. If the first result corresponding to the target read voltage is not within the first preset interval, step S109 is performed.

[0218] In step S109, it is judged whether the number of times that the first result corresponding to the target read voltage is out of the first preset interval is greater than or equal to the preset number of times. If the number of times that the first result corresponding to the target read voltage is out of the first preset interval is less than the preset number of times, step S111 is performed, the fitting read voltage is obtained according to the first parameter and the related mapping function (the first mapping function, the second mapping function or the third mapping function), and the fitting read voltage is taken as a new (adjusted) target read voltage, and step S107 is re-executed.

[0219] If the number of times that the first result corresponding to the target read voltage is out of the first preset interval is greater than or equal to the preset number of times, step S110 is performed, the value of the first parameter is adjusted, and the related mapping function (the first mapping function, the second mapping function or the third mapping function) is adjusted correspondingly. In some embodiments, when the number of times that the first result corresponding to the fitting read voltage on the first side obtained by the method in the foregoing embodiments is out of the first preset interval is greater than or equal to the preset number of times, it is indicated that a plurality of actual points have been obtained at this time, and according to the plurality of actual points obtained, the function relationship (1) of the quadratic function model and the second parameter (constant) are combined, so that the value of the adjusted first parameter can be obtained, and the value of the adjusted first parameter is substituted into the related mapping function, so that the related mapping function can be adjusted correspondingly.

[0220] After step S110, step S111 is performed, the fitting read voltage is obtained according to the adjusted first parameter and the adjusted related mapping function (the first mapping function, the second mapping function or the third mapping function), and the fitting read voltage is taken as a new (adjusted) target read voltage, and step S107 is re-executed.

[0221] In step S108, if the first result corresponding to the target read voltage is in the first preset interval, step S112 is performed, and the target read voltage is taken as a reference read voltage.

[0222] After step S112, step S113 is performed, and it is judged whether M reference read voltages have been obtained. If the M reference read voltages have not been obtained, step S107 is returned to until the M reference read voltages are obtained.

[0223] In step S113, if the M reference read voltages have been obtained, step S116 can be directly performed, the predicted valley bottom voltage is obtained according to the M reference read voltages and the M first results.

[0224] Meanwhile, if the M reference read voltages have been acquired, step S115 can also be performed first in step S113 to determine whether at least two reference read voltages are on two sides of the symmetry axis of the curve, and if the determination result of step S115 is yes, step S116 is performed, otherwise step S114 is performed. In step S114, the reference read voltages on the second side are acquired according to the reference read voltages on the first side and the corresponding first results, and the specific process can be referred to the related description of FIG. 15, which will not be repeated here.

[0225] After step S114, step S115 is re-executed.

[0226] It should be noted that the M reference read voltages are on the same side of the symmetry axis of the curve of the quadratic function model or at least two reference read voltages of the M reference read voltages are on two sides of the symmetry axis of the curve of the quadratic function model, and the predicted valley bottom voltage can be acquired.

[0227] Step S117 is performed after step S116, and the target valley bottom voltage is determined based on the predicted valley bottom voltage. Specifically, the predicted valley bottom voltage is taken as the target valley bottom voltage according to that the first result corresponding to the predicted valley bottom voltage is less than the preset threshold.

[0228] Step S118 is performed after step S117, and it is determined whether the target order is a high order. When the determination result of step S118 is no, step S120 is performed; when the determination result of step S118 is yes, step S119 is performed.

[0229] In step S119, the predicted valley bottom voltage of a low order is acquired according to the target valley bottom voltage / predicted valley bottom voltage of a high order. Here, the predicted valley bottom voltage of the low order can be acquired through the target valley bottom voltage / predicted valley bottom voltage of the high order, the order number of the low order and the related mapping function (such as the fourth mapping function described above). Step S120 is performed after step S119.

[0230] In step S120, it is determined whether all the order read voltages contained in the page have determined the corresponding target valley bottom voltage. When the determination result of step S120 is yes, it means that the target valley bottom voltages corresponding to all the order read voltages contained in the page have been determined, and at this time step S122 can be performed; when the determination result of step S120 is no, it means that there is an undetermined order for the target valley bottom voltage corresponding to the order read voltage contained in the page, and at this time step S121 is performed.

[0231] In step S121, for the order whose target valley bottom voltage is not determined, the target valley bottom voltage of each order is determined in turn. Step S121 jumps to step S102.

[0232] In step S122, the procedure of obtaining the target valley voltage is ended. It should be noted that after step S122, the determination of the target valley voltage corresponding to the read voltage of the next page can be started.

[0233] It should be noted that the execution subject of the specific implementation process of each step in FIG. 17 can be a peripheral circuit or a memory controller.

[0234] In a second aspect, the embodiments of the present application provide a memory system, as shown in FIG. 18 and FIG. 19, the memory system 102 includes one or more memory devices 104 provided in the first aspect, and a memory controller 106 coupled with the memory device 104 and controlling the memory device 104.

[0235] As shown in FIG. 18, in some specific embodiments, the memory system 102 is coupled with a host, and performs various feedbacks in response to instructions of the host. The memory system 102 can include a memory controller 106 and a memory device 104, the memory controller 106 is used to control the memory device 104 to perform read, write, erase and other operations, and the memory controller 106 can also be coupled with the memory device 104 in any suitable manner.

[0236] The memory controller 106 can include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, a data buffer 1067, and a bus 1060. The host interface 1061 is a connection interface between the host 108 and the memory controller 106, and allows the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104, and is used to implement data transmission between the memory controller 106 and the memory device 104. The control unit 1063 is used to control the memory system 106 as a whole, and the specific steps performed by the memory controller described above are mainly performed and completed by the control unit 1063 here. In some embodiments, the control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MCU), or the like. The ROM 1069 generally contains firmware or firmware program code of the memory controller 106, which is used to initialize and operate the components of the memory controller, and the RAM 1070 is generally used to cache data. The error correction module 1064 can further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain check data, and the decoding unit is used to decode the check data to detect and correct possible error data during data transmission.

[0237] The garbage collection module 1065 is used to read out valid data on some storage blocks, rewrite them, and then mark the storage blocks to obtain new spare storage blocks after the storage space of the memory device reaches a certain threshold. The general implementation of garbage collection can be divided into three steps: selecting a source storage block with less valid data; finding valid data from the source storage block; and writing the valid data to a target storage block. At this time, all data in the source storage block become invalid data, and the source storage block is marked and can be used as a new spare storage block. The wear leveling module 1066 is used to keep the wear (number of erasures) of each storage block in the memory system balanced through data statistics and algorithms. The general implementation of wear leveling can be divided into two steps: selecting a source storage block where cold data is located; and reading valid data on the source storage block and writing it to a storage block with a relatively large number of erasures, at which time the valid data in the source storage block becomes invalid data and is marked. The buffer 1067 is used to cache data.

[0238] In some embodiments, the memory controller 106 is configured to control the memory device 104 to perform a read operation on the at least one codeword.

[0239] In some embodiments, the memory device 104 comprises: a memory cell array comprising a plurality of memory cells, a preset number of memory cells forming a codeword; a peripheral circuit of the memory device 104 coupled to the memory cell array and configured to: obtain M first results corresponding to the at least one codeword under M reference read voltages; the first result comprises a number of bits representing a flipping in the first read voltage and the second read voltage twice reading results of the at least one codeword; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; according to the M first results and the M reference read voltages, a preset function model is combined to obtain a predicted valley bottom voltage; the preset function model represents the relationship between the first result and the reference read voltage; the M first results are all within a first preset interval; and determine a target valley bottom voltage based on the predicted valley bottom voltage; the target valley bottom voltage is used as a read voltage when performing a read operation on the at least one codeword.

[0240] In some embodiments, the preset function model comprises a quadratic function model, and the quadratic function model comprises the following function relationship: y = a(x + b) 2 +c

[0241] Wherein, y is the first result, x is the reference read voltage, b is used to represent the prediction parameter, a is the first parameter, and c is the second parameter.

[0242] In some embodiments, the first preset interval represents a range between a first threshold and a second threshold of the curve of the quadratic function model; the first threshold is greater than the second threshold.

[0243] In some embodiments, the first parameter and the second parameter are both constants; the peripheral circuit of the memory device 104 is configured to: obtain a first result corresponding to the at least one codeword under a target read voltage; and according to the first result corresponding to the at least one codeword under the target read voltage being within the first preset interval, take the target read voltage as a reference read voltage; according to the first result corresponding to the at least one codeword under the target read voltage being outside the first preset interval, re-obtain at least one new target read voltage, obtain a first result corresponding to the at least one new target read voltage, until the first result corresponding to the latest target read voltage is within the first preset interval.

[0244] In some embodiments, at least two of the M reference read voltages are on two sides of a symmetry axis of the curve of the quadratic function model; the peripheral circuit of the memory device 104 is configured to: when obtaining the reference read voltages, obtain a reference read voltage on a first side of the two sides of the symmetry axis of the curve of the quadratic function model; and determine a reference read voltage on a second side of the two sides of the symmetry axis according to the reference read voltage on the first side.

[0245] In some embodiments, the peripheral circuit of the memory device 104 is configured to: when the first result corresponding to the target read voltage is outside the first preset interval, obtain a fitting read voltage on the first side corresponding to the target first result based on the target read voltage, the first result corresponding to the target read voltage, the target first result, and the first mapping function; the first mapping function is obtained according to the quadratic function model, the first parameter, and the second parameter; the target first result is within the second preset interval, and the first preset interval is within the range of the second preset interval; obtain the first result corresponding to the at least one code word under the fitting read voltage on the first side; and when the first result corresponding to the fitting read voltage on the first side is within the first preset interval, take the fitting read voltage on the first side as a reference read voltage on the first side; when the first result corresponding to the fitting read voltage on the first side is outside the first preset interval, obtain the next fitting read voltage on the first side corresponding to the target first result based on the last fitting read voltage on the first side, the first result corresponding to the last fitting read voltage on the first side, the target first result, and the first mapping function, until the first result corresponding to the latest fitting read voltage on the first side is within the first preset interval, and take the latest fitting read voltage on the first side as a reference read voltage on the first side.

[0246] In some embodiments, the peripheral circuit of the memory device 104 is configured to: when the number of times that the first result corresponding to the latest fitting read voltage on the first side is outside the first preset interval is greater than or equal to a preset number of times, adjust the value of the first parameter and correspondingly adjust the first mapping function; obtain the next adjusted fitting read voltage on the first side corresponding to the target first result based on the last fitting read voltage on the first side, the first result corresponding to the last fitting read voltage on the first side, the target first result, and the adjusted first mapping function, until the first result corresponding to the latest adjusted fitting read voltage on the first side is within the first preset interval.

[0247] In some embodiments, the peripheral circuit of the memory device 104 is configured to: obtain a fitting read voltage at the second side corresponding to the target first result based on one reference read voltage at the first side, a corresponding first result at the one reference read voltage at the first side, the target first result, and a second mapping function, the second mapping function being derived from a quadratic function model, the first parameter / adjusted first parameter, and the second parameter; obtain the first result of the at least one codeword at the fitting read voltage at the second side; and determine the fitting read voltage at the second side as one reference read voltage at the second side based on the first result at the fitting read voltage at the second side being within a preset interval.

[0248] In some embodiments, the peripheral circuit of the memory device 104 is configured to: obtain a next fitting read voltage at the second side corresponding to the target first result based on a last fitting read voltage at the second side, a corresponding first result at the last fitting read voltage at the second side, the target first result, and a third mapping function, until the first result at the latest fitting read voltage at the second side is within the first preset interval, and determine the latest fitting read voltage at the second side as one reference read voltage at the second side, based on the first result at the fitting read voltage at the second side being outside the preset interval.

[0249] In some embodiments, the first parameter is a variable and the second parameter is a constant, and the peripheral circuit of the memory device 104 is configured to: obtain a predicted parameter based on the M first results and the M reference read voltages in combination with the quadratic function model; and determine the predicted parameter as the predicted valley voltage.

[0250] In some embodiments, the first parameter and the second parameter are both variables, and the peripheral circuit is configured to: obtain a predicted parameter based on the M first results and the M reference read voltages in combination with the quadratic function model; determine the predicted parameter as the target read voltage; obtain the first result of the at least one codeword at the target read voltage of the predicted parameter; obtain a new predicted parameter based on the M first results, the M reference read voltages, the predicted parameter, and the first result at the target read voltage of the predicted parameter in combination with the quadratic function model; and determine the new predicted parameter as the predicted valley voltage.

[0251] In some embodiments, the memory cell array includes memory cells with a plurality of bits per cell, the plurality of bits per cell corresponding to a plurality of pages, and at least one page corresponding to a plurality of levels, and the peripheral circuit of the memory device 104 is configured to: determine the target valley voltage of the at least one codeword at the target level, and determine the target valley voltage of at least one level other than the target level in the plurality of levels.

[0252] In some embodiments, the multiple levels include a first level and a second level, and the read voltage of the second level is lower than the read voltage of the first level; the peripheral circuit of the memory device 104 is configured to: when the determined target valley voltage corresponds to the first level, obtain, according to the target valley voltage determined for the first level, a predicted valley voltage of the second level and / or a predicted valley voltage of the remaining first levels with lower read voltages.

[0253] In some embodiments, the peripheral circuit of the memory device 104 is configured to: obtain a preset threshold according to the first result corresponding to the target read voltage of the at least one codeword; the preset threshold is used to represent the first result corresponding to the maximum value in the effective range of the predicted valley voltage; and determine the predicted valley voltage as the target valley voltage according to that the first result corresponding to the predicted valley voltage is less than the preset threshold.

[0254] In some embodiments, the peripheral circuit of the memory device 104 is configured to: obtain a second result by reading the stored data of the at least one codeword at a first read voltage; obtain a third result by reading the stored data of the at least one codeword at a second read voltage; perform a logical operation on the second result and the third result to obtain a fourth result; and obtain the first result by counting the number of bits in the fourth result representing the flipping of the third result relative to the second result.

[0255] In some embodiments, the peripheral circuit of the memory device 104 includes: a first latch, a second latch, and a third latch; the first latch is configured to store the second result; the second latch is configured to store the third result; and the third latch is configured to store the fourth result.

[0256] As shown in FIG. 19, in some embodiments, the memory controller 106 is configured to send a data acquisition instruction, the data acquisition instruction indicating to acquire a target valley voltage; the memory device 104 is configured to receive the data acquisition instruction, acquire the target valley voltage, and send information including the target valley voltage to the memory controller; and the memory controller 106 is further configured to perform a read operation on the data stored in the memory device according to the target valley voltage in the information.

[0257] In some embodiments, the memory controller 106 is further configured to perform an error correction code decoding operation on the read result of the read operation. In some implementations, the error correction code decoding operation includes a hard decoding operation using a low density parity check code (LDPC).

[0258] In some embodiments, the memory controller 106 is configured to send a mode setting command, the mode setting command indicating to set a read mode of the memory device to a single-level read mode; the single-level read mode comprising reading at least one bit of stored data stored in the memory cell by a one-level read voltage; the memory device 104 is configured to enter the single-level read mode in response to the mode setting command, and obtain, in the single-level read mode, the first result corresponding to the at least one codeword at the target read voltage.

[0259] In the second aspect, the memory system provided by the embodiments of the present application transmits the first result (the size of the first result can be several bytes) instead of the at least one codeword (for example, the size of the codeword can be 4 KB), thereby reducing the amount of data transmitted between the memory device and the memory controller; the process of obtaining the first result converges in the memory device, thereby not occupying the space of the memory controller and reducing the dependence on the memory controller; the process of obtaining the target valley voltage in the memory device according to a limited number of reference read voltages and a limited number of first results in the first preset interval in combination with the preset function model reduces the transmission time of the input and output ports of the memory device and / or the time of the error correction decoding operation of the memory controller, saves the iteration time of the error correction decoding algorithm of the memory controller, and makes the error correction decoding faster; and is suitable for the memory system of the MLC, TLC or QLC type.

[0260] In the third aspect, the embodiments of the present application provide a memory controller coupled with at least one memory device, the memory device comprising a plurality of memory cells, a preset number of memory cells forming a codeword; the memory controller comprising: a control unit configured to: obtain M first results corresponding to the at least one codeword at M reference read voltages; the first result comprising the number of bits representing the flipping in the two reading results of the at least one codeword at a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage being less than a preset voltage; M being an integer greater than or equal to 2; obtaining a predicted valley voltage according to the M first results and the M reference read voltages in combination with a preset function model; the preset function model representing the relationship between the first result and the reference read voltage; the M first results being all in a first preset interval; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage being used as a read voltage for performing a read operation on the at least one codeword.

[0261] In some specific embodiments, the first preset interval represents the numerical interval of the first result corresponding to the preset region of the curve of the preset function model.

[0262] In some embodiments, the control unit is configured to: obtain the first result corresponding to the at least one code word at the target read voltage; and take the target read voltage as a reference read voltage and take the first result in the first preset interval as the first result corresponding to the reference read voltage, according to that the first result corresponding to the at least one code word at the target read voltage is in the first preset interval.

[0263] In some embodiments, the control unit is configured to: obtain the prediction parameter of the preset function model according to the M first results and the M reference read voltages in combination with the preset function model, the prediction parameter being the reference read voltage corresponding to the minimum first result on the curve of the preset function model; and obtain the predicted valley bottom voltage according to the prediction parameter.

[0264] In some embodiments, the preset function model comprises a quadratic function model, the quadratic function model comprising the following function relationship: y = a(x + b) 2 + c

[0265] wherein y is the first result, x is the reference read voltage, b is used to represent the prediction parameter, a is a first parameter, and c is a second parameter.

[0266] In some embodiments, the first preset interval represents a range between a first threshold value and a second threshold value of the curve of the quadratic function model; the first threshold value is greater than the second threshold value.

[0267] In some embodiments, the first parameter and the second parameter are both constants; the control unit is configured to: obtain the first result corresponding to the at least one code word at the target read voltage; and take the target read voltage as a reference read voltage, according to that the first result corresponding to the at least one code word at the target read voltage is in the preset interval; and re-obtain at least one new target read voltage, obtain the first result corresponding to the at least one new target read voltage, according to that the first result corresponding to the at least one code word at the target read voltage is out of the first preset interval.

[0268] In some embodiments, at least two reference read voltages of the M reference read voltages are on two sides of a symmetry axis of the curve of the quadratic function model; the control unit is configured to: obtain the reference read voltage on a first side of the two sides of the symmetry axis of the curve of the quadratic function model, when obtaining the reference read voltage; and determine the reference read voltage on a second side of the two sides of the symmetry axis, according to the reference read voltage on the first side.

[0269] In some embodiments, the control unit is configured to: obtain a fitting read voltage on the first side corresponding to the target first result based on the target read voltage, the first result corresponding to the target read voltage, the target first result, and the first mapping function, the first mapping function being obtained according to the quadratic function model, the first parameter, and the second parameter; obtain the first result corresponding to the at least one code word at the fitting read voltage on the first side; and take the fitting read voltage on the first side as a reference read voltage on the first side according to the first result corresponding to the fitting read voltage on the first side being within the first preset interval; obtain a next fitting read voltage on the first side corresponding to the target first result based on the last fitting read voltage on the first side, the first result corresponding to the last fitting read voltage on the first side, the target first result, and the first mapping function, until the first result corresponding to the latest fitting read voltage on the first side is within the first preset interval, and take the latest fitting read voltage on the first side as a reference read voltage on the first side according to the first result corresponding to the fitting read voltage on the first side being outside the first preset interval.

[0270] In some embodiments, the control unit is configured to: adjust the value of the first parameter and correspondingly adjust the first mapping function according to the number of times that the first result corresponding to the latest fitting read voltage on the first side is outside the first preset interval being greater than or equal to a preset number; obtain a next fitting read voltage on the first side corresponding to the target first result based on the last fitting read voltage on the first side, the first result corresponding to the last fitting read voltage on the first side, the target first result, and the adjusted first mapping function, until the first result corresponding to the latest fitting read voltage on the first side is within the first preset interval.

[0271] In some embodiments, the control unit is configured to: obtain a fitting read voltage on the first side corresponding to the target first result based on the target read voltage, the first result corresponding to the target read voltage, the target first result, and the first mapping function, the first mapping function being obtained according to the quadratic function model, the first parameter, and the second parameter; obtain the first result corresponding to the at least one code word at the fitting read voltage on the first side; and take the fitting read voltage on the first side as a reference read voltage on the first side according to the first result corresponding to the fitting read voltage on the first side being within the first preset interval; obtain a next fitting read voltage on the first side corresponding to the target first result based on the last fitting read voltage on the first side, the first result corresponding to the last fitting read voltage on the first side, the target first result, and the first mapping function, until the first result corresponding to the latest fitting read voltage on the first side is within the first preset interval, and take the latest fitting read voltage on the first side as a reference read voltage on the first side according to the first result corresponding to the fitting read voltage on the first side being outside the first preset interval.

[0272] In some embodiments, the control unit is configured to: based on the corresponding first result at the fitting read voltage on the second side being outside the preset interval, obtain a next fitting read voltage on the second side corresponding to the target first result based on the last fitting read voltage on the second side, the corresponding first result at the last fitting read voltage on the second side, the target first result, and a third mapping function, until the corresponding first result at the latest fitting read voltage on the second side is within the first preset interval, and take the latest fitting read voltage on the second side as a reference read voltage on the second side; and the third mapping function is obtained based on a quadratic function model, the first parameter / adjusted first parameter, and the second parameter.

[0273] In some embodiments, the first parameter is a variable and the second parameter is a constant; and the control unit is configured to: obtain a prediction parameter based on the M first results and the M reference read voltages in combination with the quadratic function model; and take the prediction parameter as the predicted valley bottom voltage.

[0274] In some embodiments, the first parameter and the second parameter are both variables; and the control unit is configured to: obtain a prediction parameter based on the M first results and the M reference read voltages in combination with the quadratic function model; take the prediction parameter as the target read voltage, and obtain the corresponding first result of the at least one code word at the target read voltage of the prediction parameter; obtain a new prediction parameter based on the M first results, the M reference read voltages, the prediction parameter, and the corresponding first result at the target read voltage of the prediction parameter in combination with the quadratic function model; and take the new prediction parameter as the predicted valley bottom voltage.

[0275] In some embodiments, the memory cell array includes memory cells with a plurality of memory bits; the plurality of memory bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of levels; and the control unit is configured to: after determining the target valley bottom voltage of the at least one code word at the target level, determine the target valley bottom voltage of each level other than the target level in the plurality of levels respectively.

[0276] In some embodiments, the plurality of levels includes a first level and a second level, and the read voltage of the second level is lower than that of the first level; and the control unit is configured to: when the determined target valley bottom voltage corresponds to a level belonging to the first level, obtain the predicted valley bottom voltage of the second level and / or the predicted valley bottom voltage of the remaining first level with lower read voltage in the plurality of levels based on the determined target valley bottom voltage of the first level.

[0277] In some embodiments, the control unit is configured to: obtain a preset threshold based on the corresponding first result of the at least one code word at the target read voltage; the preset threshold is used to represent the corresponding first result of the maximum value in the effective range of the predicted valley bottom voltage; and take the predicted valley bottom voltage as the target valley bottom voltage based on the corresponding first result of the predicted valley bottom voltage being less than the preset threshold.

[0278] In some embodiments, the data amount of the first result is less than a preset data amount threshold. Illustratively, the data amount of the first result ranges from 1 byte to 4 bytes, and thus the data amount transmitted between the memory device and the memory controller in the process of determining the target valley voltage is small and fast, which is conducive to improving the overall speed of the read operation.

[0279] Here, the control unit can be understood in combination with the control unit shown in FIG. 18. It should be noted that in this embodiment of the present application, the execution subject is replaced by the control unit in the memory controller from the peripheral circuit. That is, in this embodiment of the present application, the memory device acquires M reference read voltages and M first results; and the control unit analyzes and processes the M reference read voltages and the M first results, and determines the target valley voltage according to the analysis and processing.

[0280] In the third aspect, the memory controller provided by the embodiments of the present application, the first result (the size of the first result can be several bytes) is transmitted between the memory device and the memory controller without transmitting at least one code word (for example, the size of the code word can be 4 KB), and thus the data amount transmitted between the memory device and the memory controller is reduced; the process of obtaining the first result converges in the memory device, and does not occupy the space of the memory controller, and thus the dependence on the memory controller is low; compared with the memory device, the efficiency and accuracy of the process of obtaining the target valley voltage according to a limited number of reference read voltages and a limited number of first results in a first preset interval in the memory controller, in combination with a preset function model, are higher, the transmission time of the input and output port of the memory device and / or the time of the error correction decoding operation of the memory controller is reduced, the iteration time of the error correction decoding algorithm of the memory controller is saved, and the speed of the error correction decoding is faster; and the memory controller is suitable for MLC, TLC or QLC type memory systems.

[0281] In the fourth aspect, the embodiments of the present application provide an operation method of a memory device, the memory device comprising a plurality of storage units, and a preset number of storage units forming a code word; the operation method comprising: acquiring M first results corresponding to at least one code word under M reference read voltages; the first result comprising the number of bits representing the flipping in the twice reading results of the at least one code word under a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage being less than a preset voltage; M being an integer greater than or equal to 2; acquiring a predicted valley voltage according to the M first results and the M reference read voltages in combination with a quadratic function model; the preset function model representing the relationship between the first result and the reference read voltage; the M first results being all in a first preset interval; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage being used as a read voltage for the at least one code word in the execution of a read operation.

[0282] In some embodiments, the first preset interval represents a numerical interval of the first result corresponding to a preset region of the curve where the preset function model is located.

[0283] In some embodiments, the operation method of the memory device includes: obtaining a first result corresponding to at least one code word under a target read voltage; and according to the first result corresponding to the at least one code word under the target read voltage being within a first preset interval, taking the target read voltage as a reference read voltage, and taking the first result within the first preset interval as a first result corresponding to the reference read voltage.

[0284] In some embodiments, the operation method of the memory device includes: obtaining a first result corresponding to at least one code word under a target read voltage; and according to the first result corresponding to the at least one code word under the target read voltage being within a first preset interval, taking the target read voltage as a reference read voltage, and taking the first result within the first preset interval as a first result corresponding to the reference read voltage.

[0285] In some embodiments, the preset function model includes a quadratic function model, and the quadratic function model includes the following function relationship: y=a(x+b) 2 +c

[0286] Wherein, y is the first result, x is the reference read voltage, b is used to represent the prediction parameter, a is the first parameter, and c is the second parameter.

[0287] In some embodiments, the first preset interval represents a range between a first threshold and a second threshold of the curve where the quadratic function model is located; the first threshold is greater than the second threshold.

[0288] In some embodiments, the first parameter and the second parameter are both constants; the operation method of the memory device includes: obtaining a first result corresponding to at least one code word under a target read voltage; and according to the first result corresponding to the at least one code word under the target read voltage being within a first preset interval, taking the target read voltage as a reference read voltage; according to the first result corresponding to the at least one code word under the target read voltage being outside the first preset interval, re-obtaining at least one new target read voltage, obtaining a first result corresponding to the at least one new target read voltage, until the first result corresponding to the latest target read voltage is within the first preset interval.

[0289] In some embodiments, at least two of the M reference read voltages are on two sides of a symmetry axis of the curve of the quadratic function model; the method for operating the memory device includes: when the reference read voltages are obtained, obtaining a reference read voltage on a first side of the two sides of the symmetry axis of the curve of the quadratic function model; and determining a reference read voltage on a second side of the two sides of the symmetry axis according to the reference read voltage on the first side.

[0290] In some embodiments, the method for operating the memory device includes: according to the first result corresponding to the target read voltage of the at least one codeword being outside the first preset interval, obtaining a fitting read voltage on the first side corresponding to the target first result based on the target read voltage, the first result corresponding to the target read voltage, the target first result, and the first mapping function; the first mapping function is obtained according to the quadratic function model, the first parameter, and the second parameter; the target first result is within the second preset interval, and the first preset interval is within the range of the second preset interval; obtaining the first result corresponding to the at least one codeword under the fitting read voltage on the first side; and according to the first result corresponding to the fitting read voltage on the first side being within the first preset interval, taking the fitting read voltage on the first side as one of the reference read voltages on the first side; according to the first result corresponding to the fitting read voltage on the first side being outside the first preset interval, obtaining the next fitting read voltage on the first side corresponding to the target first result based on the last fitting read voltage on the first side, the first result corresponding to the last fitting read voltage on the first side, the target first result, and the first mapping function, until the first result corresponding to the latest fitting read voltage on the first side is within the first preset interval, and taking the latest fitting read voltage on the first side as one of the reference read voltages on the first side.

[0291] In some embodiments, the method for operating the memory device includes: according to the number of times that the first result corresponding to the latest fitting read voltage on the first side is outside the first preset interval being greater than or equal to a preset number of times, adjusting the value of the first parameter and correspondingly adjusting the first mapping function; obtaining the next adjusted fitting read voltage on the first side corresponding to the target first result based on the last fitting read voltage on the first side, the first result corresponding to the last fitting read voltage on the first side, the target first result, and the adjusted first mapping function, until the first result corresponding to the latest adjusted fitting read voltage on the first side is within the first preset interval.

[0292] In some embodiments, the operation method of the memory device includes: obtaining a fitting read voltage at the second side corresponding to a target first result based on a reference read voltage at the first side, a corresponding first result at the reference read voltage at the first side, the target first result, and a second mapping function; the second mapping function is obtained according to a quadratic function model, a first parameter / adjusted first parameter, and a second parameter; obtaining a first result corresponding to at least one codeword at the fitting read voltage at the second side; and taking the fitting read voltage at the second side as a reference read voltage at the second side according to that the first result corresponding to the fitting read voltage at the second side is within a preset interval.

[0293] In some embodiments, the operation method of the memory device includes: obtaining a next fitting read voltage at the second side corresponding to a target first result based on a last fitting read voltage at the second side, a first result corresponding to the last fitting read voltage at the second side, the target first result, and a third mapping function according to that the first result corresponding to the fitting read voltage at the second side is not within a preset interval, until the first result corresponding to the latest fitting read voltage at the second side is within a first preset interval, and taking the latest fitting read voltage at the second side as a reference read voltage at the second side; the third mapping function is obtained according to a quadratic function model, a first parameter / adjusted first parameter, and a second parameter.

[0294] In some embodiments, the first parameter is a variable and the second parameter is a constant; the operation method of the memory device includes: obtaining a predicted parameter according to M first results and M reference read voltages in combination with a quadratic function model; and taking the predicted parameter as a predicted valley voltage.

[0295] In some embodiments, the first parameter and the second parameter are both variables; the operation method of the memory device includes: obtaining a predicted parameter according to M first results and M reference read voltages in combination with a quadratic function model; taking the predicted parameter as a target read voltage, obtaining a first result corresponding to at least one codeword at the target read voltage with the predicted parameter; obtaining a new predicted parameter according to the M first results, the M reference read voltages, the predicted parameter, and the first result corresponding to the target read voltage with the predicted parameter in combination with the quadratic function model; and taking the new predicted parameter as a predicted valley voltage.

[0296] In some embodiments, the memory cell array includes memory cells with a plurality of storage bits; the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of levels; and the operation method of the memory device includes: after determining a target valley voltage of at least one codeword at a target level, determining target valley voltages of other levels except the target level in the plurality of levels respectively.

[0297] In some embodiments, the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; the operation method of the memory device includes: when the stage corresponding to the determined target valley voltage belongs to the first stage, obtaining, according to the target valley voltage determined for the first stage, a predicted valley voltage of the second stage and / or a predicted valley voltage of the remaining first stages with lower read voltages.

[0298] In some embodiments, the operation method of the memory device includes: obtaining a preset threshold according to the first result corresponding to at least one codeword at the target read voltage; the preset threshold is used to represent the first result corresponding to the maximum value in the effective range of the predicted valley voltage; and taking the predicted valley voltage as the target valley voltage according to the first result corresponding to the predicted valley voltage being less than the preset threshold.

[0299] It should be noted that the execution subject in the operation method of the memory device can be a peripheral circuit or a memory controller.

[0300] In a fifth aspect, an embodiment of the present application provides an operation method of a memory system. A memory controller in the memory system sends a data acquisition instruction, and the data acquisition instruction indicates to acquire a target valley voltage. A memory device in the memory system receives the data acquisition instruction, acquires the target valley voltage according to the operation method of the memory device of the fourth aspect, and sends information including the target valley voltage to the memory controller. The memory controller performs a read operation on data stored in the memory device according to the target valley voltage in the information.

[0301] In some specific embodiments, the memory device in the memory system includes a plurality of storage units, and a preset number of storage units form a codeword. The operation method of the memory system includes: obtaining M first results corresponding to at least one codeword at M reference read voltages; the first result includes a number of bits that flip in two read results of the at least one codeword at a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; obtaining a predicted valley voltage according to the M first results and the M reference read voltages in combination with a quadratic function model; the preset function model represents the relationship between the first result and the reference read voltage; the M first results are all within a first preset interval; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage is used as a read voltage when performing a read operation on the at least one codeword.

[0302] In a sixth aspect, an operation method of a memory controller is provided. The memory controller is coupled to at least one memory device. The memory device includes a plurality of memory cells. A preset number of memory cells form a code word. The operation method of the memory controller includes: obtaining M first results corresponding to at least one code word under M reference read voltages; the first results include a number of bits that flip in two read results of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; obtaining a predicted valley voltage according to the M first results, the M reference read voltages, and a quadratic function model; the preset function model represents a relationship between the first results and the reference read voltages; the M first results are all in a first preset interval; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage is used as a read voltage for performing a read operation on the at least one code word.

[0303] FIG. 20 is a timing diagram of an exemplary operation of starting a single-level read mode according to an embodiment of the present application. DQx can represent a data bus signal, and Cycle Type can further represent a type of the data bus signal.

[0304] As shown in FIG. 20, a set function command can include, for example, one subcommand (e.g., EFh). Exemplarily, the memory device starts the single-level read mode in response to receiving the subcommand EFh. In the single-level read mode, the memory device transmits an address ADDR (e.g., two column addresses C1-C2 and three row addresses R1-R3) of data to be read between receiving subcommands 00h and 30h. In a read time, corresponding data DATA (e.g., Dn) in a page of the received address can be buffered in a page buffer first, and then the data DATA can be read on demand. It should be noted that the above embodiment needs to frequently transmit (Din / Dout) data (e.g., Dn) corresponding to one physical page between the memory device and the memory controller when performing a re-read operation, which consumes a relatively long time.

[0305] FIG. 21 is a timing diagram of determining a target valley voltage and performing a read operation according to an embodiment of the present application. As shown in FIG. 21, a read command can include, for example, two subcommands (e.g., 00h and 30h). Exemplarily, the memory device transmits an address ADDR (e.g., two column addresses C1-C2 and three row addresses R1-R3) of data to be read between receiving subcommands 00h and 30h. After the memory device receives the subcommand 30h, in a read time, corresponding data DATA (e.g., Dn) in a page of the received address can be buffered in a page buffer first, and then the data DATA can be read on demand.

[0306] In the example embodiment, the memory device 104 transmits the address ADDR (e.g., two column addresses C1-C2 and three row addresses R1-R3) of the data to be read between the received sub-commands 00h and 30h. After the memory device 104 receives the sub-command 30h, the memory device 104 receives the sub-commands EFh and xxh of the data acquisition instruction, and acquires M first results corresponding to the M reference read voltages of the codeword under the indication of the data acquisition instruction, and transmits the M reference read voltages and the M first results to the memory controller. The memory controller determines the target valley voltage according to the preset function model in combination with the M reference read voltages and the M first results received from the memory device, and performs a read operation on the data stored in the memory device according to the target valley voltage.

[0307] It should be noted that the data acquisition instruction provided in the embodiments of the present application is only an example, and should not be overly limited to the protection scope of the present application.

[0308] In some embodiments, the data amount of the first result is less than a preset data amount threshold, for example, the data amount of the first result ranges from 1 byte to 4 bytes, so that the data amount transmitted between the memory device and the memory controller in the process of determining the target valley voltage is small and fast, which is beneficial to improve the overall speed of the read operation.

[0309] The embodiments of the present application also provide a storage medium, and the storage medium stores executable instructions. When the executable instructions are executed, the steps of the operation method in the above embodiments of the present application can be implemented.

[0310] In some specific embodiments, the storage medium can be a ferromagnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc. The storage medium can also be various devices including one or any combination of the above storage devices.

[0311] In some embodiments, the executable instructions can take the form of programs, software, software modules, scripts, or code, written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and they can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0312] By way of example, an executable instruction can, but need not, correspond to a file in a file system. An executable instruction can be stored in one or more files, in a single file dedicated to the program in question, in a single file storing a plurality of programs, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or code portions).

[0313] By way of example, an executable instruction can be deployed to be executed on one electronic device or on multiple electronic devices that are located at one site, or that are distributed across multiple sites and that are interconnected through a communication network.

[0314] In some specific embodiments, referring to FIG. 22, which is a schematic diagram of a storage medium according to an embodiment of the present application; the storage medium includes a first storage medium corresponding to the memory device 104, a second storage medium corresponding to the memory controller 104, and a third storage medium corresponding to the memory system 102; when the executable instructions are executed by the memory device, the first storage medium can be used to implement the steps of the operation method of the memory device described in the above embodiments of the present application; when the executable instructions are executed by the memory controller, the second storage medium can be used to implement the steps of the operation method of the memory controller described in the above embodiments of the present application; when the executable instructions are executed by the memory system, the third storage medium can be used to implement the steps of the operation method of the memory system described in the above embodiments of the present application.

[0315] It should be understood that the term "in one embodiment" or "in an embodiment" as used throughout this specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the application. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the above-mentioned processes is not meant to limit the execution order, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the application. The above-mentioned sequence of the embodiments of the application is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0316] The preferred embodiments of the present application are described above with the aid of drawings, and are not intended to limit the patent scope of the present application. Any equivalent structure variations made according to the content of the specification and drawings of the present application, or direct / indirect application in other related technical fields, are included in the patent protection scope of the present application.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cells, a preset number of the memory cells forming a code word; a peripheral circuit coupled to the memory cell array and configured to: obtain M first results corresponding to at least one code word under M reference read voltages; the first results comprising a number of bits representing a flipping in two reading results of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage being less than a preset voltage; the M being an integer greater than or equal to 2; obtain a predicted valley voltage based on the M first results, the M reference read voltages, and a preset function model; the preset function model representing a relationship between the first results and the reference read voltages; the M first results being within a first preset interval; and determine a target valley voltage based on the predicted valley voltage; the target valley voltage being used as a read voltage for the at least one code word when performing a read operation. the first preset interval representing a numerical interval of the first results corresponding to a preset region of a curve of the preset function model.

2. The memory device of claim 1, wherein, the peripheral circuit is configured to:

3. The memory device of claim 1, wherein, obtain a first result corresponding to the at least one code word under a target read voltage; and determine the target read voltage as one of the reference read voltages and the first result within the first preset interval as a first result corresponding to the reference read voltage based on the first result corresponding to the at least one code word under the target read voltage being within the first preset interval. the peripheral circuit is configured to: obtain a predicted parameter of the preset function model based on the M first results, the M reference read voltages, and the preset function model; the predicted parameter being a reference read voltage corresponding to a minimum of the first results on a curve of the preset function model; and 4. The memory device of claim 1, wherein, obtain the predicted valley voltage based on the predicted parameter. the preset function model comprises a quadratic function model, the quadratic function model comprising a function relationship as follows: wherein, the y is a first result, the x is a reference read voltage, the b represents a predicted parameter, the a is a first parameter, and the c is a second parameter.

5. The memory device of claim 1, wherein, the first preset interval representing a range between a first threshold value and a second threshold value of a curve of the quadratic function model; the first threshold value being greater than the second threshold value. y = a(x + b) 2 + c the first parameter and the second parameter are both constants; the peripheral circuit is configured to:

6. The memory device of claim 5, wherein, obtain a first result corresponding to the at least one code word under a target read voltage; and 7. The memory device of claim 6, wherein, determine the target read voltage as one of the reference read voltages based on the first result corresponding to the at least one code word under the target read voltage being within the first preset interval. ​ ​ ​ According to the first result corresponding to the target read voltage of the at least one code word being outside the first preset interval, at least one new target read voltage is re-acquired, and a first result corresponding to the at least one new target read voltage is acquired until the first result corresponding to the latest target read voltage is within the first preset interval.

8. The memory device of claim 7, wherein, At least two of the M reference read voltages are on two sides of a symmetry axis of the curve of the quadratic function model; The peripheral circuit is configured to: When the reference read voltages are acquired, a reference read voltage on a first side of the two sides of the symmetry axis of the curve of the quadratic function model is acquired; and According to the reference read voltage on the first side, a reference read voltage on a second side of the two sides of the symmetry axis is determined.

9. The memory device of claim 8, wherein, The peripheral circuit is configured to: According to the first result corresponding to the target read voltage of the at least one code word being outside the first preset interval, a fitting read voltage on the first side corresponding to the target first result is acquired based on the target read voltage, the first result corresponding to the target read voltage, the target first result, and a first mapping function; The first mapping function is obtained according to the quadratic function model, the first parameter, and the second parameter; the target first result is within a second preset interval, and the first preset interval is within the range of the second preset interval; A first result corresponding to the at least one code word under the fitting read voltage on the first side is acquired; and According to the first result corresponding to the fitting read voltage on the first side being within the first preset interval, the fitting read voltage on the first side is taken as one of the reference read voltages on the first side. According to the first result corresponding to the fitting read voltage on the first side being outside the first preset interval, a next fitting read voltage on the first side corresponding to the target first result is acquired based on a previous fitting read voltage on the first side, the first result corresponding to the previous fitting read voltage on the first side, the target first result, and the first mapping function, until the first result corresponding to the latest fitting read voltage on the first side is within the first preset interval, and the latest fitting read voltage on the first side is taken as one of the reference read voltages on the first side. The peripheral circuit is configured to:

10. The memory device of claim 9, wherein, According to the number of times that the first result corresponding to the latest fitting read voltage on the first side is outside the first preset interval being greater than or equal to a preset number of times, the value of the first parameter is adjusted, and the first mapping function is correspondingly adjusted. ​ Based on the last adjusted fitting read voltage on the first side, the first result corresponding to the last adjusted fitting read voltage on the first side, the target first result and the first mapping function, a next adjusted fitting read voltage on the first side corresponding to the target first result is obtained until the first result corresponding to the latest adjusted fitting read voltage on the first side is in the first preset interval.

11. The memory device of claim 9 or 10, wherein, The peripheral circuit is configured to: Based on one of the reference read voltages on the first side, the first result corresponding to one of the reference read voltages on the first side, the target first result and a second mapping function, a fitting read voltage on the second side corresponding to the target first result is obtained; The second mapping function is obtained according to the quadratic function model, the first parameter / adjusted first parameter and the second parameter; At least one first result corresponding to at least one code word under the fitting read voltage on the second side is obtained; And According to the first result corresponding to the fitting read voltage on the second side being in a preset interval, the fitting read voltage on the second side is taken as one of the reference read voltages on the second side.

12. The memory device of claim 11, wherein, The peripheral circuit is configured to: According to the first result corresponding to the fitting read voltage on the second side being out of a preset interval, based on the last fitting read voltage on the second side, the first result corresponding to the last fitting read voltage on the second side, the target first result and a third mapping function, a next fitting read voltage on the second side corresponding to the target first result is obtained until the first result corresponding to the latest fitting read voltage on the second side is in the first preset interval, and the latest fitting read voltage on the second side is taken as one of the reference read voltages on the second side; The third mapping function is obtained according to the quadratic function model, the first parameter / adjusted first parameter and the second parameter.

13. The memory device of claim 6, wherein, The first parameter is a variable and the second parameter is a constant; the peripheral circuit is configured to: According to the M first results and the M reference read voltages, the prediction parameter is obtained by combining a quadratic function model; The prediction parameter is taken as the predicted valley bottom voltage.

14. The memory device of claim 6, wherein, The first parameter and the second parameter are both variables; the peripheral circuit is configured to: According to the M first results and the M reference read voltages, the prediction parameter is obtained by combining the quadratic function model; The prediction parameter is taken as a target read voltage, and at least one first result corresponding to at least one code word under the target read voltage is obtained; According to the M first results, the M reference read voltages, the prediction parameter and the first result corresponding to the target read voltage, a new prediction parameter is obtained by combining the quadratic function model; The new prediction parameter is taken as the predicted valley bottom voltage.

15. The memory device of claim 1, wherein, The storage unit array includes storage units with a storage bit number of multiple bits; multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple stages; the peripheral circuit is configured to: After determining the target valley bottom voltage of at least one of the code words at the target stage, the target valley bottom voltage of other stages in the multiple stages except the target stage is determined respectively.

16. The memory device of claim 15, wherein, The multiple stages include a first stage and a second stage, and the read voltage of the second stage is lower than that of the first stage; the peripheral circuit is configured to: When the stage corresponding to the determined target valley bottom voltage belongs to the first stage, the predicted valley bottom voltage of the second stage and / or the predicted valley bottom voltage of the remaining first stages with lower read voltage are obtained according to the target valley bottom voltage determined by the first stage.

17. The memory device of claim 7, wherein, The peripheral circuit is configured to: According to the first result corresponding to at least one code word at the target read voltage, a preset threshold value is obtained; The preset threshold value is used to represent the maximum value in the effective range of the predicted valley bottom voltage corresponding to the first result; According to the first result corresponding to the predicted valley bottom voltage being less than the preset threshold value, the predicted valley bottom voltage is taken as the target valley bottom voltage.

18. The memory device of claim 1, wherein, The peripheral circuit is configured to: Read the storage data of at least one of the code words at the first read voltage to obtain a second result; Read the storage data of at least one of the code words at the second read voltage to obtain a third result; Logical operation is performed on the second result and the third result to obtain a fourth result; The number of bits representing the flip of the third result compared with the second result in the fourth result is counted to obtain the first result.

19. The memory device of claim 18, wherein, The peripheral circuit includes a first latch, a second latch and a third latch; The first latch is configured to store the second result; The second latch is configured to store the third result; The third latch is configured to store the fourth result.

20. A memory system, comprising, one or more memory devices as claimed in any one of claims 1 to 19; and a memory controller coupled to the memory device and controlling the memory device.

21. The memory system of claim 20, wherein, the memory controller is configured to send a data acquisition instruction indicating to acquire a target valley bottom voltage; the memory device is configured to receive the data acquisition instruction, acquire a target valley bottom voltage, and send information including the target valley bottom voltage to the memory controller; the memory controller is further configured to perform a read operation on the data stored in the memory device according to the target valley bottom voltage in the information.

22. The memory system of claim 21, wherein, The memory controller is further configured to perform an error correction code decoding operation on the read result of the read operation.

23. A memory controller coupled to at least one memory device, the memory device comprising a plurality of memory cells, a predetermined number of the memory cells forming a code word. The memory controller includes: a control unit configured to: obtaining M first results corresponding to the at least one code word under M reference read voltages; the first results include a number of bits representing a flip in a reading result of the at least one code word under a first read voltage and a second read voltage; a difference between the first read voltage and the second read voltage is less than a preset voltage; the M is an integer greater than or equal to 2; obtaining a predicted valley bottom voltage according to the M first results and the M reference read voltages and in combination with a preset function model; the preset function model represents a relationship between the first results and the reference read voltages; the M first results are all within a first preset interval; and determining a target valley bottom voltage based on the predicted valley bottom voltage; the target valley bottom voltage is used as a read voltage for the at least one code word when performing a reading operation.

24. The memory controller of claim 23, wherein, The first preset interval represents a numerical interval of the first results corresponding to a preset region of a curve of the preset function model.

25. The memory controller of claim 23, wherein, The control unit is configured to: obtain a first result corresponding to the at least one code word under a target read voltage; and obtain the target read voltage as one of the reference read voltages and the first result within the first preset interval as the first result corresponding to the reference read voltage. The control unit is configured to:

26. The memory controller of claim 23, wherein, obtain a predicted parameter of the preset function model according to the M first results and the M reference read voltages and in combination with the preset function model; the predicted parameter is a reference read voltage corresponding to a minimum of the first results on a curve of the preset function model; and obtain the predicted valley bottom voltage according to the predicted parameter. In the equation, y represents the first result, x represents the reference read voltage, b represents the predicted parameter, a represents a first parameter, and c represents a second parameter.

27. The memory controller of claim 23, wherein, The preset function model includes a quadratic function model, and the quadratic function model includes the following function relationship: y=a(x+b) 2 +c The first preset interval represents a range between a first threshold and a second threshold of a curve of the quadratic function model; the first threshold is greater than the second threshold.

28. The memory controller of claim 27, wherein, The first parameter and the second parameter are both constants; the control unit is configured to:

29. The memory controller of claim 28, wherein, obtain a first result corresponding to the at least one code word under a target read voltage; and obtain the target read voltage as one of the reference read voltages when the first result corresponding to the at least one code word under the target read voltage is within a preset interval. When the first result corresponding to the at least one code word under the target read voltage is outside the first preset interval, re-obtain at least one new target read voltage, obtain a first result corresponding to the at least one new target read voltage, and continue until the first result corresponding to the latest target read voltage is within the first preset interval. At least two of the M reference read voltages are on two sides of a symmetry axis of the curve of the quadratic function model; and the control unit is configured to: obtain a reference read voltage on a first side of the two sides of the symmetry axis of the curve of the quadratic function model when obtaining the reference read voltage; and 30. The memory controller of claim 29, wherein, obtain a reference read voltage on a second side of the two sides of the symmetry axis of the curve of the quadratic function model when obtaining the reference read voltage. ​ According to the reference read voltage on the first side, a reference read voltage on a second side of the two sides of the symmetry axis is determined.

31. The memory controller of claim 30, wherein, The control unit is configured to: According to the first result corresponding to the target read voltage of the at least one code word being outside the first preset interval, a fitting read voltage on the first side corresponding to the target first result is obtained based on the target read voltage, the first result corresponding to the target read voltage, the target first result, and a first mapping function; The first mapping function is obtained according to the quadratic function model, the first parameter, and the second parameter; and the target first result is within a second preset interval, and the first preset interval is within the range of the second preset interval; At least one first result corresponding to the fitting read voltage on the first side of the at least one code word is obtained; And According to the first result corresponding to the fitting read voltage on the first side being within the first preset interval, the fitting read voltage on the first side is taken as one of the reference read voltages on the first side; According to the first result corresponding to the fitting read voltage on the first side being outside the first preset interval, a next fitting read voltage on the first side corresponding to the target first result is obtained based on a previous fitting read voltage on the first side, the first result corresponding to the previous fitting read voltage on the first side, the target first result, and the first mapping function, until the first result corresponding to the latest fitting read voltage on the first side is within the first preset interval, and the latest fitting read voltage on the first side is taken as one of the reference read voltages on the first side.

32. The memory controller of claim 31, wherein, The control unit is configured to: According to the number of times that the first result corresponding to the latest fitting read voltage on the first side is outside the first preset interval being greater than or equal to a preset number of times, the value of the first parameter is adjusted, and the first mapping function is correspondingly adjusted; A next adjusted fitting read voltage on the first side corresponding to the target first result is obtained based on a previous fitting read voltage on the first side, the first result corresponding to the previous fitting read voltage on the first side, the target first result, and the adjusted first mapping function, until the first result corresponding to the latest adjusted fitting read voltage on the first side is within the first preset interval.

33. The memory controller of claim 31 or 32, wherein, The control unit is configured to: A fitting read voltage on the second side corresponding to the target first result is obtained based on one of the reference read voltages on the first side, the first result corresponding to one of the reference read voltages on the first side, the target first result, and a second mapping function; The second mapping function is obtained according to the quadratic function model, the first parameter / adjusted first parameter, and the second parameter; At least one first result corresponding to the fitting read voltage on the second side of the at least one code word is obtained; And According to the first result corresponding to the fitting read voltage on the second side being in a preset interval, the fitting read voltage on the second side is taken as one of the reference read voltages on the second side.

34. The memory controller of claim 33, wherein, The control unit is configured to: According to the first result corresponding to the fitting read voltage on the second side being out of the preset interval, a next fitting read voltage on the second side corresponding to the target first result is obtained based on a previous fitting read voltage on the second side, the first result corresponding to the previous fitting read voltage on the second side, the target first result and a third mapping function, until the first result corresponding to the latest fitting read voltage on the second side is in the first preset interval, and the latest fitting read voltage on the second side is taken as one of the reference read voltages on the second side. The third mapping function is obtained according to the quadratic function model, the first parameter / adjusted first parameter and the second parameter.

35. The memory controller of claim 27, wherein, The first parameter is a variable and the second parameter is a constant; and the control unit is configured to: According to the M first results and the M reference read voltages, the prediction parameter is obtained in combination with a quadratic function model. The prediction parameter is taken as the prediction valley voltage.

36. The memory controller of claim 27, wherein, The first parameter and the second parameter are both variables; and the control unit is configured to: According to the M first results and the M reference read voltages, the prediction parameter is obtained in combination with the quadratic function model. The prediction parameter is taken as a target read voltage, and a first result corresponding to at least one code word under the target read voltage is obtained. According to the M first results, the M reference read voltages, the prediction parameter and the first result corresponding to the target read voltage, a new prediction parameter is obtained in combination with the quadratic function model. The new prediction parameter is taken as the prediction valley voltage.

37. The memory controller of claim 23, wherein, The memory cell array comprises memory cells with a plurality of bits; a plurality of memory bits correspond to a plurality of pages; at least one page corresponds to a plurality of orders; and the control unit is configured to: After determining the target valley voltage of at least one code word at a target order, target valley voltages of other orders except the target order in the plurality of orders are determined respectively.

38. The memory controller of claim 37, wherein, The plurality of orders comprises a first order and a second order, and the read voltage of the second order is lower than that of the first order; and the control unit is configured to: When the order corresponding to the determined target valley voltage belongs to the first order, a prediction valley voltage of the second order and / or a prediction valley voltage of the remaining first order with lower read voltage are obtained according to the target valley voltage determined for the first order.

39. The memory controller of claim 23, wherein, The control unit is configured to: According to the first result corresponding to the target read voltage of at least one code word, a preset threshold is obtained. The preset threshold is used to represent the first result corresponding to the maximum value in the effective range of the prediction valley voltage. According to the first result corresponding to the prediction valley voltage being less than the preset threshold, the prediction valley voltage is taken as the target valley voltage.

40. A method for operating a memory device, the memory device comprising a plurality of memory cells, a preset number of the memory cells forming a codeword; the method comprising: obtaining M first results corresponding to at least one of the codewords under M reference read voltages; the first results comprising a number of bits representing a flipping between two read results of the at least one of the codewords under a first read voltage and a second read voltage; the first read voltage and the second read voltage having a difference less than a preset voltage; the M being an integer greater than or equal to 2; obtaining a predicted valley voltage based on the M first results and the M reference read voltages in combination with a preset function model; the preset function model representing a relationship between the first results and the reference read voltages; the M first results being within a first preset interval; and determining a target valley voltage based on the predicted valley voltage; the target valley voltage being used as a read voltage for the at least one of the codewords when performing a read operation.

41. The method of operating of claim 40, wherein, the first preset interval representing a numerical interval of the first results corresponding to a preset region of a curve of the preset function model.

42. The method of operating of claim 40, wherein, the method comprising: obtaining a first result corresponding to at least one of the codewords under a target read voltage; and based on the first result corresponding to the at least one of the codewords under the target read voltage being within the first preset interval, using the target read voltage as one of the reference read voltages and using the first result within the first preset interval as the first result corresponding to the reference read voltage.

43. The method of operating of claim 40, wherein, the method comprising: obtaining a predicted parameter of the preset function model based on the M first results and the M reference read voltages in combination with the preset function model; the predicted parameter being a reference read voltage corresponding to a minimum of the first results on a curve of the preset function model; obtaining the predicted valley voltage based on the predicted parameter.

44. The method of operating of claim 40, wherein, The preset function model includes a quadratic function model, and the quadratic function model includes a function relationship formula: y=a(x+b) 2 +c wherein the y is a first result, the x is a reference read voltage, the b represents a predicted parameter, the a is a first parameter, and the c is a second parameter.

45. The method of operating of claim 44, wherein, the first preset interval representing a range between a first threshold value and a second threshold value of a curve of the quadratic function model; the first threshold value being greater than the second threshold value.

46. A storage medium having stored thereon executable instructions that, when executed, implement the steps of the method of any one of claims 40-45.

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