Preparation method for back-face p-i-n structure, and preparation method for high-efficiency crystalline silicon cell

Abstract

The present invention relates to the technical field of solar cells, and specifically relates to a preparation method for a back-face P-I-N structure, and a preparation method for a high-efficiency crystalline silicon cell. The preparation method for a back-face P-I-N structure comprises: texturing a silicon wafer; performing an oxidation treatment on a front face to obtain a front-face oxide layer, sequentially performing acid pickling and alkali polishing on a back face and then sequentially preparing a tunneling layer and an intrinsic amorphous silicon layer on the polished face; sequentially performing full-face inkjet deposition of a boron-containing solution and a silicon-containing transition solution on the intrinsic amorphous silicon layer, performing a laser curing treatment on P+ regions predefined according to requirements, and cleaning other regions to form prefabricated P+ regions; then, performing full-face inkjet deposition of a phosphorus-containing solution, performing a drying treatment, and performing a laser incision treatment on spacing regions predefined according to requirements until the intrinsic amorphous silicon layer is exposed, so as to form prefabricated N+ regions and the spacing regions; and performing high-temperature crystallization to form doping, and performing cleaning to obtain a back-face P-I-N structure. On this basis, a TBC cell is prepared. The present invention involves a simplified process route and also ensures cell efficiency.

Description

Back surface P-I-N structure preparation method and high-efficiency crystalline silicon cell preparation method TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a back surface P-I-N structure preparation method and a high-efficiency crystalline silicon cell preparation method. BACKGROUND

[0002] BC cells (Back Contact, back contact cells) are the general name of various types of back contact structure crystalline silicon solar cells, so BC cells are also called "XBC cells", and daily mentioned IBC, HBC, PBC, TBC, etc. all belong to BC cells. BC, as a platform technology with high expandability, can be combined with other cell technologies, for example, BC can be combined with PERC technology to form PBC, and the conversion efficiency can be increased to 24%-25%; BC and TOPCon are combined to form TBC (tunneling oxide passivation back contact), and the conversion efficiency can reach 25%-26%; BC and HJT are combined to form HBC (heterojunction back contact), and the conversion efficiency can reach 26%-27%.

[0003] The TBC cell structure is: the back surface PN region is prepared by mask and furnace tube diffusion, or the back surface PN region is prepared by mask and CVD in-situ doping; and a layer of ultra-thin tunneling oxide layer is deposited between the PN region and the base region; the P region and the N region are isolated and respectively contact with the metal electrode, and single-sided screen printing (without main grid or with multiple grids) is performed. The BC cell transfers all the electrode grid lines on the front surface of the cell to the back surface of the cell, reduces the shading of the electrode grid lines to sunlight, maximizes the use of sunlight, expands the effective generating area, and thus improves the conversion efficiency of the cell.

[0004] The current common production equipment process route in the industry is: sample texturing → single-sided alkali etching → LPCVD deposition of intrinsic amorphous silicon layer → high-temperature boron diffusion to complete doping and crystallization → mask → laser opening of BSG (N region) → reverse etching → LPCVD deposition of intrinsic amorphous silicon layer → high-temperature phosphorus diffusion to complete doping. In order to prepare the N+ region, the local P+ region and the isolation region therebetween (the structure combined by the three is usually referred to as a P-I-N structure), two diffusion processes, two amorphous silicon deposition processes and two laser processes are required in the existing process route, which is long in process time, seriously affects the production capacity, causes additional manufacturing costs, and the existing process route has too many high-temperature processes, i.e. two high-temperature diffusion processes (phosphorus diffusion temperature 800-1000℃, boron diffusion temperature 900-1200℃), which greatly affects the minority carrier lifetime of the substrate silicon wafer and thus adversely affects the cell efficiency. In addition, the existing TBC preparation process route is complex, the process window is small, and the problems such as additional large equipment costs result in insufficient product competitiveness. SUMMARY

[0005] In order to solve the technical problems that the existing preparation process of P-I-N structure is complex, which leads to the complex preparation process of TBC and greatly affects the minority carrier lifetime of the silicon wafer substrate, a back P-I-N structure preparation method and a high-efficiency crystalline silicon cell preparation method are provided. The back P-I-N structure can be prepared by using a transition solution containing silicon, a solid-phase source diffusion method, and laser solidification. The TBC cell structure preparation can be completed by matching once amorphous silicon deposition and once high-temperature propulsion. The process route is simplified while ensuring the cell efficiency.

[0006] In order to achieve the above purpose, the present application realizes the following technical scheme:

[0007] The back P-I-N structure preparation method comprises the following steps:

[0008] A prefabricated silicon wafer is provided, and the back surface structure of the prefabricated silicon wafer has a tunneling layer and an intrinsic amorphous silicon layer from inside to outside.

[0009] The surface of the back surface structure of the prefabricated silicon wafer is subjected to P+ region and N+ region definition, and the definition requirements are as follows: the P+ region and the N+ region are arranged alternately and there is a spacing region between the P+ region and the N+ region.

[0010] The surface of the back surface structure of the prefabricated silicon wafer is subjected to inkjet deposition of a boron-containing solution and a silicon-containing transition solution in sequence, laser solidification treatment is performed on the P+ region, and after cleaning the un-solidified area, a prefabricated P+ region is formed. Then, a phosphorus-containing solution is deposited on the whole surface, dried, and subjected to laser film opening treatment to expose the pre-deposited intrinsic amorphous silicon layer, thereby forming a prefabricated N+ region and a spacing region.

[0011] Then, high-temperature crystallization and doping are performed, and subsequent cleaning is performed to remove the front surface oxidation layer, the back surface residual oxidation layer, and the excess solidified phosphorus-containing solution (such as the solidified phosphorus-containing solution existing in the surface thin layer of the prefabricated P+ region, and also including a part of the solidified phosphorus-containing solution of the surface thin layer of the prefabricated N+ region), thereby forming a back P-I-N structure with P+ regions and N+ regions arranged alternately and spacing regions between the P+ regions and the N+ regions.

[0012] Further, after inkjet deposition of the boron-containing solution and the silicon-containing transition solution, no drying operation is required, and the laser solidification treatment is directly performed.

[0013] Further, after inkjet deposition of the phosphorus-containing solution and drying, no laser solidification treatment is required, and the laser film opening treatment is directly performed.

[0014] Further, the process parameters of inkjet deposition are as follows: inkjet flow rate is 0.15-15 mL / min, and the height of the nozzle from the coated part during spraying is 100-5000 μm.

[0015] The boron-containing solution has boron element source from one or more of boric hydroxide, boric acid, boric sulfate, ammonium borate, borane, and is in a homogeneous liquid state, which contains or does not contain a solvent, and can select an aqueous solvent or an oily solvent, and according to the selected boron element source, a corresponding solvent is selected to be used or not to be used to form a stable homogeneous liquid inkjet ink; the borane includes monomethylborane, monobutylborane, monopentylborane, monohexylborane, monocedylborane, and the like.

[0016] The silicon-containing transition solution has silicon element source from one or more of silicic acid compounds, silanol compounds, silane coupling agents, and is in a homogeneous liquid state, which contains or does not contain a solvent, and can select an aqueous solvent or an oily solvent, and according to the selected silicon element source, a corresponding solvent is selected to be used or not to be used to form a stable homogeneous liquid inkjet ink; the alternative silicic acid compounds include ethyl silicate, tetraoctyl silicate, tetramethyl silicate, tetraallyl silicate, butyl orthosilicate, propyl orthosilicate, ethyl orthosilicate, monoethyl orthosilicate, tetraethyl orthosilicate, tetra(isopropyl) silicate, tetra(2-methoxyethanol) silicate, tetra(dimethylsilyl) orthosilicate, tetra(2-ethoxybutyl) silicate, tetra-(2-butoxyethyl) orthosilicate, tetra(2-methoxy-1-methylethyl) silicate, and the like; the silanol compounds include trimethylsilanol, triethylsilanol, triphenylsilanol, dimethylphenylsilanol, tri-t-butoxysilanol, tri-t-amyloxysilanol, tri(trimethylsiloxy)silanol, tri(trimethylsilyloxy)silanol, 1,4-phenylenebis(dimethylsilanol), (3,4-dihydro-2H-pyran-6-yl)dimethylsilanol, polydimethylsiloxanol, and the like; the silane coupling agents include silane or siloxane containing double bond, silane or siloxane containing amino group, silane or siloxane containing epoxy group, and the like, and common ones include KH550, KH560, KH570, KH792, DL602, and the like.

[0017] The phosphorus-containing solution has phosphorus element source from one or more of phosphorus halide, organic phosphoric acid or ester, inorganic phosphoric acid or salt, and is in a homogeneous liquid state, which contains or does not contain a solvent, and can select an aqueous solvent or an oily solvent, and according to the selected phosphorus element source, a corresponding solvent is selected to be used or not to be used to form a stable homogeneous liquid inkjet ink; the alternative compounds include phosphoric acid, phosphorous acid, hypophosphorous acid, pyrophosphoric acid, ammonium phosphate, ammonium dihydrogen phosphate, diammonium hydrogen phosphate, ammonium phosphite, dihydrogen ammonium phosphite, ammonium hypophosphite, dihydrogen ammonium hypophosphite, hypophosphorous acid, triammonium pyrophosphate, dihydrogen diammonium pyrophosphate, trihydrogen ammonium pyrophosphate, methyl methylphosphonate, methyl ethylphosphonate, trimethylphosphonate, dimethyl methylphosphonate, diethyl methylphosphonate, methyl phosphonate, cyclohexyl methylphosphonate, diisopropyl methylphosphonate, diisobutyl methylphosphonate, diethyl amino phosphonate, diethyl hydroxymethyl phosphonate, binaphthyl methylphosphonate, and the like.

[0018] Furthermore, the laser curing process is to cure the two layers of inkjet-deposited solution in the defined P+ region using a green laser with a wavelength of 532 nm at 3-20 W, and the overlap rate between the laser spots is controlled to be 0-70%;

[0019] The cleaning after the laser curing treatment is to use an organic solvent to remove the uncured boron-containing solution and silicon-containing transition solution. The organic solvent is selected from one or more of ethanol, acetone, styrene, perchloroethylene, and trichloroethylene.

[0020] Furthermore, the drying process is carried out at a temperature of 100-200° C. and for a time of 10-60 seconds to solidify the phosphorus-containing solution;

[0021] The laser film opening process is to use infrared laser with a wavelength of 1064nm at 50-100W to ablate in a limited interval area until the intrinsic amorphous silicon layer is exposed.

[0022] Furthermore, the high temperature crystallization temperature is 750-950°C and the time is 30-60 minutes;

[0023] The cleaning after high-temperature crystallization and doping is to first remove the front oxide layer in a bath-type hydrofluoric acid aqueous solution with a volume fraction of 3-10%, and then use a mixed solution of KOH and H2O2 to complete the cleaning of the excess solidified phosphorus-containing solution, wherein the volume fraction of KOH in the mixed solution is 1-5%, and the volume fraction of H2O2 is 5-15%.

[0024] Furthermore, the atomic doping concentration of the N+ region after high temperature crystallization is 3×10 20~ 1×10 21 / cm 3 , the atomic doping concentration of the P+ region is 1×10 19 ~1×10 20 / cm 3 In the obtained back-side PIN structure, the width of the P+ region is 300-800μm, the width of the N+ region is 100-300μm, the width of the spacing region is 5-30μm, the square resistance of the P+ region is 80-200Ω / sq, and the square resistance of the N+ region is 30-100Ω / sq.

[0025] Furthermore, the preparation process of the prefabricated silicon wafer is:

[0026] S1, clean the substrate crystalline silicon and do double-sided texturing;

[0027] S2. defining one surface of the crystalline silicon as the front surface and the other surface opposite thereto as the back surface;

[0028] The front surface is subjected to oxidation treatment to obtain a front surface oxide layer, the back surface is subjected to acid washing and alkali polishing in sequence to obtain a back surface polishing surface, a tunneling layer is prepared on the polishing surface, and an intrinsic amorphous silicon layer is prepared on the tunneling layer, thereby obtaining a pre-prepared silicon wafer.

[0029] Further, the crystalline silicon is N-type monocrystalline silicon wafer with a thickness of 100-300 μm and a resistivity of 0.8-1.5 Ω·cm; the cleaning in S1 removes the damaged layer on the surface of the silicon wafer by using a mixed solution of KOH and H2O2; the texturing in S1 forms a pyramid texturing surface by etching the silicon wafer with a KOH solution, and the height of the pyramid texturing surface is controlled to be 1-5 μm;

[0030] The oxidation treatment in S2 is performed in a chain-type oxidation furnace at 600-800 ℃, and the front surface oxide layer is silicon oxide with a thickness of 3-10 nm; the acid washing in S2 removes the back surface oxide layer by using a hydrofluoric acid aqueous solution with a volume fraction of 1-5 %; and the alkali polishing is performed by using a sodium hydroxide aqueous solution with a volume fraction of 1-5 % at 80-90 ℃ until the surface reflectivity is greater than 40 %;

[0031] The thickness of the tunneling layer is 1-2 nm, and the thickness of the intrinsic amorphous silicon layer is 50-150 nm, which are prepared by using conventional methods, for example, the tunneling layer can be formed by vapor phase oxidation at a temperature of 500-650 ℃, and the thickness of the layer is controlled by controlling the gas flow and the deposition time; the intrinsic amorphous silicon layer is formed by deposition of silane at a deposition temperature of 400-600 ℃ by using PECVD or LPCVD, and the thickness of the layer is controlled by controlling the silane flow and the deposition time.

[0032] Another aspect of the present application provides a method for preparing a high-efficiency crystalline silicon cell, which comprises the following steps: preparing a back surface P-I-N structure by using the above method; depositing an aluminum oxide layer on both surfaces of the back surface P-I-N structure; depositing a silicon nitride layer on the surface of the front surface aluminum oxide layer; depositing a silicon nitride layer on the surface of the back surface aluminum oxide layer; and screen printing silver electrodes on the P+ region and the N+ region, and sintering to obtain a high-efficiency crystalline silicon cell.

[0033] Further, the thickness of the aluminum oxide layer deposited on both surfaces is 3-10 nm; the thickness of the silicon nitride layer deposited on the surface of the front surface aluminum oxide layer is 75-80 nm; and the thickness of the silicon nitride layer deposited on the surface of the back surface aluminum oxide layer is 70-100 nm.

[0034] Beneficial technical effects:

[0035] 1. The existing process route has serious capacity defects. To prepare n+Poly (N+ region) and p+Poly (P+ region), two high-temperature diffusions are required (phosphorus diffusion at 800-1000°C and boron diffusion at 900-1200°C). The long process time seriously affects production capacity, resulting in additional manufacturing costs and greatly affecting the minority carrier lifetime of the substrate silicon wafer;

[0036] The present invention combines three solutions containing boron solution, phosphorus solution and silicon transition solution for coating, which can be applied by spraying, coating, printing or transfer, and high temperature can be applied by tube type, chain type or laser type, so as to realize a one-time high temperature process, shorten the process time and reduce the loss of substrate life caused by high temperature.

[0037] 2. The existing process route requires two amorphous silicon depositions, which makes process control more difficult, increases process costs and reduces product yield;

[0038] The present invention achieves differential diffusion through two sources on the same amorphous silicon layer, and uses laser curing to remove dopants between the two layers of sources for isolation. This simplifies the process and makes it easy to control. It can also ensure that sufficient iPoly layers serve as gap areas (interval areas) according to the graphic design.

[0039] 3. The current process route is to meet the needs of local n+Poly (N+ area), p+Poly (P+ area) and gap area (interval area) at the same time, which requires two laser film openings. The process route is complex, the process window is small, and a large amount of additional equipment costs are added;

[0040] The present invention uses a single laser for curing, which requires less laser energy and does not cause laser damage. The second laser can use a conventional film-opening laser without fine control, which allows for some damage to the underlying amorphous silicon. Since the next step is high-temperature annealing for repair, damage does not need to be considered, which greatly improves the process quality rate and product performance.

[0041] 4. The current process route uses reverse etching for patterning and gap area (interval area) preparation, and the process conditions are harsh and difficult to control;

[0042] The present invention does not require a reverse etching process. When preparing the prefabricated P+ area, it is only necessary to clean and remove the unsolidified solution. The properties of the solution coated on the area that has not been laser-cured are still consistent with the solute of the original solution, and the original solvent can be used for cleaning and removal. The process has a wider process tolerance range and will not etch the underlying Poly Si layer (evolved from the intrinsic amorphous silicon layer after high-temperature crystallization) or the SiO2 generated by the reaction. There is no need to consider the impact of this step on other structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a process flow chart of the preparation of the back-side PIN structure of the present invention. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the embodiments of the present application and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and not intended to be limiting on the present application and its applications or uses. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of the present application.

[0045] Unless otherwise specified, the numerical values set forth in these embodiments do not limit the scope of the present application. Techniques, methods known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered part of the specification where appropriate. In all examples shown and discussed herein, any specific value should be interpreted as merely exemplary, and not as a limitation. Thus, other examples of the exemplary embodiments can have different values.

[0046] In addition, it should be noted that the use of "first", "second", back surface structure is only for the convenience of distinguishing the products obtained in each step, and the above words have no special meaning unless otherwise stated, and therefore cannot be understood as limiting the scope of protection of the present application.

[0047] The experimental methods in the following embodiments without specific conditions are generally determined according to the national standard; if there is no corresponding national standard, they are carried out according to the general standard requirements or general methods.

[0048] Other names of P-I-N structure: P-i-N structure or p-i-n structure. Embodiment 1

[0049] The back surface P-I-N structure preparation method, as shown in FIG. 1 (A) to (I), comprises the following steps:

[0050] S1, as shown in FIG. 1 (A) to (B), the substrate N-type monocrystalline silicon wafer (thickness 100-300 μm, resistivity 0.8-1.5 Ω· cm) is cleaned, and a mixed solution of KOH and H2O2 is used to clean and remove the damage layer on the surface of the silicon wafer;

[0051] Then, double-sided texturing is carried out, and a KOH solution with a volume fraction of 1-2% is used to etch the surface of the silicon wafer to form a pyramid texture, and the etching time is controlled to control the height of the pyramid texture to be 1.1-1.5 μm;

[0052] S2, defining one surface of the crystalline silicon as the front surface, the other surface opposite to the front surface as the back surface;

[0053] As shown in (C) of FIG. 1, the front surface is subjected to an oxidation treatment to obtain a front surface oxide layer, the front surface oxide layer being silicon oxide, the oxidation treatment being performed in a chain-type oxidation furnace at 700°C, an atmosphere of oxygen being adopted, and the thickness of the front surface oxide layer being controlled to be 3-6 nm by controlling the oxidation treatment time, the back surface being subjected to acid washing and alkali polishing in sequence, the acid washing adopting a 3% hydrofluoric acid aqueous solution to remove the back surface oxide layer generated in the aforementioned process, and the alkali polishing adopting a 4% sodium hydroxide aqueous solution to polish the back surface at 80-90°C to a surface reflectivity greater than 40%, thereby obtaining a first processed back surface structure;

[0054] S3, as shown in (D) of FIG. 1, a tunneling layer is first prepared on the alkali polished surface of the first processed back surface structure, and an intrinsic amorphous silicon layer is prepared on the tunneling layer, thereby obtaining a second processed back surface structure;

[0055] The thickness of the tunneling layer is 1-2 nm, and the thickness of the intrinsic amorphous silicon layer is 80-120 nm; the tunneling layer is deposited by a gas phase oxidation method in an LPCVD at a temperature of 500-600°C, and the thickness of the layer is controlled by controlling the gas flow rate and the deposition time; the intrinsic amorphous silicon layer is subsequently deposited by using silane at a deposition temperature of 500-600°C, and the thickness of the layer is controlled by controlling the silane flow rate and the deposition time;

[0056] S4, defining P+ regions and N+ regions on the second processed back surface, the definition requirement being that the P+ regions and the N+ regions are arranged alternately and there is a spacing region between the P+ regions and the N+ regions;

[0057] As shown in (E) and (F) of FIG. 1, after the definition requirement is met, a boron-containing solution is first deposited on the second processed back surface structure by inkjet to cover the intrinsic amorphous silicon layer, the inkjet deposition being performed under the conditions of an inkjet flow rate of 0.2-10 mL / min and a nozzle distance from the height of the piece to be coated of 100-500 μm, the boron element in the boron-containing solution being derived from boric acid, and the solvent being ethanol, the boron-containing solution being mixed uniformly to form a stable homogeneous liquid ink, the concentration of the boron element in the boron-containing solution and the thickness of the inkjet being adjusted within the range of 1×1018 atoms / cm3 to 1×1021 atoms / cm3 and 0.1-10 nm, respectively, without the need for drying; 19 ~1×10 20 / cm 3

[0058] ​Directly carry out the whole surface inkjet deposition of the silicon-containing transition solution to cover the deposited boron-containing solution, and carry out the inkjet deposition under the conditions of inkjet flow rate of 0.2-10mL / min and nozzle height of 100-500μm from the object to be coated. The silicon element source of the silicon-containing transition solution is selected from ethyl orthosilicate (liquid), and it does not contain solvent, and still does not need to be dried;

[0059] The P+ region is laser cured using a 532nm green laser at 3-15W to cure the two layers of inkjet-deposited solution in the defined P+ region. The thermal effect of the laser is used to locally cure the boron-containing solution and silicon-containing transition solution. After the laser curing treatment is completed, the remaining area is cleaned with ethanol to remove the uncured boron-containing solution and silicon-containing transition solution, forming a prefabricated P+ region (a two-layer structure with cured boron-containing solution and silicon-containing transition solution), thereby obtaining the third-processed backside structure.

[0060] As shown in Figures (G) and (H) of Figure 1, a phosphorus-containing solution is inkjet deposited on the entire surface of the third-treated back structure to cover the aforementioned prefabricated P+ area. The inkjet deposition is performed under the conditions of an inkjet flow rate of 0.2-10 mL / min and a height of 100-500 μm from the nozzle to the object to be coated. The phosphorus element in the phosphorus-containing solution is phosphoric acid, and the solvent is ethanol. After mixing evenly, a stable homogeneous liquid inkjet ink is formed. The concentration of boron in the phosphorus-containing solution and the thickness of the inkjet are based on the atomic doping concentration of 3×10 20~ 1×10 21 / cm 3 The temperature is adjusted within a certain range, and then dried at 200°C for 20-50s. Without laser curing, the defined spacing area is directly laser opened to expose the pre-deposited intrinsic amorphous silicon layer: the laser opening process uses an infrared laser with a wavelength of 1064nm at 80W to sequentially ablate and remove the inkjet-deposited phosphorus-containing solution, silicon-containing transition solution, and boron-containing solution in the defined spacing area to expose the intrinsic amorphous silicon layer, thereby forming a prefabricated N+ region and a spacing area, and obtaining the fourth processed back side structure;

[0061] S5. As shown in FIG. 1 (I) and (J), the structure is subjected to high-temperature crystallization at 900° C. for 40 minutes to form doping, and then cleaned to remove the front oxide layer and the residual oxide layer on the back side and excess solidified phosphorus-containing solution. The cleaning is first performed in a bath-type hydrofluoric acid aqueous solution with a volume fraction of 3% to remove the front oxide layer, and then a mixed solution of KOH and H2O2 is used to clean the excess solidified phosphorus-containing solution, wherein the volume fraction of KOH in the mixed solution is 2% and the volume fraction of H2O2 is 10%;

[0062] After cleaning, the back P-I-N structure with P+ region and N+ region arranged alternately and interval region between P+ region and N+ region is formed, and the back P-I-N structure is shown in (J), the P+ region sheet resistance of the back P-I-N structure is 100-180Ω / sq, the N+ region sheet resistance is 50-70Ω / sq, the P+ region width is 400-600μm, the N+ width is 100-300μm, the interval region width is 10-20μm, the P+ region height is equal to the N+ region height and in the range of 60-500nm. Example 2

[0063] A high-efficiency crystalline silicon cell preparation method, comprising the following preparation process:

[0064] Depositing 3-10nm thick aluminum oxide layer on the double surface of the back P-I-N structure prepared in Example 1;

[0065] Then, depositing 75-80nm thick silicon nitride layer on the surface of the front aluminum oxide layer, depositing 70-100nm thick silicon nitride layer on the surface of the back aluminum oxide layer, screen printing silver electrode on the P+ region and N+ region, and sintering to prepare high-efficiency crystalline silicon cell. The aluminum oxide layer deposition and silicon nitride layer deposition in the case are not different from the conventional technology.

[0066] The TBC cell prepared by Example 2 and the conventional process is subjected to cell performance test, and the results are shown in Table 1.

[0067] Table 1 Cell performance

[0068]

[0069] As shown in Table 1, after the manufacturing process of the back P-I-N structure is simplified, the TBC cell with equivalent performance can be obtained.

[0070] The above description is only the preferred embodiment of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can make equivalent replacement or change according to the technical solution and the inventive concept of the present application within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A method of fabricating a backside P-I-N structure, characterized by, The method comprises the following steps: providing a prefabricated silicon wafer, the back surface structure of the prefabricated silicon wafer sequentially comprises a tunneling layer and an intrinsic amorphous silicon layer from inside to outside; defining a P+ region and an N+ region on the surface of the back surface structure of the prefabricated silicon wafer, the definition requirement is that the P+ region and the N+ region are arranged alternately and there is a spacing region between the P+ region and the N+ region; inkjet depositing a boron-containing solution and a silicon-containing transition solution on the surface of the back surface structure of the prefabricated silicon wafer according to the requirement, performing laser curing treatment on the P+ region, cleaning the non-cured region to form a prefabricated P+ region; then inkjet depositing a phosphorus-containing solution on the whole surface, drying treatment, performing laser film opening treatment on the spacing region to expose the pre-deposited intrinsic amorphous silicon layer to form a prefabricated N+ region and the spacing region; then performing high-temperature crystallization and doping, and subsequent cleaning, thereby forming a back P-I-N structure with the P+ region and the N+ region arranged alternately and the spacing region between the P+ region and the N+ region.

2. The method of claim 1, wherein the back P-I-N structure is formed by a process comprising: After inkjet depositing the boron-containing solution and the silicon-containing transition solution, no drying operation is needed, and the laser curing treatment is directly performed.

3. The method of claim 1, wherein the backside P-I-N structure is formed by a process comprising: After inkjet depositing the phosphorus-containing solution and drying, no laser curing treatment is needed, and the laser film opening treatment is directly performed. ​ 4. The method of claim 1, wherein the backside P-I-N structure is formed by a process comprising: The process parameters of the inkjet deposition are as follows: inkjet flow is 0.15-15 mL / min, and the height of the nozzle from the to-be-coated piece during spraying is 100-5000 μm; the boron element source in the boron-containing solution is one or more of boron hydroxide, boric acid, boron sulfate, ammonium borate and borane, and the boron-containing solution is a homogeneous liquid, and a solvent is selected according to the selected boron element source; the silicon element source in the silicon-containing transition solution is one or more of a silicic acid compound, a silanol compound and a silane coupling agent, and the silicon-containing transition solution is a homogeneous liquid, and a solvent is selected according to the selected silicon element source; the phosphorus element source in the phosphorus-containing solution is one or more of a phosphorus halide, an organic phosphoric acid or ester, and an inorganic phosphoric acid or salt, and the phosphorus-containing solution is a homogeneous liquid, and a solvent is selected according to the selected phosphorus element source.

5. The method of claim 1, wherein the backside P-I-N structure is formed by a process comprising: The laser curing treatment is to cure the two layers of inkjet-deposited solutions of the defined P+ region by using a green laser with a wavelength of 532 nm at a power of 3-20 W, and the overlapping rate between laser spots is controlled to be 0-70%; ​ the cleaning after the laser curing treatment is to remove the uncured boron-containing solution and silicon-containing transition solution by using an organic solvent, and the organic solvent is selected from one or more of ethanol, acetone, styrene, perchloroethylene and trichloroethylene.

6. The method of claim 1, wherein the backside P-I-N structure is formed by a process comprising: The drying treatment is performed at a temperature of 100-200 ℃ for 10-60 s to cure the phosphorus-containing solution; ​ the laser film opening treatment is to ablate the defined spacing region to expose the intrinsic amorphous silicon layer by using an infrared laser with a wavelength of 1064 nm at a power of 50-100 W.

7. The method of claim 1-6, wherein the back P-I-N structure is prepared by the steps of: The atomic doping concentration of the N+ region after high temperature crystallization is 3×10 20~ 1×10 21 / cm 3 , the atomic doping concentration of the P+ region is 1×10 19 ~1×10 20 / cm 3 In the obtained back-side PIN structure, the width of the P+ region is 300-800μm, the width of the N+ region is 100-300μm, the width of the spacing region is 5-30μm, the square resistance of the P+ region is 80-200Ω / sq, and the square resistance of the N+ region is 30-100Ω / sq. ​ 8. The method of claim 7, wherein the backside P-I-N structure is formed by a process comprising: The preparation process of the prefabricated silicon wafer is as follows: ​ S1, cleaning the substrate crystalline silicon and double-sided texturing; S2, defining one surface of the crystalline silicon as a front surface, and the other surface opposite to the front surface as a back surface; The front surface is subjected to oxidation treatment to obtain a front surface oxide layer, the back surface is subjected to acid washing and alkali polishing in sequence to obtain a back surface polishing surface, a tunneling layer is prepared on the polishing surface, and an intrinsic amorphous silicon layer is prepared on the tunneling layer to obtain a pre-prepared silicon wafer.

9. The method of claim 8, wherein the back P-I-N structure is formed by a process comprising: The oxidation treatment is performed in a chain oxidation furnace at 600-800 ℃, and the front surface oxide layer is silicon oxide with a thickness of 3-10 nm. ​ 10. A method for manufacturing a high efficiency crystalline silicon cell, characterized by, The back surface P-I-N structure prepared by the preparation method of any one of claims 1-9 is subjected to double-sided deposition of an aluminum oxide layer, deposition of a silicon nitride layer on the surface of the front surface aluminum oxide layer, deposition of a silicon nitride layer on the surface of the back surface aluminum oxide layer, and screen printing of silver electrodes on the P+ and N+ regions to obtain a high-efficiency crystalline silicon cell after sintering. The thickness of the double-sided deposited aluminum oxide layer is 3-10 nm, the thickness of the silicon nitride layer deposited on the surface of the front surface aluminum oxide layer is 75-80 nm, and the thickness of the silicon nitride layer deposited on the surface of the back surface aluminum oxide layer is 70-100 nm.

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